1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
17 #include "ARM.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMFPUName.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMTargetMachine.h"
23 #include "ARMTargetObjectFile.h"
24 #include "InstPrinter/ARMInstPrinter.h"
25 #include "MCTargetDesc/ARMAddressingModes.h"
26 #include "MCTargetDesc/ARMMCExpr.h"
27 #include "llvm/ADT/SetVector.h"
28 #include "llvm/ADT/SmallString.h"
29 #include "llvm/Assembly/Writer.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/DebugInfo.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DataLayout.h"
36 #include "llvm/IR/Module.h"
37 #include "llvm/IR/Type.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCAssembler.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCELFStreamer.h"
42 #include "llvm/MC/MCInst.h"
43 #include "llvm/MC/MCInstBuilder.h"
44 #include "llvm/MC/MCObjectStreamer.h"
45 #include "llvm/MC/MCSectionMachO.h"
46 #include "llvm/MC/MCStreamer.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/TargetRegistry.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/Mangler.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include <cctype>
57 using namespace llvm;
58 
59 /// EmitDwarfRegOp - Emit dwarf register operation.
60 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
61                                    bool Indirect) const {
62   const TargetRegisterInfo *RI = TM.getRegisterInfo();
63   if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) {
64     AsmPrinter::EmitDwarfRegOp(MLoc, Indirect);
65     return;
66   }
67   assert(MLoc.isReg() && !Indirect &&
68          "This doesn't support offset/indirection - implement it if needed");
69   unsigned Reg = MLoc.getReg();
70   if (Reg >= ARM::S0 && Reg <= ARM::S31) {
71     assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
72     // S registers are described as bit-pieces of a register
73     // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
74     // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
75 
76     unsigned SReg = Reg - ARM::S0;
77     bool odd = SReg & 0x1;
78     unsigned Rx = 256 + (SReg >> 1);
79 
80     OutStreamer.AddComment("DW_OP_regx for S register");
81     EmitInt8(dwarf::DW_OP_regx);
82 
83     OutStreamer.AddComment(Twine(SReg));
84     EmitULEB128(Rx);
85 
86     if (odd) {
87       OutStreamer.AddComment("DW_OP_bit_piece 32 32");
88       EmitInt8(dwarf::DW_OP_bit_piece);
89       EmitULEB128(32);
90       EmitULEB128(32);
91     } else {
92       OutStreamer.AddComment("DW_OP_bit_piece 32 0");
93       EmitInt8(dwarf::DW_OP_bit_piece);
94       EmitULEB128(32);
95       EmitULEB128(0);
96     }
97   } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
98     assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
99     // Q registers Q0-Q15 are described by composing two D registers together.
100     // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
101     // DW_OP_piece(8)
102 
103     unsigned QReg = Reg - ARM::Q0;
104     unsigned D1 = 256 + 2 * QReg;
105     unsigned D2 = D1 + 1;
106 
107     OutStreamer.AddComment("DW_OP_regx for Q register: D1");
108     EmitInt8(dwarf::DW_OP_regx);
109     EmitULEB128(D1);
110     OutStreamer.AddComment("DW_OP_piece 8");
111     EmitInt8(dwarf::DW_OP_piece);
112     EmitULEB128(8);
113 
114     OutStreamer.AddComment("DW_OP_regx for Q register: D2");
115     EmitInt8(dwarf::DW_OP_regx);
116     EmitULEB128(D2);
117     OutStreamer.AddComment("DW_OP_piece 8");
118     EmitInt8(dwarf::DW_OP_piece);
119     EmitULEB128(8);
120   }
121 }
122 
123 void ARMAsmPrinter::EmitFunctionBodyEnd() {
124   // Make sure to terminate any constant pools that were at the end
125   // of the function.
126   if (!InConstantPool)
127     return;
128   InConstantPool = false;
129   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
130 }
131 
132 void ARMAsmPrinter::EmitFunctionEntryLabel() {
133   if (AFI->isThumbFunction()) {
134     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
135     OutStreamer.EmitThumbFunc(CurrentFnSym);
136   }
137 
138   OutStreamer.EmitLabel(CurrentFnSym);
139 }
140 
141 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
142   uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
143   assert(Size && "C++ constructor pointer had zero size!");
144 
145   const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
146   assert(GV && "C++ constructor pointer was not a GlobalValue!");
147 
148   const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
149                                             (Subtarget->isTargetDarwin()
150                                              ? MCSymbolRefExpr::VK_None
151                                              : MCSymbolRefExpr::VK_ARM_TARGET1),
152                                             OutContext);
153 
154   OutStreamer.EmitValue(E, Size);
155 }
156 
157 /// runOnMachineFunction - This uses the EmitInstruction()
158 /// method to print assembly for each instruction.
159 ///
160 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
161   AFI = MF.getInfo<ARMFunctionInfo>();
162   MCP = MF.getConstantPool();
163 
164   return AsmPrinter::runOnMachineFunction(MF);
165 }
166 
167 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
168                                  raw_ostream &O, const char *Modifier) {
169   const MachineOperand &MO = MI->getOperand(OpNum);
170   unsigned TF = MO.getTargetFlags();
171 
172   switch (MO.getType()) {
173   default: llvm_unreachable("<unknown operand type>");
174   case MachineOperand::MO_Register: {
175     unsigned Reg = MO.getReg();
176     assert(TargetRegisterInfo::isPhysicalRegister(Reg));
177     assert(!MO.getSubReg() && "Subregs should be eliminated!");
178     if(ARM::GPRPairRegClass.contains(Reg)) {
179       const MachineFunction &MF = *MI->getParent()->getParent();
180       const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
181       Reg = TRI->getSubReg(Reg, ARM::gsub_0);
182     }
183     O << ARMInstPrinter::getRegisterName(Reg);
184     break;
185   }
186   case MachineOperand::MO_Immediate: {
187     int64_t Imm = MO.getImm();
188     O << '#';
189     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
190         (TF == ARMII::MO_LO16))
191       O << ":lower16:";
192     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
193              (TF == ARMII::MO_HI16))
194       O << ":upper16:";
195     O << Imm;
196     break;
197   }
198   case MachineOperand::MO_MachineBasicBlock:
199     O << *MO.getMBB()->getSymbol();
200     return;
201   case MachineOperand::MO_GlobalAddress: {
202     const GlobalValue *GV = MO.getGlobal();
203     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
204         (TF & ARMII::MO_LO16))
205       O << ":lower16:";
206     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
207              (TF & ARMII::MO_HI16))
208       O << ":upper16:";
209     O << *Mang->getSymbol(GV);
210 
211     printOffset(MO.getOffset(), O);
212     if (TF == ARMII::MO_PLT)
213       O << "(PLT)";
214     break;
215   }
216   case MachineOperand::MO_ExternalSymbol: {
217     O << *GetExternalSymbolSymbol(MO.getSymbolName());
218     if (TF == ARMII::MO_PLT)
219       O << "(PLT)";
220     break;
221   }
222   case MachineOperand::MO_ConstantPoolIndex:
223     O << *GetCPISymbol(MO.getIndex());
224     break;
225   case MachineOperand::MO_JumpTableIndex:
226     O << *GetJTISymbol(MO.getIndex());
227     break;
228   }
229 }
230 
231 //===--------------------------------------------------------------------===//
232 
233 MCSymbol *ARMAsmPrinter::
234 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
235   SmallString<60> Name;
236   raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
237     << getFunctionNumber() << '_' << uid << '_' << uid2;
238   return OutContext.GetOrCreateSymbol(Name.str());
239 }
240 
241 
242 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
243   SmallString<60> Name;
244   raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
245     << getFunctionNumber();
246   return OutContext.GetOrCreateSymbol(Name.str());
247 }
248 
249 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
250                                     unsigned AsmVariant, const char *ExtraCode,
251                                     raw_ostream &O) {
252   // Does this asm operand have a single letter operand modifier?
253   if (ExtraCode && ExtraCode[0]) {
254     if (ExtraCode[1] != 0) return true; // Unknown modifier.
255 
256     switch (ExtraCode[0]) {
257     default:
258       // See if this is a generic print operand
259       return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
260     case 'a': // Print as a memory address.
261       if (MI->getOperand(OpNum).isReg()) {
262         O << "["
263           << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
264           << "]";
265         return false;
266       }
267       // Fallthrough
268     case 'c': // Don't print "#" before an immediate operand.
269       if (!MI->getOperand(OpNum).isImm())
270         return true;
271       O << MI->getOperand(OpNum).getImm();
272       return false;
273     case 'P': // Print a VFP double precision register.
274     case 'q': // Print a NEON quad precision register.
275       printOperand(MI, OpNum, O);
276       return false;
277     case 'y': // Print a VFP single precision register as indexed double.
278       if (MI->getOperand(OpNum).isReg()) {
279         unsigned Reg = MI->getOperand(OpNum).getReg();
280         const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
281         // Find the 'd' register that has this 's' register as a sub-register,
282         // and determine the lane number.
283         for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
284           if (!ARM::DPRRegClass.contains(*SR))
285             continue;
286           bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
287           O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
288           return false;
289         }
290       }
291       return true;
292     case 'B': // Bitwise inverse of integer or symbol without a preceding #.
293       if (!MI->getOperand(OpNum).isImm())
294         return true;
295       O << ~(MI->getOperand(OpNum).getImm());
296       return false;
297     case 'L': // The low 16 bits of an immediate constant.
298       if (!MI->getOperand(OpNum).isImm())
299         return true;
300       O << (MI->getOperand(OpNum).getImm() & 0xffff);
301       return false;
302     case 'M': { // A register range suitable for LDM/STM.
303       if (!MI->getOperand(OpNum).isReg())
304         return true;
305       const MachineOperand &MO = MI->getOperand(OpNum);
306       unsigned RegBegin = MO.getReg();
307       // This takes advantage of the 2 operand-ness of ldm/stm and that we've
308       // already got the operands in registers that are operands to the
309       // inline asm statement.
310       O << "{";
311       if (ARM::GPRPairRegClass.contains(RegBegin)) {
312         const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
313         unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
314         O << ARMInstPrinter::getRegisterName(Reg0) << ", ";;
315         RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
316       }
317       O << ARMInstPrinter::getRegisterName(RegBegin);
318 
319       // FIXME: The register allocator not only may not have given us the
320       // registers in sequence, but may not be in ascending registers. This
321       // will require changes in the register allocator that'll need to be
322       // propagated down here if the operands change.
323       unsigned RegOps = OpNum + 1;
324       while (MI->getOperand(RegOps).isReg()) {
325         O << ", "
326           << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
327         RegOps++;
328       }
329 
330       O << "}";
331 
332       return false;
333     }
334     case 'R': // The most significant register of a pair.
335     case 'Q': { // The least significant register of a pair.
336       if (OpNum == 0)
337         return true;
338       const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
339       if (!FlagsOP.isImm())
340         return true;
341       unsigned Flags = FlagsOP.getImm();
342 
343       // This operand may not be the one that actually provides the register. If
344       // it's tied to a previous one then we should refer instead to that one
345       // for registers and their classes.
346       unsigned TiedIdx;
347       if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
348         for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
349           unsigned OpFlags = MI->getOperand(OpNum).getImm();
350           OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
351         }
352         Flags = MI->getOperand(OpNum).getImm();
353 
354         // Later code expects OpNum to be pointing at the register rather than
355         // the flags.
356         OpNum += 1;
357       }
358 
359       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
360       unsigned RC;
361       InlineAsm::hasRegClassConstraint(Flags, RC);
362       if (RC == ARM::GPRPairRegClassID) {
363         if (NumVals != 1)
364           return true;
365         const MachineOperand &MO = MI->getOperand(OpNum);
366         if (!MO.isReg())
367           return true;
368         const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
369         unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
370             ARM::gsub_0 : ARM::gsub_1);
371         O << ARMInstPrinter::getRegisterName(Reg);
372         return false;
373       }
374       if (NumVals != 2)
375         return true;
376       unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
377       if (RegOp >= MI->getNumOperands())
378         return true;
379       const MachineOperand &MO = MI->getOperand(RegOp);
380       if (!MO.isReg())
381         return true;
382       unsigned Reg = MO.getReg();
383       O << ARMInstPrinter::getRegisterName(Reg);
384       return false;
385     }
386 
387     case 'e': // The low doubleword register of a NEON quad register.
388     case 'f': { // The high doubleword register of a NEON quad register.
389       if (!MI->getOperand(OpNum).isReg())
390         return true;
391       unsigned Reg = MI->getOperand(OpNum).getReg();
392       if (!ARM::QPRRegClass.contains(Reg))
393         return true;
394       const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
395       unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
396                                        ARM::dsub_0 : ARM::dsub_1);
397       O << ARMInstPrinter::getRegisterName(SubReg);
398       return false;
399     }
400 
401     // This modifier is not yet supported.
402     case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
403       return true;
404     case 'H': { // The highest-numbered register of a pair.
405       const MachineOperand &MO = MI->getOperand(OpNum);
406       if (!MO.isReg())
407         return true;
408       const MachineFunction &MF = *MI->getParent()->getParent();
409       const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
410       unsigned Reg = MO.getReg();
411       if(!ARM::GPRPairRegClass.contains(Reg))
412         return false;
413       Reg = TRI->getSubReg(Reg, ARM::gsub_1);
414       O << ARMInstPrinter::getRegisterName(Reg);
415       return false;
416     }
417     }
418   }
419 
420   printOperand(MI, OpNum, O);
421   return false;
422 }
423 
424 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
425                                           unsigned OpNum, unsigned AsmVariant,
426                                           const char *ExtraCode,
427                                           raw_ostream &O) {
428   // Does this asm operand have a single letter operand modifier?
429   if (ExtraCode && ExtraCode[0]) {
430     if (ExtraCode[1] != 0) return true; // Unknown modifier.
431 
432     switch (ExtraCode[0]) {
433       case 'A': // A memory operand for a VLD1/VST1 instruction.
434       default: return true;  // Unknown modifier.
435       case 'm': // The base register of a memory operand.
436         if (!MI->getOperand(OpNum).isReg())
437           return true;
438         O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
439         return false;
440     }
441   }
442 
443   const MachineOperand &MO = MI->getOperand(OpNum);
444   assert(MO.isReg() && "unexpected inline asm memory operand");
445   O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
446   return false;
447 }
448 
449 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
450   if (Subtarget->isTargetDarwin()) {
451     Reloc::Model RelocM = TM.getRelocationModel();
452     if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
453       // Declare all the text sections up front (before the DWARF sections
454       // emitted by AsmPrinter::doInitialization) so the assembler will keep
455       // them together at the beginning of the object file.  This helps
456       // avoid out-of-range branches that are due a fundamental limitation of
457       // the way symbol offsets are encoded with the current Darwin ARM
458       // relocations.
459       const TargetLoweringObjectFileMachO &TLOFMacho =
460         static_cast<const TargetLoweringObjectFileMachO &>(
461           getObjFileLowering());
462 
463       // Collect the set of sections our functions will go into.
464       SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
465         SmallPtrSet<const MCSection *, 8> > TextSections;
466       // Default text section comes first.
467       TextSections.insert(TLOFMacho.getTextSection());
468       // Now any user defined text sections from function attributes.
469       for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
470         if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
471           TextSections.insert(TLOFMacho.SectionForGlobal(F, Mang, TM));
472       // Now the coalescable sections.
473       TextSections.insert(TLOFMacho.getTextCoalSection());
474       TextSections.insert(TLOFMacho.getConstTextCoalSection());
475 
476       // Emit the sections in the .s file header to fix the order.
477       for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
478         OutStreamer.SwitchSection(TextSections[i]);
479 
480       if (RelocM == Reloc::DynamicNoPIC) {
481         const MCSection *sect =
482           OutContext.getMachOSection("__TEXT", "__symbol_stub4",
483                                      MCSectionMachO::S_SYMBOL_STUBS,
484                                      12, SectionKind::getText());
485         OutStreamer.SwitchSection(sect);
486       } else {
487         const MCSection *sect =
488           OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
489                                      MCSectionMachO::S_SYMBOL_STUBS,
490                                      16, SectionKind::getText());
491         OutStreamer.SwitchSection(sect);
492       }
493       const MCSection *StaticInitSect =
494         OutContext.getMachOSection("__TEXT", "__StaticInit",
495                                    MCSectionMachO::S_REGULAR |
496                                    MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
497                                    SectionKind::getText());
498       OutStreamer.SwitchSection(StaticInitSect);
499     }
500   }
501 
502   // Use unified assembler syntax.
503   OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
504 
505   // Emit ARM Build Attributes
506   if (Subtarget->isTargetELF())
507     emitAttributes();
508 }
509 
510 
511 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
512   if (Subtarget->isTargetDarwin()) {
513     // All darwin targets use mach-o.
514     const TargetLoweringObjectFileMachO &TLOFMacho =
515       static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
516     MachineModuleInfoMachO &MMIMacho =
517       MMI->getObjFileInfo<MachineModuleInfoMachO>();
518 
519     // Output non-lazy-pointers for external and common global variables.
520     MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
521 
522     if (!Stubs.empty()) {
523       // Switch with ".non_lazy_symbol_pointer" directive.
524       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
525       EmitAlignment(2);
526       for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
527         // L_foo$stub:
528         OutStreamer.EmitLabel(Stubs[i].first);
529         //   .indirect_symbol _foo
530         MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
531         OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
532 
533         if (MCSym.getInt())
534           // External to current translation unit.
535           OutStreamer.EmitIntValue(0, 4/*size*/);
536         else
537           // Internal to current translation unit.
538           //
539           // When we place the LSDA into the TEXT section, the type info
540           // pointers need to be indirect and pc-rel. We accomplish this by
541           // using NLPs; however, sometimes the types are local to the file.
542           // We need to fill in the value for the NLP in those cases.
543           OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
544                                                         OutContext),
545                                 4/*size*/);
546       }
547 
548       Stubs.clear();
549       OutStreamer.AddBlankLine();
550     }
551 
552     Stubs = MMIMacho.GetHiddenGVStubList();
553     if (!Stubs.empty()) {
554       OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
555       EmitAlignment(2);
556       for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
557         // L_foo$stub:
558         OutStreamer.EmitLabel(Stubs[i].first);
559         //   .long _foo
560         OutStreamer.EmitValue(MCSymbolRefExpr::
561                               Create(Stubs[i].second.getPointer(),
562                                      OutContext),
563                               4/*size*/);
564       }
565 
566       Stubs.clear();
567       OutStreamer.AddBlankLine();
568     }
569 
570     // Funny Darwin hack: This flag tells the linker that no global symbols
571     // contain code that falls through to other global symbols (e.g. the obvious
572     // implementation of multiple entry points).  If this doesn't occur, the
573     // linker can safely perform dead code stripping.  Since LLVM never
574     // generates code that does this, it is always safe to set.
575     OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
576   }
577 }
578 
579 //===----------------------------------------------------------------------===//
580 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
581 // FIXME:
582 // The following seem like one-off assembler flags, but they actually need
583 // to appear in the .ARM.attributes section in ELF.
584 // Instead of subclassing the MCELFStreamer, we do the work here.
585 
586 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
587                                             const ARMSubtarget *Subtarget) {
588   if (CPU == "xscale")
589     return ARMBuildAttrs::v5TEJ;
590 
591   if (Subtarget->hasV8Ops())
592     return ARMBuildAttrs::v8;
593   else if (Subtarget->hasV7Ops()) {
594     if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
595       return ARMBuildAttrs::v7E_M;
596     return ARMBuildAttrs::v7;
597   } else if (Subtarget->hasV6T2Ops())
598     return ARMBuildAttrs::v6T2;
599   else if (Subtarget->hasV6MOps())
600     return ARMBuildAttrs::v6S_M;
601   else if (Subtarget->hasV6Ops())
602     return ARMBuildAttrs::v6;
603   else if (Subtarget->hasV5TEOps())
604     return ARMBuildAttrs::v5TE;
605   else if (Subtarget->hasV5TOps())
606     return ARMBuildAttrs::v5T;
607   else if (Subtarget->hasV4TOps())
608     return ARMBuildAttrs::v4T;
609   else
610     return ARMBuildAttrs::v4;
611 }
612 
613 void ARMAsmPrinter::emitAttributes() {
614   MCTargetStreamer &TS = OutStreamer.getTargetStreamer();
615   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
616 
617   ATS.switchVendor("aeabi");
618 
619   std::string CPUString = Subtarget->getCPUString();
620 
621   if (CPUString != "generic")
622     ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
623 
624   ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
625                     getArchForCPU(CPUString, Subtarget));
626 
627   if (Subtarget->isAClass()) {
628     ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
629                       ARMBuildAttrs::ApplicationProfile);
630   } else if (Subtarget->isRClass()) {
631     ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
632                       ARMBuildAttrs::RealTimeProfile);
633   } else if (Subtarget->isMClass()){
634     ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
635                       ARMBuildAttrs::MicroControllerProfile);
636   }
637 
638   ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
639                       ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
640   if (Subtarget->isThumb1Only()) {
641     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
642                       ARMBuildAttrs::Allowed);
643   } else if (Subtarget->hasThumb2()) {
644     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
645                       ARMBuildAttrs::AllowThumb32);
646   }
647 
648   if (Subtarget->hasNEON()) {
649     /* NEON is not exactly a VFP architecture, but GAS emit one of
650      * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
651     if (Subtarget->hasFPARMv8()) {
652       if (Subtarget->hasCrypto())
653         ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
654       else
655         ATS.emitFPU(ARM::NEON_FP_ARMV8);
656     }
657     else if (Subtarget->hasVFP4())
658       ATS.emitFPU(ARM::NEON_VFPV4);
659     else
660       ATS.emitFPU(ARM::NEON);
661     // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
662     if (Subtarget->hasV8Ops())
663       ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
664                         ARMBuildAttrs::AllowNeonARMv8);
665   } else {
666     if (Subtarget->hasFPARMv8())
667       ATS.emitFPU(ARM::FP_ARMV8);
668     else if (Subtarget->hasVFP4())
669       ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
670     else if (Subtarget->hasVFP3())
671       ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
672     else if (Subtarget->hasVFP2())
673       ATS.emitFPU(ARM::VFPV2);
674   }
675 
676   // Signal various FP modes.
677   if (!TM.Options.UnsafeFPMath) {
678     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::Allowed);
679     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
680                       ARMBuildAttrs::Allowed);
681   }
682 
683   if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
684     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
685                       ARMBuildAttrs::Allowed);
686   else
687     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
688                       ARMBuildAttrs::AllowIEE754);
689 
690   // FIXME: add more flags to ARMBuildAttrs.h
691   // 8-bytes alignment stuff.
692   ATS.emitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
693   ATS.emitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
694 
695   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
696   if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
697     ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
698     ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
699   }
700   // FIXME: Should we signal R9 usage?
701 
702   if (Subtarget->hasDivide()) {
703     // Check if hardware divide is only available in thumb2 or ARM as well.
704     ATS.emitAttribute(ARMBuildAttrs::DIV_use,
705       Subtarget->hasDivideInARMMode() ? ARMBuildAttrs::AllowDIVExt :
706                                         ARMBuildAttrs::AllowDIVIfExists);
707   }
708 
709   ATS.finishAttributeSection();
710 }
711 
712 void ARMAsmPrinter::emitARMAttributeSection() {
713   // <format-version>
714   // [ <section-length> "vendor-name"
715   // [ <file-tag> <size> <attribute>*
716   //   | <section-tag> <size> <section-number>* 0 <attribute>*
717   //   | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
718   //   ]+
719   // ]*
720 
721   if (OutStreamer.hasRawTextSupport())
722     return;
723 
724   const ARMElfTargetObjectFile &TLOFELF =
725     static_cast<const ARMElfTargetObjectFile &>
726     (getObjFileLowering());
727 
728   OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
729 
730   // Format version
731   OutStreamer.EmitIntValue(0x41, 1);
732 }
733 
734 //===----------------------------------------------------------------------===//
735 
736 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
737                              unsigned LabelId, MCContext &Ctx) {
738 
739   MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
740                        + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
741   return Label;
742 }
743 
744 static MCSymbolRefExpr::VariantKind
745 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
746   switch (Modifier) {
747   case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
748   case ARMCP::TLSGD:       return MCSymbolRefExpr::VK_ARM_TLSGD;
749   case ARMCP::TPOFF:       return MCSymbolRefExpr::VK_ARM_TPOFF;
750   case ARMCP::GOTTPOFF:    return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
751   case ARMCP::GOT:         return MCSymbolRefExpr::VK_ARM_GOT;
752   case ARMCP::GOTOFF:      return MCSymbolRefExpr::VK_ARM_GOTOFF;
753   }
754   llvm_unreachable("Invalid ARMCPModifier!");
755 }
756 
757 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
758   bool isIndirect = Subtarget->isTargetDarwin() &&
759     Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
760   if (!isIndirect)
761     return Mang->getSymbol(GV);
762 
763   // FIXME: Remove this when Darwin transition to @GOT like syntax.
764   MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
765   MachineModuleInfoMachO &MMIMachO =
766     MMI->getObjFileInfo<MachineModuleInfoMachO>();
767   MachineModuleInfoImpl::StubValueTy &StubSym =
768     GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
769     MMIMachO.getGVStubEntry(MCSym);
770   if (StubSym.getPointer() == 0)
771     StubSym = MachineModuleInfoImpl::
772       StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
773   return MCSym;
774 }
775 
776 void ARMAsmPrinter::
777 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
778   int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
779 
780   ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
781 
782   MCSymbol *MCSym;
783   if (ACPV->isLSDA()) {
784     SmallString<128> Str;
785     raw_svector_ostream OS(Str);
786     OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
787     MCSym = OutContext.GetOrCreateSymbol(OS.str());
788   } else if (ACPV->isBlockAddress()) {
789     const BlockAddress *BA =
790       cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
791     MCSym = GetBlockAddressSymbol(BA);
792   } else if (ACPV->isGlobalValue()) {
793     const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
794     MCSym = GetARMGVSymbol(GV);
795   } else if (ACPV->isMachineBasicBlock()) {
796     const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
797     MCSym = MBB->getSymbol();
798   } else {
799     assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
800     const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
801     MCSym = GetExternalSymbolSymbol(Sym);
802   }
803 
804   // Create an MCSymbol for the reference.
805   const MCExpr *Expr =
806     MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
807                             OutContext);
808 
809   if (ACPV->getPCAdjustment()) {
810     MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
811                                     getFunctionNumber(),
812                                     ACPV->getLabelId(),
813                                     OutContext);
814     const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
815     PCRelExpr =
816       MCBinaryExpr::CreateAdd(PCRelExpr,
817                               MCConstantExpr::Create(ACPV->getPCAdjustment(),
818                                                      OutContext),
819                               OutContext);
820     if (ACPV->mustAddCurrentAddress()) {
821       // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
822       // label, so just emit a local label end reference that instead.
823       MCSymbol *DotSym = OutContext.CreateTempSymbol();
824       OutStreamer.EmitLabel(DotSym);
825       const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
826       PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
827     }
828     Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
829   }
830   OutStreamer.EmitValue(Expr, Size);
831 }
832 
833 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
834   unsigned Opcode = MI->getOpcode();
835   int OpNum = 1;
836   if (Opcode == ARM::BR_JTadd)
837     OpNum = 2;
838   else if (Opcode == ARM::BR_JTm)
839     OpNum = 3;
840 
841   const MachineOperand &MO1 = MI->getOperand(OpNum);
842   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
843   unsigned JTI = MO1.getIndex();
844 
845   // Emit a label for the jump table.
846   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
847   OutStreamer.EmitLabel(JTISymbol);
848 
849   // Mark the jump table as data-in-code.
850   OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
851 
852   // Emit each entry of the table.
853   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
854   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
855   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
856 
857   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
858     MachineBasicBlock *MBB = JTBBs[i];
859     // Construct an MCExpr for the entry. We want a value of the form:
860     // (BasicBlockAddr - TableBeginAddr)
861     //
862     // For example, a table with entries jumping to basic blocks BB0 and BB1
863     // would look like:
864     // LJTI_0_0:
865     //    .word (LBB0 - LJTI_0_0)
866     //    .word (LBB1 - LJTI_0_0)
867     const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
868 
869     if (TM.getRelocationModel() == Reloc::PIC_)
870       Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
871                                                                    OutContext),
872                                      OutContext);
873     // If we're generating a table of Thumb addresses in static relocation
874     // model, we need to add one to keep interworking correctly.
875     else if (AFI->isThumbFunction())
876       Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
877                                      OutContext);
878     OutStreamer.EmitValue(Expr, 4);
879   }
880   // Mark the end of jump table data-in-code region.
881   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
882 }
883 
884 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
885   unsigned Opcode = MI->getOpcode();
886   int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
887   const MachineOperand &MO1 = MI->getOperand(OpNum);
888   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
889   unsigned JTI = MO1.getIndex();
890 
891   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
892   OutStreamer.EmitLabel(JTISymbol);
893 
894   // Emit each entry of the table.
895   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
896   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
897   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
898   unsigned OffsetWidth = 4;
899   if (MI->getOpcode() == ARM::t2TBB_JT) {
900     OffsetWidth = 1;
901     // Mark the jump table as data-in-code.
902     OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
903   } else if (MI->getOpcode() == ARM::t2TBH_JT) {
904     OffsetWidth = 2;
905     // Mark the jump table as data-in-code.
906     OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
907   }
908 
909   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
910     MachineBasicBlock *MBB = JTBBs[i];
911     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
912                                                       OutContext);
913     // If this isn't a TBB or TBH, the entries are direct branch instructions.
914     if (OffsetWidth == 4) {
915       OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B)
916         .addExpr(MBBSymbolExpr)
917         .addImm(ARMCC::AL)
918         .addReg(0));
919       continue;
920     }
921     // Otherwise it's an offset from the dispatch instruction. Construct an
922     // MCExpr for the entry. We want a value of the form:
923     // (BasicBlockAddr - TableBeginAddr) / 2
924     //
925     // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
926     // would look like:
927     // LJTI_0_0:
928     //    .byte (LBB0 - LJTI_0_0) / 2
929     //    .byte (LBB1 - LJTI_0_0) / 2
930     const MCExpr *Expr =
931       MCBinaryExpr::CreateSub(MBBSymbolExpr,
932                               MCSymbolRefExpr::Create(JTISymbol, OutContext),
933                               OutContext);
934     Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
935                                    OutContext);
936     OutStreamer.EmitValue(Expr, OffsetWidth);
937   }
938   // Mark the end of jump table data-in-code region. 32-bit offsets use
939   // actual branch instructions here, so we don't mark those as a data-region
940   // at all.
941   if (OffsetWidth != 4)
942     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
943 }
944 
945 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
946   assert(MI->getFlag(MachineInstr::FrameSetup) &&
947       "Only instruction which are involved into frame setup code are allowed");
948 
949   MCTargetStreamer &TS = OutStreamer.getTargetStreamer();
950   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
951   const MachineFunction &MF = *MI->getParent()->getParent();
952   const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
953   const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
954 
955   unsigned FramePtr = RegInfo->getFrameRegister(MF);
956   unsigned Opc = MI->getOpcode();
957   unsigned SrcReg, DstReg;
958 
959   if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
960     // Two special cases:
961     // 1) tPUSH does not have src/dst regs.
962     // 2) for Thumb1 code we sometimes materialize the constant via constpool
963     // load. Yes, this is pretty fragile, but for now I don't see better
964     // way... :(
965     SrcReg = DstReg = ARM::SP;
966   } else {
967     SrcReg = MI->getOperand(1).getReg();
968     DstReg = MI->getOperand(0).getReg();
969   }
970 
971   // Try to figure out the unwinding opcode out of src / dst regs.
972   if (MI->mayStore()) {
973     // Register saves.
974     assert(DstReg == ARM::SP &&
975            "Only stack pointer as a destination reg is supported");
976 
977     SmallVector<unsigned, 4> RegList;
978     // Skip src & dst reg, and pred ops.
979     unsigned StartOp = 2 + 2;
980     // Use all the operands.
981     unsigned NumOffset = 0;
982 
983     switch (Opc) {
984     default:
985       MI->dump();
986       llvm_unreachable("Unsupported opcode for unwinding information");
987     case ARM::tPUSH:
988       // Special case here: no src & dst reg, but two extra imp ops.
989       StartOp = 2; NumOffset = 2;
990     case ARM::STMDB_UPD:
991     case ARM::t2STMDB_UPD:
992     case ARM::VSTMDDB_UPD:
993       assert(SrcReg == ARM::SP &&
994              "Only stack pointer as a source reg is supported");
995       for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
996            i != NumOps; ++i) {
997         const MachineOperand &MO = MI->getOperand(i);
998         // Actually, there should never be any impdef stuff here. Skip it
999         // temporary to workaround PR11902.
1000         if (MO.isImplicit())
1001           continue;
1002         RegList.push_back(MO.getReg());
1003       }
1004       break;
1005     case ARM::STR_PRE_IMM:
1006     case ARM::STR_PRE_REG:
1007     case ARM::t2STR_PRE:
1008       assert(MI->getOperand(2).getReg() == ARM::SP &&
1009              "Only stack pointer as a source reg is supported");
1010       RegList.push_back(SrcReg);
1011       break;
1012     }
1013     ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1014   } else {
1015     // Changes of stack / frame pointer.
1016     if (SrcReg == ARM::SP) {
1017       int64_t Offset = 0;
1018       switch (Opc) {
1019       default:
1020         MI->dump();
1021         llvm_unreachable("Unsupported opcode for unwinding information");
1022       case ARM::MOVr:
1023       case ARM::tMOVr:
1024         Offset = 0;
1025         break;
1026       case ARM::ADDri:
1027         Offset = -MI->getOperand(2).getImm();
1028         break;
1029       case ARM::SUBri:
1030       case ARM::t2SUBri:
1031         Offset = MI->getOperand(2).getImm();
1032         break;
1033       case ARM::tSUBspi:
1034         Offset = MI->getOperand(2).getImm()*4;
1035         break;
1036       case ARM::tADDspi:
1037       case ARM::tADDrSPi:
1038         Offset = -MI->getOperand(2).getImm()*4;
1039         break;
1040       case ARM::tLDRpci: {
1041         // Grab the constpool index and check, whether it corresponds to
1042         // original or cloned constpool entry.
1043         unsigned CPI = MI->getOperand(1).getIndex();
1044         const MachineConstantPool *MCP = MF.getConstantPool();
1045         if (CPI >= MCP->getConstants().size())
1046           CPI = AFI.getOriginalCPIdx(CPI);
1047         assert(CPI != -1U && "Invalid constpool index");
1048 
1049         // Derive the actual offset.
1050         const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1051         assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1052         // FIXME: Check for user, it should be "add" instruction!
1053         Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1054         break;
1055       }
1056       }
1057 
1058       if (DstReg == FramePtr && FramePtr != ARM::SP)
1059         // Set-up of the frame pointer. Positive values correspond to "add"
1060         // instruction.
1061         ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1062       else if (DstReg == ARM::SP) {
1063         // Change of SP by an offset. Positive values correspond to "sub"
1064         // instruction.
1065         ATS.emitPad(Offset);
1066       } else {
1067         MI->dump();
1068         llvm_unreachable("Unsupported opcode for unwinding information");
1069       }
1070     } else if (DstReg == ARM::SP) {
1071       // FIXME: .movsp goes here
1072       MI->dump();
1073       llvm_unreachable("Unsupported opcode for unwinding information");
1074     }
1075     else {
1076       MI->dump();
1077       llvm_unreachable("Unsupported opcode for unwinding information");
1078     }
1079   }
1080 }
1081 
1082 extern cl::opt<bool> EnableARMEHABI;
1083 
1084 // Simple pseudo-instructions have their lowering (with expansion to real
1085 // instructions) auto-generated.
1086 #include "ARMGenMCPseudoLowering.inc"
1087 
1088 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1089   // If we just ended a constant pool, mark it as such.
1090   if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1091     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1092     InConstantPool = false;
1093   }
1094 
1095   // Emit unwinding stuff for frame-related instructions
1096   if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1097     EmitUnwindingInstruction(MI);
1098 
1099   // Do any auto-generated pseudo lowerings.
1100   if (emitPseudoExpansionLowering(OutStreamer, MI))
1101     return;
1102 
1103   assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1104          "Pseudo flag setting opcode should be expanded early");
1105 
1106   // Check for manual lowerings.
1107   unsigned Opc = MI->getOpcode();
1108   switch (Opc) {
1109   case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1110   case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1111   case ARM::LEApcrel:
1112   case ARM::tLEApcrel:
1113   case ARM::t2LEApcrel: {
1114     // FIXME: Need to also handle globals and externals
1115     MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1116     OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1117                                               ARM::t2LEApcrel ? ARM::t2ADR
1118                   : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1119                      : ARM::ADR))
1120       .addReg(MI->getOperand(0).getReg())
1121       .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1122       // Add predicate operands.
1123       .addImm(MI->getOperand(2).getImm())
1124       .addReg(MI->getOperand(3).getReg()));
1125     return;
1126   }
1127   case ARM::LEApcrelJT:
1128   case ARM::tLEApcrelJT:
1129   case ARM::t2LEApcrelJT: {
1130     MCSymbol *JTIPICSymbol =
1131       GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1132                                   MI->getOperand(2).getImm());
1133     OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1134                                               ARM::t2LEApcrelJT ? ARM::t2ADR
1135                   : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1136                      : ARM::ADR))
1137       .addReg(MI->getOperand(0).getReg())
1138       .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1139       // Add predicate operands.
1140       .addImm(MI->getOperand(3).getImm())
1141       .addReg(MI->getOperand(4).getReg()));
1142     return;
1143   }
1144   // Darwin call instructions are just normal call instructions with different
1145   // clobber semantics (they clobber R9).
1146   case ARM::BX_CALL: {
1147     OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1148       .addReg(ARM::LR)
1149       .addReg(ARM::PC)
1150       // Add predicate operands.
1151       .addImm(ARMCC::AL)
1152       .addReg(0)
1153       // Add 's' bit operand (always reg0 for this)
1154       .addReg(0));
1155 
1156     OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1157       .addReg(MI->getOperand(0).getReg()));
1158     return;
1159   }
1160   case ARM::tBX_CALL: {
1161     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1162       .addReg(ARM::LR)
1163       .addReg(ARM::PC)
1164       // Add predicate operands.
1165       .addImm(ARMCC::AL)
1166       .addReg(0));
1167 
1168     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1169       .addReg(MI->getOperand(0).getReg())
1170       // Add predicate operands.
1171       .addImm(ARMCC::AL)
1172       .addReg(0));
1173     return;
1174   }
1175   case ARM::BMOVPCRX_CALL: {
1176     OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1177       .addReg(ARM::LR)
1178       .addReg(ARM::PC)
1179       // Add predicate operands.
1180       .addImm(ARMCC::AL)
1181       .addReg(0)
1182       // Add 's' bit operand (always reg0 for this)
1183       .addReg(0));
1184 
1185     OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1186       .addReg(ARM::PC)
1187       .addReg(MI->getOperand(0).getReg())
1188       // Add predicate operands.
1189       .addImm(ARMCC::AL)
1190       .addReg(0)
1191       // Add 's' bit operand (always reg0 for this)
1192       .addReg(0));
1193     return;
1194   }
1195   case ARM::BMOVPCB_CALL: {
1196     OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1197       .addReg(ARM::LR)
1198       .addReg(ARM::PC)
1199       // Add predicate operands.
1200       .addImm(ARMCC::AL)
1201       .addReg(0)
1202       // Add 's' bit operand (always reg0 for this)
1203       .addReg(0));
1204 
1205     const GlobalValue *GV = MI->getOperand(0).getGlobal();
1206     MCSymbol *GVSym = Mang->getSymbol(GV);
1207     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1208     OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc)
1209       .addExpr(GVSymExpr)
1210       // Add predicate operands.
1211       .addImm(ARMCC::AL)
1212       .addReg(0));
1213     return;
1214   }
1215   case ARM::MOVi16_ga_pcrel:
1216   case ARM::t2MOVi16_ga_pcrel: {
1217     MCInst TmpInst;
1218     TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1219     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1220 
1221     unsigned TF = MI->getOperand(1).getTargetFlags();
1222     bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1223     const GlobalValue *GV = MI->getOperand(1).getGlobal();
1224     MCSymbol *GVSym = GetARMGVSymbol(GV);
1225     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1226     if (isPIC) {
1227       MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1228                                        getFunctionNumber(),
1229                                        MI->getOperand(2).getImm(), OutContext);
1230       const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1231       unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1232       const MCExpr *PCRelExpr =
1233         ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1234                                   MCBinaryExpr::CreateAdd(LabelSymExpr,
1235                                       MCConstantExpr::Create(PCAdj, OutContext),
1236                                           OutContext), OutContext), OutContext);
1237       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1238     } else {
1239       const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1240       TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1241     }
1242 
1243     // Add predicate operands.
1244     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1245     TmpInst.addOperand(MCOperand::CreateReg(0));
1246     // Add 's' bit operand (always reg0 for this)
1247     TmpInst.addOperand(MCOperand::CreateReg(0));
1248     OutStreamer.EmitInstruction(TmpInst);
1249     return;
1250   }
1251   case ARM::MOVTi16_ga_pcrel:
1252   case ARM::t2MOVTi16_ga_pcrel: {
1253     MCInst TmpInst;
1254     TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1255                       ? ARM::MOVTi16 : ARM::t2MOVTi16);
1256     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1257     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1258 
1259     unsigned TF = MI->getOperand(2).getTargetFlags();
1260     bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1261     const GlobalValue *GV = MI->getOperand(2).getGlobal();
1262     MCSymbol *GVSym = GetARMGVSymbol(GV);
1263     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1264     if (isPIC) {
1265       MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1266                                        getFunctionNumber(),
1267                                        MI->getOperand(3).getImm(), OutContext);
1268       const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1269       unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1270       const MCExpr *PCRelExpr =
1271         ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1272                                    MCBinaryExpr::CreateAdd(LabelSymExpr,
1273                                       MCConstantExpr::Create(PCAdj, OutContext),
1274                                           OutContext), OutContext), OutContext);
1275       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1276     } else {
1277       const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1278       TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1279     }
1280     // Add predicate operands.
1281     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1282     TmpInst.addOperand(MCOperand::CreateReg(0));
1283     // Add 's' bit operand (always reg0 for this)
1284     TmpInst.addOperand(MCOperand::CreateReg(0));
1285     OutStreamer.EmitInstruction(TmpInst);
1286     return;
1287   }
1288   case ARM::tPICADD: {
1289     // This is a pseudo op for a label + instruction sequence, which looks like:
1290     // LPC0:
1291     //     add r0, pc
1292     // This adds the address of LPC0 to r0.
1293 
1294     // Emit the label.
1295     OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1296                           getFunctionNumber(), MI->getOperand(2).getImm(),
1297                           OutContext));
1298 
1299     // Form and emit the add.
1300     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr)
1301       .addReg(MI->getOperand(0).getReg())
1302       .addReg(MI->getOperand(0).getReg())
1303       .addReg(ARM::PC)
1304       // Add predicate operands.
1305       .addImm(ARMCC::AL)
1306       .addReg(0));
1307     return;
1308   }
1309   case ARM::PICADD: {
1310     // This is a pseudo op for a label + instruction sequence, which looks like:
1311     // LPC0:
1312     //     add r0, pc, r0
1313     // This adds the address of LPC0 to r0.
1314 
1315     // Emit the label.
1316     OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1317                           getFunctionNumber(), MI->getOperand(2).getImm(),
1318                           OutContext));
1319 
1320     // Form and emit the add.
1321     OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1322       .addReg(MI->getOperand(0).getReg())
1323       .addReg(ARM::PC)
1324       .addReg(MI->getOperand(1).getReg())
1325       // Add predicate operands.
1326       .addImm(MI->getOperand(3).getImm())
1327       .addReg(MI->getOperand(4).getReg())
1328       // Add 's' bit operand (always reg0 for this)
1329       .addReg(0));
1330     return;
1331   }
1332   case ARM::PICSTR:
1333   case ARM::PICSTRB:
1334   case ARM::PICSTRH:
1335   case ARM::PICLDR:
1336   case ARM::PICLDRB:
1337   case ARM::PICLDRH:
1338   case ARM::PICLDRSB:
1339   case ARM::PICLDRSH: {
1340     // This is a pseudo op for a label + instruction sequence, which looks like:
1341     // LPC0:
1342     //     OP r0, [pc, r0]
1343     // The LCP0 label is referenced by a constant pool entry in order to get
1344     // a PC-relative address at the ldr instruction.
1345 
1346     // Emit the label.
1347     OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1348                           getFunctionNumber(), MI->getOperand(2).getImm(),
1349                           OutContext));
1350 
1351     // Form and emit the load
1352     unsigned Opcode;
1353     switch (MI->getOpcode()) {
1354     default:
1355       llvm_unreachable("Unexpected opcode!");
1356     case ARM::PICSTR:   Opcode = ARM::STRrs; break;
1357     case ARM::PICSTRB:  Opcode = ARM::STRBrs; break;
1358     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
1359     case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
1360     case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
1361     case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
1362     case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1363     case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1364     }
1365     OutStreamer.EmitInstruction(MCInstBuilder(Opcode)
1366       .addReg(MI->getOperand(0).getReg())
1367       .addReg(ARM::PC)
1368       .addReg(MI->getOperand(1).getReg())
1369       .addImm(0)
1370       // Add predicate operands.
1371       .addImm(MI->getOperand(3).getImm())
1372       .addReg(MI->getOperand(4).getReg()));
1373 
1374     return;
1375   }
1376   case ARM::CONSTPOOL_ENTRY: {
1377     /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1378     /// in the function.  The first operand is the ID# for this instruction, the
1379     /// second is the index into the MachineConstantPool that this is, the third
1380     /// is the size in bytes of this constant pool entry.
1381     /// The required alignment is specified on the basic block holding this MI.
1382     unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1383     unsigned CPIdx   = (unsigned)MI->getOperand(1).getIndex();
1384 
1385     // If this is the first entry of the pool, mark it.
1386     if (!InConstantPool) {
1387       OutStreamer.EmitDataRegion(MCDR_DataRegion);
1388       InConstantPool = true;
1389     }
1390 
1391     OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1392 
1393     const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1394     if (MCPE.isMachineConstantPoolEntry())
1395       EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1396     else
1397       EmitGlobalConstant(MCPE.Val.ConstVal);
1398     return;
1399   }
1400   case ARM::t2BR_JT: {
1401     // Lower and emit the instruction itself, then the jump table following it.
1402     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1403       .addReg(ARM::PC)
1404       .addReg(MI->getOperand(0).getReg())
1405       // Add predicate operands.
1406       .addImm(ARMCC::AL)
1407       .addReg(0));
1408 
1409     // Output the data for the jump table itself
1410     EmitJump2Table(MI);
1411     return;
1412   }
1413   case ARM::t2TBB_JT: {
1414     // Lower and emit the instruction itself, then the jump table following it.
1415     OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB)
1416       .addReg(ARM::PC)
1417       .addReg(MI->getOperand(0).getReg())
1418       // Add predicate operands.
1419       .addImm(ARMCC::AL)
1420       .addReg(0));
1421 
1422     // Output the data for the jump table itself
1423     EmitJump2Table(MI);
1424     // Make sure the next instruction is 2-byte aligned.
1425     EmitAlignment(1);
1426     return;
1427   }
1428   case ARM::t2TBH_JT: {
1429     // Lower and emit the instruction itself, then the jump table following it.
1430     OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH)
1431       .addReg(ARM::PC)
1432       .addReg(MI->getOperand(0).getReg())
1433       // Add predicate operands.
1434       .addImm(ARMCC::AL)
1435       .addReg(0));
1436 
1437     // Output the data for the jump table itself
1438     EmitJump2Table(MI);
1439     return;
1440   }
1441   case ARM::tBR_JTr:
1442   case ARM::BR_JTr: {
1443     // Lower and emit the instruction itself, then the jump table following it.
1444     // mov pc, target
1445     MCInst TmpInst;
1446     unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1447       ARM::MOVr : ARM::tMOVr;
1448     TmpInst.setOpcode(Opc);
1449     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1450     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1451     // Add predicate operands.
1452     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1453     TmpInst.addOperand(MCOperand::CreateReg(0));
1454     // Add 's' bit operand (always reg0 for this)
1455     if (Opc == ARM::MOVr)
1456       TmpInst.addOperand(MCOperand::CreateReg(0));
1457     OutStreamer.EmitInstruction(TmpInst);
1458 
1459     // Make sure the Thumb jump table is 4-byte aligned.
1460     if (Opc == ARM::tMOVr)
1461       EmitAlignment(2);
1462 
1463     // Output the data for the jump table itself
1464     EmitJumpTable(MI);
1465     return;
1466   }
1467   case ARM::BR_JTm: {
1468     // Lower and emit the instruction itself, then the jump table following it.
1469     // ldr pc, target
1470     MCInst TmpInst;
1471     if (MI->getOperand(1).getReg() == 0) {
1472       // literal offset
1473       TmpInst.setOpcode(ARM::LDRi12);
1474       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1475       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1476       TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1477     } else {
1478       TmpInst.setOpcode(ARM::LDRrs);
1479       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1480       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1481       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1482       TmpInst.addOperand(MCOperand::CreateImm(0));
1483     }
1484     // Add predicate operands.
1485     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1486     TmpInst.addOperand(MCOperand::CreateReg(0));
1487     OutStreamer.EmitInstruction(TmpInst);
1488 
1489     // Output the data for the jump table itself
1490     EmitJumpTable(MI);
1491     return;
1492   }
1493   case ARM::BR_JTadd: {
1494     // Lower and emit the instruction itself, then the jump table following it.
1495     // add pc, target, idx
1496     OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1497       .addReg(ARM::PC)
1498       .addReg(MI->getOperand(0).getReg())
1499       .addReg(MI->getOperand(1).getReg())
1500       // Add predicate operands.
1501       .addImm(ARMCC::AL)
1502       .addReg(0)
1503       // Add 's' bit operand (always reg0 for this)
1504       .addReg(0));
1505 
1506     // Output the data for the jump table itself
1507     EmitJumpTable(MI);
1508     return;
1509   }
1510   case ARM::TRAP: {
1511     // Non-Darwin binutils don't yet support the "trap" mnemonic.
1512     // FIXME: Remove this special case when they do.
1513     if (!Subtarget->isTargetDarwin()) {
1514       //.long 0xe7ffdefe @ trap
1515       uint32_t Val = 0xe7ffdefeUL;
1516       OutStreamer.AddComment("trap");
1517       OutStreamer.EmitIntValue(Val, 4);
1518       return;
1519     }
1520     break;
1521   }
1522   case ARM::TRAPNaCl: {
1523     //.long 0xe7fedef0 @ trap
1524     uint32_t Val = 0xe7fedef0UL;
1525     OutStreamer.AddComment("trap");
1526     OutStreamer.EmitIntValue(Val, 4);
1527     return;
1528   }
1529   case ARM::tTRAP: {
1530     // Non-Darwin binutils don't yet support the "trap" mnemonic.
1531     // FIXME: Remove this special case when they do.
1532     if (!Subtarget->isTargetDarwin()) {
1533       //.short 57086 @ trap
1534       uint16_t Val = 0xdefe;
1535       OutStreamer.AddComment("trap");
1536       OutStreamer.EmitIntValue(Val, 2);
1537       return;
1538     }
1539     break;
1540   }
1541   case ARM::t2Int_eh_sjlj_setjmp:
1542   case ARM::t2Int_eh_sjlj_setjmp_nofp:
1543   case ARM::tInt_eh_sjlj_setjmp: {
1544     // Two incoming args: GPR:$src, GPR:$val
1545     // mov $val, pc
1546     // adds $val, #7
1547     // str $val, [$src, #4]
1548     // movs r0, #0
1549     // b 1f
1550     // movs r0, #1
1551     // 1:
1552     unsigned SrcReg = MI->getOperand(0).getReg();
1553     unsigned ValReg = MI->getOperand(1).getReg();
1554     MCSymbol *Label = GetARMSJLJEHLabel();
1555     OutStreamer.AddComment("eh_setjmp begin");
1556     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1557       .addReg(ValReg)
1558       .addReg(ARM::PC)
1559       // Predicate.
1560       .addImm(ARMCC::AL)
1561       .addReg(0));
1562 
1563     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3)
1564       .addReg(ValReg)
1565       // 's' bit operand
1566       .addReg(ARM::CPSR)
1567       .addReg(ValReg)
1568       .addImm(7)
1569       // Predicate.
1570       .addImm(ARMCC::AL)
1571       .addReg(0));
1572 
1573     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi)
1574       .addReg(ValReg)
1575       .addReg(SrcReg)
1576       // The offset immediate is #4. The operand value is scaled by 4 for the
1577       // tSTR instruction.
1578       .addImm(1)
1579       // Predicate.
1580       .addImm(ARMCC::AL)
1581       .addReg(0));
1582 
1583     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1584       .addReg(ARM::R0)
1585       .addReg(ARM::CPSR)
1586       .addImm(0)
1587       // Predicate.
1588       .addImm(ARMCC::AL)
1589       .addReg(0));
1590 
1591     const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1592     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB)
1593       .addExpr(SymbolExpr)
1594       .addImm(ARMCC::AL)
1595       .addReg(0));
1596 
1597     OutStreamer.AddComment("eh_setjmp end");
1598     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1599       .addReg(ARM::R0)
1600       .addReg(ARM::CPSR)
1601       .addImm(1)
1602       // Predicate.
1603       .addImm(ARMCC::AL)
1604       .addReg(0));
1605 
1606     OutStreamer.EmitLabel(Label);
1607     return;
1608   }
1609 
1610   case ARM::Int_eh_sjlj_setjmp_nofp:
1611   case ARM::Int_eh_sjlj_setjmp: {
1612     // Two incoming args: GPR:$src, GPR:$val
1613     // add $val, pc, #8
1614     // str $val, [$src, #+4]
1615     // mov r0, #0
1616     // add pc, pc, #0
1617     // mov r0, #1
1618     unsigned SrcReg = MI->getOperand(0).getReg();
1619     unsigned ValReg = MI->getOperand(1).getReg();
1620 
1621     OutStreamer.AddComment("eh_setjmp begin");
1622     OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1623       .addReg(ValReg)
1624       .addReg(ARM::PC)
1625       .addImm(8)
1626       // Predicate.
1627       .addImm(ARMCC::AL)
1628       .addReg(0)
1629       // 's' bit operand (always reg0 for this).
1630       .addReg(0));
1631 
1632     OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12)
1633       .addReg(ValReg)
1634       .addReg(SrcReg)
1635       .addImm(4)
1636       // Predicate.
1637       .addImm(ARMCC::AL)
1638       .addReg(0));
1639 
1640     OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1641       .addReg(ARM::R0)
1642       .addImm(0)
1643       // Predicate.
1644       .addImm(ARMCC::AL)
1645       .addReg(0)
1646       // 's' bit operand (always reg0 for this).
1647       .addReg(0));
1648 
1649     OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1650       .addReg(ARM::PC)
1651       .addReg(ARM::PC)
1652       .addImm(0)
1653       // Predicate.
1654       .addImm(ARMCC::AL)
1655       .addReg(0)
1656       // 's' bit operand (always reg0 for this).
1657       .addReg(0));
1658 
1659     OutStreamer.AddComment("eh_setjmp end");
1660     OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1661       .addReg(ARM::R0)
1662       .addImm(1)
1663       // Predicate.
1664       .addImm(ARMCC::AL)
1665       .addReg(0)
1666       // 's' bit operand (always reg0 for this).
1667       .addReg(0));
1668     return;
1669   }
1670   case ARM::Int_eh_sjlj_longjmp: {
1671     // ldr sp, [$src, #8]
1672     // ldr $scratch, [$src, #4]
1673     // ldr r7, [$src]
1674     // bx $scratch
1675     unsigned SrcReg = MI->getOperand(0).getReg();
1676     unsigned ScratchReg = MI->getOperand(1).getReg();
1677     OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1678       .addReg(ARM::SP)
1679       .addReg(SrcReg)
1680       .addImm(8)
1681       // Predicate.
1682       .addImm(ARMCC::AL)
1683       .addReg(0));
1684 
1685     OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1686       .addReg(ScratchReg)
1687       .addReg(SrcReg)
1688       .addImm(4)
1689       // Predicate.
1690       .addImm(ARMCC::AL)
1691       .addReg(0));
1692 
1693     OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1694       .addReg(ARM::R7)
1695       .addReg(SrcReg)
1696       .addImm(0)
1697       // Predicate.
1698       .addImm(ARMCC::AL)
1699       .addReg(0));
1700 
1701     OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1702       .addReg(ScratchReg)
1703       // Predicate.
1704       .addImm(ARMCC::AL)
1705       .addReg(0));
1706     return;
1707   }
1708   case ARM::tInt_eh_sjlj_longjmp: {
1709     // ldr $scratch, [$src, #8]
1710     // mov sp, $scratch
1711     // ldr $scratch, [$src, #4]
1712     // ldr r7, [$src]
1713     // bx $scratch
1714     unsigned SrcReg = MI->getOperand(0).getReg();
1715     unsigned ScratchReg = MI->getOperand(1).getReg();
1716     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1717       .addReg(ScratchReg)
1718       .addReg(SrcReg)
1719       // The offset immediate is #8. The operand value is scaled by 4 for the
1720       // tLDR instruction.
1721       .addImm(2)
1722       // Predicate.
1723       .addImm(ARMCC::AL)
1724       .addReg(0));
1725 
1726     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1727       .addReg(ARM::SP)
1728       .addReg(ScratchReg)
1729       // Predicate.
1730       .addImm(ARMCC::AL)
1731       .addReg(0));
1732 
1733     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1734       .addReg(ScratchReg)
1735       .addReg(SrcReg)
1736       .addImm(1)
1737       // Predicate.
1738       .addImm(ARMCC::AL)
1739       .addReg(0));
1740 
1741     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1742       .addReg(ARM::R7)
1743       .addReg(SrcReg)
1744       .addImm(0)
1745       // Predicate.
1746       .addImm(ARMCC::AL)
1747       .addReg(0));
1748 
1749     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1750       .addReg(ScratchReg)
1751       // Predicate.
1752       .addImm(ARMCC::AL)
1753       .addReg(0));
1754     return;
1755   }
1756   }
1757 
1758   MCInst TmpInst;
1759   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1760 
1761   OutStreamer.EmitInstruction(TmpInst);
1762 }
1763 
1764 //===----------------------------------------------------------------------===//
1765 // Target Registry Stuff
1766 //===----------------------------------------------------------------------===//
1767 
1768 // Force static initialization.
1769 extern "C" void LLVMInitializeARMAsmPrinter() {
1770   RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1771   RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1772 }
1773