1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
17 #include "ARM.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMFPUName.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMTargetMachine.h"
23 #include "ARMTargetObjectFile.h"
24 #include "InstPrinter/ARMInstPrinter.h"
25 #include "MCTargetDesc/ARMAddressingModes.h"
26 #include "MCTargetDesc/ARMMCExpr.h"
27 #include "llvm/ADT/SetVector.h"
28 #include "llvm/ADT/SmallString.h"
29 #include "llvm/Assembly/Writer.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/DebugInfo.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DataLayout.h"
36 #include "llvm/IR/Module.h"
37 #include "llvm/IR/Type.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCAssembler.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCELFStreamer.h"
42 #include "llvm/MC/MCInst.h"
43 #include "llvm/MC/MCInstBuilder.h"
44 #include "llvm/MC/MCObjectStreamer.h"
45 #include "llvm/MC/MCSectionMachO.h"
46 #include "llvm/MC/MCStreamer.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/TargetRegistry.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/Mangler.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include <cctype>
57 using namespace llvm;
58 
59 /// EmitDwarfRegOp - Emit dwarf register operation.
60 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
61                                    bool Indirect) const {
62   const TargetRegisterInfo *RI = TM.getRegisterInfo();
63   if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) {
64     AsmPrinter::EmitDwarfRegOp(MLoc, Indirect);
65     return;
66   }
67   assert(MLoc.isReg() && !Indirect &&
68          "This doesn't support offset/indirection - implement it if needed");
69   unsigned Reg = MLoc.getReg();
70   if (Reg >= ARM::S0 && Reg <= ARM::S31) {
71     assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
72     // S registers are described as bit-pieces of a register
73     // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
74     // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
75 
76     unsigned SReg = Reg - ARM::S0;
77     bool odd = SReg & 0x1;
78     unsigned Rx = 256 + (SReg >> 1);
79 
80     OutStreamer.AddComment("DW_OP_regx for S register");
81     EmitInt8(dwarf::DW_OP_regx);
82 
83     OutStreamer.AddComment(Twine(SReg));
84     EmitULEB128(Rx);
85 
86     if (odd) {
87       OutStreamer.AddComment("DW_OP_bit_piece 32 32");
88       EmitInt8(dwarf::DW_OP_bit_piece);
89       EmitULEB128(32);
90       EmitULEB128(32);
91     } else {
92       OutStreamer.AddComment("DW_OP_bit_piece 32 0");
93       EmitInt8(dwarf::DW_OP_bit_piece);
94       EmitULEB128(32);
95       EmitULEB128(0);
96     }
97   } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
98     assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
99     // Q registers Q0-Q15 are described by composing two D registers together.
100     // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
101     // DW_OP_piece(8)
102 
103     unsigned QReg = Reg - ARM::Q0;
104     unsigned D1 = 256 + 2 * QReg;
105     unsigned D2 = D1 + 1;
106 
107     OutStreamer.AddComment("DW_OP_regx for Q register: D1");
108     EmitInt8(dwarf::DW_OP_regx);
109     EmitULEB128(D1);
110     OutStreamer.AddComment("DW_OP_piece 8");
111     EmitInt8(dwarf::DW_OP_piece);
112     EmitULEB128(8);
113 
114     OutStreamer.AddComment("DW_OP_regx for Q register: D2");
115     EmitInt8(dwarf::DW_OP_regx);
116     EmitULEB128(D2);
117     OutStreamer.AddComment("DW_OP_piece 8");
118     EmitInt8(dwarf::DW_OP_piece);
119     EmitULEB128(8);
120   }
121 }
122 
123 void ARMAsmPrinter::EmitFunctionBodyEnd() {
124   // Make sure to terminate any constant pools that were at the end
125   // of the function.
126   if (!InConstantPool)
127     return;
128   InConstantPool = false;
129   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
130 }
131 
132 void ARMAsmPrinter::EmitFunctionEntryLabel() {
133   if (AFI->isThumbFunction()) {
134     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
135     OutStreamer.EmitThumbFunc(CurrentFnSym);
136   }
137 
138   OutStreamer.EmitLabel(CurrentFnSym);
139 }
140 
141 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
142   uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
143   assert(Size && "C++ constructor pointer had zero size!");
144 
145   const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
146   assert(GV && "C++ constructor pointer was not a GlobalValue!");
147 
148   const MCExpr *E = MCSymbolRefExpr::Create(getSymbol(GV),
149                                             (Subtarget->isTargetDarwin()
150                                              ? MCSymbolRefExpr::VK_None
151                                              : MCSymbolRefExpr::VK_ARM_TARGET1),
152                                             OutContext);
153 
154   OutStreamer.EmitValue(E, Size);
155 }
156 
157 /// runOnMachineFunction - This uses the EmitInstruction()
158 /// method to print assembly for each instruction.
159 ///
160 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
161   AFI = MF.getInfo<ARMFunctionInfo>();
162   MCP = MF.getConstantPool();
163 
164   return AsmPrinter::runOnMachineFunction(MF);
165 }
166 
167 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
168                                  raw_ostream &O, const char *Modifier) {
169   const MachineOperand &MO = MI->getOperand(OpNum);
170   unsigned TF = MO.getTargetFlags();
171 
172   switch (MO.getType()) {
173   default: llvm_unreachable("<unknown operand type>");
174   case MachineOperand::MO_Register: {
175     unsigned Reg = MO.getReg();
176     assert(TargetRegisterInfo::isPhysicalRegister(Reg));
177     assert(!MO.getSubReg() && "Subregs should be eliminated!");
178     if(ARM::GPRPairRegClass.contains(Reg)) {
179       const MachineFunction &MF = *MI->getParent()->getParent();
180       const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
181       Reg = TRI->getSubReg(Reg, ARM::gsub_0);
182     }
183     O << ARMInstPrinter::getRegisterName(Reg);
184     break;
185   }
186   case MachineOperand::MO_Immediate: {
187     int64_t Imm = MO.getImm();
188     O << '#';
189     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
190         (TF == ARMII::MO_LO16))
191       O << ":lower16:";
192     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
193              (TF == ARMII::MO_HI16))
194       O << ":upper16:";
195     O << Imm;
196     break;
197   }
198   case MachineOperand::MO_MachineBasicBlock:
199     O << *MO.getMBB()->getSymbol();
200     return;
201   case MachineOperand::MO_GlobalAddress: {
202     const GlobalValue *GV = MO.getGlobal();
203     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
204         (TF & ARMII::MO_LO16))
205       O << ":lower16:";
206     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
207              (TF & ARMII::MO_HI16))
208       O << ":upper16:";
209     O << *getSymbol(GV);
210 
211     printOffset(MO.getOffset(), O);
212     if (TF == ARMII::MO_PLT)
213       O << "(PLT)";
214     break;
215   }
216   case MachineOperand::MO_ExternalSymbol: {
217     O << *GetExternalSymbolSymbol(MO.getSymbolName());
218     if (TF == ARMII::MO_PLT)
219       O << "(PLT)";
220     break;
221   }
222   case MachineOperand::MO_ConstantPoolIndex:
223     O << *GetCPISymbol(MO.getIndex());
224     break;
225   case MachineOperand::MO_JumpTableIndex:
226     O << *GetJTISymbol(MO.getIndex());
227     break;
228   }
229 }
230 
231 //===--------------------------------------------------------------------===//
232 
233 MCSymbol *ARMAsmPrinter::
234 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
235   SmallString<60> Name;
236   raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
237     << getFunctionNumber() << '_' << uid << '_' << uid2;
238   return OutContext.GetOrCreateSymbol(Name.str());
239 }
240 
241 
242 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
243   SmallString<60> Name;
244   raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
245     << getFunctionNumber();
246   return OutContext.GetOrCreateSymbol(Name.str());
247 }
248 
249 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
250                                     unsigned AsmVariant, const char *ExtraCode,
251                                     raw_ostream &O) {
252   // Does this asm operand have a single letter operand modifier?
253   if (ExtraCode && ExtraCode[0]) {
254     if (ExtraCode[1] != 0) return true; // Unknown modifier.
255 
256     switch (ExtraCode[0]) {
257     default:
258       // See if this is a generic print operand
259       return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
260     case 'a': // Print as a memory address.
261       if (MI->getOperand(OpNum).isReg()) {
262         O << "["
263           << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
264           << "]";
265         return false;
266       }
267       // Fallthrough
268     case 'c': // Don't print "#" before an immediate operand.
269       if (!MI->getOperand(OpNum).isImm())
270         return true;
271       O << MI->getOperand(OpNum).getImm();
272       return false;
273     case 'P': // Print a VFP double precision register.
274     case 'q': // Print a NEON quad precision register.
275       printOperand(MI, OpNum, O);
276       return false;
277     case 'y': // Print a VFP single precision register as indexed double.
278       if (MI->getOperand(OpNum).isReg()) {
279         unsigned Reg = MI->getOperand(OpNum).getReg();
280         const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
281         // Find the 'd' register that has this 's' register as a sub-register,
282         // and determine the lane number.
283         for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
284           if (!ARM::DPRRegClass.contains(*SR))
285             continue;
286           bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
287           O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
288           return false;
289         }
290       }
291       return true;
292     case 'B': // Bitwise inverse of integer or symbol without a preceding #.
293       if (!MI->getOperand(OpNum).isImm())
294         return true;
295       O << ~(MI->getOperand(OpNum).getImm());
296       return false;
297     case 'L': // The low 16 bits of an immediate constant.
298       if (!MI->getOperand(OpNum).isImm())
299         return true;
300       O << (MI->getOperand(OpNum).getImm() & 0xffff);
301       return false;
302     case 'M': { // A register range suitable for LDM/STM.
303       if (!MI->getOperand(OpNum).isReg())
304         return true;
305       const MachineOperand &MO = MI->getOperand(OpNum);
306       unsigned RegBegin = MO.getReg();
307       // This takes advantage of the 2 operand-ness of ldm/stm and that we've
308       // already got the operands in registers that are operands to the
309       // inline asm statement.
310       O << "{";
311       if (ARM::GPRPairRegClass.contains(RegBegin)) {
312         const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
313         unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
314         O << ARMInstPrinter::getRegisterName(Reg0) << ", ";;
315         RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
316       }
317       O << ARMInstPrinter::getRegisterName(RegBegin);
318 
319       // FIXME: The register allocator not only may not have given us the
320       // registers in sequence, but may not be in ascending registers. This
321       // will require changes in the register allocator that'll need to be
322       // propagated down here if the operands change.
323       unsigned RegOps = OpNum + 1;
324       while (MI->getOperand(RegOps).isReg()) {
325         O << ", "
326           << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
327         RegOps++;
328       }
329 
330       O << "}";
331 
332       return false;
333     }
334     case 'R': // The most significant register of a pair.
335     case 'Q': { // The least significant register of a pair.
336       if (OpNum == 0)
337         return true;
338       const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
339       if (!FlagsOP.isImm())
340         return true;
341       unsigned Flags = FlagsOP.getImm();
342 
343       // This operand may not be the one that actually provides the register. If
344       // it's tied to a previous one then we should refer instead to that one
345       // for registers and their classes.
346       unsigned TiedIdx;
347       if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
348         for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
349           unsigned OpFlags = MI->getOperand(OpNum).getImm();
350           OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
351         }
352         Flags = MI->getOperand(OpNum).getImm();
353 
354         // Later code expects OpNum to be pointing at the register rather than
355         // the flags.
356         OpNum += 1;
357       }
358 
359       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
360       unsigned RC;
361       InlineAsm::hasRegClassConstraint(Flags, RC);
362       if (RC == ARM::GPRPairRegClassID) {
363         if (NumVals != 1)
364           return true;
365         const MachineOperand &MO = MI->getOperand(OpNum);
366         if (!MO.isReg())
367           return true;
368         const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
369         unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
370             ARM::gsub_0 : ARM::gsub_1);
371         O << ARMInstPrinter::getRegisterName(Reg);
372         return false;
373       }
374       if (NumVals != 2)
375         return true;
376       unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
377       if (RegOp >= MI->getNumOperands())
378         return true;
379       const MachineOperand &MO = MI->getOperand(RegOp);
380       if (!MO.isReg())
381         return true;
382       unsigned Reg = MO.getReg();
383       O << ARMInstPrinter::getRegisterName(Reg);
384       return false;
385     }
386 
387     case 'e': // The low doubleword register of a NEON quad register.
388     case 'f': { // The high doubleword register of a NEON quad register.
389       if (!MI->getOperand(OpNum).isReg())
390         return true;
391       unsigned Reg = MI->getOperand(OpNum).getReg();
392       if (!ARM::QPRRegClass.contains(Reg))
393         return true;
394       const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
395       unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
396                                        ARM::dsub_0 : ARM::dsub_1);
397       O << ARMInstPrinter::getRegisterName(SubReg);
398       return false;
399     }
400 
401     // This modifier is not yet supported.
402     case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
403       return true;
404     case 'H': { // The highest-numbered register of a pair.
405       const MachineOperand &MO = MI->getOperand(OpNum);
406       if (!MO.isReg())
407         return true;
408       const MachineFunction &MF = *MI->getParent()->getParent();
409       const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
410       unsigned Reg = MO.getReg();
411       if(!ARM::GPRPairRegClass.contains(Reg))
412         return false;
413       Reg = TRI->getSubReg(Reg, ARM::gsub_1);
414       O << ARMInstPrinter::getRegisterName(Reg);
415       return false;
416     }
417     }
418   }
419 
420   printOperand(MI, OpNum, O);
421   return false;
422 }
423 
424 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
425                                           unsigned OpNum, unsigned AsmVariant,
426                                           const char *ExtraCode,
427                                           raw_ostream &O) {
428   // Does this asm operand have a single letter operand modifier?
429   if (ExtraCode && ExtraCode[0]) {
430     if (ExtraCode[1] != 0) return true; // Unknown modifier.
431 
432     switch (ExtraCode[0]) {
433       case 'A': // A memory operand for a VLD1/VST1 instruction.
434       default: return true;  // Unknown modifier.
435       case 'm': // The base register of a memory operand.
436         if (!MI->getOperand(OpNum).isReg())
437           return true;
438         O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
439         return false;
440     }
441   }
442 
443   const MachineOperand &MO = MI->getOperand(OpNum);
444   assert(MO.isReg() && "unexpected inline asm memory operand");
445   O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
446   return false;
447 }
448 
449 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
450   if (Subtarget->isTargetDarwin()) {
451     Reloc::Model RelocM = TM.getRelocationModel();
452     if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
453       // Declare all the text sections up front (before the DWARF sections
454       // emitted by AsmPrinter::doInitialization) so the assembler will keep
455       // them together at the beginning of the object file.  This helps
456       // avoid out-of-range branches that are due a fundamental limitation of
457       // the way symbol offsets are encoded with the current Darwin ARM
458       // relocations.
459       const TargetLoweringObjectFileMachO &TLOFMacho =
460         static_cast<const TargetLoweringObjectFileMachO &>(
461           getObjFileLowering());
462 
463       // Collect the set of sections our functions will go into.
464       SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
465         SmallPtrSet<const MCSection *, 8> > TextSections;
466       // Default text section comes first.
467       TextSections.insert(TLOFMacho.getTextSection());
468       // Now any user defined text sections from function attributes.
469       for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
470         if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
471           TextSections.insert(TLOFMacho.SectionForGlobal(F, Mang, TM));
472       // Now the coalescable sections.
473       TextSections.insert(TLOFMacho.getTextCoalSection());
474       TextSections.insert(TLOFMacho.getConstTextCoalSection());
475 
476       // Emit the sections in the .s file header to fix the order.
477       for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
478         OutStreamer.SwitchSection(TextSections[i]);
479 
480       if (RelocM == Reloc::DynamicNoPIC) {
481         const MCSection *sect =
482           OutContext.getMachOSection("__TEXT", "__symbol_stub4",
483                                      MCSectionMachO::S_SYMBOL_STUBS,
484                                      12, SectionKind::getText());
485         OutStreamer.SwitchSection(sect);
486       } else {
487         const MCSection *sect =
488           OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
489                                      MCSectionMachO::S_SYMBOL_STUBS,
490                                      16, SectionKind::getText());
491         OutStreamer.SwitchSection(sect);
492       }
493       const MCSection *StaticInitSect =
494         OutContext.getMachOSection("__TEXT", "__StaticInit",
495                                    MCSectionMachO::S_REGULAR |
496                                    MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
497                                    SectionKind::getText());
498       OutStreamer.SwitchSection(StaticInitSect);
499     }
500   }
501 
502   // Use unified assembler syntax.
503   OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
504 
505   // Emit ARM Build Attributes
506   if (Subtarget->isTargetELF())
507     emitAttributes();
508 }
509 
510 
511 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
512   if (Subtarget->isTargetDarwin()) {
513     // All darwin targets use mach-o.
514     const TargetLoweringObjectFileMachO &TLOFMacho =
515       static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
516     MachineModuleInfoMachO &MMIMacho =
517       MMI->getObjFileInfo<MachineModuleInfoMachO>();
518 
519     // Output non-lazy-pointers for external and common global variables.
520     MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
521 
522     if (!Stubs.empty()) {
523       // Switch with ".non_lazy_symbol_pointer" directive.
524       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
525       EmitAlignment(2);
526       for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
527         // L_foo$stub:
528         OutStreamer.EmitLabel(Stubs[i].first);
529         //   .indirect_symbol _foo
530         MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
531         OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
532 
533         if (MCSym.getInt())
534           // External to current translation unit.
535           OutStreamer.EmitIntValue(0, 4/*size*/);
536         else
537           // Internal to current translation unit.
538           //
539           // When we place the LSDA into the TEXT section, the type info
540           // pointers need to be indirect and pc-rel. We accomplish this by
541           // using NLPs; however, sometimes the types are local to the file.
542           // We need to fill in the value for the NLP in those cases.
543           OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
544                                                         OutContext),
545                                 4/*size*/);
546       }
547 
548       Stubs.clear();
549       OutStreamer.AddBlankLine();
550     }
551 
552     Stubs = MMIMacho.GetHiddenGVStubList();
553     if (!Stubs.empty()) {
554       OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
555       EmitAlignment(2);
556       for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
557         // L_foo$stub:
558         OutStreamer.EmitLabel(Stubs[i].first);
559         //   .long _foo
560         OutStreamer.EmitValue(MCSymbolRefExpr::
561                               Create(Stubs[i].second.getPointer(),
562                                      OutContext),
563                               4/*size*/);
564       }
565 
566       Stubs.clear();
567       OutStreamer.AddBlankLine();
568     }
569 
570     // Funny Darwin hack: This flag tells the linker that no global symbols
571     // contain code that falls through to other global symbols (e.g. the obvious
572     // implementation of multiple entry points).  If this doesn't occur, the
573     // linker can safely perform dead code stripping.  Since LLVM never
574     // generates code that does this, it is always safe to set.
575     OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
576   }
577 }
578 
579 //===----------------------------------------------------------------------===//
580 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
581 // FIXME:
582 // The following seem like one-off assembler flags, but they actually need
583 // to appear in the .ARM.attributes section in ELF.
584 // Instead of subclassing the MCELFStreamer, we do the work here.
585 
586 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
587                                             const ARMSubtarget *Subtarget) {
588   if (CPU == "xscale")
589     return ARMBuildAttrs::v5TEJ;
590 
591   if (Subtarget->hasV8Ops())
592     return ARMBuildAttrs::v8;
593   else if (Subtarget->hasV7Ops()) {
594     if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
595       return ARMBuildAttrs::v7E_M;
596     return ARMBuildAttrs::v7;
597   } else if (Subtarget->hasV6T2Ops())
598     return ARMBuildAttrs::v6T2;
599   else if (Subtarget->hasV6MOps())
600     return ARMBuildAttrs::v6S_M;
601   else if (Subtarget->hasV6Ops())
602     return ARMBuildAttrs::v6;
603   else if (Subtarget->hasV5TEOps())
604     return ARMBuildAttrs::v5TE;
605   else if (Subtarget->hasV5TOps())
606     return ARMBuildAttrs::v5T;
607   else if (Subtarget->hasV4TOps())
608     return ARMBuildAttrs::v4T;
609   else
610     return ARMBuildAttrs::v4;
611 }
612 
613 void ARMAsmPrinter::emitAttributes() {
614   MCTargetStreamer &TS = OutStreamer.getTargetStreamer();
615   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
616 
617   ATS.switchVendor("aeabi");
618 
619   std::string CPUString = Subtarget->getCPUString();
620 
621   if (CPUString != "generic")
622     ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
623 
624   ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
625                     getArchForCPU(CPUString, Subtarget));
626 
627   if (Subtarget->isAClass()) {
628     ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
629                       ARMBuildAttrs::ApplicationProfile);
630   } else if (Subtarget->isRClass()) {
631     ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
632                       ARMBuildAttrs::RealTimeProfile);
633   } else if (Subtarget->isMClass()){
634     ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
635                       ARMBuildAttrs::MicroControllerProfile);
636   }
637 
638   ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
639                       ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
640   if (Subtarget->isThumb1Only()) {
641     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
642                       ARMBuildAttrs::Allowed);
643   } else if (Subtarget->hasThumb2()) {
644     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
645                       ARMBuildAttrs::AllowThumb32);
646   }
647 
648   if (Subtarget->hasNEON()) {
649     /* NEON is not exactly a VFP architecture, but GAS emit one of
650      * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
651     if (Subtarget->hasFPARMv8()) {
652       if (Subtarget->hasCrypto())
653         ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
654       else
655         ATS.emitFPU(ARM::NEON_FP_ARMV8);
656     }
657     else if (Subtarget->hasVFP4())
658       ATS.emitFPU(ARM::NEON_VFPV4);
659     else
660       ATS.emitFPU(ARM::NEON);
661     // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
662     if (Subtarget->hasV8Ops())
663       ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
664                         ARMBuildAttrs::AllowNeonARMv8);
665   } else {
666     if (Subtarget->hasFPARMv8())
667       ATS.emitFPU(ARM::FP_ARMV8);
668     else if (Subtarget->hasVFP4())
669       ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
670     else if (Subtarget->hasVFP3())
671       ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
672     else if (Subtarget->hasVFP2())
673       ATS.emitFPU(ARM::VFPV2);
674   }
675 
676   // Signal various FP modes.
677   if (!TM.Options.UnsafeFPMath) {
678     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::Allowed);
679     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
680                       ARMBuildAttrs::Allowed);
681   }
682 
683   if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
684     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
685                       ARMBuildAttrs::Allowed);
686   else
687     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
688                       ARMBuildAttrs::AllowIEE754);
689 
690   // FIXME: add more flags to ARMBuildAttrs.h
691   // 8-bytes alignment stuff.
692   ATS.emitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
693   ATS.emitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
694 
695   // ABI_HardFP_use attribute to indicate single precision FP.
696   if (Subtarget->isFPOnlySP())
697     ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
698                       ARMBuildAttrs::HardFPSinglePrecision);
699 
700   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
701   if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
702     ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
703 
704   // FIXME: Should we signal R9 usage?
705 
706   if (Subtarget->hasFP16())
707       ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
708 
709   if (Subtarget->hasMPExtension())
710       ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
711 
712   if (Subtarget->hasDivide()) {
713     // Check if hardware divide is only available in thumb2 or ARM as well.
714     ATS.emitAttribute(ARMBuildAttrs::DIV_use,
715       Subtarget->hasDivideInARMMode() ? ARMBuildAttrs::AllowDIVExt :
716                                         ARMBuildAttrs::AllowDIVIfExists);
717   }
718 
719   if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
720       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
721                         ARMBuildAttrs::AllowTZVirtualization);
722   else if (Subtarget->hasTrustZone())
723       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
724                         ARMBuildAttrs::AllowTZ);
725   else if (Subtarget->hasVirtualization())
726       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
727                         ARMBuildAttrs::AllowVirtualization);
728 
729   ATS.finishAttributeSection();
730 }
731 
732 void ARMAsmPrinter::emitARMAttributeSection() {
733   // <format-version>
734   // [ <section-length> "vendor-name"
735   // [ <file-tag> <size> <attribute>*
736   //   | <section-tag> <size> <section-number>* 0 <attribute>*
737   //   | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
738   //   ]+
739   // ]*
740 
741   if (OutStreamer.hasRawTextSupport())
742     return;
743 
744   const ARMElfTargetObjectFile &TLOFELF =
745     static_cast<const ARMElfTargetObjectFile &>
746     (getObjFileLowering());
747 
748   OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
749 
750   // Format version
751   OutStreamer.EmitIntValue(0x41, 1);
752 }
753 
754 //===----------------------------------------------------------------------===//
755 
756 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
757                              unsigned LabelId, MCContext &Ctx) {
758 
759   MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
760                        + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
761   return Label;
762 }
763 
764 static MCSymbolRefExpr::VariantKind
765 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
766   switch (Modifier) {
767   case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
768   case ARMCP::TLSGD:       return MCSymbolRefExpr::VK_ARM_TLSGD;
769   case ARMCP::TPOFF:       return MCSymbolRefExpr::VK_ARM_TPOFF;
770   case ARMCP::GOTTPOFF:    return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
771   case ARMCP::GOT:         return MCSymbolRefExpr::VK_ARM_GOT;
772   case ARMCP::GOTOFF:      return MCSymbolRefExpr::VK_ARM_GOTOFF;
773   }
774   llvm_unreachable("Invalid ARMCPModifier!");
775 }
776 
777 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
778                                         unsigned char TargetFlags) {
779   bool isIndirect = Subtarget->isTargetDarwin() &&
780     (TargetFlags & ARMII::MO_NONLAZY) &&
781     Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
782   if (!isIndirect)
783     return getSymbol(GV);
784 
785   // FIXME: Remove this when Darwin transition to @GOT like syntax.
786   MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
787   MachineModuleInfoMachO &MMIMachO =
788     MMI->getObjFileInfo<MachineModuleInfoMachO>();
789   MachineModuleInfoImpl::StubValueTy &StubSym =
790     GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
791     MMIMachO.getGVStubEntry(MCSym);
792   if (StubSym.getPointer() == 0)
793     StubSym = MachineModuleInfoImpl::
794       StubValueTy(getSymbol(GV), !GV->hasInternalLinkage());
795   return MCSym;
796 }
797 
798 void ARMAsmPrinter::
799 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
800   int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
801 
802   ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
803 
804   MCSymbol *MCSym;
805   if (ACPV->isLSDA()) {
806     SmallString<128> Str;
807     raw_svector_ostream OS(Str);
808     OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
809     MCSym = OutContext.GetOrCreateSymbol(OS.str());
810   } else if (ACPV->isBlockAddress()) {
811     const BlockAddress *BA =
812       cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
813     MCSym = GetBlockAddressSymbol(BA);
814   } else if (ACPV->isGlobalValue()) {
815     const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
816 
817     // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
818     // flag the global as MO_NONLAZY.
819     unsigned char TF = Subtarget->isTargetDarwin() ? ARMII::MO_NONLAZY : 0;
820     MCSym = GetARMGVSymbol(GV, TF);
821   } else if (ACPV->isMachineBasicBlock()) {
822     const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
823     MCSym = MBB->getSymbol();
824   } else {
825     assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
826     const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
827     MCSym = GetExternalSymbolSymbol(Sym);
828   }
829 
830   // Create an MCSymbol for the reference.
831   const MCExpr *Expr =
832     MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
833                             OutContext);
834 
835   if (ACPV->getPCAdjustment()) {
836     MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
837                                     getFunctionNumber(),
838                                     ACPV->getLabelId(),
839                                     OutContext);
840     const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
841     PCRelExpr =
842       MCBinaryExpr::CreateAdd(PCRelExpr,
843                               MCConstantExpr::Create(ACPV->getPCAdjustment(),
844                                                      OutContext),
845                               OutContext);
846     if (ACPV->mustAddCurrentAddress()) {
847       // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
848       // label, so just emit a local label end reference that instead.
849       MCSymbol *DotSym = OutContext.CreateTempSymbol();
850       OutStreamer.EmitLabel(DotSym);
851       const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
852       PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
853     }
854     Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
855   }
856   OutStreamer.EmitValue(Expr, Size);
857 }
858 
859 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
860   unsigned Opcode = MI->getOpcode();
861   int OpNum = 1;
862   if (Opcode == ARM::BR_JTadd)
863     OpNum = 2;
864   else if (Opcode == ARM::BR_JTm)
865     OpNum = 3;
866 
867   const MachineOperand &MO1 = MI->getOperand(OpNum);
868   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
869   unsigned JTI = MO1.getIndex();
870 
871   // Emit a label for the jump table.
872   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
873   OutStreamer.EmitLabel(JTISymbol);
874 
875   // Mark the jump table as data-in-code.
876   OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
877 
878   // Emit each entry of the table.
879   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
880   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
881   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
882 
883   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
884     MachineBasicBlock *MBB = JTBBs[i];
885     // Construct an MCExpr for the entry. We want a value of the form:
886     // (BasicBlockAddr - TableBeginAddr)
887     //
888     // For example, a table with entries jumping to basic blocks BB0 and BB1
889     // would look like:
890     // LJTI_0_0:
891     //    .word (LBB0 - LJTI_0_0)
892     //    .word (LBB1 - LJTI_0_0)
893     const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
894 
895     if (TM.getRelocationModel() == Reloc::PIC_)
896       Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
897                                                                    OutContext),
898                                      OutContext);
899     // If we're generating a table of Thumb addresses in static relocation
900     // model, we need to add one to keep interworking correctly.
901     else if (AFI->isThumbFunction())
902       Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
903                                      OutContext);
904     OutStreamer.EmitValue(Expr, 4);
905   }
906   // Mark the end of jump table data-in-code region.
907   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
908 }
909 
910 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
911   unsigned Opcode = MI->getOpcode();
912   int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
913   const MachineOperand &MO1 = MI->getOperand(OpNum);
914   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
915   unsigned JTI = MO1.getIndex();
916 
917   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
918   OutStreamer.EmitLabel(JTISymbol);
919 
920   // Emit each entry of the table.
921   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
922   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
923   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
924   unsigned OffsetWidth = 4;
925   if (MI->getOpcode() == ARM::t2TBB_JT) {
926     OffsetWidth = 1;
927     // Mark the jump table as data-in-code.
928     OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
929   } else if (MI->getOpcode() == ARM::t2TBH_JT) {
930     OffsetWidth = 2;
931     // Mark the jump table as data-in-code.
932     OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
933   }
934 
935   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
936     MachineBasicBlock *MBB = JTBBs[i];
937     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
938                                                       OutContext);
939     // If this isn't a TBB or TBH, the entries are direct branch instructions.
940     if (OffsetWidth == 4) {
941       OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B)
942         .addExpr(MBBSymbolExpr)
943         .addImm(ARMCC::AL)
944         .addReg(0));
945       continue;
946     }
947     // Otherwise it's an offset from the dispatch instruction. Construct an
948     // MCExpr for the entry. We want a value of the form:
949     // (BasicBlockAddr - TableBeginAddr) / 2
950     //
951     // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
952     // would look like:
953     // LJTI_0_0:
954     //    .byte (LBB0 - LJTI_0_0) / 2
955     //    .byte (LBB1 - LJTI_0_0) / 2
956     const MCExpr *Expr =
957       MCBinaryExpr::CreateSub(MBBSymbolExpr,
958                               MCSymbolRefExpr::Create(JTISymbol, OutContext),
959                               OutContext);
960     Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
961                                    OutContext);
962     OutStreamer.EmitValue(Expr, OffsetWidth);
963   }
964   // Mark the end of jump table data-in-code region. 32-bit offsets use
965   // actual branch instructions here, so we don't mark those as a data-region
966   // at all.
967   if (OffsetWidth != 4)
968     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
969 }
970 
971 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
972   assert(MI->getFlag(MachineInstr::FrameSetup) &&
973       "Only instruction which are involved into frame setup code are allowed");
974 
975   MCTargetStreamer &TS = OutStreamer.getTargetStreamer();
976   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
977   const MachineFunction &MF = *MI->getParent()->getParent();
978   const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
979   const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
980 
981   unsigned FramePtr = RegInfo->getFrameRegister(MF);
982   unsigned Opc = MI->getOpcode();
983   unsigned SrcReg, DstReg;
984 
985   if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
986     // Two special cases:
987     // 1) tPUSH does not have src/dst regs.
988     // 2) for Thumb1 code we sometimes materialize the constant via constpool
989     // load. Yes, this is pretty fragile, but for now I don't see better
990     // way... :(
991     SrcReg = DstReg = ARM::SP;
992   } else {
993     SrcReg = MI->getOperand(1).getReg();
994     DstReg = MI->getOperand(0).getReg();
995   }
996 
997   // Try to figure out the unwinding opcode out of src / dst regs.
998   if (MI->mayStore()) {
999     // Register saves.
1000     assert(DstReg == ARM::SP &&
1001            "Only stack pointer as a destination reg is supported");
1002 
1003     SmallVector<unsigned, 4> RegList;
1004     // Skip src & dst reg, and pred ops.
1005     unsigned StartOp = 2 + 2;
1006     // Use all the operands.
1007     unsigned NumOffset = 0;
1008 
1009     switch (Opc) {
1010     default:
1011       MI->dump();
1012       llvm_unreachable("Unsupported opcode for unwinding information");
1013     case ARM::tPUSH:
1014       // Special case here: no src & dst reg, but two extra imp ops.
1015       StartOp = 2; NumOffset = 2;
1016     case ARM::STMDB_UPD:
1017     case ARM::t2STMDB_UPD:
1018     case ARM::VSTMDDB_UPD:
1019       assert(SrcReg == ARM::SP &&
1020              "Only stack pointer as a source reg is supported");
1021       for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1022            i != NumOps; ++i) {
1023         const MachineOperand &MO = MI->getOperand(i);
1024         // Actually, there should never be any impdef stuff here. Skip it
1025         // temporary to workaround PR11902.
1026         if (MO.isImplicit())
1027           continue;
1028         RegList.push_back(MO.getReg());
1029       }
1030       break;
1031     case ARM::STR_PRE_IMM:
1032     case ARM::STR_PRE_REG:
1033     case ARM::t2STR_PRE:
1034       assert(MI->getOperand(2).getReg() == ARM::SP &&
1035              "Only stack pointer as a source reg is supported");
1036       RegList.push_back(SrcReg);
1037       break;
1038     }
1039     ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1040   } else {
1041     // Changes of stack / frame pointer.
1042     if (SrcReg == ARM::SP) {
1043       int64_t Offset = 0;
1044       switch (Opc) {
1045       default:
1046         MI->dump();
1047         llvm_unreachable("Unsupported opcode for unwinding information");
1048       case ARM::MOVr:
1049       case ARM::tMOVr:
1050         Offset = 0;
1051         break;
1052       case ARM::ADDri:
1053         Offset = -MI->getOperand(2).getImm();
1054         break;
1055       case ARM::SUBri:
1056       case ARM::t2SUBri:
1057         Offset = MI->getOperand(2).getImm();
1058         break;
1059       case ARM::tSUBspi:
1060         Offset = MI->getOperand(2).getImm()*4;
1061         break;
1062       case ARM::tADDspi:
1063       case ARM::tADDrSPi:
1064         Offset = -MI->getOperand(2).getImm()*4;
1065         break;
1066       case ARM::tLDRpci: {
1067         // Grab the constpool index and check, whether it corresponds to
1068         // original or cloned constpool entry.
1069         unsigned CPI = MI->getOperand(1).getIndex();
1070         const MachineConstantPool *MCP = MF.getConstantPool();
1071         if (CPI >= MCP->getConstants().size())
1072           CPI = AFI.getOriginalCPIdx(CPI);
1073         assert(CPI != -1U && "Invalid constpool index");
1074 
1075         // Derive the actual offset.
1076         const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1077         assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1078         // FIXME: Check for user, it should be "add" instruction!
1079         Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1080         break;
1081       }
1082       }
1083 
1084       if (DstReg == FramePtr && FramePtr != ARM::SP)
1085         // Set-up of the frame pointer. Positive values correspond to "add"
1086         // instruction.
1087         ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1088       else if (DstReg == ARM::SP) {
1089         // Change of SP by an offset. Positive values correspond to "sub"
1090         // instruction.
1091         ATS.emitPad(Offset);
1092       } else {
1093         MI->dump();
1094         llvm_unreachable("Unsupported opcode for unwinding information");
1095       }
1096     } else if (DstReg == ARM::SP) {
1097       // FIXME: .movsp goes here
1098       MI->dump();
1099       llvm_unreachable("Unsupported opcode for unwinding information");
1100     }
1101     else {
1102       MI->dump();
1103       llvm_unreachable("Unsupported opcode for unwinding information");
1104     }
1105   }
1106 }
1107 
1108 extern cl::opt<bool> EnableARMEHABI;
1109 
1110 // Simple pseudo-instructions have their lowering (with expansion to real
1111 // instructions) auto-generated.
1112 #include "ARMGenMCPseudoLowering.inc"
1113 
1114 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1115   // If we just ended a constant pool, mark it as such.
1116   if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1117     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1118     InConstantPool = false;
1119   }
1120 
1121   // Emit unwinding stuff for frame-related instructions
1122   if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1123     EmitUnwindingInstruction(MI);
1124 
1125   // Do any auto-generated pseudo lowerings.
1126   if (emitPseudoExpansionLowering(OutStreamer, MI))
1127     return;
1128 
1129   assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1130          "Pseudo flag setting opcode should be expanded early");
1131 
1132   // Check for manual lowerings.
1133   unsigned Opc = MI->getOpcode();
1134   switch (Opc) {
1135   case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1136   case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1137   case ARM::LEApcrel:
1138   case ARM::tLEApcrel:
1139   case ARM::t2LEApcrel: {
1140     // FIXME: Need to also handle globals and externals
1141     MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1142     OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1143                                               ARM::t2LEApcrel ? ARM::t2ADR
1144                   : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1145                      : ARM::ADR))
1146       .addReg(MI->getOperand(0).getReg())
1147       .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1148       // Add predicate operands.
1149       .addImm(MI->getOperand(2).getImm())
1150       .addReg(MI->getOperand(3).getReg()));
1151     return;
1152   }
1153   case ARM::LEApcrelJT:
1154   case ARM::tLEApcrelJT:
1155   case ARM::t2LEApcrelJT: {
1156     MCSymbol *JTIPICSymbol =
1157       GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1158                                   MI->getOperand(2).getImm());
1159     OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1160                                               ARM::t2LEApcrelJT ? ARM::t2ADR
1161                   : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1162                      : ARM::ADR))
1163       .addReg(MI->getOperand(0).getReg())
1164       .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1165       // Add predicate operands.
1166       .addImm(MI->getOperand(3).getImm())
1167       .addReg(MI->getOperand(4).getReg()));
1168     return;
1169   }
1170   // Darwin call instructions are just normal call instructions with different
1171   // clobber semantics (they clobber R9).
1172   case ARM::BX_CALL: {
1173     OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1174       .addReg(ARM::LR)
1175       .addReg(ARM::PC)
1176       // Add predicate operands.
1177       .addImm(ARMCC::AL)
1178       .addReg(0)
1179       // Add 's' bit operand (always reg0 for this)
1180       .addReg(0));
1181 
1182     OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1183       .addReg(MI->getOperand(0).getReg()));
1184     return;
1185   }
1186   case ARM::tBX_CALL: {
1187     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1188       .addReg(ARM::LR)
1189       .addReg(ARM::PC)
1190       // Add predicate operands.
1191       .addImm(ARMCC::AL)
1192       .addReg(0));
1193 
1194     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1195       .addReg(MI->getOperand(0).getReg())
1196       // Add predicate operands.
1197       .addImm(ARMCC::AL)
1198       .addReg(0));
1199     return;
1200   }
1201   case ARM::BMOVPCRX_CALL: {
1202     OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1203       .addReg(ARM::LR)
1204       .addReg(ARM::PC)
1205       // Add predicate operands.
1206       .addImm(ARMCC::AL)
1207       .addReg(0)
1208       // Add 's' bit operand (always reg0 for this)
1209       .addReg(0));
1210 
1211     OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1212       .addReg(ARM::PC)
1213       .addReg(MI->getOperand(0).getReg())
1214       // Add predicate operands.
1215       .addImm(ARMCC::AL)
1216       .addReg(0)
1217       // Add 's' bit operand (always reg0 for this)
1218       .addReg(0));
1219     return;
1220   }
1221   case ARM::BMOVPCB_CALL: {
1222     OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1223       .addReg(ARM::LR)
1224       .addReg(ARM::PC)
1225       // Add predicate operands.
1226       .addImm(ARMCC::AL)
1227       .addReg(0)
1228       // Add 's' bit operand (always reg0 for this)
1229       .addReg(0));
1230 
1231     const GlobalValue *GV = MI->getOperand(0).getGlobal();
1232     MCSymbol *GVSym = getSymbol(GV);
1233     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1234     OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc)
1235       .addExpr(GVSymExpr)
1236       // Add predicate operands.
1237       .addImm(ARMCC::AL)
1238       .addReg(0));
1239     return;
1240   }
1241   case ARM::MOVi16_ga_pcrel:
1242   case ARM::t2MOVi16_ga_pcrel: {
1243     MCInst TmpInst;
1244     TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1245     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1246 
1247     unsigned TF = MI->getOperand(1).getTargetFlags();
1248     const GlobalValue *GV = MI->getOperand(1).getGlobal();
1249     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1250     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1251 
1252     MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1253                                      getFunctionNumber(),
1254                                      MI->getOperand(2).getImm(), OutContext);
1255     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1256     unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1257     const MCExpr *PCRelExpr =
1258       ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1259                                       MCBinaryExpr::CreateAdd(LabelSymExpr,
1260                                       MCConstantExpr::Create(PCAdj, OutContext),
1261                                       OutContext), OutContext), OutContext);
1262       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1263 
1264     // Add predicate operands.
1265     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1266     TmpInst.addOperand(MCOperand::CreateReg(0));
1267     // Add 's' bit operand (always reg0 for this)
1268     TmpInst.addOperand(MCOperand::CreateReg(0));
1269     OutStreamer.EmitInstruction(TmpInst);
1270     return;
1271   }
1272   case ARM::MOVTi16_ga_pcrel:
1273   case ARM::t2MOVTi16_ga_pcrel: {
1274     MCInst TmpInst;
1275     TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1276                       ? ARM::MOVTi16 : ARM::t2MOVTi16);
1277     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1278     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1279 
1280     unsigned TF = MI->getOperand(2).getTargetFlags();
1281     const GlobalValue *GV = MI->getOperand(2).getGlobal();
1282     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1283     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1284 
1285     MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1286                                      getFunctionNumber(),
1287                                      MI->getOperand(3).getImm(), OutContext);
1288     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1289     unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1290     const MCExpr *PCRelExpr =
1291         ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1292                                    MCBinaryExpr::CreateAdd(LabelSymExpr,
1293                                       MCConstantExpr::Create(PCAdj, OutContext),
1294                                           OutContext), OutContext), OutContext);
1295       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1296     // Add predicate operands.
1297     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1298     TmpInst.addOperand(MCOperand::CreateReg(0));
1299     // Add 's' bit operand (always reg0 for this)
1300     TmpInst.addOperand(MCOperand::CreateReg(0));
1301     OutStreamer.EmitInstruction(TmpInst);
1302     return;
1303   }
1304   case ARM::tPICADD: {
1305     // This is a pseudo op for a label + instruction sequence, which looks like:
1306     // LPC0:
1307     //     add r0, pc
1308     // This adds the address of LPC0 to r0.
1309 
1310     // Emit the label.
1311     OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1312                           getFunctionNumber(), MI->getOperand(2).getImm(),
1313                           OutContext));
1314 
1315     // Form and emit the add.
1316     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr)
1317       .addReg(MI->getOperand(0).getReg())
1318       .addReg(MI->getOperand(0).getReg())
1319       .addReg(ARM::PC)
1320       // Add predicate operands.
1321       .addImm(ARMCC::AL)
1322       .addReg(0));
1323     return;
1324   }
1325   case ARM::PICADD: {
1326     // This is a pseudo op for a label + instruction sequence, which looks like:
1327     // LPC0:
1328     //     add r0, pc, r0
1329     // This adds the address of LPC0 to r0.
1330 
1331     // Emit the label.
1332     OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1333                           getFunctionNumber(), MI->getOperand(2).getImm(),
1334                           OutContext));
1335 
1336     // Form and emit the add.
1337     OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1338       .addReg(MI->getOperand(0).getReg())
1339       .addReg(ARM::PC)
1340       .addReg(MI->getOperand(1).getReg())
1341       // Add predicate operands.
1342       .addImm(MI->getOperand(3).getImm())
1343       .addReg(MI->getOperand(4).getReg())
1344       // Add 's' bit operand (always reg0 for this)
1345       .addReg(0));
1346     return;
1347   }
1348   case ARM::PICSTR:
1349   case ARM::PICSTRB:
1350   case ARM::PICSTRH:
1351   case ARM::PICLDR:
1352   case ARM::PICLDRB:
1353   case ARM::PICLDRH:
1354   case ARM::PICLDRSB:
1355   case ARM::PICLDRSH: {
1356     // This is a pseudo op for a label + instruction sequence, which looks like:
1357     // LPC0:
1358     //     OP r0, [pc, r0]
1359     // The LCP0 label is referenced by a constant pool entry in order to get
1360     // a PC-relative address at the ldr instruction.
1361 
1362     // Emit the label.
1363     OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1364                           getFunctionNumber(), MI->getOperand(2).getImm(),
1365                           OutContext));
1366 
1367     // Form and emit the load
1368     unsigned Opcode;
1369     switch (MI->getOpcode()) {
1370     default:
1371       llvm_unreachable("Unexpected opcode!");
1372     case ARM::PICSTR:   Opcode = ARM::STRrs; break;
1373     case ARM::PICSTRB:  Opcode = ARM::STRBrs; break;
1374     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
1375     case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
1376     case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
1377     case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
1378     case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1379     case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1380     }
1381     OutStreamer.EmitInstruction(MCInstBuilder(Opcode)
1382       .addReg(MI->getOperand(0).getReg())
1383       .addReg(ARM::PC)
1384       .addReg(MI->getOperand(1).getReg())
1385       .addImm(0)
1386       // Add predicate operands.
1387       .addImm(MI->getOperand(3).getImm())
1388       .addReg(MI->getOperand(4).getReg()));
1389 
1390     return;
1391   }
1392   case ARM::CONSTPOOL_ENTRY: {
1393     /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1394     /// in the function.  The first operand is the ID# for this instruction, the
1395     /// second is the index into the MachineConstantPool that this is, the third
1396     /// is the size in bytes of this constant pool entry.
1397     /// The required alignment is specified on the basic block holding this MI.
1398     unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1399     unsigned CPIdx   = (unsigned)MI->getOperand(1).getIndex();
1400 
1401     // If this is the first entry of the pool, mark it.
1402     if (!InConstantPool) {
1403       OutStreamer.EmitDataRegion(MCDR_DataRegion);
1404       InConstantPool = true;
1405     }
1406 
1407     OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1408 
1409     const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1410     if (MCPE.isMachineConstantPoolEntry())
1411       EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1412     else
1413       EmitGlobalConstant(MCPE.Val.ConstVal);
1414     return;
1415   }
1416   case ARM::t2BR_JT: {
1417     // Lower and emit the instruction itself, then the jump table following it.
1418     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1419       .addReg(ARM::PC)
1420       .addReg(MI->getOperand(0).getReg())
1421       // Add predicate operands.
1422       .addImm(ARMCC::AL)
1423       .addReg(0));
1424 
1425     // Output the data for the jump table itself
1426     EmitJump2Table(MI);
1427     return;
1428   }
1429   case ARM::t2TBB_JT: {
1430     // Lower and emit the instruction itself, then the jump table following it.
1431     OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB)
1432       .addReg(ARM::PC)
1433       .addReg(MI->getOperand(0).getReg())
1434       // Add predicate operands.
1435       .addImm(ARMCC::AL)
1436       .addReg(0));
1437 
1438     // Output the data for the jump table itself
1439     EmitJump2Table(MI);
1440     // Make sure the next instruction is 2-byte aligned.
1441     EmitAlignment(1);
1442     return;
1443   }
1444   case ARM::t2TBH_JT: {
1445     // Lower and emit the instruction itself, then the jump table following it.
1446     OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH)
1447       .addReg(ARM::PC)
1448       .addReg(MI->getOperand(0).getReg())
1449       // Add predicate operands.
1450       .addImm(ARMCC::AL)
1451       .addReg(0));
1452 
1453     // Output the data for the jump table itself
1454     EmitJump2Table(MI);
1455     return;
1456   }
1457   case ARM::tBR_JTr:
1458   case ARM::BR_JTr: {
1459     // Lower and emit the instruction itself, then the jump table following it.
1460     // mov pc, target
1461     MCInst TmpInst;
1462     unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1463       ARM::MOVr : ARM::tMOVr;
1464     TmpInst.setOpcode(Opc);
1465     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1466     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1467     // Add predicate operands.
1468     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1469     TmpInst.addOperand(MCOperand::CreateReg(0));
1470     // Add 's' bit operand (always reg0 for this)
1471     if (Opc == ARM::MOVr)
1472       TmpInst.addOperand(MCOperand::CreateReg(0));
1473     OutStreamer.EmitInstruction(TmpInst);
1474 
1475     // Make sure the Thumb jump table is 4-byte aligned.
1476     if (Opc == ARM::tMOVr)
1477       EmitAlignment(2);
1478 
1479     // Output the data for the jump table itself
1480     EmitJumpTable(MI);
1481     return;
1482   }
1483   case ARM::BR_JTm: {
1484     // Lower and emit the instruction itself, then the jump table following it.
1485     // ldr pc, target
1486     MCInst TmpInst;
1487     if (MI->getOperand(1).getReg() == 0) {
1488       // literal offset
1489       TmpInst.setOpcode(ARM::LDRi12);
1490       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1491       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1492       TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1493     } else {
1494       TmpInst.setOpcode(ARM::LDRrs);
1495       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1496       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1497       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1498       TmpInst.addOperand(MCOperand::CreateImm(0));
1499     }
1500     // Add predicate operands.
1501     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1502     TmpInst.addOperand(MCOperand::CreateReg(0));
1503     OutStreamer.EmitInstruction(TmpInst);
1504 
1505     // Output the data for the jump table itself
1506     EmitJumpTable(MI);
1507     return;
1508   }
1509   case ARM::BR_JTadd: {
1510     // Lower and emit the instruction itself, then the jump table following it.
1511     // add pc, target, idx
1512     OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1513       .addReg(ARM::PC)
1514       .addReg(MI->getOperand(0).getReg())
1515       .addReg(MI->getOperand(1).getReg())
1516       // Add predicate operands.
1517       .addImm(ARMCC::AL)
1518       .addReg(0)
1519       // Add 's' bit operand (always reg0 for this)
1520       .addReg(0));
1521 
1522     // Output the data for the jump table itself
1523     EmitJumpTable(MI);
1524     return;
1525   }
1526   case ARM::TRAP: {
1527     // Non-Darwin binutils don't yet support the "trap" mnemonic.
1528     // FIXME: Remove this special case when they do.
1529     if (!Subtarget->isTargetDarwin()) {
1530       //.long 0xe7ffdefe @ trap
1531       uint32_t Val = 0xe7ffdefeUL;
1532       OutStreamer.AddComment("trap");
1533       OutStreamer.EmitIntValue(Val, 4);
1534       return;
1535     }
1536     break;
1537   }
1538   case ARM::TRAPNaCl: {
1539     //.long 0xe7fedef0 @ trap
1540     uint32_t Val = 0xe7fedef0UL;
1541     OutStreamer.AddComment("trap");
1542     OutStreamer.EmitIntValue(Val, 4);
1543     return;
1544   }
1545   case ARM::tTRAP: {
1546     // Non-Darwin binutils don't yet support the "trap" mnemonic.
1547     // FIXME: Remove this special case when they do.
1548     if (!Subtarget->isTargetDarwin()) {
1549       //.short 57086 @ trap
1550       uint16_t Val = 0xdefe;
1551       OutStreamer.AddComment("trap");
1552       OutStreamer.EmitIntValue(Val, 2);
1553       return;
1554     }
1555     break;
1556   }
1557   case ARM::t2Int_eh_sjlj_setjmp:
1558   case ARM::t2Int_eh_sjlj_setjmp_nofp:
1559   case ARM::tInt_eh_sjlj_setjmp: {
1560     // Two incoming args: GPR:$src, GPR:$val
1561     // mov $val, pc
1562     // adds $val, #7
1563     // str $val, [$src, #4]
1564     // movs r0, #0
1565     // b 1f
1566     // movs r0, #1
1567     // 1:
1568     unsigned SrcReg = MI->getOperand(0).getReg();
1569     unsigned ValReg = MI->getOperand(1).getReg();
1570     MCSymbol *Label = GetARMSJLJEHLabel();
1571     OutStreamer.AddComment("eh_setjmp begin");
1572     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1573       .addReg(ValReg)
1574       .addReg(ARM::PC)
1575       // Predicate.
1576       .addImm(ARMCC::AL)
1577       .addReg(0));
1578 
1579     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3)
1580       .addReg(ValReg)
1581       // 's' bit operand
1582       .addReg(ARM::CPSR)
1583       .addReg(ValReg)
1584       .addImm(7)
1585       // Predicate.
1586       .addImm(ARMCC::AL)
1587       .addReg(0));
1588 
1589     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi)
1590       .addReg(ValReg)
1591       .addReg(SrcReg)
1592       // The offset immediate is #4. The operand value is scaled by 4 for the
1593       // tSTR instruction.
1594       .addImm(1)
1595       // Predicate.
1596       .addImm(ARMCC::AL)
1597       .addReg(0));
1598 
1599     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1600       .addReg(ARM::R0)
1601       .addReg(ARM::CPSR)
1602       .addImm(0)
1603       // Predicate.
1604       .addImm(ARMCC::AL)
1605       .addReg(0));
1606 
1607     const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1608     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB)
1609       .addExpr(SymbolExpr)
1610       .addImm(ARMCC::AL)
1611       .addReg(0));
1612 
1613     OutStreamer.AddComment("eh_setjmp end");
1614     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1615       .addReg(ARM::R0)
1616       .addReg(ARM::CPSR)
1617       .addImm(1)
1618       // Predicate.
1619       .addImm(ARMCC::AL)
1620       .addReg(0));
1621 
1622     OutStreamer.EmitLabel(Label);
1623     return;
1624   }
1625 
1626   case ARM::Int_eh_sjlj_setjmp_nofp:
1627   case ARM::Int_eh_sjlj_setjmp: {
1628     // Two incoming args: GPR:$src, GPR:$val
1629     // add $val, pc, #8
1630     // str $val, [$src, #+4]
1631     // mov r0, #0
1632     // add pc, pc, #0
1633     // mov r0, #1
1634     unsigned SrcReg = MI->getOperand(0).getReg();
1635     unsigned ValReg = MI->getOperand(1).getReg();
1636 
1637     OutStreamer.AddComment("eh_setjmp begin");
1638     OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1639       .addReg(ValReg)
1640       .addReg(ARM::PC)
1641       .addImm(8)
1642       // Predicate.
1643       .addImm(ARMCC::AL)
1644       .addReg(0)
1645       // 's' bit operand (always reg0 for this).
1646       .addReg(0));
1647 
1648     OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12)
1649       .addReg(ValReg)
1650       .addReg(SrcReg)
1651       .addImm(4)
1652       // Predicate.
1653       .addImm(ARMCC::AL)
1654       .addReg(0));
1655 
1656     OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1657       .addReg(ARM::R0)
1658       .addImm(0)
1659       // Predicate.
1660       .addImm(ARMCC::AL)
1661       .addReg(0)
1662       // 's' bit operand (always reg0 for this).
1663       .addReg(0));
1664 
1665     OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1666       .addReg(ARM::PC)
1667       .addReg(ARM::PC)
1668       .addImm(0)
1669       // Predicate.
1670       .addImm(ARMCC::AL)
1671       .addReg(0)
1672       // 's' bit operand (always reg0 for this).
1673       .addReg(0));
1674 
1675     OutStreamer.AddComment("eh_setjmp end");
1676     OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1677       .addReg(ARM::R0)
1678       .addImm(1)
1679       // Predicate.
1680       .addImm(ARMCC::AL)
1681       .addReg(0)
1682       // 's' bit operand (always reg0 for this).
1683       .addReg(0));
1684     return;
1685   }
1686   case ARM::Int_eh_sjlj_longjmp: {
1687     // ldr sp, [$src, #8]
1688     // ldr $scratch, [$src, #4]
1689     // ldr r7, [$src]
1690     // bx $scratch
1691     unsigned SrcReg = MI->getOperand(0).getReg();
1692     unsigned ScratchReg = MI->getOperand(1).getReg();
1693     OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1694       .addReg(ARM::SP)
1695       .addReg(SrcReg)
1696       .addImm(8)
1697       // Predicate.
1698       .addImm(ARMCC::AL)
1699       .addReg(0));
1700 
1701     OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1702       .addReg(ScratchReg)
1703       .addReg(SrcReg)
1704       .addImm(4)
1705       // Predicate.
1706       .addImm(ARMCC::AL)
1707       .addReg(0));
1708 
1709     OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1710       .addReg(ARM::R7)
1711       .addReg(SrcReg)
1712       .addImm(0)
1713       // Predicate.
1714       .addImm(ARMCC::AL)
1715       .addReg(0));
1716 
1717     OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1718       .addReg(ScratchReg)
1719       // Predicate.
1720       .addImm(ARMCC::AL)
1721       .addReg(0));
1722     return;
1723   }
1724   case ARM::tInt_eh_sjlj_longjmp: {
1725     // ldr $scratch, [$src, #8]
1726     // mov sp, $scratch
1727     // ldr $scratch, [$src, #4]
1728     // ldr r7, [$src]
1729     // bx $scratch
1730     unsigned SrcReg = MI->getOperand(0).getReg();
1731     unsigned ScratchReg = MI->getOperand(1).getReg();
1732     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1733       .addReg(ScratchReg)
1734       .addReg(SrcReg)
1735       // The offset immediate is #8. The operand value is scaled by 4 for the
1736       // tLDR instruction.
1737       .addImm(2)
1738       // Predicate.
1739       .addImm(ARMCC::AL)
1740       .addReg(0));
1741 
1742     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1743       .addReg(ARM::SP)
1744       .addReg(ScratchReg)
1745       // Predicate.
1746       .addImm(ARMCC::AL)
1747       .addReg(0));
1748 
1749     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1750       .addReg(ScratchReg)
1751       .addReg(SrcReg)
1752       .addImm(1)
1753       // Predicate.
1754       .addImm(ARMCC::AL)
1755       .addReg(0));
1756 
1757     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1758       .addReg(ARM::R7)
1759       .addReg(SrcReg)
1760       .addImm(0)
1761       // Predicate.
1762       .addImm(ARMCC::AL)
1763       .addReg(0));
1764 
1765     OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1766       .addReg(ScratchReg)
1767       // Predicate.
1768       .addImm(ARMCC::AL)
1769       .addReg(0));
1770     return;
1771   }
1772   }
1773 
1774   MCInst TmpInst;
1775   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1776 
1777   OutStreamer.EmitInstruction(TmpInst);
1778 }
1779 
1780 //===----------------------------------------------------------------------===//
1781 // Target Registry Stuff
1782 //===----------------------------------------------------------------------===//
1783 
1784 // Force static initialization.
1785 extern "C" void LLVMInitializeARMAsmPrinter() {
1786   RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1787   RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1788 }
1789