1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
17 #include "ARM.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/Constants.h"
27 #include "llvm/DebugInfo.h"
28 #include "llvm/Module.h"
29 #include "llvm/Type.h"
30 #include "llvm/Assembly/Writer.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCAssembler.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCObjectStreamer.h"
40 #include "llvm/MC/MCStreamer.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/Target/Mangler.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/ADT/SmallString.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/TargetRegistry.h"
50 #include "llvm/Support/raw_ostream.h"
51 #include <cctype>
52 using namespace llvm;
53 
54 namespace {
55 
56   // Per section and per symbol attributes are not supported.
57   // To implement them we would need the ability to delay this emission
58   // until the assembly file is fully parsed/generated as only then do we
59   // know the symbol and section numbers.
60   class AttributeEmitter {
61   public:
62     virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
63     virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
64     virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
65     virtual void Finish() = 0;
66     virtual ~AttributeEmitter() {}
67   };
68 
69   class AsmAttributeEmitter : public AttributeEmitter {
70     MCStreamer &Streamer;
71 
72   public:
73     AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
74     void MaybeSwitchVendor(StringRef Vendor) { }
75 
76     void EmitAttribute(unsigned Attribute, unsigned Value) {
77       Streamer.EmitRawText("\t.eabi_attribute " +
78                            Twine(Attribute) + ", " + Twine(Value));
79     }
80 
81     void EmitTextAttribute(unsigned Attribute, StringRef String) {
82       switch (Attribute) {
83       default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
84       case ARMBuildAttrs::CPU_name:
85         Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
86         break;
87       /* GAS requires .fpu to be emitted regardless of EABI attribute */
88       case ARMBuildAttrs::Advanced_SIMD_arch:
89       case ARMBuildAttrs::VFP_arch:
90         Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
91         break;
92       }
93     }
94     void Finish() { }
95   };
96 
97   class ObjectAttributeEmitter : public AttributeEmitter {
98     // This structure holds all attributes, accounting for
99     // their string/numeric value, so we can later emmit them
100     // in declaration order, keeping all in the same vector
101     struct AttributeItemType {
102       enum {
103         HiddenAttribute = 0,
104         NumericAttribute,
105         TextAttribute
106       } Type;
107       unsigned Tag;
108       unsigned IntValue;
109       StringRef StringValue;
110     } AttributeItem;
111 
112     MCObjectStreamer &Streamer;
113     StringRef CurrentVendor;
114     SmallVector<AttributeItemType, 64> Contents;
115 
116     // Account for the ULEB/String size of each item,
117     // not just the number of items
118     size_t ContentsSize;
119     // FIXME: this should be in a more generic place, but
120     // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
121     size_t getULEBSize(int Value) {
122       size_t Size = 0;
123       do {
124         Value >>= 7;
125         Size += sizeof(int8_t); // Is this really necessary?
126       } while (Value);
127       return Size;
128     }
129 
130   public:
131     ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
132       Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
133 
134     void MaybeSwitchVendor(StringRef Vendor) {
135       assert(!Vendor.empty() && "Vendor cannot be empty.");
136 
137       if (CurrentVendor.empty())
138         CurrentVendor = Vendor;
139       else if (CurrentVendor == Vendor)
140         return;
141       else
142         Finish();
143 
144       CurrentVendor = Vendor;
145 
146       assert(Contents.size() == 0);
147     }
148 
149     void EmitAttribute(unsigned Attribute, unsigned Value) {
150       AttributeItemType attr = {
151         AttributeItemType::NumericAttribute,
152         Attribute,
153         Value,
154         StringRef("")
155       };
156       ContentsSize += getULEBSize(Attribute);
157       ContentsSize += getULEBSize(Value);
158       Contents.push_back(attr);
159     }
160 
161     void EmitTextAttribute(unsigned Attribute, StringRef String) {
162       AttributeItemType attr = {
163         AttributeItemType::TextAttribute,
164         Attribute,
165         0,
166         String
167       };
168       ContentsSize += getULEBSize(Attribute);
169       // String + \0
170       ContentsSize += String.size()+1;
171 
172       Contents.push_back(attr);
173     }
174 
175     void Finish() {
176       // Vendor size + Vendor name + '\0'
177       const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
178 
179       // Tag + Tag Size
180       const size_t TagHeaderSize = 1 + 4;
181 
182       Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
183       Streamer.EmitBytes(CurrentVendor, 0);
184       Streamer.EmitIntValue(0, 1); // '\0'
185 
186       Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
187       Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
188 
189       // Size should have been accounted for already, now
190       // emit each field as its type (ULEB or String)
191       for (unsigned int i=0; i<Contents.size(); ++i) {
192         AttributeItemType item = Contents[i];
193         Streamer.EmitULEB128IntValue(item.Tag, 0);
194         switch (item.Type) {
195         default: llvm_unreachable("Invalid attribute type");
196         case AttributeItemType::NumericAttribute:
197           Streamer.EmitULEB128IntValue(item.IntValue, 0);
198           break;
199         case AttributeItemType::TextAttribute:
200           Streamer.EmitBytes(item.StringValue.upper(), 0);
201           Streamer.EmitIntValue(0, 1); // '\0'
202           break;
203         }
204       }
205 
206       Contents.clear();
207     }
208   };
209 
210 } // end of anonymous namespace
211 
212 MachineLocation ARMAsmPrinter::
213 getDebugValueLocation(const MachineInstr *MI) const {
214   MachineLocation Location;
215   assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
216   // Frame address.  Currently handles register +- offset only.
217   if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
218     Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
219   else {
220     DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
221   }
222   return Location;
223 }
224 
225 /// EmitDwarfRegOp - Emit dwarf register operation.
226 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
227   const TargetRegisterInfo *RI = TM.getRegisterInfo();
228   if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
229     AsmPrinter::EmitDwarfRegOp(MLoc);
230   else {
231     unsigned Reg = MLoc.getReg();
232     if (Reg >= ARM::S0 && Reg <= ARM::S31) {
233       assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
234       // S registers are described as bit-pieces of a register
235       // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
236       // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
237 
238       unsigned SReg = Reg - ARM::S0;
239       bool odd = SReg & 0x1;
240       unsigned Rx = 256 + (SReg >> 1);
241 
242       OutStreamer.AddComment("DW_OP_regx for S register");
243       EmitInt8(dwarf::DW_OP_regx);
244 
245       OutStreamer.AddComment(Twine(SReg));
246       EmitULEB128(Rx);
247 
248       if (odd) {
249         OutStreamer.AddComment("DW_OP_bit_piece 32 32");
250         EmitInt8(dwarf::DW_OP_bit_piece);
251         EmitULEB128(32);
252         EmitULEB128(32);
253       } else {
254         OutStreamer.AddComment("DW_OP_bit_piece 32 0");
255         EmitInt8(dwarf::DW_OP_bit_piece);
256         EmitULEB128(32);
257         EmitULEB128(0);
258       }
259     } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
260       assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
261       // Q registers Q0-Q15 are described by composing two D registers together.
262       // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
263       // DW_OP_piece(8)
264 
265       unsigned QReg = Reg - ARM::Q0;
266       unsigned D1 = 256 + 2 * QReg;
267       unsigned D2 = D1 + 1;
268 
269       OutStreamer.AddComment("DW_OP_regx for Q register: D1");
270       EmitInt8(dwarf::DW_OP_regx);
271       EmitULEB128(D1);
272       OutStreamer.AddComment("DW_OP_piece 8");
273       EmitInt8(dwarf::DW_OP_piece);
274       EmitULEB128(8);
275 
276       OutStreamer.AddComment("DW_OP_regx for Q register: D2");
277       EmitInt8(dwarf::DW_OP_regx);
278       EmitULEB128(D2);
279       OutStreamer.AddComment("DW_OP_piece 8");
280       EmitInt8(dwarf::DW_OP_piece);
281       EmitULEB128(8);
282     }
283   }
284 }
285 
286 void ARMAsmPrinter::EmitFunctionBodyEnd() {
287   // Make sure to terminate any constant pools that were at the end
288   // of the function.
289   if (!InConstantPool)
290     return;
291   InConstantPool = false;
292   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
293 }
294 
295 void ARMAsmPrinter::EmitFunctionEntryLabel() {
296   if (AFI->isThumbFunction()) {
297     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
298     OutStreamer.EmitThumbFunc(CurrentFnSym);
299   }
300 
301   OutStreamer.EmitLabel(CurrentFnSym);
302 }
303 
304 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
305   uint64_t Size = TM.getTargetData()->getTypeAllocSize(CV->getType());
306   assert(Size && "C++ constructor pointer had zero size!");
307 
308   const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
309   assert(GV && "C++ constructor pointer was not a GlobalValue!");
310 
311   const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
312                                             (Subtarget->isTargetDarwin()
313                                              ? MCSymbolRefExpr::VK_None
314                                              : MCSymbolRefExpr::VK_ARM_TARGET1),
315                                             OutContext);
316 
317   OutStreamer.EmitValue(E, Size);
318 }
319 
320 /// runOnMachineFunction - This uses the EmitInstruction()
321 /// method to print assembly for each instruction.
322 ///
323 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
324   AFI = MF.getInfo<ARMFunctionInfo>();
325   MCP = MF.getConstantPool();
326 
327   return AsmPrinter::runOnMachineFunction(MF);
328 }
329 
330 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
331                                  raw_ostream &O, const char *Modifier) {
332   const MachineOperand &MO = MI->getOperand(OpNum);
333   unsigned TF = MO.getTargetFlags();
334 
335   switch (MO.getType()) {
336   default: llvm_unreachable("<unknown operand type>");
337   case MachineOperand::MO_Register: {
338     unsigned Reg = MO.getReg();
339     assert(TargetRegisterInfo::isPhysicalRegister(Reg));
340     assert(!MO.getSubReg() && "Subregs should be eliminated!");
341     O << ARMInstPrinter::getRegisterName(Reg);
342     break;
343   }
344   case MachineOperand::MO_Immediate: {
345     int64_t Imm = MO.getImm();
346     O << '#';
347     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
348         (TF == ARMII::MO_LO16))
349       O << ":lower16:";
350     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
351              (TF == ARMII::MO_HI16))
352       O << ":upper16:";
353     O << Imm;
354     break;
355   }
356   case MachineOperand::MO_MachineBasicBlock:
357     O << *MO.getMBB()->getSymbol();
358     return;
359   case MachineOperand::MO_GlobalAddress: {
360     const GlobalValue *GV = MO.getGlobal();
361     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
362         (TF & ARMII::MO_LO16))
363       O << ":lower16:";
364     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
365              (TF & ARMII::MO_HI16))
366       O << ":upper16:";
367     O << *Mang->getSymbol(GV);
368 
369     printOffset(MO.getOffset(), O);
370     if (TF == ARMII::MO_PLT)
371       O << "(PLT)";
372     break;
373   }
374   case MachineOperand::MO_ExternalSymbol: {
375     O << *GetExternalSymbolSymbol(MO.getSymbolName());
376     if (TF == ARMII::MO_PLT)
377       O << "(PLT)";
378     break;
379   }
380   case MachineOperand::MO_ConstantPoolIndex:
381     O << *GetCPISymbol(MO.getIndex());
382     break;
383   case MachineOperand::MO_JumpTableIndex:
384     O << *GetJTISymbol(MO.getIndex());
385     break;
386   }
387 }
388 
389 //===--------------------------------------------------------------------===//
390 
391 MCSymbol *ARMAsmPrinter::
392 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
393                             const MachineBasicBlock *MBB) const {
394   SmallString<60> Name;
395   raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
396     << getFunctionNumber() << '_' << uid << '_' << uid2
397     << "_set_" << MBB->getNumber();
398   return OutContext.GetOrCreateSymbol(Name.str());
399 }
400 
401 MCSymbol *ARMAsmPrinter::
402 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
403   SmallString<60> Name;
404   raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
405     << getFunctionNumber() << '_' << uid << '_' << uid2;
406   return OutContext.GetOrCreateSymbol(Name.str());
407 }
408 
409 
410 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
411   SmallString<60> Name;
412   raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
413     << getFunctionNumber();
414   return OutContext.GetOrCreateSymbol(Name.str());
415 }
416 
417 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
418                                     unsigned AsmVariant, const char *ExtraCode,
419                                     raw_ostream &O) {
420   // Does this asm operand have a single letter operand modifier?
421   if (ExtraCode && ExtraCode[0]) {
422     if (ExtraCode[1] != 0) return true; // Unknown modifier.
423 
424     switch (ExtraCode[0]) {
425     default:
426       // See if this is a generic print operand
427       return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
428     case 'a': // Print as a memory address.
429       if (MI->getOperand(OpNum).isReg()) {
430         O << "["
431           << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
432           << "]";
433         return false;
434       }
435       // Fallthrough
436     case 'c': // Don't print "#" before an immediate operand.
437       if (!MI->getOperand(OpNum).isImm())
438         return true;
439       O << MI->getOperand(OpNum).getImm();
440       return false;
441     case 'P': // Print a VFP double precision register.
442     case 'q': // Print a NEON quad precision register.
443       printOperand(MI, OpNum, O);
444       return false;
445     case 'y': // Print a VFP single precision register as indexed double.
446       if (MI->getOperand(OpNum).isReg()) {
447         unsigned Reg = MI->getOperand(OpNum).getReg();
448         const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
449         // Find the 'd' register that has this 's' register as a sub-register,
450         // and determine the lane number.
451         for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
452           if (!ARM::DPRRegClass.contains(*SR))
453             continue;
454           bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
455           O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
456           return false;
457         }
458       }
459       return true;
460     case 'B': // Bitwise inverse of integer or symbol without a preceding #.
461       if (!MI->getOperand(OpNum).isImm())
462         return true;
463       O << ~(MI->getOperand(OpNum).getImm());
464       return false;
465     case 'L': // The low 16 bits of an immediate constant.
466       if (!MI->getOperand(OpNum).isImm())
467         return true;
468       O << (MI->getOperand(OpNum).getImm() & 0xffff);
469       return false;
470     case 'M': { // A register range suitable for LDM/STM.
471       if (!MI->getOperand(OpNum).isReg())
472         return true;
473       const MachineOperand &MO = MI->getOperand(OpNum);
474       unsigned RegBegin = MO.getReg();
475       // This takes advantage of the 2 operand-ness of ldm/stm and that we've
476       // already got the operands in registers that are operands to the
477       // inline asm statement.
478 
479       O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
480 
481       // FIXME: The register allocator not only may not have given us the
482       // registers in sequence, but may not be in ascending registers. This
483       // will require changes in the register allocator that'll need to be
484       // propagated down here if the operands change.
485       unsigned RegOps = OpNum + 1;
486       while (MI->getOperand(RegOps).isReg()) {
487         O << ", "
488           << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
489         RegOps++;
490       }
491 
492       O << "}";
493 
494       return false;
495     }
496     case 'R': // The most significant register of a pair.
497     case 'Q': { // The least significant register of a pair.
498       if (OpNum == 0)
499         return true;
500       const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
501       if (!FlagsOP.isImm())
502         return true;
503       unsigned Flags = FlagsOP.getImm();
504       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
505       if (NumVals != 2)
506         return true;
507       unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
508       if (RegOp >= MI->getNumOperands())
509         return true;
510       const MachineOperand &MO = MI->getOperand(RegOp);
511       if (!MO.isReg())
512         return true;
513       unsigned Reg = MO.getReg();
514       O << ARMInstPrinter::getRegisterName(Reg);
515       return false;
516     }
517 
518     case 'e': // The low doubleword register of a NEON quad register.
519     case 'f': { // The high doubleword register of a NEON quad register.
520       if (!MI->getOperand(OpNum).isReg())
521         return true;
522       unsigned Reg = MI->getOperand(OpNum).getReg();
523       if (!ARM::QPRRegClass.contains(Reg))
524         return true;
525       const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
526       unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
527                                        ARM::dsub_0 : ARM::dsub_1);
528       O << ARMInstPrinter::getRegisterName(SubReg);
529       return false;
530     }
531 
532     // These modifiers are not yet supported.
533     case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
534     case 'H': // The highest-numbered register of a pair.
535       return true;
536     }
537   }
538 
539   printOperand(MI, OpNum, O);
540   return false;
541 }
542 
543 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
544                                           unsigned OpNum, unsigned AsmVariant,
545                                           const char *ExtraCode,
546                                           raw_ostream &O) {
547   // Does this asm operand have a single letter operand modifier?
548   if (ExtraCode && ExtraCode[0]) {
549     if (ExtraCode[1] != 0) return true; // Unknown modifier.
550 
551     switch (ExtraCode[0]) {
552       case 'A': // A memory operand for a VLD1/VST1 instruction.
553       default: return true;  // Unknown modifier.
554       case 'm': // The base register of a memory operand.
555         if (!MI->getOperand(OpNum).isReg())
556           return true;
557         O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
558         return false;
559     }
560   }
561 
562   const MachineOperand &MO = MI->getOperand(OpNum);
563   assert(MO.isReg() && "unexpected inline asm memory operand");
564   O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
565   return false;
566 }
567 
568 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
569   if (Subtarget->isTargetDarwin()) {
570     Reloc::Model RelocM = TM.getRelocationModel();
571     if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
572       // Declare all the text sections up front (before the DWARF sections
573       // emitted by AsmPrinter::doInitialization) so the assembler will keep
574       // them together at the beginning of the object file.  This helps
575       // avoid out-of-range branches that are due a fundamental limitation of
576       // the way symbol offsets are encoded with the current Darwin ARM
577       // relocations.
578       const TargetLoweringObjectFileMachO &TLOFMacho =
579         static_cast<const TargetLoweringObjectFileMachO &>(
580           getObjFileLowering());
581       OutStreamer.SwitchSection(TLOFMacho.getTextSection());
582       OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
583       OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
584       if (RelocM == Reloc::DynamicNoPIC) {
585         const MCSection *sect =
586           OutContext.getMachOSection("__TEXT", "__symbol_stub4",
587                                      MCSectionMachO::S_SYMBOL_STUBS,
588                                      12, SectionKind::getText());
589         OutStreamer.SwitchSection(sect);
590       } else {
591         const MCSection *sect =
592           OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
593                                      MCSectionMachO::S_SYMBOL_STUBS,
594                                      16, SectionKind::getText());
595         OutStreamer.SwitchSection(sect);
596       }
597       const MCSection *StaticInitSect =
598         OutContext.getMachOSection("__TEXT", "__StaticInit",
599                                    MCSectionMachO::S_REGULAR |
600                                    MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
601                                    SectionKind::getText());
602       OutStreamer.SwitchSection(StaticInitSect);
603     }
604   }
605 
606   // Use unified assembler syntax.
607   OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
608 
609   // Emit ARM Build Attributes
610   if (Subtarget->isTargetELF())
611     emitAttributes();
612 }
613 
614 
615 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
616   if (Subtarget->isTargetDarwin()) {
617     // All darwin targets use mach-o.
618     const TargetLoweringObjectFileMachO &TLOFMacho =
619       static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
620     MachineModuleInfoMachO &MMIMacho =
621       MMI->getObjFileInfo<MachineModuleInfoMachO>();
622 
623     // Output non-lazy-pointers for external and common global variables.
624     MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
625 
626     if (!Stubs.empty()) {
627       // Switch with ".non_lazy_symbol_pointer" directive.
628       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
629       EmitAlignment(2);
630       for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
631         // L_foo$stub:
632         OutStreamer.EmitLabel(Stubs[i].first);
633         //   .indirect_symbol _foo
634         MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
635         OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
636 
637         if (MCSym.getInt())
638           // External to current translation unit.
639           OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
640         else
641           // Internal to current translation unit.
642           //
643           // When we place the LSDA into the TEXT section, the type info
644           // pointers need to be indirect and pc-rel. We accomplish this by
645           // using NLPs; however, sometimes the types are local to the file.
646           // We need to fill in the value for the NLP in those cases.
647           OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
648                                                         OutContext),
649                                 4/*size*/, 0/*addrspace*/);
650       }
651 
652       Stubs.clear();
653       OutStreamer.AddBlankLine();
654     }
655 
656     Stubs = MMIMacho.GetHiddenGVStubList();
657     if (!Stubs.empty()) {
658       OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
659       EmitAlignment(2);
660       for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
661         // L_foo$stub:
662         OutStreamer.EmitLabel(Stubs[i].first);
663         //   .long _foo
664         OutStreamer.EmitValue(MCSymbolRefExpr::
665                               Create(Stubs[i].second.getPointer(),
666                                      OutContext),
667                               4/*size*/, 0/*addrspace*/);
668       }
669 
670       Stubs.clear();
671       OutStreamer.AddBlankLine();
672     }
673 
674     // Funny Darwin hack: This flag tells the linker that no global symbols
675     // contain code that falls through to other global symbols (e.g. the obvious
676     // implementation of multiple entry points).  If this doesn't occur, the
677     // linker can safely perform dead code stripping.  Since LLVM never
678     // generates code that does this, it is always safe to set.
679     OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
680   }
681 }
682 
683 //===----------------------------------------------------------------------===//
684 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
685 // FIXME:
686 // The following seem like one-off assembler flags, but they actually need
687 // to appear in the .ARM.attributes section in ELF.
688 // Instead of subclassing the MCELFStreamer, we do the work here.
689 
690 void ARMAsmPrinter::emitAttributes() {
691 
692   emitARMAttributeSection();
693 
694   /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
695   bool emitFPU = false;
696   AttributeEmitter *AttrEmitter;
697   if (OutStreamer.hasRawTextSupport()) {
698     AttrEmitter = new AsmAttributeEmitter(OutStreamer);
699     emitFPU = true;
700   } else {
701     MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
702     AttrEmitter = new ObjectAttributeEmitter(O);
703   }
704 
705   AttrEmitter->MaybeSwitchVendor("aeabi");
706 
707   std::string CPUString = Subtarget->getCPUString();
708 
709   if (CPUString == "cortex-a8" ||
710       Subtarget->isCortexA8()) {
711     AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
712     AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
713     AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
714                                ARMBuildAttrs::ApplicationProfile);
715     AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
716                                ARMBuildAttrs::Allowed);
717     AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
718                                ARMBuildAttrs::AllowThumb32);
719     // Fixme: figure out when this is emitted.
720     //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
721     //                           ARMBuildAttrs::AllowWMMXv1);
722     //
723 
724     /// ADD additional Else-cases here!
725   } else if (CPUString == "xscale") {
726     AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
727     AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
728                                ARMBuildAttrs::Allowed);
729     AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
730                                ARMBuildAttrs::Allowed);
731   } else if (CPUString == "generic") {
732     // FIXME: Why these defaults?
733     AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
734     AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
735                                ARMBuildAttrs::Allowed);
736     AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
737                                ARMBuildAttrs::Allowed);
738   }
739 
740   if (Subtarget->hasNEON() && emitFPU) {
741     /* NEON is not exactly a VFP architecture, but GAS emit one of
742      * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
743     if (Subtarget->hasVFP4())
744       AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
745                                      "neon-vfpv4");
746     else
747       AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
748     /* If emitted for NEON, omit from VFP below, since you can have both
749      * NEON and VFP in build attributes but only one .fpu */
750     emitFPU = false;
751   }
752 
753   /* VFPv4 + .fpu */
754   if (Subtarget->hasVFP4()) {
755     AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
756                                ARMBuildAttrs::AllowFPv4A);
757     if (emitFPU)
758       AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
759 
760   /* VFPv3 + .fpu */
761   } else if (Subtarget->hasVFP3()) {
762     AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
763                                ARMBuildAttrs::AllowFPv3A);
764     if (emitFPU)
765       AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
766 
767   /* VFPv2 + .fpu */
768   } else if (Subtarget->hasVFP2()) {
769     AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
770                                ARMBuildAttrs::AllowFPv2);
771     if (emitFPU)
772       AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
773   }
774 
775   /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
776    * since NEON can have 1 (allowed) or 2 (MAC operations) */
777   if (Subtarget->hasNEON()) {
778     AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
779                                ARMBuildAttrs::Allowed);
780   }
781 
782   // Signal various FP modes.
783   if (!TM.Options.UnsafeFPMath) {
784     AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
785                                ARMBuildAttrs::Allowed);
786     AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
787                                ARMBuildAttrs::Allowed);
788   }
789 
790   if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
791     AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
792                                ARMBuildAttrs::Allowed);
793   else
794     AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
795                                ARMBuildAttrs::AllowIEE754);
796 
797   // FIXME: add more flags to ARMBuildAttrs.h
798   // 8-bytes alignment stuff.
799   AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
800   AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
801 
802   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
803   if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
804     AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
805     AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
806   }
807   // FIXME: Should we signal R9 usage?
808 
809   if (Subtarget->hasDivide())
810     AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
811 
812   AttrEmitter->Finish();
813   delete AttrEmitter;
814 }
815 
816 void ARMAsmPrinter::emitARMAttributeSection() {
817   // <format-version>
818   // [ <section-length> "vendor-name"
819   // [ <file-tag> <size> <attribute>*
820   //   | <section-tag> <size> <section-number>* 0 <attribute>*
821   //   | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
822   //   ]+
823   // ]*
824 
825   if (OutStreamer.hasRawTextSupport())
826     return;
827 
828   const ARMElfTargetObjectFile &TLOFELF =
829     static_cast<const ARMElfTargetObjectFile &>
830     (getObjFileLowering());
831 
832   OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
833 
834   // Format version
835   OutStreamer.EmitIntValue(0x41, 1);
836 }
837 
838 //===----------------------------------------------------------------------===//
839 
840 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
841                              unsigned LabelId, MCContext &Ctx) {
842 
843   MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
844                        + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
845   return Label;
846 }
847 
848 static MCSymbolRefExpr::VariantKind
849 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
850   switch (Modifier) {
851   case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
852   case ARMCP::TLSGD:       return MCSymbolRefExpr::VK_ARM_TLSGD;
853   case ARMCP::TPOFF:       return MCSymbolRefExpr::VK_ARM_TPOFF;
854   case ARMCP::GOTTPOFF:    return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
855   case ARMCP::GOT:         return MCSymbolRefExpr::VK_ARM_GOT;
856   case ARMCP::GOTOFF:      return MCSymbolRefExpr::VK_ARM_GOTOFF;
857   }
858   llvm_unreachable("Invalid ARMCPModifier!");
859 }
860 
861 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
862   bool isIndirect = Subtarget->isTargetDarwin() &&
863     Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
864   if (!isIndirect)
865     return Mang->getSymbol(GV);
866 
867   // FIXME: Remove this when Darwin transition to @GOT like syntax.
868   MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
869   MachineModuleInfoMachO &MMIMachO =
870     MMI->getObjFileInfo<MachineModuleInfoMachO>();
871   MachineModuleInfoImpl::StubValueTy &StubSym =
872     GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
873     MMIMachO.getGVStubEntry(MCSym);
874   if (StubSym.getPointer() == 0)
875     StubSym = MachineModuleInfoImpl::
876       StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
877   return MCSym;
878 }
879 
880 void ARMAsmPrinter::
881 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
882   int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
883 
884   ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
885 
886   MCSymbol *MCSym;
887   if (ACPV->isLSDA()) {
888     SmallString<128> Str;
889     raw_svector_ostream OS(Str);
890     OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
891     MCSym = OutContext.GetOrCreateSymbol(OS.str());
892   } else if (ACPV->isBlockAddress()) {
893     const BlockAddress *BA =
894       cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
895     MCSym = GetBlockAddressSymbol(BA);
896   } else if (ACPV->isGlobalValue()) {
897     const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
898     MCSym = GetARMGVSymbol(GV);
899   } else if (ACPV->isMachineBasicBlock()) {
900     const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
901     MCSym = MBB->getSymbol();
902   } else {
903     assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
904     const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
905     MCSym = GetExternalSymbolSymbol(Sym);
906   }
907 
908   // Create an MCSymbol for the reference.
909   const MCExpr *Expr =
910     MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
911                             OutContext);
912 
913   if (ACPV->getPCAdjustment()) {
914     MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
915                                     getFunctionNumber(),
916                                     ACPV->getLabelId(),
917                                     OutContext);
918     const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
919     PCRelExpr =
920       MCBinaryExpr::CreateAdd(PCRelExpr,
921                               MCConstantExpr::Create(ACPV->getPCAdjustment(),
922                                                      OutContext),
923                               OutContext);
924     if (ACPV->mustAddCurrentAddress()) {
925       // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
926       // label, so just emit a local label end reference that instead.
927       MCSymbol *DotSym = OutContext.CreateTempSymbol();
928       OutStreamer.EmitLabel(DotSym);
929       const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
930       PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
931     }
932     Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
933   }
934   OutStreamer.EmitValue(Expr, Size);
935 }
936 
937 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
938   unsigned Opcode = MI->getOpcode();
939   int OpNum = 1;
940   if (Opcode == ARM::BR_JTadd)
941     OpNum = 2;
942   else if (Opcode == ARM::BR_JTm)
943     OpNum = 3;
944 
945   const MachineOperand &MO1 = MI->getOperand(OpNum);
946   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
947   unsigned JTI = MO1.getIndex();
948 
949   // Emit a label for the jump table.
950   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
951   OutStreamer.EmitLabel(JTISymbol);
952 
953   // Mark the jump table as data-in-code.
954   OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
955 
956   // Emit each entry of the table.
957   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
958   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
959   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
960 
961   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
962     MachineBasicBlock *MBB = JTBBs[i];
963     // Construct an MCExpr for the entry. We want a value of the form:
964     // (BasicBlockAddr - TableBeginAddr)
965     //
966     // For example, a table with entries jumping to basic blocks BB0 and BB1
967     // would look like:
968     // LJTI_0_0:
969     //    .word (LBB0 - LJTI_0_0)
970     //    .word (LBB1 - LJTI_0_0)
971     const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
972 
973     if (TM.getRelocationModel() == Reloc::PIC_)
974       Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
975                                                                    OutContext),
976                                      OutContext);
977     // If we're generating a table of Thumb addresses in static relocation
978     // model, we need to add one to keep interworking correctly.
979     else if (AFI->isThumbFunction())
980       Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
981                                      OutContext);
982     OutStreamer.EmitValue(Expr, 4);
983   }
984   // Mark the end of jump table data-in-code region.
985   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
986 }
987 
988 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
989   unsigned Opcode = MI->getOpcode();
990   int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
991   const MachineOperand &MO1 = MI->getOperand(OpNum);
992   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
993   unsigned JTI = MO1.getIndex();
994 
995   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
996   OutStreamer.EmitLabel(JTISymbol);
997 
998   // Emit each entry of the table.
999   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1000   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1001   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1002   unsigned OffsetWidth = 4;
1003   if (MI->getOpcode() == ARM::t2TBB_JT) {
1004     OffsetWidth = 1;
1005     // Mark the jump table as data-in-code.
1006     OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
1007   } else if (MI->getOpcode() == ARM::t2TBH_JT) {
1008     OffsetWidth = 2;
1009     // Mark the jump table as data-in-code.
1010     OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
1011   }
1012 
1013   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1014     MachineBasicBlock *MBB = JTBBs[i];
1015     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1016                                                       OutContext);
1017     // If this isn't a TBB or TBH, the entries are direct branch instructions.
1018     if (OffsetWidth == 4) {
1019       MCInst BrInst;
1020       BrInst.setOpcode(ARM::t2B);
1021       BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
1022       BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1023       BrInst.addOperand(MCOperand::CreateReg(0));
1024       OutStreamer.EmitInstruction(BrInst);
1025       continue;
1026     }
1027     // Otherwise it's an offset from the dispatch instruction. Construct an
1028     // MCExpr for the entry. We want a value of the form:
1029     // (BasicBlockAddr - TableBeginAddr) / 2
1030     //
1031     // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1032     // would look like:
1033     // LJTI_0_0:
1034     //    .byte (LBB0 - LJTI_0_0) / 2
1035     //    .byte (LBB1 - LJTI_0_0) / 2
1036     const MCExpr *Expr =
1037       MCBinaryExpr::CreateSub(MBBSymbolExpr,
1038                               MCSymbolRefExpr::Create(JTISymbol, OutContext),
1039                               OutContext);
1040     Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1041                                    OutContext);
1042     OutStreamer.EmitValue(Expr, OffsetWidth);
1043   }
1044   // Mark the end of jump table data-in-code region. 32-bit offsets use
1045   // actual branch instructions here, so we don't mark those as a data-region
1046   // at all.
1047   if (OffsetWidth != 4)
1048     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1049 }
1050 
1051 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1052                                            raw_ostream &OS) {
1053   unsigned NOps = MI->getNumOperands();
1054   assert(NOps==4);
1055   OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1056   // cast away const; DIetc do not take const operands for some reason.
1057   DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1058   OS << V.getName();
1059   OS << " <- ";
1060   // Frame address.  Currently handles register +- offset only.
1061   assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1062   OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1063   OS << ']';
1064   OS << "+";
1065   printOperand(MI, NOps-2, OS);
1066 }
1067 
1068 static void populateADROperands(MCInst &Inst, unsigned Dest,
1069                                 const MCSymbol *Label,
1070                                 unsigned pred, unsigned ccreg,
1071                                 MCContext &Ctx) {
1072   const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1073   Inst.addOperand(MCOperand::CreateReg(Dest));
1074   Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1075   // Add predicate operands.
1076   Inst.addOperand(MCOperand::CreateImm(pred));
1077   Inst.addOperand(MCOperand::CreateReg(ccreg));
1078 }
1079 
1080 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
1081                                            unsigned Opcode) {
1082   MCInst TmpInst;
1083 
1084   // Emit the instruction as usual, just patch the opcode.
1085   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1086   TmpInst.setOpcode(Opcode);
1087   OutStreamer.EmitInstruction(TmpInst);
1088 }
1089 
1090 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1091   assert(MI->getFlag(MachineInstr::FrameSetup) &&
1092       "Only instruction which are involved into frame setup code are allowed");
1093 
1094   const MachineFunction &MF = *MI->getParent()->getParent();
1095   const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1096   const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1097 
1098   unsigned FramePtr = RegInfo->getFrameRegister(MF);
1099   unsigned Opc = MI->getOpcode();
1100   unsigned SrcReg, DstReg;
1101 
1102   if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1103     // Two special cases:
1104     // 1) tPUSH does not have src/dst regs.
1105     // 2) for Thumb1 code we sometimes materialize the constant via constpool
1106     // load. Yes, this is pretty fragile, but for now I don't see better
1107     // way... :(
1108     SrcReg = DstReg = ARM::SP;
1109   } else {
1110     SrcReg = MI->getOperand(1).getReg();
1111     DstReg = MI->getOperand(0).getReg();
1112   }
1113 
1114   // Try to figure out the unwinding opcode out of src / dst regs.
1115   if (MI->mayStore()) {
1116     // Register saves.
1117     assert(DstReg == ARM::SP &&
1118            "Only stack pointer as a destination reg is supported");
1119 
1120     SmallVector<unsigned, 4> RegList;
1121     // Skip src & dst reg, and pred ops.
1122     unsigned StartOp = 2 + 2;
1123     // Use all the operands.
1124     unsigned NumOffset = 0;
1125 
1126     switch (Opc) {
1127     default:
1128       MI->dump();
1129       llvm_unreachable("Unsupported opcode for unwinding information");
1130     case ARM::tPUSH:
1131       // Special case here: no src & dst reg, but two extra imp ops.
1132       StartOp = 2; NumOffset = 2;
1133     case ARM::STMDB_UPD:
1134     case ARM::t2STMDB_UPD:
1135     case ARM::VSTMDDB_UPD:
1136       assert(SrcReg == ARM::SP &&
1137              "Only stack pointer as a source reg is supported");
1138       for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1139            i != NumOps; ++i) {
1140         const MachineOperand &MO = MI->getOperand(i);
1141         // Actually, there should never be any impdef stuff here. Skip it
1142         // temporary to workaround PR11902.
1143         if (MO.isImplicit())
1144           continue;
1145         RegList.push_back(MO.getReg());
1146       }
1147       break;
1148     case ARM::STR_PRE_IMM:
1149     case ARM::STR_PRE_REG:
1150     case ARM::t2STR_PRE:
1151       assert(MI->getOperand(2).getReg() == ARM::SP &&
1152              "Only stack pointer as a source reg is supported");
1153       RegList.push_back(SrcReg);
1154       break;
1155     }
1156     OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1157   } else {
1158     // Changes of stack / frame pointer.
1159     if (SrcReg == ARM::SP) {
1160       int64_t Offset = 0;
1161       switch (Opc) {
1162       default:
1163         MI->dump();
1164         llvm_unreachable("Unsupported opcode for unwinding information");
1165       case ARM::MOVr:
1166       case ARM::tMOVr:
1167         Offset = 0;
1168         break;
1169       case ARM::ADDri:
1170         Offset = -MI->getOperand(2).getImm();
1171         break;
1172       case ARM::SUBri:
1173       case ARM::t2SUBri:
1174         Offset = MI->getOperand(2).getImm();
1175         break;
1176       case ARM::tSUBspi:
1177         Offset = MI->getOperand(2).getImm()*4;
1178         break;
1179       case ARM::tADDspi:
1180       case ARM::tADDrSPi:
1181         Offset = -MI->getOperand(2).getImm()*4;
1182         break;
1183       case ARM::tLDRpci: {
1184         // Grab the constpool index and check, whether it corresponds to
1185         // original or cloned constpool entry.
1186         unsigned CPI = MI->getOperand(1).getIndex();
1187         const MachineConstantPool *MCP = MF.getConstantPool();
1188         if (CPI >= MCP->getConstants().size())
1189           CPI = AFI.getOriginalCPIdx(CPI);
1190         assert(CPI != -1U && "Invalid constpool index");
1191 
1192         // Derive the actual offset.
1193         const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1194         assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1195         // FIXME: Check for user, it should be "add" instruction!
1196         Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1197         break;
1198       }
1199       }
1200 
1201       if (DstReg == FramePtr && FramePtr != ARM::SP)
1202         // Set-up of the frame pointer. Positive values correspond to "add"
1203         // instruction.
1204         OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1205       else if (DstReg == ARM::SP) {
1206         // Change of SP by an offset. Positive values correspond to "sub"
1207         // instruction.
1208         OutStreamer.EmitPad(Offset);
1209       } else {
1210         MI->dump();
1211         llvm_unreachable("Unsupported opcode for unwinding information");
1212       }
1213     } else if (DstReg == ARM::SP) {
1214       // FIXME: .movsp goes here
1215       MI->dump();
1216       llvm_unreachable("Unsupported opcode for unwinding information");
1217     }
1218     else {
1219       MI->dump();
1220       llvm_unreachable("Unsupported opcode for unwinding information");
1221     }
1222   }
1223 }
1224 
1225 extern cl::opt<bool> EnableARMEHABI;
1226 
1227 // Simple pseudo-instructions have their lowering (with expansion to real
1228 // instructions) auto-generated.
1229 #include "ARMGenMCPseudoLowering.inc"
1230 
1231 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1232   // If we just ended a constant pool, mark it as such.
1233   if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1234     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1235     InConstantPool = false;
1236   }
1237 
1238   // Emit unwinding stuff for frame-related instructions
1239   if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1240     EmitUnwindingInstruction(MI);
1241 
1242   // Do any auto-generated pseudo lowerings.
1243   if (emitPseudoExpansionLowering(OutStreamer, MI))
1244     return;
1245 
1246   assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1247          "Pseudo flag setting opcode should be expanded early");
1248 
1249   // Check for manual lowerings.
1250   unsigned Opc = MI->getOpcode();
1251   switch (Opc) {
1252   case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1253   case ARM::DBG_VALUE: {
1254     if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1255       SmallString<128> TmpStr;
1256       raw_svector_ostream OS(TmpStr);
1257       PrintDebugValueComment(MI, OS);
1258       OutStreamer.EmitRawText(StringRef(OS.str()));
1259     }
1260     return;
1261   }
1262   case ARM::LEApcrel:
1263   case ARM::tLEApcrel:
1264   case ARM::t2LEApcrel: {
1265     // FIXME: Need to also handle globals and externals
1266     MCInst TmpInst;
1267     TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1268                       : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1269                          : ARM::ADR));
1270     populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1271                         GetCPISymbol(MI->getOperand(1).getIndex()),
1272                         MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1273                         OutContext);
1274     OutStreamer.EmitInstruction(TmpInst);
1275     return;
1276   }
1277   case ARM::LEApcrelJT:
1278   case ARM::tLEApcrelJT:
1279   case ARM::t2LEApcrelJT: {
1280     MCInst TmpInst;
1281     TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1282                       : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1283                          : ARM::ADR));
1284     populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1285                       GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1286                                                   MI->getOperand(2).getImm()),
1287                       MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1288                       OutContext);
1289     OutStreamer.EmitInstruction(TmpInst);
1290     return;
1291   }
1292   // Darwin call instructions are just normal call instructions with different
1293   // clobber semantics (they clobber R9).
1294   case ARM::BX_CALL: {
1295     {
1296       MCInst TmpInst;
1297       TmpInst.setOpcode(ARM::MOVr);
1298       TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1299       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1300       // Add predicate operands.
1301       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1302       TmpInst.addOperand(MCOperand::CreateReg(0));
1303       // Add 's' bit operand (always reg0 for this)
1304       TmpInst.addOperand(MCOperand::CreateReg(0));
1305       OutStreamer.EmitInstruction(TmpInst);
1306     }
1307     {
1308       MCInst TmpInst;
1309       TmpInst.setOpcode(ARM::BX);
1310       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1311       OutStreamer.EmitInstruction(TmpInst);
1312     }
1313     return;
1314   }
1315   case ARM::tBX_CALL: {
1316     {
1317       MCInst TmpInst;
1318       TmpInst.setOpcode(ARM::tMOVr);
1319       TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1320       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1321       // Add predicate operands.
1322       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1323       TmpInst.addOperand(MCOperand::CreateReg(0));
1324       OutStreamer.EmitInstruction(TmpInst);
1325     }
1326     {
1327       MCInst TmpInst;
1328       TmpInst.setOpcode(ARM::tBX);
1329       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1330       // Add predicate operands.
1331       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1332       TmpInst.addOperand(MCOperand::CreateReg(0));
1333       OutStreamer.EmitInstruction(TmpInst);
1334     }
1335     return;
1336   }
1337   case ARM::BMOVPCRX_CALL: {
1338     {
1339       MCInst TmpInst;
1340       TmpInst.setOpcode(ARM::MOVr);
1341       TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1342       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1343       // Add predicate operands.
1344       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1345       TmpInst.addOperand(MCOperand::CreateReg(0));
1346       // Add 's' bit operand (always reg0 for this)
1347       TmpInst.addOperand(MCOperand::CreateReg(0));
1348       OutStreamer.EmitInstruction(TmpInst);
1349     }
1350     {
1351       MCInst TmpInst;
1352       TmpInst.setOpcode(ARM::MOVr);
1353       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1354       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1355       // Add predicate operands.
1356       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1357       TmpInst.addOperand(MCOperand::CreateReg(0));
1358       // Add 's' bit operand (always reg0 for this)
1359       TmpInst.addOperand(MCOperand::CreateReg(0));
1360       OutStreamer.EmitInstruction(TmpInst);
1361     }
1362     return;
1363   }
1364   case ARM::BMOVPCB_CALL: {
1365     {
1366       MCInst TmpInst;
1367       TmpInst.setOpcode(ARM::MOVr);
1368       TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1369       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1370       // Add predicate operands.
1371       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1372       TmpInst.addOperand(MCOperand::CreateReg(0));
1373       // Add 's' bit operand (always reg0 for this)
1374       TmpInst.addOperand(MCOperand::CreateReg(0));
1375       OutStreamer.EmitInstruction(TmpInst);
1376     }
1377     {
1378       MCInst TmpInst;
1379       TmpInst.setOpcode(ARM::Bcc);
1380       const GlobalValue *GV = MI->getOperand(0).getGlobal();
1381       MCSymbol *GVSym = Mang->getSymbol(GV);
1382       const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1383       TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1384       // Add predicate operands.
1385       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1386       TmpInst.addOperand(MCOperand::CreateReg(0));
1387       OutStreamer.EmitInstruction(TmpInst);
1388     }
1389     return;
1390   }
1391   case ARM::t2BMOVPCB_CALL: {
1392     {
1393       MCInst TmpInst;
1394       TmpInst.setOpcode(ARM::tMOVr);
1395       TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1396       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1397       // Add predicate operands.
1398       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1399       TmpInst.addOperand(MCOperand::CreateReg(0));
1400       OutStreamer.EmitInstruction(TmpInst);
1401     }
1402     {
1403       MCInst TmpInst;
1404       TmpInst.setOpcode(ARM::t2B);
1405       const GlobalValue *GV = MI->getOperand(0).getGlobal();
1406       MCSymbol *GVSym = Mang->getSymbol(GV);
1407       const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1408       TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1409       // Add predicate operands.
1410       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1411       TmpInst.addOperand(MCOperand::CreateReg(0));
1412       OutStreamer.EmitInstruction(TmpInst);
1413     }
1414     return;
1415   }
1416   case ARM::MOVi16_ga_pcrel:
1417   case ARM::t2MOVi16_ga_pcrel: {
1418     MCInst TmpInst;
1419     TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1420     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1421 
1422     unsigned TF = MI->getOperand(1).getTargetFlags();
1423     bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1424     const GlobalValue *GV = MI->getOperand(1).getGlobal();
1425     MCSymbol *GVSym = GetARMGVSymbol(GV);
1426     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1427     if (isPIC) {
1428       MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1429                                        getFunctionNumber(),
1430                                        MI->getOperand(2).getImm(), OutContext);
1431       const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1432       unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1433       const MCExpr *PCRelExpr =
1434         ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1435                                   MCBinaryExpr::CreateAdd(LabelSymExpr,
1436                                       MCConstantExpr::Create(PCAdj, OutContext),
1437                                           OutContext), OutContext), OutContext);
1438       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1439     } else {
1440       const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1441       TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1442     }
1443 
1444     // Add predicate operands.
1445     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1446     TmpInst.addOperand(MCOperand::CreateReg(0));
1447     // Add 's' bit operand (always reg0 for this)
1448     TmpInst.addOperand(MCOperand::CreateReg(0));
1449     OutStreamer.EmitInstruction(TmpInst);
1450     return;
1451   }
1452   case ARM::MOVTi16_ga_pcrel:
1453   case ARM::t2MOVTi16_ga_pcrel: {
1454     MCInst TmpInst;
1455     TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1456                       ? ARM::MOVTi16 : ARM::t2MOVTi16);
1457     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1458     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1459 
1460     unsigned TF = MI->getOperand(2).getTargetFlags();
1461     bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1462     const GlobalValue *GV = MI->getOperand(2).getGlobal();
1463     MCSymbol *GVSym = GetARMGVSymbol(GV);
1464     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1465     if (isPIC) {
1466       MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1467                                        getFunctionNumber(),
1468                                        MI->getOperand(3).getImm(), OutContext);
1469       const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1470       unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1471       const MCExpr *PCRelExpr =
1472         ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1473                                    MCBinaryExpr::CreateAdd(LabelSymExpr,
1474                                       MCConstantExpr::Create(PCAdj, OutContext),
1475                                           OutContext), OutContext), OutContext);
1476       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1477     } else {
1478       const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1479       TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1480     }
1481     // Add predicate operands.
1482     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1483     TmpInst.addOperand(MCOperand::CreateReg(0));
1484     // Add 's' bit operand (always reg0 for this)
1485     TmpInst.addOperand(MCOperand::CreateReg(0));
1486     OutStreamer.EmitInstruction(TmpInst);
1487     return;
1488   }
1489   case ARM::tPICADD: {
1490     // This is a pseudo op for a label + instruction sequence, which looks like:
1491     // LPC0:
1492     //     add r0, pc
1493     // This adds the address of LPC0 to r0.
1494 
1495     // Emit the label.
1496     OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1497                           getFunctionNumber(), MI->getOperand(2).getImm(),
1498                           OutContext));
1499 
1500     // Form and emit the add.
1501     MCInst AddInst;
1502     AddInst.setOpcode(ARM::tADDhirr);
1503     AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1504     AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1505     AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1506     // Add predicate operands.
1507     AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1508     AddInst.addOperand(MCOperand::CreateReg(0));
1509     OutStreamer.EmitInstruction(AddInst);
1510     return;
1511   }
1512   case ARM::PICADD: {
1513     // This is a pseudo op for a label + instruction sequence, which looks like:
1514     // LPC0:
1515     //     add r0, pc, r0
1516     // This adds the address of LPC0 to r0.
1517 
1518     // Emit the label.
1519     OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1520                           getFunctionNumber(), MI->getOperand(2).getImm(),
1521                           OutContext));
1522 
1523     // Form and emit the add.
1524     MCInst AddInst;
1525     AddInst.setOpcode(ARM::ADDrr);
1526     AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1527     AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1528     AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1529     // Add predicate operands.
1530     AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1531     AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1532     // Add 's' bit operand (always reg0 for this)
1533     AddInst.addOperand(MCOperand::CreateReg(0));
1534     OutStreamer.EmitInstruction(AddInst);
1535     return;
1536   }
1537   case ARM::PICSTR:
1538   case ARM::PICSTRB:
1539   case ARM::PICSTRH:
1540   case ARM::PICLDR:
1541   case ARM::PICLDRB:
1542   case ARM::PICLDRH:
1543   case ARM::PICLDRSB:
1544   case ARM::PICLDRSH: {
1545     // This is a pseudo op for a label + instruction sequence, which looks like:
1546     // LPC0:
1547     //     OP r0, [pc, r0]
1548     // The LCP0 label is referenced by a constant pool entry in order to get
1549     // a PC-relative address at the ldr instruction.
1550 
1551     // Emit the label.
1552     OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1553                           getFunctionNumber(), MI->getOperand(2).getImm(),
1554                           OutContext));
1555 
1556     // Form and emit the load
1557     unsigned Opcode;
1558     switch (MI->getOpcode()) {
1559     default:
1560       llvm_unreachable("Unexpected opcode!");
1561     case ARM::PICSTR:   Opcode = ARM::STRrs; break;
1562     case ARM::PICSTRB:  Opcode = ARM::STRBrs; break;
1563     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
1564     case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
1565     case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
1566     case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
1567     case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1568     case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1569     }
1570     MCInst LdStInst;
1571     LdStInst.setOpcode(Opcode);
1572     LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1573     LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1574     LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1575     LdStInst.addOperand(MCOperand::CreateImm(0));
1576     // Add predicate operands.
1577     LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1578     LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1579     OutStreamer.EmitInstruction(LdStInst);
1580 
1581     return;
1582   }
1583   case ARM::CONSTPOOL_ENTRY: {
1584     /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1585     /// in the function.  The first operand is the ID# for this instruction, the
1586     /// second is the index into the MachineConstantPool that this is, the third
1587     /// is the size in bytes of this constant pool entry.
1588     /// The required alignment is specified on the basic block holding this MI.
1589     unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1590     unsigned CPIdx   = (unsigned)MI->getOperand(1).getIndex();
1591 
1592     // If this is the first entry of the pool, mark it.
1593     if (!InConstantPool) {
1594       OutStreamer.EmitDataRegion(MCDR_DataRegion);
1595       InConstantPool = true;
1596     }
1597 
1598     OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1599 
1600     const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1601     if (MCPE.isMachineConstantPoolEntry())
1602       EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1603     else
1604       EmitGlobalConstant(MCPE.Val.ConstVal);
1605     return;
1606   }
1607   case ARM::t2BR_JT: {
1608     // Lower and emit the instruction itself, then the jump table following it.
1609     MCInst TmpInst;
1610     TmpInst.setOpcode(ARM::tMOVr);
1611     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1612     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1613     // Add predicate operands.
1614     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1615     TmpInst.addOperand(MCOperand::CreateReg(0));
1616     OutStreamer.EmitInstruction(TmpInst);
1617     // Output the data for the jump table itself
1618     EmitJump2Table(MI);
1619     return;
1620   }
1621   case ARM::t2TBB_JT: {
1622     // Lower and emit the instruction itself, then the jump table following it.
1623     MCInst TmpInst;
1624 
1625     TmpInst.setOpcode(ARM::t2TBB);
1626     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1627     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1628     // Add predicate operands.
1629     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1630     TmpInst.addOperand(MCOperand::CreateReg(0));
1631     OutStreamer.EmitInstruction(TmpInst);
1632     // Output the data for the jump table itself
1633     EmitJump2Table(MI);
1634     // Make sure the next instruction is 2-byte aligned.
1635     EmitAlignment(1);
1636     return;
1637   }
1638   case ARM::t2TBH_JT: {
1639     // Lower and emit the instruction itself, then the jump table following it.
1640     MCInst TmpInst;
1641 
1642     TmpInst.setOpcode(ARM::t2TBH);
1643     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1644     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1645     // Add predicate operands.
1646     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1647     TmpInst.addOperand(MCOperand::CreateReg(0));
1648     OutStreamer.EmitInstruction(TmpInst);
1649     // Output the data for the jump table itself
1650     EmitJump2Table(MI);
1651     return;
1652   }
1653   case ARM::tBR_JTr:
1654   case ARM::BR_JTr: {
1655     // Lower and emit the instruction itself, then the jump table following it.
1656     // mov pc, target
1657     MCInst TmpInst;
1658     unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1659       ARM::MOVr : ARM::tMOVr;
1660     TmpInst.setOpcode(Opc);
1661     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1662     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1663     // Add predicate operands.
1664     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1665     TmpInst.addOperand(MCOperand::CreateReg(0));
1666     // Add 's' bit operand (always reg0 for this)
1667     if (Opc == ARM::MOVr)
1668       TmpInst.addOperand(MCOperand::CreateReg(0));
1669     OutStreamer.EmitInstruction(TmpInst);
1670 
1671     // Make sure the Thumb jump table is 4-byte aligned.
1672     if (Opc == ARM::tMOVr)
1673       EmitAlignment(2);
1674 
1675     // Output the data for the jump table itself
1676     EmitJumpTable(MI);
1677     return;
1678   }
1679   case ARM::BR_JTm: {
1680     // Lower and emit the instruction itself, then the jump table following it.
1681     // ldr pc, target
1682     MCInst TmpInst;
1683     if (MI->getOperand(1).getReg() == 0) {
1684       // literal offset
1685       TmpInst.setOpcode(ARM::LDRi12);
1686       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1687       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1688       TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1689     } else {
1690       TmpInst.setOpcode(ARM::LDRrs);
1691       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1692       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1693       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1694       TmpInst.addOperand(MCOperand::CreateImm(0));
1695     }
1696     // Add predicate operands.
1697     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1698     TmpInst.addOperand(MCOperand::CreateReg(0));
1699     OutStreamer.EmitInstruction(TmpInst);
1700 
1701     // Output the data for the jump table itself
1702     EmitJumpTable(MI);
1703     return;
1704   }
1705   case ARM::BR_JTadd: {
1706     // Lower and emit the instruction itself, then the jump table following it.
1707     // add pc, target, idx
1708     MCInst TmpInst;
1709     TmpInst.setOpcode(ARM::ADDrr);
1710     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1711     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1712     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1713     // Add predicate operands.
1714     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1715     TmpInst.addOperand(MCOperand::CreateReg(0));
1716     // Add 's' bit operand (always reg0 for this)
1717     TmpInst.addOperand(MCOperand::CreateReg(0));
1718     OutStreamer.EmitInstruction(TmpInst);
1719 
1720     // Output the data for the jump table itself
1721     EmitJumpTable(MI);
1722     return;
1723   }
1724   case ARM::TRAP: {
1725     // Non-Darwin binutils don't yet support the "trap" mnemonic.
1726     // FIXME: Remove this special case when they do.
1727     if (!Subtarget->isTargetDarwin()) {
1728       //.long 0xe7ffdefe @ trap
1729       uint32_t Val = 0xe7ffdefeUL;
1730       OutStreamer.AddComment("trap");
1731       OutStreamer.EmitIntValue(Val, 4);
1732       return;
1733     }
1734     break;
1735   }
1736   case ARM::tTRAP: {
1737     // Non-Darwin binutils don't yet support the "trap" mnemonic.
1738     // FIXME: Remove this special case when they do.
1739     if (!Subtarget->isTargetDarwin()) {
1740       //.short 57086 @ trap
1741       uint16_t Val = 0xdefe;
1742       OutStreamer.AddComment("trap");
1743       OutStreamer.EmitIntValue(Val, 2);
1744       return;
1745     }
1746     break;
1747   }
1748   case ARM::t2Int_eh_sjlj_setjmp:
1749   case ARM::t2Int_eh_sjlj_setjmp_nofp:
1750   case ARM::tInt_eh_sjlj_setjmp: {
1751     // Two incoming args: GPR:$src, GPR:$val
1752     // mov $val, pc
1753     // adds $val, #7
1754     // str $val, [$src, #4]
1755     // movs r0, #0
1756     // b 1f
1757     // movs r0, #1
1758     // 1:
1759     unsigned SrcReg = MI->getOperand(0).getReg();
1760     unsigned ValReg = MI->getOperand(1).getReg();
1761     MCSymbol *Label = GetARMSJLJEHLabel();
1762     {
1763       MCInst TmpInst;
1764       TmpInst.setOpcode(ARM::tMOVr);
1765       TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1766       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1767       // Predicate.
1768       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1769       TmpInst.addOperand(MCOperand::CreateReg(0));
1770       OutStreamer.AddComment("eh_setjmp begin");
1771       OutStreamer.EmitInstruction(TmpInst);
1772     }
1773     {
1774       MCInst TmpInst;
1775       TmpInst.setOpcode(ARM::tADDi3);
1776       TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1777       // 's' bit operand
1778       TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1779       TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1780       TmpInst.addOperand(MCOperand::CreateImm(7));
1781       // Predicate.
1782       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1783       TmpInst.addOperand(MCOperand::CreateReg(0));
1784       OutStreamer.EmitInstruction(TmpInst);
1785     }
1786     {
1787       MCInst TmpInst;
1788       TmpInst.setOpcode(ARM::tSTRi);
1789       TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1790       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1791       // The offset immediate is #4. The operand value is scaled by 4 for the
1792       // tSTR instruction.
1793       TmpInst.addOperand(MCOperand::CreateImm(1));
1794       // Predicate.
1795       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1796       TmpInst.addOperand(MCOperand::CreateReg(0));
1797       OutStreamer.EmitInstruction(TmpInst);
1798     }
1799     {
1800       MCInst TmpInst;
1801       TmpInst.setOpcode(ARM::tMOVi8);
1802       TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1803       TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1804       TmpInst.addOperand(MCOperand::CreateImm(0));
1805       // Predicate.
1806       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1807       TmpInst.addOperand(MCOperand::CreateReg(0));
1808       OutStreamer.EmitInstruction(TmpInst);
1809     }
1810     {
1811       const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1812       MCInst TmpInst;
1813       TmpInst.setOpcode(ARM::tB);
1814       TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1815       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1816       TmpInst.addOperand(MCOperand::CreateReg(0));
1817       OutStreamer.EmitInstruction(TmpInst);
1818     }
1819     {
1820       MCInst TmpInst;
1821       TmpInst.setOpcode(ARM::tMOVi8);
1822       TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1823       TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1824       TmpInst.addOperand(MCOperand::CreateImm(1));
1825       // Predicate.
1826       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1827       TmpInst.addOperand(MCOperand::CreateReg(0));
1828       OutStreamer.AddComment("eh_setjmp end");
1829       OutStreamer.EmitInstruction(TmpInst);
1830     }
1831     OutStreamer.EmitLabel(Label);
1832     return;
1833   }
1834 
1835   case ARM::Int_eh_sjlj_setjmp_nofp:
1836   case ARM::Int_eh_sjlj_setjmp: {
1837     // Two incoming args: GPR:$src, GPR:$val
1838     // add $val, pc, #8
1839     // str $val, [$src, #+4]
1840     // mov r0, #0
1841     // add pc, pc, #0
1842     // mov r0, #1
1843     unsigned SrcReg = MI->getOperand(0).getReg();
1844     unsigned ValReg = MI->getOperand(1).getReg();
1845 
1846     {
1847       MCInst TmpInst;
1848       TmpInst.setOpcode(ARM::ADDri);
1849       TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1850       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1851       TmpInst.addOperand(MCOperand::CreateImm(8));
1852       // Predicate.
1853       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1854       TmpInst.addOperand(MCOperand::CreateReg(0));
1855       // 's' bit operand (always reg0 for this).
1856       TmpInst.addOperand(MCOperand::CreateReg(0));
1857       OutStreamer.AddComment("eh_setjmp begin");
1858       OutStreamer.EmitInstruction(TmpInst);
1859     }
1860     {
1861       MCInst TmpInst;
1862       TmpInst.setOpcode(ARM::STRi12);
1863       TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1864       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1865       TmpInst.addOperand(MCOperand::CreateImm(4));
1866       // Predicate.
1867       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1868       TmpInst.addOperand(MCOperand::CreateReg(0));
1869       OutStreamer.EmitInstruction(TmpInst);
1870     }
1871     {
1872       MCInst TmpInst;
1873       TmpInst.setOpcode(ARM::MOVi);
1874       TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1875       TmpInst.addOperand(MCOperand::CreateImm(0));
1876       // Predicate.
1877       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1878       TmpInst.addOperand(MCOperand::CreateReg(0));
1879       // 's' bit operand (always reg0 for this).
1880       TmpInst.addOperand(MCOperand::CreateReg(0));
1881       OutStreamer.EmitInstruction(TmpInst);
1882     }
1883     {
1884       MCInst TmpInst;
1885       TmpInst.setOpcode(ARM::ADDri);
1886       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1887       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1888       TmpInst.addOperand(MCOperand::CreateImm(0));
1889       // Predicate.
1890       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1891       TmpInst.addOperand(MCOperand::CreateReg(0));
1892       // 's' bit operand (always reg0 for this).
1893       TmpInst.addOperand(MCOperand::CreateReg(0));
1894       OutStreamer.EmitInstruction(TmpInst);
1895     }
1896     {
1897       MCInst TmpInst;
1898       TmpInst.setOpcode(ARM::MOVi);
1899       TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1900       TmpInst.addOperand(MCOperand::CreateImm(1));
1901       // Predicate.
1902       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1903       TmpInst.addOperand(MCOperand::CreateReg(0));
1904       // 's' bit operand (always reg0 for this).
1905       TmpInst.addOperand(MCOperand::CreateReg(0));
1906       OutStreamer.AddComment("eh_setjmp end");
1907       OutStreamer.EmitInstruction(TmpInst);
1908     }
1909     return;
1910   }
1911   case ARM::Int_eh_sjlj_longjmp: {
1912     // ldr sp, [$src, #8]
1913     // ldr $scratch, [$src, #4]
1914     // ldr r7, [$src]
1915     // bx $scratch
1916     unsigned SrcReg = MI->getOperand(0).getReg();
1917     unsigned ScratchReg = MI->getOperand(1).getReg();
1918     {
1919       MCInst TmpInst;
1920       TmpInst.setOpcode(ARM::LDRi12);
1921       TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1922       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1923       TmpInst.addOperand(MCOperand::CreateImm(8));
1924       // Predicate.
1925       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1926       TmpInst.addOperand(MCOperand::CreateReg(0));
1927       OutStreamer.EmitInstruction(TmpInst);
1928     }
1929     {
1930       MCInst TmpInst;
1931       TmpInst.setOpcode(ARM::LDRi12);
1932       TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1933       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1934       TmpInst.addOperand(MCOperand::CreateImm(4));
1935       // Predicate.
1936       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1937       TmpInst.addOperand(MCOperand::CreateReg(0));
1938       OutStreamer.EmitInstruction(TmpInst);
1939     }
1940     {
1941       MCInst TmpInst;
1942       TmpInst.setOpcode(ARM::LDRi12);
1943       TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1944       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1945       TmpInst.addOperand(MCOperand::CreateImm(0));
1946       // Predicate.
1947       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1948       TmpInst.addOperand(MCOperand::CreateReg(0));
1949       OutStreamer.EmitInstruction(TmpInst);
1950     }
1951     {
1952       MCInst TmpInst;
1953       TmpInst.setOpcode(ARM::BX);
1954       TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1955       // Predicate.
1956       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1957       TmpInst.addOperand(MCOperand::CreateReg(0));
1958       OutStreamer.EmitInstruction(TmpInst);
1959     }
1960     return;
1961   }
1962   case ARM::tInt_eh_sjlj_longjmp: {
1963     // ldr $scratch, [$src, #8]
1964     // mov sp, $scratch
1965     // ldr $scratch, [$src, #4]
1966     // ldr r7, [$src]
1967     // bx $scratch
1968     unsigned SrcReg = MI->getOperand(0).getReg();
1969     unsigned ScratchReg = MI->getOperand(1).getReg();
1970     {
1971       MCInst TmpInst;
1972       TmpInst.setOpcode(ARM::tLDRi);
1973       TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1974       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1975       // The offset immediate is #8. The operand value is scaled by 4 for the
1976       // tLDR instruction.
1977       TmpInst.addOperand(MCOperand::CreateImm(2));
1978       // Predicate.
1979       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1980       TmpInst.addOperand(MCOperand::CreateReg(0));
1981       OutStreamer.EmitInstruction(TmpInst);
1982     }
1983     {
1984       MCInst TmpInst;
1985       TmpInst.setOpcode(ARM::tMOVr);
1986       TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1987       TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1988       // Predicate.
1989       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1990       TmpInst.addOperand(MCOperand::CreateReg(0));
1991       OutStreamer.EmitInstruction(TmpInst);
1992     }
1993     {
1994       MCInst TmpInst;
1995       TmpInst.setOpcode(ARM::tLDRi);
1996       TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1997       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1998       TmpInst.addOperand(MCOperand::CreateImm(1));
1999       // Predicate.
2000       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2001       TmpInst.addOperand(MCOperand::CreateReg(0));
2002       OutStreamer.EmitInstruction(TmpInst);
2003     }
2004     {
2005       MCInst TmpInst;
2006       TmpInst.setOpcode(ARM::tLDRi);
2007       TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
2008       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
2009       TmpInst.addOperand(MCOperand::CreateImm(0));
2010       // Predicate.
2011       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2012       TmpInst.addOperand(MCOperand::CreateReg(0));
2013       OutStreamer.EmitInstruction(TmpInst);
2014     }
2015     {
2016       MCInst TmpInst;
2017       TmpInst.setOpcode(ARM::tBX);
2018       TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2019       // Predicate.
2020       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2021       TmpInst.addOperand(MCOperand::CreateReg(0));
2022       OutStreamer.EmitInstruction(TmpInst);
2023     }
2024     return;
2025   }
2026   }
2027 
2028   MCInst TmpInst;
2029   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2030 
2031   OutStreamer.EmitInstruction(TmpInst);
2032 }
2033 
2034 //===----------------------------------------------------------------------===//
2035 // Target Registry Stuff
2036 //===----------------------------------------------------------------------===//
2037 
2038 // Force static initialization.
2039 extern "C" void LLVMInitializeARMAsmPrinter() {
2040   RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
2041   RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
2042 }
2043