1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Target-independent interfaces which we are implementing 15//===----------------------------------------------------------------------===// 16 17include "llvm/Target/Target.td" 18 19//===----------------------------------------------------------------------===// 20// ARM Helper classes. 21// 22 23class ProcNoItin<string Name, list<SubtargetFeature> Features> 24 : Processor<Name, NoItineraries, Features>; 25 26class Architecture<string fname, string aname, list<SubtargetFeature> features > 27 : SubtargetFeature<fname, "ARMArch", aname, 28 !strconcat(aname, " architecture"), features>; 29 30//===----------------------------------------------------------------------===// 31// ARM Subtarget state. 32// 33 34def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true", 35 "Thumb mode">; 36 37def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true", 38 "Use software floating point features.">; 39 40//===----------------------------------------------------------------------===// 41// ARM Subtarget features. 42// 43 44def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 45 "Enable VFP2 instructions">; 46def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true", 47 "Enable VFP3 instructions", 48 [FeatureVFP2]>; 49def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 50 "Enable NEON instructions", 51 [FeatureVFP3]>; 52def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 53 "Enable Thumb2 instructions">; 54def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 55 "Does not support ARM mode execution", 56 [ModeThumb]>; 57def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 58 "Enable half-precision floating point">; 59def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true", 60 "Enable VFP4 instructions", 61 [FeatureVFP3, FeatureFP16]>; 62def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", 63 "true", "Enable ARMv8 FP", 64 [FeatureVFP4]>; 65def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 66 "Enable full half-precision floating point", 67 [FeatureFPARMv8]>; 68def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true", 69 "Restrict FP to 16 double registers">; 70def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true", 71 "Enable divide instructions">; 72def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", 73 "HasHardwareDivideInARM", "true", 74 "Enable divide instructions in ARM mode">; 75def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true", 76 "Enable Thumb2 extract and pack instructions">; 77def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 78 "Has data barrier (dmb / dsb) instructions">; 79def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", 80 "Has v7 clrex instruction">; 81def FeatureAcquireRelease : SubtargetFeature<"acquire-release", 82 "HasAcquireRelease", "true", 83 "Has v8 acquire/release (lda/ldaex etc) instructions">; 84def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 85 "FP compare + branch is slow">; 86def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true", 87 "Floating point unit supports single precision only">; 88def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 89 "Enable support for Performance Monitor extensions">; 90def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", 91 "Enable support for TrustZone security extensions">; 92def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true", 93 "Enable support for ARMv8-M Security Extensions">; 94def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 95 "Enable support for Cryptography extensions", 96 [FeatureNEON]>; 97def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 98 "Enable support for CRC instructions">; 99// Not to be confused with FeatureHasRetAddrStack (return address stack) 100def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 101 "Enable Reliability, Availability and Serviceability extensions">; 102 103 104// Cyclone has preferred instructions for zeroing VFP registers, which can 105// execute in 0 cycles. 106def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 107 "Has zero-cycle zeroing instructions">; 108 109// Whether or not it may be profitable to unpredicate certain instructions 110// during if conversion. 111def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr", 112 "IsProfitableToUnpredicate", 113 "true", 114 "Is profitable to unpredicate">; 115 116// Some targets (e.g. Swift) have microcoded VGETLNi32. 117def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32", 118 "HasSlowVGETLNi32", "true", 119 "Has slow VGETLNi32 - prefer VMOV">; 120 121// Some targets (e.g. Swift) have microcoded VDUP32. 122def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", "true", 123 "Has slow VDUP32 - prefer VMOV">; 124 125// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON 126// for scalar FP, as this allows more effective execution domain optimization. 127def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR", 128 "true", "Prefer VMOVSR">; 129 130// Swift has ISHST barriers compatible with Atomic Release semantics but weaker 131// than ISH 132def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST", 133 "true", "Prefer ISHST barriers">; 134 135// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from 136// VFP to NEON, as an execution domain optimization. 137def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", "UseNEONForFPMovs", 138 "true", "Convert VMOVSR, VMOVRS, VMOVS to NEON">; 139 140// Some processors benefit from using NEON instructions for scalar 141// single-precision FP operations. This affects instruction selection and should 142// only be enabled if the handling of denormals is not important. 143def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", 144 "true", 145 "Use NEON for single precision FP">; 146 147// On some processors, VLDn instructions that access unaligned data take one 148// extra cycle. Take that into account when computing operand latencies. 149def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign", 150 "true", 151 "Check for VLDn unaligned access">; 152 153// Some processors have a nonpipelined VFP coprocessor. 154def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp", 155 "NonpipelinedVFP", "true", 156 "VFP instructions are not pipelined">; 157 158// Some processors have FP multiply-accumulate instructions that don't 159// play nicely with other VFP / NEON instructions, and it's generally better 160// to just not use them. 161def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 162 "Disable VFP / NEON MAC instructions">; 163 164// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 165def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 166 "HasVMLxForwarding", "true", 167 "Has multiplier accumulator forwarding">; 168 169// Disable 32-bit to 16-bit narrowing for experimentation. 170def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 171 "Prefer 32-bit Thumb instrs">; 172 173/// Some instructions update CPSR partially, which can add false dependency for 174/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 175/// mapped to a separate physical register. Avoid partial CPSR update for these 176/// processors. 177def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 178 "AvoidCPSRPartialUpdate", "true", 179 "Avoid CPSR partial update for OOO execution">; 180 181def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", 182 "AvoidMOVsShifterOperand", "true", 183 "Avoid movs instructions with shifter operand">; 184 185// Some processors perform return stack prediction. CodeGen should avoid issue 186// "normal" call instructions to callees which do not return. 187def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", "HasRetAddrStack", "true", 188 "Has return address stack">; 189 190/// DSP extension. 191def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", 192 "Supports DSP instructions in ARM and/or Thumb2">; 193 194// Multiprocessing extension. 195def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 196 "Supports Multiprocessing extension">; 197 198// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). 199def FeatureVirtualization : SubtargetFeature<"virtualization", 200 "HasVirtualization", "true", 201 "Supports Virtualization extension", 202 [FeatureHWDiv, FeatureHWDivARM]>; 203 204// M-series ISA 205def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", 206 "Is microcontroller profile ('M' series)">; 207 208// R-series ISA 209def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", 210 "Is realtime profile ('R' series)">; 211 212// A-series ISA 213def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", 214 "Is application profile ('A' series)">; 215 216// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. 217// See ARMInstrInfo.td for details. 218def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", 219 "NaCl trap">; 220 221def FeatureStrictAlign : SubtargetFeature<"strict-align", 222 "StrictAlign", "true", 223 "Disallow all unaligned memory " 224 "access">; 225 226def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", 227 "Generate calls via indirect call " 228 "instructions">; 229 230def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", 231 "Reserve R9, making it unavailable as " 232 "GPR">; 233 234def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", 235 "Don't use movt/movw pairs for 32-bit " 236 "imms">; 237 238 239//===----------------------------------------------------------------------===// 240// ARM ISAa. 241// 242 243def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 244 "Support ARM v4T instructions">; 245def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 246 "Support ARM v5T instructions", 247 [HasV4TOps]>; 248def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 249 "Support ARM v5TE, v5TEj, and v5TExp instructions", 250 [HasV5TOps]>; 251def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 252 "Support ARM v6 instructions", 253 [HasV5TEOps]>; 254def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", 255 "Support ARM v6M instructions", 256 [HasV6Ops]>; 257def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true", 258 "Support ARM v8M Baseline instructions", 259 [HasV6MOps]>; 260def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true", 261 "Support ARM v6k instructions", 262 [HasV6Ops]>; 263def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 264 "Support ARM v6t2 instructions", 265 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>; 266def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 267 "Support ARM v7 instructions", 268 [HasV6T2Ops, FeaturePerfMon, 269 FeatureV7Clrex]>; 270def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", 271 "Support ARM v8 instructions", 272 [HasV7Ops, FeatureAcquireRelease]>; 273def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 274 "Support ARM v8.1a instructions", 275 [HasV8Ops]>; 276def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 277 "Support ARM v8.2a instructions", 278 [HasV8_1aOps]>; 279def HasV8MMainlineOps : SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true", 280 "Support ARM v8M Mainline instructions", 281 [HasV7Ops]>; 282 283 284//===----------------------------------------------------------------------===// 285// ARM Processor subtarget features. 286// 287 288def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", 289 "Cortex-A5 ARM processors", []>; 290def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", 291 "Cortex-A7 ARM processors", []>; 292def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 293 "Cortex-A8 ARM processors", []>; 294def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 295 "Cortex-A9 ARM processors", []>; 296def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", 297 "Cortex-A12 ARM processors", []>; 298def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", 299 "Cortex-A15 ARM processors", []>; 300def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", 301 "Cortex-A17 ARM processors", []>; 302def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32", 303 "Cortex-A32 ARM processors", []>; 304def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 305 "Cortex-A35 ARM processors", []>; 306def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 307 "Cortex-A53 ARM processors", []>; 308def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 309 "Cortex-A57 ARM processors", []>; 310def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 311 "Cortex-A72 ARM processors", []>; 312def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 313 "Cortex-A73 ARM processors", []>; 314 315def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", 316 "Qualcomm ARM processors", []>; 317def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", 318 "Swift ARM processors", []>; 319 320def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1", 321 "Samsung Exynos-M1 processors", []>; 322 323def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", 324 "Cortex-R4 ARM processors", []>; 325def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", 326 "Cortex-R5 ARM processors", []>; 327def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", 328 "Cortex-R7 ARM processors", []>; 329 330def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", 331 "Cortex-M3 ARM processors", []>; 332 333//===----------------------------------------------------------------------===// 334// ARM schedules. 335// 336 337include "ARMSchedule.td" 338 339 340//===----------------------------------------------------------------------===// 341// ARM architectures 342// 343 344def ARMv2 : Architecture<"armv2", "ARMv2", []>; 345 346def ARMv2a : Architecture<"armv2a", "ARMv2a", []>; 347 348def ARMv3 : Architecture<"armv3", "ARMv3", []>; 349 350def ARMv3m : Architecture<"armv3m", "ARMv3m", []>; 351 352def ARMv4 : Architecture<"armv4", "ARMv4", []>; 353 354def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>; 355 356def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>; 357 358def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>; 359 360def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>; 361 362def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>; 363 364def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, 365 FeatureDSP]>; 366 367def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; 368 369def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, 370 FeatureTrustZone]>; 371 372def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, 373 FeatureNoARM, 374 FeatureDB, 375 FeatureMClass]>; 376 377def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, 378 FeatureNoARM, 379 FeatureDB, 380 FeatureMClass]>; 381 382def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, 383 FeatureNEON, 384 FeatureDB, 385 FeatureDSP, 386 FeatureAClass]>; 387 388def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, 389 FeatureDB, 390 FeatureDSP, 391 FeatureHWDiv, 392 FeatureRClass]>; 393 394def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, 395 FeatureThumb2, 396 FeatureNoARM, 397 FeatureDB, 398 FeatureHWDiv, 399 FeatureMClass]>; 400 401def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, 402 FeatureThumb2, 403 FeatureNoARM, 404 FeatureDB, 405 FeatureHWDiv, 406 FeatureMClass, 407 FeatureDSP, 408 FeatureT2XtPk]>; 409 410def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, 411 FeatureAClass, 412 FeatureDB, 413 FeatureFPARMv8, 414 FeatureNEON, 415 FeatureDSP, 416 FeatureTrustZone, 417 FeatureMP, 418 FeatureVirtualization, 419 FeatureCrypto, 420 FeatureCRC]>; 421 422def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps, 423 FeatureAClass, 424 FeatureDB, 425 FeatureFPARMv8, 426 FeatureNEON, 427 FeatureDSP, 428 FeatureTrustZone, 429 FeatureMP, 430 FeatureVirtualization, 431 FeatureCrypto, 432 FeatureCRC]>; 433 434def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, 435 FeatureAClass, 436 FeatureDB, 437 FeatureFPARMv8, 438 FeatureNEON, 439 FeatureDSP, 440 FeatureTrustZone, 441 FeatureMP, 442 FeatureVirtualization, 443 FeatureCrypto, 444 FeatureCRC, 445 FeatureRAS]>; 446 447def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", 448 [HasV8MBaselineOps, 449 FeatureNoARM, 450 FeatureDB, 451 FeatureHWDiv, 452 FeatureV7Clrex, 453 Feature8MSecExt, 454 FeatureAcquireRelease, 455 FeatureMClass]>; 456 457def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", 458 [HasV8MMainlineOps, 459 FeatureNoARM, 460 FeatureDB, 461 FeatureHWDiv, 462 Feature8MSecExt, 463 FeatureAcquireRelease, 464 FeatureMClass]>; 465 466// Aliases 467def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; 468def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; 469def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; 470def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; 471def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; 472def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; 473 474 475//===----------------------------------------------------------------------===// 476// ARM processors 477// 478 479// Dummy CPU, used to target architectures 480def : ProcNoItin<"generic", []>; 481 482def : ProcNoItin<"arm8", [ARMv4]>; 483def : ProcNoItin<"arm810", [ARMv4]>; 484def : ProcNoItin<"strongarm", [ARMv4]>; 485def : ProcNoItin<"strongarm110", [ARMv4]>; 486def : ProcNoItin<"strongarm1100", [ARMv4]>; 487def : ProcNoItin<"strongarm1110", [ARMv4]>; 488 489def : ProcNoItin<"arm7tdmi", [ARMv4t]>; 490def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>; 491def : ProcNoItin<"arm710t", [ARMv4t]>; 492def : ProcNoItin<"arm720t", [ARMv4t]>; 493def : ProcNoItin<"arm9", [ARMv4t]>; 494def : ProcNoItin<"arm9tdmi", [ARMv4t]>; 495def : ProcNoItin<"arm920", [ARMv4t]>; 496def : ProcNoItin<"arm920t", [ARMv4t]>; 497def : ProcNoItin<"arm922t", [ARMv4t]>; 498def : ProcNoItin<"arm940t", [ARMv4t]>; 499def : ProcNoItin<"ep9312", [ARMv4t]>; 500 501def : ProcNoItin<"arm10tdmi", [ARMv5t]>; 502def : ProcNoItin<"arm1020t", [ARMv5t]>; 503 504def : ProcNoItin<"arm9e", [ARMv5te]>; 505def : ProcNoItin<"arm926ej-s", [ARMv5te]>; 506def : ProcNoItin<"arm946e-s", [ARMv5te]>; 507def : ProcNoItin<"arm966e-s", [ARMv5te]>; 508def : ProcNoItin<"arm968e-s", [ARMv5te]>; 509def : ProcNoItin<"arm10e", [ARMv5te]>; 510def : ProcNoItin<"arm1020e", [ARMv5te]>; 511def : ProcNoItin<"arm1022e", [ARMv5te]>; 512def : ProcNoItin<"xscale", [ARMv5te]>; 513def : ProcNoItin<"iwmmxt", [ARMv5te]>; 514 515def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>; 516def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, 517 FeatureVFP2, 518 FeatureHasSlowFPVMLx]>; 519 520def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>; 521def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>; 522def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>; 523def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>; 524 525def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; 526def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, 527 FeatureVFP2, 528 FeatureHasSlowFPVMLx]>; 529 530def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>; 531def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k, 532 FeatureVFP2, 533 FeatureHasSlowFPVMLx]>; 534 535def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>; 536def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2, 537 FeatureVFP2, 538 FeatureHasSlowFPVMLx]>; 539 540// FIXME: A5 has currently the same Schedule model as A8 541def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5, 542 FeatureHasRetAddrStack, 543 FeatureTrustZone, 544 FeatureSlowFPBrcc, 545 FeatureHasSlowFPVMLx, 546 FeatureVMLxForwarding, 547 FeatureT2XtPk, 548 FeatureMP, 549 FeatureVFP4]>; 550 551def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7, 552 FeatureHasRetAddrStack, 553 FeatureTrustZone, 554 FeatureSlowFPBrcc, 555 FeatureHasSlowFPVMLx, 556 FeatureVMLxForwarding, 557 FeatureT2XtPk, 558 FeatureMP, 559 FeatureVFP4, 560 FeatureHWDiv, 561 FeatureHWDivARM, 562 FeatureVirtualization]>; 563 564def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, 565 FeatureHasRetAddrStack, 566 FeatureNonpipelinedVFP, 567 FeatureTrustZone, 568 FeatureSlowFPBrcc, 569 FeatureHasSlowFPVMLx, 570 FeatureVMLxForwarding, 571 FeatureT2XtPk]>; 572 573def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9, 574 FeatureHasRetAddrStack, 575 FeatureTrustZone, 576 FeatureVMLxForwarding, 577 FeatureT2XtPk, 578 FeatureFP16, 579 FeatureAvoidPartialCPSR, 580 FeaturePreferVMOVSR, 581 FeatureNEONForFPMovs, 582 FeatureCheckVLDnAlign, 583 FeatureMP]>; 584 585// FIXME: A12 has currently the same Schedule model as A9 586def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12, 587 FeatureHasRetAddrStack, 588 FeatureTrustZone, 589 FeatureVMLxForwarding, 590 FeatureT2XtPk, 591 FeatureVFP4, 592 FeatureHWDiv, 593 FeatureHWDivARM, 594 FeatureAvoidPartialCPSR, 595 FeatureVirtualization, 596 FeatureMP]>; 597 598// FIXME: A15 has currently the same Schedule model as A9. 599def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, 600 FeatureHasRetAddrStack, 601 FeatureTrustZone, 602 FeatureT2XtPk, 603 FeatureVFP4, 604 FeatureMP, 605 FeatureCheckVLDnAlign, 606 FeatureHWDiv, 607 FeatureHWDivARM, 608 FeatureAvoidPartialCPSR, 609 FeatureVirtualization]>; 610 611// FIXME: A17 has currently the same Schedule model as A9 612def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17, 613 FeatureHasRetAddrStack, 614 FeatureTrustZone, 615 FeatureMP, 616 FeatureVMLxForwarding, 617 FeatureT2XtPk, 618 FeatureVFP4, 619 FeatureHWDiv, 620 FeatureHWDivARM, 621 FeatureAvoidPartialCPSR, 622 FeatureVirtualization]>; 623 624// FIXME: krait has currently the same Schedule model as A9 625// FIXME: krait has currently the same features as A9 plus VFP4 and hardware 626// division features. 627def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, 628 FeatureHasRetAddrStack, 629 FeatureCheckVLDnAlign, 630 FeatureVMLxForwarding, 631 FeatureT2XtPk, 632 FeatureFP16, 633 FeatureAvoidPartialCPSR, 634 FeatureVFP4, 635 FeatureHWDiv, 636 FeatureHWDivARM]>; 637 638def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, 639 FeatureHasRetAddrStack, 640 FeatureNEONForFP, 641 FeatureT2XtPk, 642 FeatureVFP4, 643 FeatureMP, 644 FeatureHWDiv, 645 FeatureHWDivARM, 646 FeatureAvoidPartialCPSR, 647 FeatureAvoidMOVsShOp, 648 FeatureHasSlowFPVMLx, 649 FeatureProfUnpredicate, 650 FeaturePrefISHSTBarrier, 651 FeatureSlowVGETLNi32, 652 FeatureSlowVDUP32]>; 653 654// FIXME: R4 has currently the same ProcessorModel as A8. 655def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, 656 FeatureHasRetAddrStack, 657 FeatureAvoidPartialCPSR, 658 FeatureT2XtPk]>; 659 660// FIXME: R4F has currently the same ProcessorModel as A8. 661def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4, 662 FeatureHasRetAddrStack, 663 FeatureSlowFPBrcc, 664 FeatureHasSlowFPVMLx, 665 FeatureVFP3, 666 FeatureD16, 667 FeatureAvoidPartialCPSR, 668 FeatureT2XtPk]>; 669 670// FIXME: R5 has currently the same ProcessorModel as A8. 671def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, 672 FeatureHasRetAddrStack, 673 FeatureVFP3, 674 FeatureD16, 675 FeatureSlowFPBrcc, 676 FeatureHWDivARM, 677 FeatureHasSlowFPVMLx, 678 FeatureAvoidPartialCPSR, 679 FeatureT2XtPk]>; 680 681// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5. 682def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, 683 FeatureHasRetAddrStack, 684 FeatureVFP3, 685 FeatureD16, 686 FeatureFP16, 687 FeatureMP, 688 FeatureSlowFPBrcc, 689 FeatureHWDivARM, 690 FeatureHasSlowFPVMLx, 691 FeatureAvoidPartialCPSR, 692 FeatureT2XtPk]>; 693 694def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, 695 FeatureHasRetAddrStack, 696 FeatureVFP3, 697 FeatureD16, 698 FeatureFP16, 699 FeatureMP, 700 FeatureSlowFPBrcc, 701 FeatureHWDivARM, 702 FeatureHasSlowFPVMLx, 703 FeatureAvoidPartialCPSR, 704 FeatureT2XtPk]>; 705 706def : ProcNoItin<"cortex-m3", [ARMv7m, ProcM3]>; 707def : ProcNoItin<"sc300", [ARMv7m, ProcM3]>; 708 709def : ProcNoItin<"cortex-m4", [ARMv7em, 710 FeatureVFP4, 711 FeatureVFPOnlySP, 712 FeatureD16]>; 713 714def : ProcNoItin<"cortex-m7", [ARMv7em, 715 FeatureFPARMv8, 716 FeatureD16]>; 717 718def : ProcNoItin<"cortex-a32", [ARMv8a, 719 FeatureHWDiv, 720 FeatureHWDivARM, 721 FeatureT2XtPk, 722 FeatureCrypto, 723 FeatureCRC]>; 724 725def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, 726 FeatureHWDiv, 727 FeatureHWDivARM, 728 FeatureT2XtPk, 729 FeatureCrypto, 730 FeatureCRC]>; 731 732def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, 733 FeatureHWDiv, 734 FeatureHWDivARM, 735 FeatureT2XtPk, 736 FeatureCrypto, 737 FeatureCRC]>; 738 739def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57, 740 FeatureHWDiv, 741 FeatureHWDivARM, 742 FeatureT2XtPk, 743 FeatureCrypto, 744 FeatureCRC]>; 745 746def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72, 747 FeatureHWDiv, 748 FeatureHWDivARM, 749 FeatureT2XtPk, 750 FeatureCrypto, 751 FeatureCRC]>; 752 753def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73, 754 FeatureHWDiv, 755 FeatureHWDivARM, 756 FeatureT2XtPk, 757 FeatureCrypto, 758 FeatureCRC]>; 759 760// Cyclone is very similar to swift 761def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, 762 FeatureHasRetAddrStack, 763 FeatureNEONForFP, 764 FeatureT2XtPk, 765 FeatureVFP4, 766 FeatureMP, 767 FeatureHWDiv, 768 FeatureHWDivARM, 769 FeatureAvoidPartialCPSR, 770 FeatureAvoidMOVsShOp, 771 FeatureHasSlowFPVMLx, 772 FeatureCrypto, 773 FeatureZCZeroing]>; 774 775def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1, 776 FeatureHWDiv, 777 FeatureHWDivARM, 778 FeatureT2XtPk, 779 FeatureCrypto, 780 FeatureCRC]>; 781 782//===----------------------------------------------------------------------===// 783// Register File Description 784//===----------------------------------------------------------------------===// 785 786include "ARMRegisterInfo.td" 787 788include "ARMCallingConv.td" 789 790//===----------------------------------------------------------------------===// 791// Instruction Descriptions 792//===----------------------------------------------------------------------===// 793 794include "ARMInstrInfo.td" 795 796def ARMInstrInfo : InstrInfo; 797 798//===----------------------------------------------------------------------===// 799// Declare the target which we are implementing 800//===----------------------------------------------------------------------===// 801 802def ARMAsmWriter : AsmWriter { 803 string AsmWriterClassName = "InstPrinter"; 804 int PassSubtarget = 1; 805 int Variant = 0; 806 bit isMCAsmWriter = 1; 807} 808 809def ARMAsmParserVariant : AsmParserVariant { 810 int Variant = 0; 811 string Name = "ARM"; 812 string BreakCharacters = "."; 813} 814 815def ARM : Target { 816 // Pull in Instruction Info: 817 let InstructionSet = ARMInstrInfo; 818 let AssemblyWriters = [ARMAsmWriter]; 819 let AssemblyParserVariants = [ARMAsmParserVariant]; 820} 821