1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Target-independent interfaces which we are implementing 15//===----------------------------------------------------------------------===// 16 17include "llvm/Target/Target.td" 18 19//===----------------------------------------------------------------------===// 20// ARM Helper classes. 21// 22 23class ProcNoItin<string Name, list<SubtargetFeature> Features> 24 : Processor<Name, NoItineraries, Features>; 25 26class Architecture<string fname, string aname, list<SubtargetFeature> features > 27 : SubtargetFeature<fname, "ARMArch", aname, 28 !strconcat(aname, " architecture"), features>; 29 30//===----------------------------------------------------------------------===// 31// ARM Subtarget state. 32// 33 34def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true", 35 "Thumb mode">; 36 37def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true", 38 "Use software floating point features.">; 39 40//===----------------------------------------------------------------------===// 41// ARM Subtarget features. 42// 43 44def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 45 "Enable VFP2 instructions">; 46def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true", 47 "Enable VFP3 instructions", 48 [FeatureVFP2]>; 49def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 50 "Enable NEON instructions", 51 [FeatureVFP3]>; 52def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 53 "Enable Thumb2 instructions">; 54def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 55 "Does not support ARM mode execution", 56 [ModeThumb]>; 57def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 58 "Enable half-precision floating point">; 59def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true", 60 "Enable VFP4 instructions", 61 [FeatureVFP3, FeatureFP16]>; 62def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", 63 "true", "Enable ARMv8 FP", 64 [FeatureVFP4]>; 65def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 66 "Enable full half-precision floating point", 67 [FeatureFPARMv8]>; 68def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true", 69 "Restrict FP to 16 double registers">; 70def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true", 71 "Enable divide instructions">; 72def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", 73 "HasHardwareDivideInARM", "true", 74 "Enable divide instructions in ARM mode">; 75def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true", 76 "Enable Thumb2 extract and pack instructions">; 77def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 78 "Has data barrier (dmb / dsb) instructions">; 79def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", 80 "Has v7 clrex instruction">; 81def FeatureAcquireRelease : SubtargetFeature<"acquire-release", 82 "HasAcquireRelease", "true", 83 "Has v8 acquire/release (lda/ldaex etc) instructions">; 84def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 85 "FP compare + branch is slow">; 86def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true", 87 "Floating point unit supports single precision only">; 88def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 89 "Enable support for Performance Monitor extensions">; 90def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", 91 "Enable support for TrustZone security extensions">; 92def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true", 93 "Enable support for ARMv8-M Security Extensions">; 94def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 95 "Enable support for Cryptography extensions", 96 [FeatureNEON]>; 97def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 98 "Enable support for CRC instructions">; 99 100// Cyclone has preferred instructions for zeroing VFP registers, which can 101// execute in 0 cycles. 102def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 103 "Has zero-cycle zeroing instructions">; 104 105// Some processors have FP multiply-accumulate instructions that don't 106// play nicely with other VFP / NEON instructions, and it's generally better 107// to just not use them. 108def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 109 "Disable VFP / NEON MAC instructions">; 110 111// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 112def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 113 "HasVMLxForwarding", "true", 114 "Has multiplier accumulator forwarding">; 115 116// Some processors benefit from using NEON instructions for scalar 117// single-precision FP operations. 118def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", 119 "true", 120 "Use NEON for single precision FP">; 121 122// Disable 32-bit to 16-bit narrowing for experimentation. 123def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 124 "Prefer 32-bit Thumb instrs">; 125 126/// Some instructions update CPSR partially, which can add false dependency for 127/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 128/// mapped to a separate physical register. Avoid partial CPSR update for these 129/// processors. 130def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 131 "AvoidCPSRPartialUpdate", "true", 132 "Avoid CPSR partial update for OOO execution">; 133 134def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", 135 "AvoidMOVsShifterOperand", "true", 136 "Avoid movs instructions with shifter operand">; 137 138// Some processors perform return stack prediction. CodeGen should avoid issue 139// "normal" call instructions to callees which do not return. 140def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true", 141 "Has return address stack">; 142 143/// DSP extension. 144def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", 145 "Supports DSP instructions in ARM and/or Thumb2">; 146 147// Multiprocessing extension. 148def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 149 "Supports Multiprocessing extension">; 150 151// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). 152def FeatureVirtualization : SubtargetFeature<"virtualization", 153 "HasVirtualization", "true", 154 "Supports Virtualization extension", 155 [FeatureHWDiv, FeatureHWDivARM]>; 156 157// M-series ISA 158def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", 159 "Is microcontroller profile ('M' series)">; 160 161// R-series ISA 162def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", 163 "Is realtime profile ('R' series)">; 164 165// A-series ISA 166def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", 167 "Is application profile ('A' series)">; 168 169// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. 170// See ARMInstrInfo.td for details. 171def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", 172 "NaCl trap">; 173 174def FeatureStrictAlign : SubtargetFeature<"strict-align", 175 "StrictAlign", "true", 176 "Disallow all unaligned memory " 177 "access">; 178 179def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", 180 "Generate calls via indirect call " 181 "instructions">; 182 183def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", 184 "Reserve R9, making it unavailable as " 185 "GPR">; 186 187def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", 188 "Don't use movt/movw pairs for 32-bit " 189 "imms">; 190 191 192//===----------------------------------------------------------------------===// 193// ARM ISAa. 194// 195 196def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 197 "Support ARM v4T instructions">; 198def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 199 "Support ARM v5T instructions", 200 [HasV4TOps]>; 201def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 202 "Support ARM v5TE, v5TEj, and v5TExp instructions", 203 [HasV5TOps]>; 204def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 205 "Support ARM v6 instructions", 206 [HasV5TEOps]>; 207def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", 208 "Support ARM v6M instructions", 209 [HasV6Ops]>; 210def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true", 211 "Support ARM v8M Baseline instructions", 212 [HasV6MOps]>; 213def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true", 214 "Support ARM v6k instructions", 215 [HasV6Ops]>; 216def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 217 "Support ARM v6t2 instructions", 218 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>; 219def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 220 "Support ARM v7 instructions", 221 [HasV6T2Ops, FeaturePerfMon, 222 FeatureV7Clrex]>; 223def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", 224 "Support ARM v8 instructions", 225 [HasV7Ops, FeatureAcquireRelease]>; 226def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 227 "Support ARM v8.1a instructions", 228 [HasV8Ops]>; 229def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 230 "Support ARM v8.2a instructions", 231 [HasV8_1aOps]>; 232def HasV8MMainlineOps : SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true", 233 "Support ARM v8M Mainline instructions", 234 [HasV7Ops]>; 235 236 237//===----------------------------------------------------------------------===// 238// ARM Processor subtarget features. 239// 240 241def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", 242 "Cortex-A5 ARM processors", []>; 243def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", 244 "Cortex-A7 ARM processors", []>; 245def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 246 "Cortex-A8 ARM processors", []>; 247def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 248 "Cortex-A9 ARM processors", []>; 249def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", 250 "Cortex-A12 ARM processors", []>; 251def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", 252 "Cortex-A15 ARM processors", []>; 253def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", 254 "Cortex-A17 ARM processors", []>; 255def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32", 256 "Cortex-A32 ARM processors", []>; 257def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 258 "Cortex-A35 ARM processors", []>; 259def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 260 "Cortex-A53 ARM processors", []>; 261def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 262 "Cortex-A57 ARM processors", []>; 263def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 264 "Cortex-A72 ARM processors", []>; 265 266def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", 267 "Qualcomm ARM processors", []>; 268def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", 269 "Swift ARM processors", []>; 270 271def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1", 272 "Samsung Exynos-M1 processors", []>; 273 274def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", 275 "Cortex-R4 ARM processors", []>; 276def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", 277 "Cortex-R5 ARM processors", []>; 278def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", 279 "Cortex-R7 ARM processors", []>; 280 281def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", 282 "Cortex-M3 ARM processors", []>; 283 284//===----------------------------------------------------------------------===// 285// ARM schedules. 286// 287 288include "ARMSchedule.td" 289 290 291//===----------------------------------------------------------------------===// 292// ARM architectures 293// 294 295def ARMv2 : Architecture<"armv2", "ARMv2", []>; 296 297def ARMv2a : Architecture<"armv2a", "ARMv2a", []>; 298 299def ARMv3 : Architecture<"armv3", "ARMv3", []>; 300 301def ARMv3m : Architecture<"armv3m", "ARMv3m", []>; 302 303def ARMv4 : Architecture<"armv4", "ARMv4", []>; 304 305def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>; 306 307def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>; 308 309def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>; 310 311def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>; 312 313def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>; 314 315def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, 316 FeatureDSP]>; 317 318def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; 319 320def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, 321 FeatureTrustZone]>; 322 323def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, 324 FeatureNoARM, 325 FeatureDB, 326 FeatureMClass]>; 327 328def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, 329 FeatureNoARM, 330 FeatureDB, 331 FeatureMClass]>; 332 333def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, 334 FeatureNEON, 335 FeatureDB, 336 FeatureDSP, 337 FeatureAClass]>; 338 339def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, 340 FeatureDB, 341 FeatureDSP, 342 FeatureHWDiv, 343 FeatureRClass]>; 344 345def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, 346 FeatureThumb2, 347 FeatureNoARM, 348 FeatureDB, 349 FeatureHWDiv, 350 FeatureMClass]>; 351 352def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, 353 FeatureThumb2, 354 FeatureNoARM, 355 FeatureDB, 356 FeatureHWDiv, 357 FeatureMClass, 358 FeatureDSP, 359 FeatureT2XtPk]>; 360 361def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, 362 FeatureAClass, 363 FeatureDB, 364 FeatureFPARMv8, 365 FeatureNEON, 366 FeatureDSP, 367 FeatureTrustZone, 368 FeatureMP, 369 FeatureVirtualization, 370 FeatureCrypto, 371 FeatureCRC]>; 372 373def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps, 374 FeatureAClass, 375 FeatureDB, 376 FeatureFPARMv8, 377 FeatureNEON, 378 FeatureDSP, 379 FeatureTrustZone, 380 FeatureMP, 381 FeatureVirtualization, 382 FeatureCrypto, 383 FeatureCRC]>; 384 385def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, 386 FeatureAClass, 387 FeatureDB, 388 FeatureFPARMv8, 389 FeatureNEON, 390 FeatureDSP, 391 FeatureTrustZone, 392 FeatureMP, 393 FeatureVirtualization, 394 FeatureCrypto, 395 FeatureCRC]>; 396 397def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", 398 [HasV8MBaselineOps, 399 FeatureNoARM, 400 FeatureDB, 401 FeatureHWDiv, 402 FeatureV7Clrex, 403 Feature8MSecExt, 404 FeatureAcquireRelease, 405 FeatureMClass]>; 406 407def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", 408 [HasV8MMainlineOps, 409 FeatureNoARM, 410 FeatureDB, 411 FeatureHWDiv, 412 Feature8MSecExt, 413 FeatureAcquireRelease, 414 FeatureMClass]>; 415 416// Aliases 417def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; 418def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; 419def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; 420def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; 421def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; 422def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; 423 424 425//===----------------------------------------------------------------------===// 426// ARM processors 427// 428 429// Dummy CPU, used to target architectures 430def : ProcNoItin<"generic", []>; 431 432def : ProcNoItin<"arm8", [ARMv4]>; 433def : ProcNoItin<"arm810", [ARMv4]>; 434def : ProcNoItin<"strongarm", [ARMv4]>; 435def : ProcNoItin<"strongarm110", [ARMv4]>; 436def : ProcNoItin<"strongarm1100", [ARMv4]>; 437def : ProcNoItin<"strongarm1110", [ARMv4]>; 438 439def : ProcNoItin<"arm7tdmi", [ARMv4t]>; 440def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>; 441def : ProcNoItin<"arm710t", [ARMv4t]>; 442def : ProcNoItin<"arm720t", [ARMv4t]>; 443def : ProcNoItin<"arm9", [ARMv4t]>; 444def : ProcNoItin<"arm9tdmi", [ARMv4t]>; 445def : ProcNoItin<"arm920", [ARMv4t]>; 446def : ProcNoItin<"arm920t", [ARMv4t]>; 447def : ProcNoItin<"arm922t", [ARMv4t]>; 448def : ProcNoItin<"arm940t", [ARMv4t]>; 449def : ProcNoItin<"ep9312", [ARMv4t]>; 450 451def : ProcNoItin<"arm10tdmi", [ARMv5t]>; 452def : ProcNoItin<"arm1020t", [ARMv5t]>; 453 454def : ProcNoItin<"arm9e", [ARMv5te]>; 455def : ProcNoItin<"arm926ej-s", [ARMv5te]>; 456def : ProcNoItin<"arm946e-s", [ARMv5te]>; 457def : ProcNoItin<"arm966e-s", [ARMv5te]>; 458def : ProcNoItin<"arm968e-s", [ARMv5te]>; 459def : ProcNoItin<"arm10e", [ARMv5te]>; 460def : ProcNoItin<"arm1020e", [ARMv5te]>; 461def : ProcNoItin<"arm1022e", [ARMv5te]>; 462def : ProcNoItin<"xscale", [ARMv5te]>; 463def : ProcNoItin<"iwmmxt", [ARMv5te]>; 464 465def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>; 466def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, 467 FeatureVFP2, 468 FeatureHasSlowFPVMLx]>; 469 470def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>; 471def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>; 472def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>; 473def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>; 474 475def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; 476def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, 477 FeatureVFP2, 478 FeatureHasSlowFPVMLx]>; 479 480def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>; 481def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k, 482 FeatureVFP2, 483 FeatureHasSlowFPVMLx]>; 484 485def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>; 486def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2, 487 FeatureVFP2, 488 FeatureHasSlowFPVMLx]>; 489 490// FIXME: A5 has currently the same Schedule model as A8 491def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5, 492 FeatureHasRAS, 493 FeatureTrustZone, 494 FeatureSlowFPBrcc, 495 FeatureHasSlowFPVMLx, 496 FeatureVMLxForwarding, 497 FeatureT2XtPk, 498 FeatureMP, 499 FeatureVFP4]>; 500 501def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7, 502 FeatureHasRAS, 503 FeatureTrustZone, 504 FeatureSlowFPBrcc, 505 FeatureHasSlowFPVMLx, 506 FeatureVMLxForwarding, 507 FeatureT2XtPk, 508 FeatureMP, 509 FeatureVFP4, 510 FeatureHWDiv, 511 FeatureHWDivARM, 512 FeatureVirtualization]>; 513 514def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, 515 FeatureHasRAS, 516 FeatureTrustZone, 517 FeatureSlowFPBrcc, 518 FeatureHasSlowFPVMLx, 519 FeatureVMLxForwarding, 520 FeatureT2XtPk]>; 521 522def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9, 523 FeatureHasRAS, 524 FeatureTrustZone, 525 FeatureVMLxForwarding, 526 FeatureT2XtPk, 527 FeatureFP16, 528 FeatureAvoidPartialCPSR, 529 FeatureMP]>; 530 531// FIXME: A12 has currently the same Schedule model as A9 532def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12, 533 FeatureHasRAS, 534 FeatureTrustZone, 535 FeatureVMLxForwarding, 536 FeatureT2XtPk, 537 FeatureVFP4, 538 FeatureHWDiv, 539 FeatureHWDivARM, 540 FeatureAvoidPartialCPSR, 541 FeatureVirtualization, 542 FeatureMP]>; 543 544// FIXME: A15 has currently the same Schedule model as A9. 545def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, 546 FeatureHasRAS, 547 FeatureTrustZone, 548 FeatureT2XtPk, 549 FeatureVFP4, 550 FeatureMP, 551 FeatureHWDiv, 552 FeatureHWDivARM, 553 FeatureAvoidPartialCPSR, 554 FeatureVirtualization]>; 555 556// FIXME: A17 has currently the same Schedule model as A9 557def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17, 558 FeatureHasRAS, 559 FeatureTrustZone, 560 FeatureMP, 561 FeatureVMLxForwarding, 562 FeatureT2XtPk, 563 FeatureVFP4, 564 FeatureHWDiv, 565 FeatureHWDivARM, 566 FeatureAvoidPartialCPSR, 567 FeatureVirtualization]>; 568 569// FIXME: krait has currently the same Schedule model as A9 570// FIXME: krait has currently the same features as A9 plus VFP4 and hardware 571// division features. 572def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, 573 FeatureHasRAS, 574 FeatureVMLxForwarding, 575 FeatureT2XtPk, 576 FeatureFP16, 577 FeatureAvoidPartialCPSR, 578 FeatureVFP4, 579 FeatureHWDiv, 580 FeatureHWDivARM]>; 581 582def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, 583 FeatureHasRAS, 584 FeatureNEONForFP, 585 FeatureT2XtPk, 586 FeatureVFP4, 587 FeatureMP, 588 FeatureHWDiv, 589 FeatureHWDivARM, 590 FeatureAvoidPartialCPSR, 591 FeatureAvoidMOVsShOp, 592 FeatureHasSlowFPVMLx]>; 593 594// FIXME: R4 has currently the same ProcessorModel as A8. 595def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, 596 FeatureHasRAS, 597 FeatureAvoidPartialCPSR, 598 FeatureT2XtPk]>; 599 600// FIXME: R4F has currently the same ProcessorModel as A8. 601def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4, 602 FeatureHasRAS, 603 FeatureSlowFPBrcc, 604 FeatureHasSlowFPVMLx, 605 FeatureVFP3, 606 FeatureD16, 607 FeatureAvoidPartialCPSR, 608 FeatureT2XtPk]>; 609 610// FIXME: R5 has currently the same ProcessorModel as A8. 611def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, 612 FeatureHasRAS, 613 FeatureVFP3, 614 FeatureD16, 615 FeatureSlowFPBrcc, 616 FeatureHWDivARM, 617 FeatureHasSlowFPVMLx, 618 FeatureAvoidPartialCPSR, 619 FeatureT2XtPk]>; 620 621// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5. 622def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, 623 FeatureHasRAS, 624 FeatureVFP3, 625 FeatureD16, 626 FeatureFP16, 627 FeatureMP, 628 FeatureSlowFPBrcc, 629 FeatureHWDivARM, 630 FeatureHasSlowFPVMLx, 631 FeatureAvoidPartialCPSR, 632 FeatureT2XtPk]>; 633 634def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, 635 FeatureHasRAS, 636 FeatureVFP3, 637 FeatureD16, 638 FeatureFP16, 639 FeatureMP, 640 FeatureSlowFPBrcc, 641 FeatureHWDivARM, 642 FeatureHasSlowFPVMLx, 643 FeatureAvoidPartialCPSR, 644 FeatureT2XtPk]>; 645 646def : ProcNoItin<"cortex-m3", [ARMv7m, ProcM3]>; 647def : ProcNoItin<"sc300", [ARMv7m, ProcM3]>; 648 649def : ProcNoItin<"cortex-m4", [ARMv7em, 650 FeatureVFP4, 651 FeatureVFPOnlySP, 652 FeatureD16]>; 653 654def : ProcNoItin<"cortex-m7", [ARMv7em, 655 FeatureFPARMv8, 656 FeatureD16]>; 657 658def : ProcNoItin<"cortex-a32", [ARMv8a, 659 FeatureHWDiv, 660 FeatureHWDivARM, 661 FeatureT2XtPk, 662 FeatureCrypto, 663 FeatureCRC]>; 664 665def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, 666 FeatureHWDiv, 667 FeatureHWDivARM, 668 FeatureT2XtPk, 669 FeatureCrypto, 670 FeatureCRC]>; 671 672def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, 673 FeatureHWDiv, 674 FeatureHWDivARM, 675 FeatureT2XtPk, 676 FeatureCrypto, 677 FeatureCRC]>; 678 679def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57, 680 FeatureHWDiv, 681 FeatureHWDivARM, 682 FeatureT2XtPk, 683 FeatureCrypto, 684 FeatureCRC]>; 685 686def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72, 687 FeatureHWDiv, 688 FeatureHWDivARM, 689 FeatureT2XtPk, 690 FeatureCrypto, 691 FeatureCRC]>; 692 693// Cyclone is very similar to swift 694def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, 695 FeatureHasRAS, 696 FeatureNEONForFP, 697 FeatureT2XtPk, 698 FeatureVFP4, 699 FeatureMP, 700 FeatureHWDiv, 701 FeatureHWDivARM, 702 FeatureAvoidPartialCPSR, 703 FeatureAvoidMOVsShOp, 704 FeatureHasSlowFPVMLx, 705 FeatureCrypto, 706 FeatureZCZeroing]>; 707 708def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1, 709 FeatureHWDiv, 710 FeatureHWDivARM, 711 FeatureT2XtPk, 712 FeatureCrypto, 713 FeatureCRC]>; 714 715//===----------------------------------------------------------------------===// 716// Register File Description 717//===----------------------------------------------------------------------===// 718 719include "ARMRegisterInfo.td" 720 721include "ARMCallingConv.td" 722 723//===----------------------------------------------------------------------===// 724// Instruction Descriptions 725//===----------------------------------------------------------------------===// 726 727include "ARMInstrInfo.td" 728 729def ARMInstrInfo : InstrInfo; 730 731//===----------------------------------------------------------------------===// 732// Declare the target which we are implementing 733//===----------------------------------------------------------------------===// 734 735def ARMAsmWriter : AsmWriter { 736 string AsmWriterClassName = "InstPrinter"; 737 int PassSubtarget = 1; 738 int Variant = 0; 739 bit isMCAsmWriter = 1; 740} 741 742def ARMAsmParserVariant : AsmParserVariant { 743 int Variant = 0; 744 string Name = "ARM"; 745 string BreakCharacters = "."; 746} 747 748def ARM : Target { 749 // Pull in Instruction Info: 750 let InstructionSet = ARMInstrInfo; 751 let AssemblyWriters = [ARMAsmWriter]; 752 let AssemblyParserVariants = [ARMAsmParserVariant]; 753} 754