1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// ARM Subtarget state. 20// 21 22def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", 23 "true", "Thumb mode">; 24 25def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat", 26 "true", "Use software floating " 27 "point features.">; 28 29 30//===----------------------------------------------------------------------===// 31// ARM Subtarget features. 32// 33 34// Floating Point, HW Division and Neon Support 35 36// FP loads/stores/moves, shared between VFP and MVE (even in the integer-only 37// version). 38def FeatureFPRegs : SubtargetFeature<"fpregs", "HasFPRegs", "true", 39 "Enable FP registers">; 40 41// 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16 42// extension) and MVE (even in the integer-only version). 43def FeatureFPRegs16 : SubtargetFeature<"fpregs16", "HasFPRegs16", "true", 44 "Enable 16-bit FP registers", 45 [FeatureFPRegs]>; 46 47def FeatureFPRegs64 : SubtargetFeature<"fpregs64", "HasFPRegs64", "true", 48 "Enable 64-bit FP registers", 49 [FeatureFPRegs]>; 50 51def FeatureFP64 : SubtargetFeature<"fp64", "HasFP64", "true", 52 "Floating point unit supports " 53 "double precision", 54 [FeatureFPRegs64]>; 55 56def FeatureD32 : SubtargetFeature<"d32", "HasD32", "true", 57 "Extend FP to 32 double registers">; 58 59multiclass VFPver<string name, string query, string description, 60 list<SubtargetFeature> prev, 61 list<SubtargetFeature> otherimplies, 62 list<SubtargetFeature> vfp2prev = []> { 63 def _D16_SP: SubtargetFeature< 64 name#"d16sp", query#"D16SP", "true", 65 description#" with only 16 d-registers and no double precision", 66 !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) # 67 !foreach(v, vfp2prev, !cast<SubtargetFeature>(v # "_SP")) # 68 otherimplies>; 69 def _SP: SubtargetFeature< 70 name#"sp", query#"SP", "true", 71 description#" with no double precision", 72 !foreach(v, prev, !cast<SubtargetFeature>(v # "_SP")) # 73 otherimplies # [FeatureD32, !cast<SubtargetFeature>(NAME # "_D16_SP")]>; 74 def _D16: SubtargetFeature< 75 name#"d16", query#"D16", "true", 76 description#" with only 16 d-registers", 77 !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16")) # 78 vfp2prev # 79 otherimplies # [FeatureFP64, !cast<SubtargetFeature>(NAME # "_D16_SP")]>; 80 def "": SubtargetFeature< 81 name, query, "true", description, 82 prev # otherimplies # [ 83 !cast<SubtargetFeature>(NAME # "_D16"), 84 !cast<SubtargetFeature>(NAME # "_SP")]>; 85} 86 87def FeatureVFP2_SP : SubtargetFeature<"vfp2sp", "HasVFPv2SP", "true", 88 "Enable VFP2 instructions with " 89 "no double precision", 90 [FeatureFPRegs]>; 91 92def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 93 "Enable VFP2 instructions", 94 [FeatureFP64, FeatureVFP2_SP]>; 95 96defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions", 97 [], [], [FeatureVFP2]>; 98 99def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 100 "Enable NEON instructions", 101 [FeatureVFP3]>; 102 103def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 104 "Enable half-precision " 105 "floating point">; 106 107defm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions", 108 [FeatureVFP3], [FeatureFP16]>; 109 110defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP", 111 [FeatureVFP4], []>; 112 113def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 114 "Enable full half-precision " 115 "floating point", 116 [FeatureFPARMv8_D16_SP, FeatureFPRegs16]>; 117 118def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 119 "Enable full half-precision " 120 "floating point fml instructions", 121 [FeatureFullFP16]>; 122 123def FeatureHWDivThumb : SubtargetFeature<"hwdiv", 124 "HasHardwareDivideInThumb", "true", 125 "Enable divide instructions in Thumb">; 126 127def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", 128 "HasHardwareDivideInARM", "true", 129 "Enable divide instructions in ARM mode">; 130 131// Atomic Support 132def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 133 "Has data barrier (dmb/dsb) instructions">; 134 135def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", 136 "Has v7 clrex instruction">; 137 138def FeatureDFB : SubtargetFeature<"dfb", "HasFullDataBarrier", "true", 139 "Has full data barrier (dfb) instruction">; 140 141def FeatureAcquireRelease : SubtargetFeature<"acquire-release", 142 "HasAcquireRelease", "true", 143 "Has v8 acquire/release (lda/ldaex " 144 " etc) instructions">; 145 146 147def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 148 "FP compare + branch is slow">; 149 150def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 151 "Enable support for Performance " 152 "Monitor extensions">; 153 154 155// TrustZone Security Extensions 156def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", 157 "Enable support for TrustZone " 158 "security extensions">; 159 160def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true", 161 "Enable support for ARMv8-M " 162 "Security Extensions">; 163 164def FeatureSHA2 : SubtargetFeature<"sha2", "HasSHA2", "true", 165 "Enable SHA1 and SHA256 support", [FeatureNEON]>; 166 167def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", 168 "Enable AES support", [FeatureNEON]>; 169 170def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 171 "Enable support for " 172 "Cryptography extensions", 173 [FeatureNEON, FeatureSHA2, FeatureAES]>; 174 175def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 176 "Enable support for CRC instructions">; 177 178def FeatureDotProd : SubtargetFeature<"dotprod", "HasDotProd", "true", 179 "Enable support for dot product instructions", 180 [FeatureNEON]>; 181 182// Not to be confused with FeatureHasRetAddrStack (return address stack) 183def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 184 "Enable Reliability, Availability " 185 "and Serviceability extensions">; 186 187// Fast computation of non-negative address offsets 188def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true", 189 "Enable fast computation of " 190 "positive address offsets">; 191 192// Fast execution of AES crypto operations 193def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true", 194 "CPU fuses AES crypto operations">; 195 196// Fast execution of bottom and top halves of literal generation 197def FeatureFuseLiterals : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true", 198 "CPU fuses literal generation operations">; 199 200// The way of reading thread pointer 201def FeatureReadTp : SubtargetFeature<"read-tp-hard", "ReadTPHard", "true", 202 "Reading thread pointer from register">; 203 204// Cyclone can zero VFP registers in 0 cycles. 205def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 206 "Has zero-cycle zeroing instructions">; 207 208// Whether it is profitable to unpredicate certain instructions during if-conversion 209def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr", 210 "IsProfitableToUnpredicate", "true", 211 "Is profitable to unpredicate">; 212 213// Some targets (e.g. Swift) have microcoded VGETLNi32. 214def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32", 215 "HasSlowVGETLNi32", "true", 216 "Has slow VGETLNi32 - prefer VMOV">; 217 218// Some targets (e.g. Swift) have microcoded VDUP32. 219def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", 220 "true", 221 "Has slow VDUP32 - prefer VMOV">; 222 223// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON 224// for scalar FP, as this allows more effective execution domain optimization. 225def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR", 226 "true", "Prefer VMOVSR">; 227 228// Swift has ISHST barriers compatible with Atomic Release semantics but weaker 229// than ISH 230def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST", 231 "true", "Prefer ISHST barriers">; 232 233// Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU. 234def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", 235 "true", 236 "Has muxed AGU and NEON/FPU">; 237 238// Whether VLDM/VSTM starting with odd register number need more microops 239// than single VLDRS 240def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister", 241 "true", "VLDM/VSTM starting " 242 "with an odd register is slow">; 243 244// Some targets have a renaming dependency when loading into D subregisters. 245def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg", 246 "SlowLoadDSubregister", "true", 247 "Loading into D subregs is slow">; 248 249def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp", 250 "UseWideStrideVFP", "true", 251 "Use a wide stride when allocating VFP registers">; 252 253// Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD. 254def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs", 255 "DontWidenVMOVS", "true", 256 "Don't widen VMOVS to VMOVD">; 257 258// Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different 259// VFP register widths. 260def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon", 261 "SplatVFPToNeon", "true", 262 "Splat register from VFP to NEON", 263 [FeatureDontWidenVMOVS]>; 264 265// Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions. 266def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", 267 "ExpandMLx", "true", 268 "Expand VFP/NEON MLA/MLS instructions">; 269 270// Some targets have special RAW hazards for VFP/NEON VMLA/VMLS. 271def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards", 272 "true", "Has VMLx hazards">; 273 274// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from 275// VFP to NEON, as an execution domain optimization. 276def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", 277 "UseNEONForFPMovs", "true", 278 "Convert VMOVSR, VMOVRS, " 279 "VMOVS to NEON">; 280 281// Some processors benefit from using NEON instructions for scalar 282// single-precision FP operations. This affects instruction selection and should 283// only be enabled if the handling of denormals is not important. 284def FeatureNEONForFP : SubtargetFeature<"neonfp", 285 "UseNEONForSinglePrecisionFP", 286 "true", 287 "Use NEON for single precision FP">; 288 289// On some processors, VLDn instructions that access unaligned data take one 290// extra cycle. Take that into account when computing operand latencies. 291def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign", 292 "true", 293 "Check for VLDn unaligned access">; 294 295// Some processors have a nonpipelined VFP coprocessor. 296def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp", 297 "NonpipelinedVFP", "true", 298 "VFP instructions are not pipelined">; 299 300// Some processors have FP multiply-accumulate instructions that don't 301// play nicely with other VFP / NEON instructions, and it's generally better 302// to just not use them. 303def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 304 "Disable VFP / NEON MAC instructions">; 305 306// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 307def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 308 "HasVMLxForwarding", "true", 309 "Has multiplier accumulator forwarding">; 310 311// Disable 32-bit to 16-bit narrowing for experimentation. 312def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 313 "Prefer 32-bit Thumb instrs">; 314 315def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopLogAlignment","2", 316 "Prefer 32-bit alignment for loops">; 317 318def FeatureMVEVectorCostFactor1 : SubtargetFeature<"mve1beat", "MVEVectorCostFactor", "1", 319 "Model MVE instructions as a 1 beat per tick architecture">; 320 321def FeatureMVEVectorCostFactor2 : SubtargetFeature<"mve2beat", "MVEVectorCostFactor", "2", 322 "Model MVE instructions as a 2 beats per tick architecture">; 323 324def FeatureMVEVectorCostFactor4 : SubtargetFeature<"mve4beat", "MVEVectorCostFactor", "4", 325 "Model MVE instructions as a 4 beats per tick architecture">; 326 327/// Some instructions update CPSR partially, which can add false dependency for 328/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 329/// mapped to a separate physical register. Avoid partial CPSR update for these 330/// processors. 331def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 332 "AvoidCPSRPartialUpdate", "true", 333 "Avoid CPSR partial update for OOO execution">; 334 335/// Disable +1 predication cost for instructions updating CPSR. 336/// Enabled for Cortex-A57. 337def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr", 338 "CheapPredicableCPSRDef", 339 "true", 340 "Disable +1 predication cost for instructions updating CPSR">; 341 342def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", 343 "AvoidMOVsShifterOperand", "true", 344 "Avoid movs instructions with " 345 "shifter operand">; 346 347// Some processors perform return stack prediction. CodeGen should avoid issue 348// "normal" call instructions to callees which do not return. 349def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", 350 "HasRetAddrStack", "true", 351 "Has return address stack">; 352 353// Some processors have no branch predictor, which changes the expected cost of 354// taking a branch which affects the choice of whether to use predicated 355// instructions. 356def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor", 357 "HasBranchPredictor", "false", 358 "Has no branch predictor">; 359 360/// DSP extension. 361def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", 362 "Supports DSP instructions in " 363 "ARM and/or Thumb2">; 364 365// Multiprocessing extension. 366def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 367 "Supports Multiprocessing extension">; 368 369// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). 370def FeatureVirtualization : SubtargetFeature<"virtualization", 371 "HasVirtualization", "true", 372 "Supports Virtualization extension", 373 [FeatureHWDivThumb, FeatureHWDivARM]>; 374 375// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. 376// See ARMInstrInfo.td for details. 377def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", 378 "NaCl trap">; 379 380def FeatureStrictAlign : SubtargetFeature<"strict-align", 381 "StrictAlign", "true", 382 "Disallow all unaligned memory " 383 "access">; 384 385def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", 386 "Generate calls via indirect call " 387 "instructions">; 388 389def FeatureExecuteOnly : SubtargetFeature<"execute-only", 390 "GenExecuteOnly", "true", 391 "Enable the generation of " 392 "execute only code.">; 393 394def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", 395 "Reserve R9, making it unavailable" 396 " as GPR">; 397 398def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", 399 "Don't use movt/movw pairs for " 400 "32-bit imms">; 401 402def FeatureNoNegativeImmediates 403 : SubtargetFeature<"no-neg-immediates", 404 "NegativeImmediates", "false", 405 "Convert immediates and instructions " 406 "to their negated or complemented " 407 "equivalent when the immediate does " 408 "not fit in the encoding.">; 409 410// Use the MachineScheduler for instruction scheduling for the subtarget. 411def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true", 412 "Use the MachineScheduler">; 413 414def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler", 415 "DisablePostRAScheduler", "true", 416 "Don't schedule again after register allocation">; 417 418// Armv8.5-A extensions 419 420def FeatureSB : SubtargetFeature<"sb", "HasSB", "true", 421 "Enable v8.5a Speculation Barrier" >; 422 423// Armv8.1-M extensions 424 425def FeatureLOB : SubtargetFeature<"lob", "HasLOB", "true", 426 "Enable Low Overhead Branch " 427 "extensions">; 428 429//===----------------------------------------------------------------------===// 430// ARM architecture class 431// 432 433// A-series ISA 434def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", 435 "Is application profile ('A' series)">; 436 437// R-series ISA 438def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", 439 "Is realtime profile ('R' series)">; 440 441// M-series ISA 442def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", 443 "Is microcontroller profile ('M' series)">; 444 445 446def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 447 "Enable Thumb2 instructions">; 448 449def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 450 "Does not support ARM mode execution">; 451 452//===----------------------------------------------------------------------===// 453// ARM ISAa. 454// 455 456def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 457 "Support ARM v4T instructions">; 458 459def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 460 "Support ARM v5T instructions", 461 [HasV4TOps]>; 462 463def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 464 "Support ARM v5TE, v5TEj, and " 465 "v5TExp instructions", 466 [HasV5TOps]>; 467 468def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 469 "Support ARM v6 instructions", 470 [HasV5TEOps]>; 471 472def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", 473 "Support ARM v6M instructions", 474 [HasV6Ops]>; 475 476def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true", 477 "Support ARM v8M Baseline instructions", 478 [HasV6MOps]>; 479 480def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true", 481 "Support ARM v6k instructions", 482 [HasV6Ops]>; 483 484def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 485 "Support ARM v6t2 instructions", 486 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>; 487 488def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 489 "Support ARM v7 instructions", 490 [HasV6T2Ops, FeaturePerfMon, 491 FeatureV7Clrex]>; 492 493def HasV8MMainlineOps : 494 SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true", 495 "Support ARM v8M Mainline instructions", 496 [HasV7Ops]>; 497 498def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", 499 "Support ARM v8 instructions", 500 [HasV7Ops, FeatureAcquireRelease]>; 501 502def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 503 "Support ARM v8.1a instructions", 504 [HasV8Ops]>; 505 506def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 507 "Support ARM v8.2a instructions", 508 [HasV8_1aOps]>; 509 510def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 511 "Support ARM v8.3a instructions", 512 [HasV8_2aOps]>; 513 514def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 515 "Support ARM v8.4a instructions", 516 [HasV8_3aOps, FeatureDotProd]>; 517 518def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true", 519 "Support ARM v8.5a instructions", 520 [HasV8_4aOps, FeatureSB]>; 521 522def HasV8_1MMainlineOps : SubtargetFeature< 523 "v8.1m.main", "HasV8_1MMainlineOps", "true", 524 "Support ARM v8-1M Mainline instructions", 525 [HasV8MMainlineOps]>; 526def HasMVEIntegerOps : SubtargetFeature< 527 "mve", "HasMVEIntegerOps", "true", 528 "Support M-Class Vector Extension with integer ops", 529 [HasV8_1MMainlineOps, FeatureDSP, FeatureFPRegs16, FeatureFPRegs64]>; 530def HasMVEFloatOps : SubtargetFeature< 531 "mve.fp", "HasMVEFloatOps", "true", 532 "Support M-Class Vector Extension with integer and floating ops", 533 [HasMVEIntegerOps, FeatureFPARMv8_D16_SP, FeatureFullFP16]>; 534 535//===----------------------------------------------------------------------===// 536// ARM Processor subtarget features. 537// 538 539def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", 540 "Cortex-A5 ARM processors", []>; 541def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", 542 "Cortex-A7 ARM processors", []>; 543def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 544 "Cortex-A8 ARM processors", []>; 545def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 546 "Cortex-A9 ARM processors", []>; 547def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", 548 "Cortex-A12 ARM processors", []>; 549def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", 550 "Cortex-A15 ARM processors", []>; 551def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", 552 "Cortex-A17 ARM processors", []>; 553def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32", 554 "Cortex-A32 ARM processors", []>; 555def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 556 "Cortex-A35 ARM processors", []>; 557def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 558 "Cortex-A53 ARM processors", []>; 559def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 560 "Cortex-A55 ARM processors", []>; 561def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 562 "Cortex-A57 ARM processors", []>; 563def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 564 "Cortex-A72 ARM processors", []>; 565def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 566 "Cortex-A73 ARM processors", []>; 567def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 568 "Cortex-A75 ARM processors", []>; 569def ProcA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 570 "Cortex-A76 ARM processors", []>; 571 572def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", 573 "Qualcomm Krait processors", []>; 574def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 575 "Qualcomm Kryo processors", []>; 576def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", 577 "Swift ARM processors", []>; 578 579def ProcExynos : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos", 580 "Samsung Exynos processors", 581 [FeatureZCZeroing, 582 FeatureUseWideStrideVFP, 583 FeatureSplatVFPToNeon, 584 FeatureSlowVGETLNi32, 585 FeatureSlowVDUP32, 586 FeatureSlowFPBrcc, 587 FeatureProfUnpredicate, 588 FeatureHWDivThumb, 589 FeatureHWDivARM, 590 FeatureHasSlowFPVMLx, 591 FeatureHasRetAddrStack, 592 FeatureFuseLiterals, 593 FeatureFuseAES, 594 FeatureExpandMLx, 595 FeatureCrypto, 596 FeatureCRC]>; 597 598def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", 599 "Cortex-R4 ARM processors", []>; 600def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", 601 "Cortex-R5 ARM processors", []>; 602def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", 603 "Cortex-R7 ARM processors", []>; 604def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52", 605 "Cortex-R52 ARM processors", []>; 606 607def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", 608 "Cortex-M3 ARM processors", []>; 609 610 611//===----------------------------------------------------------------------===// 612// ARM Helper classes. 613// 614 615class Architecture<string fname, string aname, list<SubtargetFeature> features> 616 : SubtargetFeature<fname, "ARMArch", aname, 617 !strconcat(aname, " architecture"), features>; 618 619class ProcNoItin<string Name, list<SubtargetFeature> Features> 620 : Processor<Name, NoItineraries, Features>; 621 622 623//===----------------------------------------------------------------------===// 624// ARM architectures 625// 626 627def ARMv2 : Architecture<"armv2", "ARMv2", []>; 628 629def ARMv2a : Architecture<"armv2a", "ARMv2a", []>; 630 631def ARMv3 : Architecture<"armv3", "ARMv3", []>; 632 633def ARMv3m : Architecture<"armv3m", "ARMv3m", []>; 634 635def ARMv4 : Architecture<"armv4", "ARMv4", []>; 636 637def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>; 638 639def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>; 640 641def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>; 642 643def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>; 644 645def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops, 646 FeatureDSP]>; 647 648def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, 649 FeatureDSP]>; 650 651def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; 652 653def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, 654 FeatureTrustZone]>; 655 656def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, 657 FeatureNoARM, 658 ModeThumb, 659 FeatureDB, 660 FeatureMClass, 661 FeatureStrictAlign]>; 662 663def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, 664 FeatureNoARM, 665 ModeThumb, 666 FeatureDB, 667 FeatureMClass, 668 FeatureStrictAlign]>; 669 670def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, 671 FeatureNEON, 672 FeatureDB, 673 FeatureDSP, 674 FeatureAClass]>; 675 676def ARMv7ve : Architecture<"armv7ve", "ARMv7ve", [HasV7Ops, 677 FeatureNEON, 678 FeatureDB, 679 FeatureDSP, 680 FeatureTrustZone, 681 FeatureMP, 682 FeatureVirtualization, 683 FeatureAClass]>; 684 685def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, 686 FeatureDB, 687 FeatureDSP, 688 FeatureHWDivThumb, 689 FeatureRClass]>; 690 691def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, 692 FeatureThumb2, 693 FeatureNoARM, 694 ModeThumb, 695 FeatureDB, 696 FeatureHWDivThumb, 697 FeatureMClass]>; 698 699def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, 700 FeatureThumb2, 701 FeatureNoARM, 702 ModeThumb, 703 FeatureDB, 704 FeatureHWDivThumb, 705 FeatureMClass, 706 FeatureDSP]>; 707 708def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, 709 FeatureAClass, 710 FeatureDB, 711 FeatureFPARMv8, 712 FeatureNEON, 713 FeatureDSP, 714 FeatureTrustZone, 715 FeatureMP, 716 FeatureVirtualization, 717 FeatureCrypto, 718 FeatureCRC]>; 719 720def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps, 721 FeatureAClass, 722 FeatureDB, 723 FeatureFPARMv8, 724 FeatureNEON, 725 FeatureDSP, 726 FeatureTrustZone, 727 FeatureMP, 728 FeatureVirtualization, 729 FeatureCrypto, 730 FeatureCRC]>; 731 732def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, 733 FeatureAClass, 734 FeatureDB, 735 FeatureFPARMv8, 736 FeatureNEON, 737 FeatureDSP, 738 FeatureTrustZone, 739 FeatureMP, 740 FeatureVirtualization, 741 FeatureCrypto, 742 FeatureCRC, 743 FeatureRAS]>; 744 745def ARMv83a : Architecture<"armv8.3-a", "ARMv83a", [HasV8_3aOps, 746 FeatureAClass, 747 FeatureDB, 748 FeatureFPARMv8, 749 FeatureNEON, 750 FeatureDSP, 751 FeatureTrustZone, 752 FeatureMP, 753 FeatureVirtualization, 754 FeatureCrypto, 755 FeatureCRC, 756 FeatureRAS]>; 757 758def ARMv84a : Architecture<"armv8.4-a", "ARMv84a", [HasV8_4aOps, 759 FeatureAClass, 760 FeatureDB, 761 FeatureFPARMv8, 762 FeatureNEON, 763 FeatureDSP, 764 FeatureTrustZone, 765 FeatureMP, 766 FeatureVirtualization, 767 FeatureCrypto, 768 FeatureCRC, 769 FeatureRAS, 770 FeatureDotProd]>; 771 772def ARMv85a : Architecture<"armv8.5-a", "ARMv85a", [HasV8_5aOps, 773 FeatureAClass, 774 FeatureDB, 775 FeatureFPARMv8, 776 FeatureNEON, 777 FeatureDSP, 778 FeatureTrustZone, 779 FeatureMP, 780 FeatureVirtualization, 781 FeatureCrypto, 782 FeatureCRC, 783 FeatureRAS, 784 FeatureDotProd]>; 785 786def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, 787 FeatureRClass, 788 FeatureDB, 789 FeatureDFB, 790 FeatureDSP, 791 FeatureCRC, 792 FeatureMP, 793 FeatureVirtualization, 794 FeatureFPARMv8, 795 FeatureNEON]>; 796 797def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", 798 [HasV8MBaselineOps, 799 FeatureNoARM, 800 ModeThumb, 801 FeatureDB, 802 FeatureHWDivThumb, 803 FeatureV7Clrex, 804 Feature8MSecExt, 805 FeatureAcquireRelease, 806 FeatureMClass, 807 FeatureStrictAlign]>; 808 809def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", 810 [HasV8MMainlineOps, 811 FeatureNoARM, 812 ModeThumb, 813 FeatureDB, 814 FeatureHWDivThumb, 815 Feature8MSecExt, 816 FeatureAcquireRelease, 817 FeatureMClass]>; 818 819def ARMv81mMainline : Architecture<"armv8.1-m.main", "ARMv81mMainline", 820 [HasV8_1MMainlineOps, 821 FeatureNoARM, 822 ModeThumb, 823 FeatureDB, 824 FeatureHWDivThumb, 825 Feature8MSecExt, 826 FeatureAcquireRelease, 827 FeatureMClass, 828 FeatureRAS, 829 FeatureLOB]>; 830 831// Aliases 832def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; 833def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; 834def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; 835def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; 836def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; 837def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; 838 839 840//===----------------------------------------------------------------------===// 841// ARM schedules. 842//===----------------------------------------------------------------------===// 843// 844include "ARMPredicates.td" 845include "ARMSchedule.td" 846 847//===----------------------------------------------------------------------===// 848// ARM processors 849// 850 851// Dummy CPU, used to target architectures 852def : ProcessorModel<"generic", CortexA8Model, []>; 853 854// FIXME: Several processors below are not using their own scheduler 855// model, but one of similar/previous processor. These should be fixed. 856 857def : ProcNoItin<"arm8", [ARMv4]>; 858def : ProcNoItin<"arm810", [ARMv4]>; 859def : ProcNoItin<"strongarm", [ARMv4]>; 860def : ProcNoItin<"strongarm110", [ARMv4]>; 861def : ProcNoItin<"strongarm1100", [ARMv4]>; 862def : ProcNoItin<"strongarm1110", [ARMv4]>; 863 864def : ProcNoItin<"arm7tdmi", [ARMv4t]>; 865def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>; 866def : ProcNoItin<"arm710t", [ARMv4t]>; 867def : ProcNoItin<"arm720t", [ARMv4t]>; 868def : ProcNoItin<"arm9", [ARMv4t]>; 869def : ProcNoItin<"arm9tdmi", [ARMv4t]>; 870def : ProcNoItin<"arm920", [ARMv4t]>; 871def : ProcNoItin<"arm920t", [ARMv4t]>; 872def : ProcNoItin<"arm922t", [ARMv4t]>; 873def : ProcNoItin<"arm940t", [ARMv4t]>; 874def : ProcNoItin<"ep9312", [ARMv4t]>; 875 876def : ProcNoItin<"arm10tdmi", [ARMv5t]>; 877def : ProcNoItin<"arm1020t", [ARMv5t]>; 878 879def : ProcNoItin<"arm9e", [ARMv5te]>; 880def : ProcNoItin<"arm926ej-s", [ARMv5te]>; 881def : ProcNoItin<"arm946e-s", [ARMv5te]>; 882def : ProcNoItin<"arm966e-s", [ARMv5te]>; 883def : ProcNoItin<"arm968e-s", [ARMv5te]>; 884def : ProcNoItin<"arm10e", [ARMv5te]>; 885def : ProcNoItin<"arm1020e", [ARMv5te]>; 886def : ProcNoItin<"arm1022e", [ARMv5te]>; 887def : ProcNoItin<"xscale", [ARMv5te]>; 888def : ProcNoItin<"iwmmxt", [ARMv5te]>; 889 890def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>; 891def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, 892 FeatureVFP2, 893 FeatureHasSlowFPVMLx]>; 894 895def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>; 896def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>; 897def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>; 898def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>; 899 900def : Processor<"arm1176j-s", ARMV6Itineraries, [ARMv6kz]>; 901def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; 902def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, 903 FeatureVFP2, 904 FeatureHasSlowFPVMLx]>; 905 906def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>; 907def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k, 908 FeatureVFP2, 909 FeatureHasSlowFPVMLx]>; 910 911def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>; 912def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2, 913 FeatureVFP2, 914 FeatureHasSlowFPVMLx]>; 915 916def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5, 917 FeatureHasRetAddrStack, 918 FeatureTrustZone, 919 FeatureSlowFPBrcc, 920 FeatureHasSlowFPVMLx, 921 FeatureVMLxForwarding, 922 FeatureMP, 923 FeatureVFP4]>; 924 925def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7, 926 FeatureHasRetAddrStack, 927 FeatureTrustZone, 928 FeatureSlowFPBrcc, 929 FeatureHasVMLxHazards, 930 FeatureHasSlowFPVMLx, 931 FeatureVMLxForwarding, 932 FeatureMP, 933 FeatureVFP4, 934 FeatureVirtualization]>; 935 936def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, 937 FeatureHasRetAddrStack, 938 FeatureNonpipelinedVFP, 939 FeatureTrustZone, 940 FeatureSlowFPBrcc, 941 FeatureHasVMLxHazards, 942 FeatureHasSlowFPVMLx, 943 FeatureVMLxForwarding]>; 944 945def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9, 946 FeatureHasRetAddrStack, 947 FeatureTrustZone, 948 FeatureHasVMLxHazards, 949 FeatureVMLxForwarding, 950 FeatureFP16, 951 FeatureAvoidPartialCPSR, 952 FeatureExpandMLx, 953 FeaturePreferVMOVSR, 954 FeatureMuxedUnits, 955 FeatureNEONForFPMovs, 956 FeatureCheckVLDnAlign, 957 FeatureMP]>; 958 959def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12, 960 FeatureHasRetAddrStack, 961 FeatureTrustZone, 962 FeatureVMLxForwarding, 963 FeatureVFP4, 964 FeatureAvoidPartialCPSR, 965 FeatureVirtualization, 966 FeatureMP]>; 967 968def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, 969 FeatureDontWidenVMOVS, 970 FeatureSplatVFPToNeon, 971 FeatureHasRetAddrStack, 972 FeatureMuxedUnits, 973 FeatureTrustZone, 974 FeatureVFP4, 975 FeatureMP, 976 FeatureCheckVLDnAlign, 977 FeatureAvoidPartialCPSR, 978 FeatureVirtualization]>; 979 980def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17, 981 FeatureHasRetAddrStack, 982 FeatureTrustZone, 983 FeatureMP, 984 FeatureVMLxForwarding, 985 FeatureVFP4, 986 FeatureAvoidPartialCPSR, 987 FeatureVirtualization]>; 988 989// FIXME: krait has currently the same features as A9 plus VFP4 and HWDiv 990def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, 991 FeatureHasRetAddrStack, 992 FeatureMuxedUnits, 993 FeatureCheckVLDnAlign, 994 FeatureVMLxForwarding, 995 FeatureFP16, 996 FeatureAvoidPartialCPSR, 997 FeatureVFP4, 998 FeatureHWDivThumb, 999 FeatureHWDivARM]>; 1000 1001def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, 1002 FeatureHasRetAddrStack, 1003 FeatureNEONForFP, 1004 FeatureVFP4, 1005 FeatureUseWideStrideVFP, 1006 FeatureMP, 1007 FeatureHWDivThumb, 1008 FeatureHWDivARM, 1009 FeatureAvoidPartialCPSR, 1010 FeatureAvoidMOVsShOp, 1011 FeatureHasSlowFPVMLx, 1012 FeatureHasVMLxHazards, 1013 FeatureProfUnpredicate, 1014 FeaturePrefISHSTBarrier, 1015 FeatureSlowOddRegister, 1016 FeatureSlowLoadDSubreg, 1017 FeatureSlowVGETLNi32, 1018 FeatureSlowVDUP32, 1019 FeatureUseMISched, 1020 FeatureNoPostRASched]>; 1021 1022def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, 1023 FeatureHasRetAddrStack, 1024 FeatureAvoidPartialCPSR]>; 1025 1026def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4, 1027 FeatureHasRetAddrStack, 1028 FeatureSlowFPBrcc, 1029 FeatureHasSlowFPVMLx, 1030 FeatureVFP3_D16, 1031 FeatureAvoidPartialCPSR]>; 1032 1033def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, 1034 FeatureHasRetAddrStack, 1035 FeatureVFP3_D16, 1036 FeatureSlowFPBrcc, 1037 FeatureHWDivARM, 1038 FeatureHasSlowFPVMLx, 1039 FeatureAvoidPartialCPSR]>; 1040 1041def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, 1042 FeatureHasRetAddrStack, 1043 FeatureVFP3_D16, 1044 FeatureFP16, 1045 FeatureMP, 1046 FeatureSlowFPBrcc, 1047 FeatureHWDivARM, 1048 FeatureHasSlowFPVMLx, 1049 FeatureAvoidPartialCPSR]>; 1050 1051def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, 1052 FeatureHasRetAddrStack, 1053 FeatureVFP3_D16, 1054 FeatureFP16, 1055 FeatureMP, 1056 FeatureSlowFPBrcc, 1057 FeatureHWDivARM, 1058 FeatureHasSlowFPVMLx, 1059 FeatureAvoidPartialCPSR]>; 1060 1061def : ProcessorModel<"cortex-m3", CortexM4Model, [ARMv7m, 1062 ProcM3, 1063 FeaturePrefLoopAlign32, 1064 FeatureUseMISched, 1065 FeatureHasNoBranchPredictor]>; 1066 1067def : ProcessorModel<"sc300", CortexM4Model, [ARMv7m, 1068 ProcM3, 1069 FeatureUseMISched, 1070 FeatureHasNoBranchPredictor]>; 1071 1072def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em, 1073 FeatureVFP4_D16_SP, 1074 FeaturePrefLoopAlign32, 1075 FeatureHasSlowFPVMLx, 1076 FeatureUseMISched, 1077 FeatureHasNoBranchPredictor]>; 1078 1079def : ProcNoItin<"cortex-m7", [ARMv7em, 1080 FeatureFPARMv8_D16]>; 1081 1082def : ProcNoItin<"cortex-m23", [ARMv8mBaseline, 1083 FeatureNoMovt]>; 1084 1085def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline, 1086 FeatureDSP, 1087 FeatureFPARMv8_D16_SP, 1088 FeaturePrefLoopAlign32, 1089 FeatureHasSlowFPVMLx, 1090 FeatureUseMISched, 1091 FeatureHasNoBranchPredictor]>; 1092 1093def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline, 1094 FeatureDSP, 1095 FeatureFPARMv8_D16_SP, 1096 FeaturePrefLoopAlign32, 1097 FeatureHasSlowFPVMLx, 1098 FeatureUseMISched, 1099 FeatureHasNoBranchPredictor]>; 1100 1101 1102def : ProcNoItin<"cortex-a32", [ARMv8a, 1103 FeatureHWDivThumb, 1104 FeatureHWDivARM, 1105 FeatureCrypto, 1106 FeatureCRC]>; 1107 1108def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, 1109 FeatureHWDivThumb, 1110 FeatureHWDivARM, 1111 FeatureCrypto, 1112 FeatureCRC]>; 1113 1114def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, 1115 FeatureHWDivThumb, 1116 FeatureHWDivARM, 1117 FeatureCrypto, 1118 FeatureCRC, 1119 FeatureFPAO]>; 1120 1121def : ProcNoItin<"cortex-a55", [ARMv82a, ProcA55, 1122 FeatureHWDivThumb, 1123 FeatureHWDivARM, 1124 FeatureDotProd]>; 1125 1126def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57, 1127 FeatureHWDivThumb, 1128 FeatureHWDivARM, 1129 FeatureCrypto, 1130 FeatureCRC, 1131 FeatureFPAO, 1132 FeatureAvoidPartialCPSR, 1133 FeatureCheapPredicableCPSR]>; 1134 1135def : ProcessorModel<"cortex-a72", CortexA57Model, [ARMv8a, ProcA72, 1136 FeatureHWDivThumb, 1137 FeatureHWDivARM, 1138 FeatureCrypto, 1139 FeatureCRC]>; 1140 1141def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73, 1142 FeatureHWDivThumb, 1143 FeatureHWDivARM, 1144 FeatureCrypto, 1145 FeatureCRC]>; 1146 1147def : ProcNoItin<"cortex-a75", [ARMv82a, ProcA75, 1148 FeatureHWDivThumb, 1149 FeatureHWDivARM, 1150 FeatureDotProd]>; 1151 1152def : ProcNoItin<"cortex-a76", [ARMv82a, ProcA76, 1153 FeatureHWDivThumb, 1154 FeatureHWDivARM, 1155 FeatureCrypto, 1156 FeatureCRC, 1157 FeatureFullFP16, 1158 FeatureDotProd]>; 1159 1160def : ProcNoItin<"cortex-a76ae", [ARMv82a, ProcA76, 1161 FeatureHWDivThumb, 1162 FeatureHWDivARM, 1163 FeatureCrypto, 1164 FeatureCRC, 1165 FeatureFullFP16, 1166 FeatureDotProd]>; 1167 1168def : ProcNoItin<"neoverse-n1", [ARMv82a, 1169 FeatureHWDivThumb, 1170 FeatureHWDivARM, 1171 FeatureCrypto, 1172 FeatureCRC, 1173 FeatureDotProd]>; 1174 1175def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, 1176 FeatureHasRetAddrStack, 1177 FeatureNEONForFP, 1178 FeatureVFP4, 1179 FeatureMP, 1180 FeatureHWDivThumb, 1181 FeatureHWDivARM, 1182 FeatureAvoidPartialCPSR, 1183 FeatureAvoidMOVsShOp, 1184 FeatureHasSlowFPVMLx, 1185 FeatureCrypto, 1186 FeatureUseMISched, 1187 FeatureZCZeroing, 1188 FeatureNoPostRASched]>; 1189 1190def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynos]>; 1191def : ProcNoItin<"exynos-m4", [ARMv82a, ProcExynos, 1192 FeatureFullFP16, 1193 FeatureDotProd]>; 1194def : ProcNoItin<"exynos-m5", [ARMv82a, ProcExynos, 1195 FeatureFullFP16, 1196 FeatureDotProd]>; 1197 1198def : ProcNoItin<"kryo", [ARMv8a, ProcKryo, 1199 FeatureHWDivThumb, 1200 FeatureHWDivARM, 1201 FeatureCrypto, 1202 FeatureCRC]>; 1203 1204def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, 1205 FeatureUseMISched, 1206 FeatureFPAO]>; 1207 1208//===----------------------------------------------------------------------===// 1209// Register File Description 1210//===----------------------------------------------------------------------===// 1211 1212include "ARMRegisterInfo.td" 1213include "ARMRegisterBanks.td" 1214include "ARMCallingConv.td" 1215 1216//===----------------------------------------------------------------------===// 1217// Instruction Descriptions 1218//===----------------------------------------------------------------------===// 1219 1220include "ARMInstrInfo.td" 1221def ARMInstrInfo : InstrInfo; 1222 1223//===----------------------------------------------------------------------===// 1224// Declare the target which we are implementing 1225//===----------------------------------------------------------------------===// 1226 1227def ARMAsmWriter : AsmWriter { 1228 string AsmWriterClassName = "InstPrinter"; 1229 int PassSubtarget = 1; 1230 int Variant = 0; 1231 bit isMCAsmWriter = 1; 1232} 1233 1234def ARMAsmParser : AsmParser { 1235 bit ReportMultipleNearMisses = 1; 1236} 1237 1238def ARMAsmParserVariant : AsmParserVariant { 1239 int Variant = 0; 1240 string Name = "ARM"; 1241 string BreakCharacters = "."; 1242} 1243 1244def ARM : Target { 1245 // Pull in Instruction Info. 1246 let InstructionSet = ARMInstrInfo; 1247 let AssemblyWriters = [ARMAsmWriter]; 1248 let AssemblyParsers = [ARMAsmParser]; 1249 let AssemblyParserVariants = [ARMAsmParserVariant]; 1250 let AllowRegisterRenaming = 1; 1251} 1252