1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// ARM Subtarget state. 20// 21 22def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", 23 "true", "Thumb mode">; 24 25def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat", 26 "true", "Use software floating " 27 "point features.">; 28 29 30//===----------------------------------------------------------------------===// 31// ARM Subtarget features. 32// 33 34// Floating Point, HW Division and Neon Support 35def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 36 "Enable VFP2 instructions">; 37 38def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true", 39 "Enable VFP3 instructions", 40 [FeatureVFP2]>; 41 42def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 43 "Enable NEON instructions", 44 [FeatureVFP3]>; 45 46def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 47 "Enable half-precision " 48 "floating point">; 49 50def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true", 51 "Enable VFP4 instructions", 52 [FeatureVFP3, FeatureFP16]>; 53 54def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", 55 "true", "Enable ARMv8 FP", 56 [FeatureVFP4]>; 57 58def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 59 "Enable full half-precision " 60 "floating point", 61 [FeatureFPARMv8]>; 62 63def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 64 "Enable full half-precision " 65 "floating point fml instructions", 66 [FeatureFullFP16]>; 67 68def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true", 69 "Floating point unit supports " 70 "single precision only">; 71 72def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true", 73 "Restrict FP to 16 double registers">; 74 75def FeatureHWDivThumb : SubtargetFeature<"hwdiv", 76 "HasHardwareDivideInThumb", "true", 77 "Enable divide instructions in Thumb">; 78 79def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", 80 "HasHardwareDivideInARM", "true", 81 "Enable divide instructions in ARM mode">; 82 83// Atomic Support 84def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 85 "Has data barrier (dmb/dsb) instructions">; 86 87def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", 88 "Has v7 clrex instruction">; 89 90def FeatureDFB : SubtargetFeature<"dfb", "HasFullDataBarrier", "true", 91 "Has full data barrier (dfb) instruction">; 92 93def FeatureAcquireRelease : SubtargetFeature<"acquire-release", 94 "HasAcquireRelease", "true", 95 "Has v8 acquire/release (lda/ldaex " 96 " etc) instructions">; 97 98 99def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 100 "FP compare + branch is slow">; 101 102def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 103 "Enable support for Performance " 104 "Monitor extensions">; 105 106 107// TrustZone Security Extensions 108def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", 109 "Enable support for TrustZone " 110 "security extensions">; 111 112def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true", 113 "Enable support for ARMv8-M " 114 "Security Extensions">; 115 116def FeatureSHA2 : SubtargetFeature<"sha2", "HasSHA2", "true", 117 "Enable SHA1 and SHA256 support", [FeatureNEON]>; 118 119def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", 120 "Enable AES support", [FeatureNEON]>; 121 122def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 123 "Enable support for " 124 "Cryptography extensions", 125 [FeatureNEON, FeatureSHA2, FeatureAES]>; 126 127def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 128 "Enable support for CRC instructions">; 129 130def FeatureDotProd : SubtargetFeature<"dotprod", "HasDotProd", "true", 131 "Enable support for dot product instructions", 132 [FeatureNEON]>; 133 134// Not to be confused with FeatureHasRetAddrStack (return address stack) 135def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 136 "Enable Reliability, Availability " 137 "and Serviceability extensions">; 138 139// Fast computation of non-negative address offsets 140def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true", 141 "Enable fast computation of " 142 "positive address offsets">; 143 144// Fast execution of AES crypto operations 145def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true", 146 "CPU fuses AES crypto operations">; 147 148// Fast execution of bottom and top halves of literal generation 149def FeatureFuseLiterals : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true", 150 "CPU fuses literal generation operations">; 151 152// The way of reading thread pointer 153def FeatureReadTp : SubtargetFeature<"read-tp-hard", "ReadTPHard", "true", 154 "Reading thread pointer from register">; 155 156// Cyclone can zero VFP registers in 0 cycles. 157def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 158 "Has zero-cycle zeroing instructions">; 159 160// Whether it is profitable to unpredicate certain instructions during if-conversion 161def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr", 162 "IsProfitableToUnpredicate", "true", 163 "Is profitable to unpredicate">; 164 165// Some targets (e.g. Swift) have microcoded VGETLNi32. 166def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32", 167 "HasSlowVGETLNi32", "true", 168 "Has slow VGETLNi32 - prefer VMOV">; 169 170// Some targets (e.g. Swift) have microcoded VDUP32. 171def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", 172 "true", 173 "Has slow VDUP32 - prefer VMOV">; 174 175// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON 176// for scalar FP, as this allows more effective execution domain optimization. 177def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR", 178 "true", "Prefer VMOVSR">; 179 180// Swift has ISHST barriers compatible with Atomic Release semantics but weaker 181// than ISH 182def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST", 183 "true", "Prefer ISHST barriers">; 184 185// Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU. 186def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", 187 "true", 188 "Has muxed AGU and NEON/FPU">; 189 190// Whether VLDM/VSTM starting with odd register number need more microops 191// than single VLDRS 192def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister", 193 "true", "VLDM/VSTM starting " 194 "with an odd register is slow">; 195 196// Some targets have a renaming dependency when loading into D subregisters. 197def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg", 198 "SlowLoadDSubregister", "true", 199 "Loading into D subregs is slow">; 200 201def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp", 202 "UseWideStrideVFP", "true", 203 "Use a wide stride when allocating VFP registers">; 204 205// Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD. 206def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs", 207 "DontWidenVMOVS", "true", 208 "Don't widen VMOVS to VMOVD">; 209 210// Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different 211// VFP register widths. 212def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon", 213 "SplatVFPToNeon", "true", 214 "Splat register from VFP to NEON", 215 [FeatureDontWidenVMOVS]>; 216 217// Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions. 218def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", 219 "ExpandMLx", "true", 220 "Expand VFP/NEON MLA/MLS instructions">; 221 222// Some targets have special RAW hazards for VFP/NEON VMLA/VMLS. 223def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards", 224 "true", "Has VMLx hazards">; 225 226// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from 227// VFP to NEON, as an execution domain optimization. 228def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", 229 "UseNEONForFPMovs", "true", 230 "Convert VMOVSR, VMOVRS, " 231 "VMOVS to NEON">; 232 233// Some processors benefit from using NEON instructions for scalar 234// single-precision FP operations. This affects instruction selection and should 235// only be enabled if the handling of denormals is not important. 236def FeatureNEONForFP : SubtargetFeature<"neonfp", 237 "UseNEONForSinglePrecisionFP", 238 "true", 239 "Use NEON for single precision FP">; 240 241// On some processors, VLDn instructions that access unaligned data take one 242// extra cycle. Take that into account when computing operand latencies. 243def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign", 244 "true", 245 "Check for VLDn unaligned access">; 246 247// Some processors have a nonpipelined VFP coprocessor. 248def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp", 249 "NonpipelinedVFP", "true", 250 "VFP instructions are not pipelined">; 251 252// Some processors have FP multiply-accumulate instructions that don't 253// play nicely with other VFP / NEON instructions, and it's generally better 254// to just not use them. 255def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 256 "Disable VFP / NEON MAC instructions">; 257 258// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 259def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 260 "HasVMLxForwarding", "true", 261 "Has multiplier accumulator forwarding">; 262 263// Disable 32-bit to 16-bit narrowing for experimentation. 264def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 265 "Prefer 32-bit Thumb instrs">; 266 267def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopAlignment","2", 268 "Prefer 32-bit alignment for loops">; 269 270/// Some instructions update CPSR partially, which can add false dependency for 271/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 272/// mapped to a separate physical register. Avoid partial CPSR update for these 273/// processors. 274def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 275 "AvoidCPSRPartialUpdate", "true", 276 "Avoid CPSR partial update for OOO execution">; 277 278/// Disable +1 predication cost for instructions updating CPSR. 279/// Enabled for Cortex-A57. 280def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr", 281 "CheapPredicableCPSRDef", 282 "true", 283 "Disable +1 predication cost for instructions updating CPSR">; 284 285def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", 286 "AvoidMOVsShifterOperand", "true", 287 "Avoid movs instructions with " 288 "shifter operand">; 289 290// Some processors perform return stack prediction. CodeGen should avoid issue 291// "normal" call instructions to callees which do not return. 292def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", 293 "HasRetAddrStack", "true", 294 "Has return address stack">; 295 296// Some processors have no branch predictor, which changes the expected cost of 297// taking a branch which affects the choice of whether to use predicated 298// instructions. 299def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor", 300 "HasBranchPredictor", "false", 301 "Has no branch predictor">; 302 303/// DSP extension. 304def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", 305 "Supports DSP instructions in " 306 "ARM and/or Thumb2">; 307 308// Multiprocessing extension. 309def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 310 "Supports Multiprocessing extension">; 311 312// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). 313def FeatureVirtualization : SubtargetFeature<"virtualization", 314 "HasVirtualization", "true", 315 "Supports Virtualization extension", 316 [FeatureHWDivThumb, FeatureHWDivARM]>; 317 318// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. 319// See ARMInstrInfo.td for details. 320def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", 321 "NaCl trap">; 322 323def FeatureStrictAlign : SubtargetFeature<"strict-align", 324 "StrictAlign", "true", 325 "Disallow all unaligned memory " 326 "access">; 327 328def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", 329 "Generate calls via indirect call " 330 "instructions">; 331 332def FeatureExecuteOnly : SubtargetFeature<"execute-only", 333 "GenExecuteOnly", "true", 334 "Enable the generation of " 335 "execute only code.">; 336 337def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", 338 "Reserve R9, making it unavailable" 339 " as GPR">; 340 341def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", 342 "Don't use movt/movw pairs for " 343 "32-bit imms">; 344 345def FeatureNoNegativeImmediates 346 : SubtargetFeature<"no-neg-immediates", 347 "NegativeImmediates", "false", 348 "Convert immediates and instructions " 349 "to their negated or complemented " 350 "equivalent when the immediate does " 351 "not fit in the encoding.">; 352 353// Use the MachineScheduler for instruction scheduling for the subtarget. 354def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true", 355 "Use the MachineScheduler">; 356 357def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler", 358 "DisablePostRAScheduler", "true", 359 "Don't schedule again after register allocation">; 360 361// Enable use of alias analysis during code generation 362def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", 363 "Use alias analysis during codegen">; 364 365// Armv8.5-A extensions 366 367def FeatureSB : SubtargetFeature<"sb", "HasSB", "true", 368 "Enable v8.5a Speculation Barrier" >; 369 370//===----------------------------------------------------------------------===// 371// ARM architecture class 372// 373 374// A-series ISA 375def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", 376 "Is application profile ('A' series)">; 377 378// R-series ISA 379def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", 380 "Is realtime profile ('R' series)">; 381 382// M-series ISA 383def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", 384 "Is microcontroller profile ('M' series)">; 385 386 387def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 388 "Enable Thumb2 instructions">; 389 390def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 391 "Does not support ARM mode execution">; 392 393//===----------------------------------------------------------------------===// 394// ARM ISAa. 395// 396 397def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 398 "Support ARM v4T instructions">; 399 400def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 401 "Support ARM v5T instructions", 402 [HasV4TOps]>; 403 404def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 405 "Support ARM v5TE, v5TEj, and " 406 "v5TExp instructions", 407 [HasV5TOps]>; 408 409def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 410 "Support ARM v6 instructions", 411 [HasV5TEOps]>; 412 413def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", 414 "Support ARM v6M instructions", 415 [HasV6Ops]>; 416 417def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true", 418 "Support ARM v8M Baseline instructions", 419 [HasV6MOps]>; 420 421def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true", 422 "Support ARM v6k instructions", 423 [HasV6Ops]>; 424 425def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 426 "Support ARM v6t2 instructions", 427 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>; 428 429def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 430 "Support ARM v7 instructions", 431 [HasV6T2Ops, FeaturePerfMon, 432 FeatureV7Clrex]>; 433 434def HasV8MMainlineOps : 435 SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true", 436 "Support ARM v8M Mainline instructions", 437 [HasV7Ops]>; 438 439def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", 440 "Support ARM v8 instructions", 441 [HasV7Ops, FeatureAcquireRelease]>; 442 443def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 444 "Support ARM v8.1a instructions", 445 [HasV8Ops]>; 446 447def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 448 "Support ARM v8.2a instructions", 449 [HasV8_1aOps]>; 450 451def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 452 "Support ARM v8.3a instructions", 453 [HasV8_2aOps]>; 454 455def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 456 "Support ARM v8.4a instructions", 457 [HasV8_3aOps, FeatureDotProd]>; 458 459def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true", 460 "Support ARM v8.5a instructions", 461 [HasV8_4aOps, FeatureSB]>; 462 463//===----------------------------------------------------------------------===// 464// ARM Processor subtarget features. 465// 466 467def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", 468 "Cortex-A5 ARM processors", []>; 469def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", 470 "Cortex-A7 ARM processors", []>; 471def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 472 "Cortex-A8 ARM processors", []>; 473def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 474 "Cortex-A9 ARM processors", []>; 475def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", 476 "Cortex-A12 ARM processors", []>; 477def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", 478 "Cortex-A15 ARM processors", []>; 479def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", 480 "Cortex-A17 ARM processors", []>; 481def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32", 482 "Cortex-A32 ARM processors", []>; 483def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 484 "Cortex-A35 ARM processors", []>; 485def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 486 "Cortex-A53 ARM processors", []>; 487def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 488 "Cortex-A55 ARM processors", []>; 489def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 490 "Cortex-A57 ARM processors", []>; 491def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 492 "Cortex-A72 ARM processors", []>; 493def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 494 "Cortex-A73 ARM processors", []>; 495def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 496 "Cortex-A75 ARM processors", []>; 497def ProcA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 498 "Cortex-A76 ARM processors", []>; 499 500def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", 501 "Qualcomm Krait processors", []>; 502def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 503 "Qualcomm Kryo processors", []>; 504def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", 505 "Swift ARM processors", []>; 506 507def ProcExynos : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos", 508 "Samsung Exynos processors", 509 [FeatureZCZeroing, 510 FeatureUseWideStrideVFP, 511 FeatureUseAA, 512 FeatureSplatVFPToNeon, 513 FeatureSlowVGETLNi32, 514 FeatureSlowVDUP32, 515 FeatureSlowFPBrcc, 516 FeatureProfUnpredicate, 517 FeatureHWDivThumb, 518 FeatureHWDivARM, 519 FeatureHasSlowFPVMLx, 520 FeatureHasRetAddrStack, 521 FeatureFuseLiterals, 522 FeatureFuseAES, 523 FeatureExpandMLx, 524 FeatureCrypto, 525 FeatureCRC]>; 526 527def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", 528 "Cortex-R4 ARM processors", []>; 529def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", 530 "Cortex-R5 ARM processors", []>; 531def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", 532 "Cortex-R7 ARM processors", []>; 533def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52", 534 "Cortex-R52 ARM processors", []>; 535 536def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", 537 "Cortex-M3 ARM processors", []>; 538 539 540//===----------------------------------------------------------------------===// 541// ARM Helper classes. 542// 543 544class Architecture<string fname, string aname, list<SubtargetFeature> features> 545 : SubtargetFeature<fname, "ARMArch", aname, 546 !strconcat(aname, " architecture"), features>; 547 548class ProcNoItin<string Name, list<SubtargetFeature> Features> 549 : Processor<Name, NoItineraries, Features>; 550 551 552//===----------------------------------------------------------------------===// 553// ARM architectures 554// 555 556def ARMv2 : Architecture<"armv2", "ARMv2", []>; 557 558def ARMv2a : Architecture<"armv2a", "ARMv2a", []>; 559 560def ARMv3 : Architecture<"armv3", "ARMv3", []>; 561 562def ARMv3m : Architecture<"armv3m", "ARMv3m", []>; 563 564def ARMv4 : Architecture<"armv4", "ARMv4", []>; 565 566def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>; 567 568def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>; 569 570def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>; 571 572def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>; 573 574def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops, 575 FeatureDSP]>; 576 577def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, 578 FeatureDSP]>; 579 580def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; 581 582def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, 583 FeatureTrustZone]>; 584 585def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, 586 FeatureNoARM, 587 ModeThumb, 588 FeatureDB, 589 FeatureMClass, 590 FeatureStrictAlign]>; 591 592def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, 593 FeatureNoARM, 594 ModeThumb, 595 FeatureDB, 596 FeatureMClass, 597 FeatureStrictAlign]>; 598 599def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, 600 FeatureNEON, 601 FeatureDB, 602 FeatureDSP, 603 FeatureAClass]>; 604 605def ARMv7ve : Architecture<"armv7ve", "ARMv7ve", [HasV7Ops, 606 FeatureNEON, 607 FeatureDB, 608 FeatureDSP, 609 FeatureTrustZone, 610 FeatureMP, 611 FeatureVirtualization, 612 FeatureAClass]>; 613 614def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, 615 FeatureDB, 616 FeatureDSP, 617 FeatureHWDivThumb, 618 FeatureRClass]>; 619 620def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, 621 FeatureThumb2, 622 FeatureNoARM, 623 ModeThumb, 624 FeatureDB, 625 FeatureHWDivThumb, 626 FeatureMClass]>; 627 628def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, 629 FeatureThumb2, 630 FeatureNoARM, 631 ModeThumb, 632 FeatureDB, 633 FeatureHWDivThumb, 634 FeatureMClass, 635 FeatureDSP]>; 636 637def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, 638 FeatureAClass, 639 FeatureDB, 640 FeatureFPARMv8, 641 FeatureNEON, 642 FeatureDSP, 643 FeatureTrustZone, 644 FeatureMP, 645 FeatureVirtualization, 646 FeatureCrypto, 647 FeatureCRC]>; 648 649def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps, 650 FeatureAClass, 651 FeatureDB, 652 FeatureFPARMv8, 653 FeatureNEON, 654 FeatureDSP, 655 FeatureTrustZone, 656 FeatureMP, 657 FeatureVirtualization, 658 FeatureCrypto, 659 FeatureCRC]>; 660 661def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, 662 FeatureAClass, 663 FeatureDB, 664 FeatureFPARMv8, 665 FeatureNEON, 666 FeatureDSP, 667 FeatureTrustZone, 668 FeatureMP, 669 FeatureVirtualization, 670 FeatureCrypto, 671 FeatureCRC, 672 FeatureRAS]>; 673 674def ARMv83a : Architecture<"armv8.3-a", "ARMv83a", [HasV8_3aOps, 675 FeatureAClass, 676 FeatureDB, 677 FeatureFPARMv8, 678 FeatureNEON, 679 FeatureDSP, 680 FeatureTrustZone, 681 FeatureMP, 682 FeatureVirtualization, 683 FeatureCrypto, 684 FeatureCRC, 685 FeatureRAS]>; 686 687def ARMv84a : Architecture<"armv8.4-a", "ARMv84a", [HasV8_4aOps, 688 FeatureAClass, 689 FeatureDB, 690 FeatureFPARMv8, 691 FeatureNEON, 692 FeatureDSP, 693 FeatureTrustZone, 694 FeatureMP, 695 FeatureVirtualization, 696 FeatureCrypto, 697 FeatureCRC, 698 FeatureRAS, 699 FeatureDotProd]>; 700 701def ARMv85a : Architecture<"armv8.5-a", "ARMv85a", [HasV8_5aOps, 702 FeatureAClass, 703 FeatureDB, 704 FeatureFPARMv8, 705 FeatureNEON, 706 FeatureDSP, 707 FeatureTrustZone, 708 FeatureMP, 709 FeatureVirtualization, 710 FeatureCrypto, 711 FeatureCRC, 712 FeatureRAS, 713 FeatureDotProd]>; 714 715def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, 716 FeatureRClass, 717 FeatureDB, 718 FeatureDFB, 719 FeatureDSP, 720 FeatureCRC, 721 FeatureMP, 722 FeatureVirtualization, 723 FeatureFPARMv8, 724 FeatureNEON]>; 725 726def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", 727 [HasV8MBaselineOps, 728 FeatureNoARM, 729 ModeThumb, 730 FeatureDB, 731 FeatureHWDivThumb, 732 FeatureV7Clrex, 733 Feature8MSecExt, 734 FeatureAcquireRelease, 735 FeatureMClass, 736 FeatureStrictAlign]>; 737 738def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", 739 [HasV8MMainlineOps, 740 FeatureNoARM, 741 ModeThumb, 742 FeatureDB, 743 FeatureHWDivThumb, 744 Feature8MSecExt, 745 FeatureAcquireRelease, 746 FeatureMClass]>; 747 748// Aliases 749def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; 750def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; 751def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; 752def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; 753def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; 754def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; 755 756 757//===----------------------------------------------------------------------===// 758// ARM schedules. 759//===----------------------------------------------------------------------===// 760// 761include "ARMSchedule.td" 762 763//===----------------------------------------------------------------------===// 764// ARM processors 765// 766 767// Dummy CPU, used to target architectures 768def : ProcessorModel<"generic", CortexA8Model, []>; 769 770// FIXME: Several processors below are not using their own scheduler 771// model, but one of similar/previous processor. These should be fixed. 772 773def : ProcNoItin<"arm8", [ARMv4]>; 774def : ProcNoItin<"arm810", [ARMv4]>; 775def : ProcNoItin<"strongarm", [ARMv4]>; 776def : ProcNoItin<"strongarm110", [ARMv4]>; 777def : ProcNoItin<"strongarm1100", [ARMv4]>; 778def : ProcNoItin<"strongarm1110", [ARMv4]>; 779 780def : ProcNoItin<"arm7tdmi", [ARMv4t]>; 781def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>; 782def : ProcNoItin<"arm710t", [ARMv4t]>; 783def : ProcNoItin<"arm720t", [ARMv4t]>; 784def : ProcNoItin<"arm9", [ARMv4t]>; 785def : ProcNoItin<"arm9tdmi", [ARMv4t]>; 786def : ProcNoItin<"arm920", [ARMv4t]>; 787def : ProcNoItin<"arm920t", [ARMv4t]>; 788def : ProcNoItin<"arm922t", [ARMv4t]>; 789def : ProcNoItin<"arm940t", [ARMv4t]>; 790def : ProcNoItin<"ep9312", [ARMv4t]>; 791 792def : ProcNoItin<"arm10tdmi", [ARMv5t]>; 793def : ProcNoItin<"arm1020t", [ARMv5t]>; 794 795def : ProcNoItin<"arm9e", [ARMv5te]>; 796def : ProcNoItin<"arm926ej-s", [ARMv5te]>; 797def : ProcNoItin<"arm946e-s", [ARMv5te]>; 798def : ProcNoItin<"arm966e-s", [ARMv5te]>; 799def : ProcNoItin<"arm968e-s", [ARMv5te]>; 800def : ProcNoItin<"arm10e", [ARMv5te]>; 801def : ProcNoItin<"arm1020e", [ARMv5te]>; 802def : ProcNoItin<"arm1022e", [ARMv5te]>; 803def : ProcNoItin<"xscale", [ARMv5te]>; 804def : ProcNoItin<"iwmmxt", [ARMv5te]>; 805 806def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>; 807def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, 808 FeatureVFP2, 809 FeatureHasSlowFPVMLx]>; 810 811def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>; 812def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>; 813def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>; 814def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>; 815 816def : Processor<"arm1176j-s", ARMV6Itineraries, [ARMv6kz]>; 817def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; 818def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, 819 FeatureVFP2, 820 FeatureHasSlowFPVMLx]>; 821 822def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>; 823def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k, 824 FeatureVFP2, 825 FeatureHasSlowFPVMLx]>; 826 827def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>; 828def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2, 829 FeatureVFP2, 830 FeatureHasSlowFPVMLx]>; 831 832def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5, 833 FeatureHasRetAddrStack, 834 FeatureTrustZone, 835 FeatureSlowFPBrcc, 836 FeatureHasSlowFPVMLx, 837 FeatureVMLxForwarding, 838 FeatureMP, 839 FeatureVFP4]>; 840 841def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7, 842 FeatureHasRetAddrStack, 843 FeatureTrustZone, 844 FeatureSlowFPBrcc, 845 FeatureHasVMLxHazards, 846 FeatureHasSlowFPVMLx, 847 FeatureVMLxForwarding, 848 FeatureMP, 849 FeatureVFP4, 850 FeatureVirtualization]>; 851 852def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, 853 FeatureHasRetAddrStack, 854 FeatureNonpipelinedVFP, 855 FeatureTrustZone, 856 FeatureSlowFPBrcc, 857 FeatureHasVMLxHazards, 858 FeatureHasSlowFPVMLx, 859 FeatureVMLxForwarding]>; 860 861def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9, 862 FeatureHasRetAddrStack, 863 FeatureTrustZone, 864 FeatureHasVMLxHazards, 865 FeatureVMLxForwarding, 866 FeatureFP16, 867 FeatureAvoidPartialCPSR, 868 FeatureExpandMLx, 869 FeaturePreferVMOVSR, 870 FeatureMuxedUnits, 871 FeatureNEONForFPMovs, 872 FeatureCheckVLDnAlign, 873 FeatureMP]>; 874 875def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12, 876 FeatureHasRetAddrStack, 877 FeatureTrustZone, 878 FeatureVMLxForwarding, 879 FeatureVFP4, 880 FeatureAvoidPartialCPSR, 881 FeatureVirtualization, 882 FeatureMP]>; 883 884def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, 885 FeatureDontWidenVMOVS, 886 FeatureSplatVFPToNeon, 887 FeatureHasRetAddrStack, 888 FeatureMuxedUnits, 889 FeatureTrustZone, 890 FeatureVFP4, 891 FeatureMP, 892 FeatureCheckVLDnAlign, 893 FeatureAvoidPartialCPSR, 894 FeatureVirtualization]>; 895 896def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17, 897 FeatureHasRetAddrStack, 898 FeatureTrustZone, 899 FeatureMP, 900 FeatureVMLxForwarding, 901 FeatureVFP4, 902 FeatureAvoidPartialCPSR, 903 FeatureVirtualization]>; 904 905// FIXME: krait has currently the same features as A9 plus VFP4 and HWDiv 906def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, 907 FeatureHasRetAddrStack, 908 FeatureMuxedUnits, 909 FeatureCheckVLDnAlign, 910 FeatureVMLxForwarding, 911 FeatureFP16, 912 FeatureAvoidPartialCPSR, 913 FeatureVFP4, 914 FeatureHWDivThumb, 915 FeatureHWDivARM]>; 916 917def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, 918 FeatureHasRetAddrStack, 919 FeatureNEONForFP, 920 FeatureVFP4, 921 FeatureUseWideStrideVFP, 922 FeatureMP, 923 FeatureHWDivThumb, 924 FeatureHWDivARM, 925 FeatureAvoidPartialCPSR, 926 FeatureAvoidMOVsShOp, 927 FeatureHasSlowFPVMLx, 928 FeatureHasVMLxHazards, 929 FeatureProfUnpredicate, 930 FeaturePrefISHSTBarrier, 931 FeatureSlowOddRegister, 932 FeatureSlowLoadDSubreg, 933 FeatureSlowVGETLNi32, 934 FeatureSlowVDUP32, 935 FeatureUseMISched, 936 FeatureNoPostRASched]>; 937 938def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, 939 FeatureHasRetAddrStack, 940 FeatureAvoidPartialCPSR]>; 941 942def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4, 943 FeatureHasRetAddrStack, 944 FeatureSlowFPBrcc, 945 FeatureHasSlowFPVMLx, 946 FeatureVFP3, 947 FeatureD16, 948 FeatureAvoidPartialCPSR]>; 949 950def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, 951 FeatureHasRetAddrStack, 952 FeatureVFP3, 953 FeatureD16, 954 FeatureSlowFPBrcc, 955 FeatureHWDivARM, 956 FeatureHasSlowFPVMLx, 957 FeatureAvoidPartialCPSR]>; 958 959def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, 960 FeatureHasRetAddrStack, 961 FeatureVFP3, 962 FeatureD16, 963 FeatureFP16, 964 FeatureMP, 965 FeatureSlowFPBrcc, 966 FeatureHWDivARM, 967 FeatureHasSlowFPVMLx, 968 FeatureAvoidPartialCPSR]>; 969 970def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, 971 FeatureHasRetAddrStack, 972 FeatureVFP3, 973 FeatureD16, 974 FeatureFP16, 975 FeatureMP, 976 FeatureSlowFPBrcc, 977 FeatureHWDivARM, 978 FeatureHasSlowFPVMLx, 979 FeatureAvoidPartialCPSR]>; 980 981def : ProcessorModel<"cortex-m3", CortexM3Model, [ARMv7m, 982 ProcM3, 983 FeaturePrefLoopAlign32, 984 FeatureHasNoBranchPredictor]>; 985 986def : ProcessorModel<"sc300", CortexM3Model, [ARMv7m, 987 ProcM3, 988 FeatureHasNoBranchPredictor]>; 989 990def : ProcessorModel<"cortex-m4", CortexM3Model, [ARMv7em, 991 FeatureVFP4, 992 FeatureVFPOnlySP, 993 FeatureD16, 994 FeaturePrefLoopAlign32, 995 FeatureHasSlowFPVMLx, 996 FeatureHasNoBranchPredictor]>; 997 998def : ProcNoItin<"cortex-m7", [ARMv7em, 999 FeatureFPARMv8, 1000 FeatureD16]>; 1001 1002def : ProcNoItin<"cortex-m23", [ARMv8mBaseline, 1003 FeatureNoMovt]>; 1004 1005def : ProcessorModel<"cortex-m33", CortexM3Model, [ARMv8mMainline, 1006 FeatureDSP, 1007 FeatureFPARMv8, 1008 FeatureD16, 1009 FeatureVFPOnlySP, 1010 FeaturePrefLoopAlign32, 1011 FeatureHasSlowFPVMLx, 1012 FeatureHasNoBranchPredictor]>; 1013 1014def : ProcessorModel<"cortex-m35p", CortexM3Model, [ARMv8mMainline, 1015 FeatureDSP, 1016 FeatureFPARMv8, 1017 FeatureD16, 1018 FeatureVFPOnlySP, 1019 FeaturePrefLoopAlign32, 1020 FeatureHasSlowFPVMLx, 1021 FeatureHasNoBranchPredictor]>; 1022 1023 1024def : ProcNoItin<"cortex-a32", [ARMv8a, 1025 FeatureHWDivThumb, 1026 FeatureHWDivARM, 1027 FeatureCrypto, 1028 FeatureCRC]>; 1029 1030def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, 1031 FeatureHWDivThumb, 1032 FeatureHWDivARM, 1033 FeatureCrypto, 1034 FeatureCRC]>; 1035 1036def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, 1037 FeatureHWDivThumb, 1038 FeatureHWDivARM, 1039 FeatureCrypto, 1040 FeatureCRC, 1041 FeatureFPAO]>; 1042 1043def : ProcNoItin<"cortex-a55", [ARMv82a, ProcA55, 1044 FeatureHWDivThumb, 1045 FeatureHWDivARM, 1046 FeatureDotProd]>; 1047 1048def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57, 1049 FeatureHWDivThumb, 1050 FeatureHWDivARM, 1051 FeatureCrypto, 1052 FeatureCRC, 1053 FeatureFPAO, 1054 FeatureAvoidPartialCPSR, 1055 FeatureCheapPredicableCPSR]>; 1056 1057def : ProcessorModel<"cortex-a72", CortexA57Model, [ARMv8a, ProcA72, 1058 FeatureHWDivThumb, 1059 FeatureHWDivARM, 1060 FeatureCrypto, 1061 FeatureCRC]>; 1062 1063def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73, 1064 FeatureHWDivThumb, 1065 FeatureHWDivARM, 1066 FeatureCrypto, 1067 FeatureCRC]>; 1068 1069def : ProcNoItin<"cortex-a75", [ARMv82a, ProcA75, 1070 FeatureHWDivThumb, 1071 FeatureHWDivARM, 1072 FeatureDotProd]>; 1073 1074def : ProcNoItin<"cortex-a76", [ARMv82a, ProcA76, 1075 FeatureHWDivThumb, 1076 FeatureHWDivARM, 1077 FeatureCrypto, 1078 FeatureCRC, 1079 FeatureFullFP16, 1080 FeatureDotProd]>; 1081 1082def : ProcNoItin<"cortex-a76ae", [ARMv82a, ProcA76, 1083 FeatureHWDivThumb, 1084 FeatureHWDivARM, 1085 FeatureCrypto, 1086 FeatureCRC, 1087 FeatureFullFP16, 1088 FeatureDotProd]>; 1089 1090def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, 1091 FeatureHasRetAddrStack, 1092 FeatureNEONForFP, 1093 FeatureVFP4, 1094 FeatureMP, 1095 FeatureHWDivThumb, 1096 FeatureHWDivARM, 1097 FeatureAvoidPartialCPSR, 1098 FeatureAvoidMOVsShOp, 1099 FeatureHasSlowFPVMLx, 1100 FeatureCrypto, 1101 FeatureUseMISched, 1102 FeatureZCZeroing, 1103 FeatureNoPostRASched]>; 1104 1105def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynos]>; 1106def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynos]>; 1107def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynos]>; 1108def : ProcNoItin<"exynos-m4", [ARMv82a, ProcExynos, 1109 FeatureFullFP16, 1110 FeatureDotProd]>; 1111def : ProcNoItin<"exynos-m5", [ARMv82a, ProcExynos, 1112 FeatureFullFP16, 1113 FeatureDotProd]>; 1114 1115def : ProcNoItin<"kryo", [ARMv8a, ProcKryo, 1116 FeatureHWDivThumb, 1117 FeatureHWDivARM, 1118 FeatureCrypto, 1119 FeatureCRC]>; 1120 1121def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, 1122 FeatureUseMISched, 1123 FeatureFPAO, 1124 FeatureUseAA]>; 1125 1126//===----------------------------------------------------------------------===// 1127// Register File Description 1128//===----------------------------------------------------------------------===// 1129 1130include "ARMRegisterInfo.td" 1131include "ARMRegisterBanks.td" 1132include "ARMCallingConv.td" 1133 1134//===----------------------------------------------------------------------===// 1135// Instruction Descriptions 1136//===----------------------------------------------------------------------===// 1137 1138include "ARMInstrInfo.td" 1139def ARMInstrInfo : InstrInfo; 1140 1141//===----------------------------------------------------------------------===// 1142// Declare the target which we are implementing 1143//===----------------------------------------------------------------------===// 1144 1145def ARMAsmWriter : AsmWriter { 1146 string AsmWriterClassName = "InstPrinter"; 1147 int PassSubtarget = 1; 1148 int Variant = 0; 1149 bit isMCAsmWriter = 1; 1150} 1151 1152def ARMAsmParser : AsmParser { 1153 bit ReportMultipleNearMisses = 1; 1154} 1155 1156def ARMAsmParserVariant : AsmParserVariant { 1157 int Variant = 0; 1158 string Name = "ARM"; 1159 string BreakCharacters = "."; 1160} 1161 1162def ARM : Target { 1163 // Pull in Instruction Info. 1164 let InstructionSet = ARMInstrInfo; 1165 let AssemblyWriters = [ARMAsmWriter]; 1166 let AssemblyParsers = [ARMAsmParser]; 1167 let AssemblyParserVariants = [ARMAsmParserVariant]; 1168 let AllowRegisterRenaming = 1; 1169} 1170