xref: /llvm-project-15.0.7/llvm/lib/Target/ARM/ARM.td (revision bbabd39c) 
1//===- ARM.td - Describe the ARM Target Machine -----------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// Target-independent interfaces which we are implementing
15//===----------------------------------------------------------------------===//
16
17include "llvm/Target/Target.td"
18
19//===----------------------------------------------------------------------===//
20// ARM Subtarget features.
21//
22
23def ArchV4T     : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
24                                   "ARM v4T">;
25def ArchV5T     : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
26                                   "ARM v5T">;
27def ArchV5TE    : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
28                                   "ARM v5TE, v5TEj, v5TExp">;
29def ArchV6      : SubtargetFeature<"v6", "ARMArchVersion", "V6",
30                                   "ARM v6">;
31def ArchV6T2    : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
32                                   "ARM v6t2">;
33def ArchV7A     : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
34                                   "ARM v7A">;
35def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
36                                   "Enable VFP2 instructions">;
37def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
38                                   "Enable VFP3 instructions">;
39def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
40                                   "Enable NEON instructions">;
41def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
42                                     "Enable Thumb2 instructions">;
43
44//===----------------------------------------------------------------------===//
45// ARM Processors supported.
46//
47
48include "ARMSchedule.td"
49
50class ProcNoItin<string Name, list<SubtargetFeature> Features>
51 : Processor<Name, GenericItineraries, Features>;
52
53// V4 Processors.
54def : ProcNoItin<"generic",         []>;
55def : ProcNoItin<"arm8",            []>;
56def : ProcNoItin<"arm810",          []>;
57def : ProcNoItin<"strongarm",       []>;
58def : ProcNoItin<"strongarm110",    []>;
59def : ProcNoItin<"strongarm1100",   []>;
60def : ProcNoItin<"strongarm1110",   []>;
61
62// V4T Processors.
63def : ProcNoItin<"arm7tdmi",        [ArchV4T]>;
64def : ProcNoItin<"arm7tdmi-s",      [ArchV4T]>;
65def : ProcNoItin<"arm710t",         [ArchV4T]>;
66def : ProcNoItin<"arm720t",         [ArchV4T]>;
67def : ProcNoItin<"arm9",            [ArchV4T]>;
68def : ProcNoItin<"arm9tdmi",        [ArchV4T]>;
69def : ProcNoItin<"arm920",          [ArchV4T]>;
70def : ProcNoItin<"arm920t",         [ArchV4T]>;
71def : ProcNoItin<"arm922t",         [ArchV4T]>;
72def : ProcNoItin<"arm940t",         [ArchV4T]>;
73def : ProcNoItin<"ep9312",          [ArchV4T]>;
74
75// V5T Processors.
76def : ProcNoItin<"arm10tdmi",       [ArchV5T]>;
77def : ProcNoItin<"arm1020t",        [ArchV5T]>;
78
79// V5TE Processors.
80def : ProcNoItin<"arm9e",           [ArchV5TE]>;
81def : ProcNoItin<"arm926ej-s",      [ArchV5TE]>;
82def : ProcNoItin<"arm946e-s",       [ArchV5TE]>;
83def : ProcNoItin<"arm966e-s",       [ArchV5TE]>;
84def : ProcNoItin<"arm968e-s",       [ArchV5TE]>;
85def : ProcNoItin<"arm10e",          [ArchV5TE]>;
86def : ProcNoItin<"arm1020e",        [ArchV5TE]>;
87def : ProcNoItin<"arm1022e",        [ArchV5TE]>;
88def : ProcNoItin<"xscale",          [ArchV5TE]>;
89def : ProcNoItin<"iwmmxt",          [ArchV5TE]>;
90
91// V6 Processors.
92def : Processor<"arm1136j-s",       V6Itineraries,
93                [ArchV6]>;
94def : Processor<"arm1136jf-s",      V6Itineraries,
95                [ArchV6, FeatureVFP2]>;
96def : Processor<"arm1176jz-s",      V6Itineraries,
97                [ArchV6]>;
98def : Processor<"arm1176jzf-s",     V6Itineraries,
99                [ArchV6, FeatureVFP2]>;
100def : Processor<"mpcorenovfp",      V6Itineraries,
101                [ArchV6]>;
102def : Processor<"mpcore",           V6Itineraries,
103                [ArchV6, FeatureVFP2]>;
104
105// V6T2 Processors.
106def : Processor<"arm1156t2-s",      V6Itineraries,
107                [ArchV6T2, FeatureThumb2]>;
108def : Processor<"arm1156t2f-s",     V6Itineraries,
109                [ArchV6T2, FeatureThumb2, FeatureVFP2]>;
110
111// V7 Processors.
112def : Processor<"cortex-a8",        CortexA8Itineraries,
113                [ArchV7A, FeatureThumb2, FeatureNEON]>;
114def : Processor<"cortex-a9",        V7Itineraries,
115                [ArchV7A, FeatureThumb2, FeatureNEON]>;
116
117//===----------------------------------------------------------------------===//
118// Register File Description
119//===----------------------------------------------------------------------===//
120
121include "ARMRegisterInfo.td"
122
123include "ARMCallingConv.td"
124
125//===----------------------------------------------------------------------===//
126// Instruction Descriptions
127//===----------------------------------------------------------------------===//
128
129include "ARMInstrInfo.td"
130
131def ARMInstrInfo : InstrInfo {
132  // Define how we want to layout our target-specific information field.
133  let TSFlagsFields = ["AddrModeBits",
134                       "SizeFlag",
135                       "IndexModeBits",
136                       "Form",
137                       "isUnaryDataProc"];
138  let TSFlagsShifts = [0,
139                       4,
140                       7,
141                       9,
142                       15];
143}
144
145//===----------------------------------------------------------------------===//
146// Declare the target which we are implementing
147//===----------------------------------------------------------------------===//
148
149def ARM : Target {
150  // Pull in Instruction Info:
151  let InstructionSet = ARMInstrInfo;
152}
153