1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Target-independent interfaces which we are implementing 15//===----------------------------------------------------------------------===// 16 17include "llvm/Target/Target.td" 18 19//===----------------------------------------------------------------------===// 20// ARM Subtarget state. 21// 22 23def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", 24 "true", "Thumb mode">; 25 26def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat", 27 "true", "Use software floating " 28 "point features.">; 29 30 31//===----------------------------------------------------------------------===// 32// ARM Subtarget features. 33// 34 35// Floating Point, HW Division and Neon Support 36def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 37 "Enable VFP2 instructions">; 38 39def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true", 40 "Enable VFP3 instructions", 41 [FeatureVFP2]>; 42 43def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 44 "Enable NEON instructions", 45 [FeatureVFP3]>; 46 47def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 48 "Enable half-precision " 49 "floating point">; 50 51def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true", 52 "Enable VFP4 instructions", 53 [FeatureVFP3, FeatureFP16]>; 54 55def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", 56 "true", "Enable ARMv8 FP", 57 [FeatureVFP4]>; 58 59def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 60 "Enable full half-precision " 61 "floating point", 62 [FeatureFPARMv8]>; 63 64def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 65 "Enable full half-precision " 66 "floating point fml instructions", 67 [FeatureFullFP16]>; 68 69def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true", 70 "Floating point unit supports " 71 "single precision only">; 72 73def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true", 74 "Restrict FP to 16 double registers">; 75 76def FeatureHWDivThumb : SubtargetFeature<"hwdiv", 77 "HasHardwareDivideInThumb", "true", 78 "Enable divide instructions in Thumb">; 79 80def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", 81 "HasHardwareDivideInARM", "true", 82 "Enable divide instructions in ARM mode">; 83 84// Atomic Support 85def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 86 "Has data barrier (dmb/dsb) instructions">; 87 88def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", 89 "Has v7 clrex instruction">; 90 91def FeatureDFB : SubtargetFeature<"dfb", "HasFullDataBarrier", "true", 92 "Has full data barrier (dfb) instruction">; 93 94def FeatureAcquireRelease : SubtargetFeature<"acquire-release", 95 "HasAcquireRelease", "true", 96 "Has v8 acquire/release (lda/ldaex " 97 " etc) instructions">; 98 99 100def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 101 "FP compare + branch is slow">; 102 103def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 104 "Enable support for Performance " 105 "Monitor extensions">; 106 107 108// TrustZone Security Extensions 109def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", 110 "Enable support for TrustZone " 111 "security extensions">; 112 113def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true", 114 "Enable support for ARMv8-M " 115 "Security Extensions">; 116 117def FeatureSHA2 : SubtargetFeature<"sha2", "HasSHA2", "true", 118 "Enable SHA1 and SHA256 support", [FeatureNEON]>; 119 120def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", 121 "Enable AES support", [FeatureNEON]>; 122 123def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 124 "Enable support for " 125 "Cryptography extensions", 126 [FeatureNEON, FeatureSHA2, FeatureAES]>; 127 128def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 129 "Enable support for CRC instructions">; 130 131def FeatureDotProd : SubtargetFeature<"dotprod", "HasDotProd", "true", 132 "Enable support for dot product instructions", 133 [FeatureNEON]>; 134 135// Not to be confused with FeatureHasRetAddrStack (return address stack) 136def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 137 "Enable Reliability, Availability " 138 "and Serviceability extensions">; 139 140// Fast computation of non-negative address offsets 141def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true", 142 "Enable fast computation of " 143 "positive address offsets">; 144 145// Fast execution of AES crypto operations 146def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true", 147 "CPU fuses AES crypto operations">; 148 149// Fast execution of bottom and top halves of literal generation 150def FeatureFuseLiterals : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true", 151 "CPU fuses literal generation operations">; 152 153// The way of reading thread pointer 154def FeatureReadTp : SubtargetFeature<"read-tp-hard", "ReadTPHard", "true", 155 "Reading thread pointer from register">; 156 157// Cyclone can zero VFP registers in 0 cycles. 158def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 159 "Has zero-cycle zeroing instructions">; 160 161// Whether it is profitable to unpredicate certain instructions during if-conversion 162def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr", 163 "IsProfitableToUnpredicate", "true", 164 "Is profitable to unpredicate">; 165 166// Some targets (e.g. Swift) have microcoded VGETLNi32. 167def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32", 168 "HasSlowVGETLNi32", "true", 169 "Has slow VGETLNi32 - prefer VMOV">; 170 171// Some targets (e.g. Swift) have microcoded VDUP32. 172def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", 173 "true", 174 "Has slow VDUP32 - prefer VMOV">; 175 176// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON 177// for scalar FP, as this allows more effective execution domain optimization. 178def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR", 179 "true", "Prefer VMOVSR">; 180 181// Swift has ISHST barriers compatible with Atomic Release semantics but weaker 182// than ISH 183def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST", 184 "true", "Prefer ISHST barriers">; 185 186// Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU. 187def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", 188 "true", 189 "Has muxed AGU and NEON/FPU">; 190 191// Whether VLDM/VSTM starting with odd register number need more microops 192// than single VLDRS 193def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister", 194 "true", "VLDM/VSTM starting " 195 "with an odd register is slow">; 196 197// Some targets have a renaming dependency when loading into D subregisters. 198def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg", 199 "SlowLoadDSubregister", "true", 200 "Loading into D subregs is slow">; 201 202def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp", 203 "UseWideStrideVFP", "true", 204 "Use a wide stride when allocating VFP registers">; 205 206// Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD. 207def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs", 208 "DontWidenVMOVS", "true", 209 "Don't widen VMOVS to VMOVD">; 210 211// Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different 212// VFP register widths. 213def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon", 214 "SplatVFPToNeon", "true", 215 "Splat register from VFP to NEON", 216 [FeatureDontWidenVMOVS]>; 217 218// Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions. 219def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", 220 "ExpandMLx", "true", 221 "Expand VFP/NEON MLA/MLS instructions">; 222 223// Some targets have special RAW hazards for VFP/NEON VMLA/VMLS. 224def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards", 225 "true", "Has VMLx hazards">; 226 227// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from 228// VFP to NEON, as an execution domain optimization. 229def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", 230 "UseNEONForFPMovs", "true", 231 "Convert VMOVSR, VMOVRS, " 232 "VMOVS to NEON">; 233 234// Some processors benefit from using NEON instructions for scalar 235// single-precision FP operations. This affects instruction selection and should 236// only be enabled if the handling of denormals is not important. 237def FeatureNEONForFP : SubtargetFeature<"neonfp", 238 "UseNEONForSinglePrecisionFP", 239 "true", 240 "Use NEON for single precision FP">; 241 242// On some processors, VLDn instructions that access unaligned data take one 243// extra cycle. Take that into account when computing operand latencies. 244def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign", 245 "true", 246 "Check for VLDn unaligned access">; 247 248// Some processors have a nonpipelined VFP coprocessor. 249def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp", 250 "NonpipelinedVFP", "true", 251 "VFP instructions are not pipelined">; 252 253// Some processors have FP multiply-accumulate instructions that don't 254// play nicely with other VFP / NEON instructions, and it's generally better 255// to just not use them. 256def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 257 "Disable VFP / NEON MAC instructions">; 258 259// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 260def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 261 "HasVMLxForwarding", "true", 262 "Has multiplier accumulator forwarding">; 263 264// Disable 32-bit to 16-bit narrowing for experimentation. 265def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 266 "Prefer 32-bit Thumb instrs">; 267 268def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopAlignment","2", 269 "Prefer 32-bit alignment for loops">; 270 271/// Some instructions update CPSR partially, which can add false dependency for 272/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 273/// mapped to a separate physical register. Avoid partial CPSR update for these 274/// processors. 275def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 276 "AvoidCPSRPartialUpdate", "true", 277 "Avoid CPSR partial update for OOO execution">; 278 279/// Disable +1 predication cost for instructions updating CPSR. 280/// Enabled for Cortex-A57. 281def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr", 282 "CheapPredicableCPSRDef", 283 "true", 284 "Disable +1 predication cost for instructions updating CPSR">; 285 286def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", 287 "AvoidMOVsShifterOperand", "true", 288 "Avoid movs instructions with " 289 "shifter operand">; 290 291// Some processors perform return stack prediction. CodeGen should avoid issue 292// "normal" call instructions to callees which do not return. 293def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", 294 "HasRetAddrStack", "true", 295 "Has return address stack">; 296 297// Some processors have no branch predictor, which changes the expected cost of 298// taking a branch which affects the choice of whether to use predicated 299// instructions. 300def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor", 301 "HasBranchPredictor", "false", 302 "Has no branch predictor">; 303 304/// DSP extension. 305def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", 306 "Supports DSP instructions in " 307 "ARM and/or Thumb2">; 308 309// Multiprocessing extension. 310def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 311 "Supports Multiprocessing extension">; 312 313// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). 314def FeatureVirtualization : SubtargetFeature<"virtualization", 315 "HasVirtualization", "true", 316 "Supports Virtualization extension", 317 [FeatureHWDivThumb, FeatureHWDivARM]>; 318 319// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. 320// See ARMInstrInfo.td for details. 321def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", 322 "NaCl trap">; 323 324def FeatureStrictAlign : SubtargetFeature<"strict-align", 325 "StrictAlign", "true", 326 "Disallow all unaligned memory " 327 "access">; 328 329def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", 330 "Generate calls via indirect call " 331 "instructions">; 332 333def FeatureExecuteOnly : SubtargetFeature<"execute-only", 334 "GenExecuteOnly", "true", 335 "Enable the generation of " 336 "execute only code.">; 337 338def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", 339 "Reserve R9, making it unavailable" 340 " as GPR">; 341 342def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", 343 "Don't use movt/movw pairs for " 344 "32-bit imms">; 345 346def FeatureNoNegativeImmediates 347 : SubtargetFeature<"no-neg-immediates", 348 "NegativeImmediates", "false", 349 "Convert immediates and instructions " 350 "to their negated or complemented " 351 "equivalent when the immediate does " 352 "not fit in the encoding.">; 353 354// Use the MachineScheduler for instruction scheduling for the subtarget. 355def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true", 356 "Use the MachineScheduler">; 357 358def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler", 359 "DisablePostRAScheduler", "true", 360 "Don't schedule again after register allocation">; 361 362// Enable use of alias analysis during code generation 363def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", 364 "Use alias analysis during codegen">; 365 366// Armv8.5-A extensions 367 368def FeatureSpecCtrl : SubtargetFeature<"specctrl", "HasSpecCtrl", "true", 369 "Enable speculation control barrier" >; 370 371//===----------------------------------------------------------------------===// 372// ARM architecture class 373// 374 375// A-series ISA 376def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", 377 "Is application profile ('A' series)">; 378 379// R-series ISA 380def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", 381 "Is realtime profile ('R' series)">; 382 383// M-series ISA 384def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", 385 "Is microcontroller profile ('M' series)">; 386 387 388def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 389 "Enable Thumb2 instructions">; 390 391def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 392 "Does not support ARM mode execution">; 393 394//===----------------------------------------------------------------------===// 395// ARM ISAa. 396// 397 398def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 399 "Support ARM v4T instructions">; 400 401def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 402 "Support ARM v5T instructions", 403 [HasV4TOps]>; 404 405def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 406 "Support ARM v5TE, v5TEj, and " 407 "v5TExp instructions", 408 [HasV5TOps]>; 409 410def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 411 "Support ARM v6 instructions", 412 [HasV5TEOps]>; 413 414def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", 415 "Support ARM v6M instructions", 416 [HasV6Ops]>; 417 418def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true", 419 "Support ARM v8M Baseline instructions", 420 [HasV6MOps]>; 421 422def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true", 423 "Support ARM v6k instructions", 424 [HasV6Ops]>; 425 426def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 427 "Support ARM v6t2 instructions", 428 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>; 429 430def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 431 "Support ARM v7 instructions", 432 [HasV6T2Ops, FeaturePerfMon, 433 FeatureV7Clrex]>; 434 435def HasV8MMainlineOps : 436 SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true", 437 "Support ARM v8M Mainline instructions", 438 [HasV7Ops]>; 439 440def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", 441 "Support ARM v8 instructions", 442 [HasV7Ops, FeatureAcquireRelease]>; 443 444def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 445 "Support ARM v8.1a instructions", 446 [HasV8Ops]>; 447 448def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 449 "Support ARM v8.2a instructions", 450 [HasV8_1aOps]>; 451 452def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 453 "Support ARM v8.3a instructions", 454 [HasV8_2aOps]>; 455 456def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 457 "Support ARM v8.4a instructions", 458 [HasV8_3aOps, FeatureDotProd]>; 459 460def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true", 461 "Support ARM v8.5a instructions", 462 [HasV8_4aOps, FeatureSpecCtrl]>; 463 464//===----------------------------------------------------------------------===// 465// ARM Processor subtarget features. 466// 467 468def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", 469 "Cortex-A5 ARM processors", []>; 470def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", 471 "Cortex-A7 ARM processors", []>; 472def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 473 "Cortex-A8 ARM processors", []>; 474def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 475 "Cortex-A9 ARM processors", []>; 476def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", 477 "Cortex-A12 ARM processors", []>; 478def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", 479 "Cortex-A15 ARM processors", []>; 480def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", 481 "Cortex-A17 ARM processors", []>; 482def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32", 483 "Cortex-A32 ARM processors", []>; 484def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 485 "Cortex-A35 ARM processors", []>; 486def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 487 "Cortex-A53 ARM processors", []>; 488def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 489 "Cortex-A55 ARM processors", []>; 490def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 491 "Cortex-A57 ARM processors", []>; 492def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 493 "Cortex-A72 ARM processors", []>; 494def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 495 "Cortex-A73 ARM processors", []>; 496def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 497 "Cortex-A75 ARM processors", []>; 498 499def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", 500 "Qualcomm Krait processors", []>; 501def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 502 "Qualcomm Kryo processors", []>; 503def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", 504 "Swift ARM processors", []>; 505 506def ProcExynos : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos", 507 "Samsung Exynos processors", 508 [FeatureZCZeroing, 509 FeatureUseWideStrideVFP, 510 FeatureUseAA, 511 FeatureSplatVFPToNeon, 512 FeatureSlowVGETLNi32, 513 FeatureSlowVDUP32, 514 FeatureSlowFPBrcc, 515 FeatureProfUnpredicate, 516 FeatureHWDivThumb, 517 FeatureHWDivARM, 518 FeatureHasSlowFPVMLx, 519 FeatureHasRetAddrStack, 520 FeatureFuseLiterals, 521 FeatureFuseAES, 522 FeatureExpandMLx, 523 FeatureCrypto, 524 FeatureCRC]>; 525 526def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", 527 "Cortex-R4 ARM processors", []>; 528def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", 529 "Cortex-R5 ARM processors", []>; 530def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", 531 "Cortex-R7 ARM processors", []>; 532def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52", 533 "Cortex-R52 ARM processors", []>; 534 535def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", 536 "Cortex-M3 ARM processors", []>; 537 538 539//===----------------------------------------------------------------------===// 540// ARM Helper classes. 541// 542 543class Architecture<string fname, string aname, list<SubtargetFeature> features> 544 : SubtargetFeature<fname, "ARMArch", aname, 545 !strconcat(aname, " architecture"), features>; 546 547class ProcNoItin<string Name, list<SubtargetFeature> Features> 548 : Processor<Name, NoItineraries, Features>; 549 550 551//===----------------------------------------------------------------------===// 552// ARM architectures 553// 554 555def ARMv2 : Architecture<"armv2", "ARMv2", []>; 556 557def ARMv2a : Architecture<"armv2a", "ARMv2a", []>; 558 559def ARMv3 : Architecture<"armv3", "ARMv3", []>; 560 561def ARMv3m : Architecture<"armv3m", "ARMv3m", []>; 562 563def ARMv4 : Architecture<"armv4", "ARMv4", []>; 564 565def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>; 566 567def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>; 568 569def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>; 570 571def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>; 572 573def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops, 574 FeatureDSP]>; 575 576def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, 577 FeatureDSP]>; 578 579def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; 580 581def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, 582 FeatureTrustZone]>; 583 584def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, 585 FeatureNoARM, 586 ModeThumb, 587 FeatureDB, 588 FeatureMClass, 589 FeatureStrictAlign]>; 590 591def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, 592 FeatureNoARM, 593 ModeThumb, 594 FeatureDB, 595 FeatureMClass, 596 FeatureStrictAlign]>; 597 598def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, 599 FeatureNEON, 600 FeatureDB, 601 FeatureDSP, 602 FeatureAClass]>; 603 604def ARMv7ve : Architecture<"armv7ve", "ARMv7ve", [HasV7Ops, 605 FeatureNEON, 606 FeatureDB, 607 FeatureDSP, 608 FeatureTrustZone, 609 FeatureMP, 610 FeatureVirtualization, 611 FeatureAClass]>; 612 613def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, 614 FeatureDB, 615 FeatureDSP, 616 FeatureHWDivThumb, 617 FeatureRClass]>; 618 619def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, 620 FeatureThumb2, 621 FeatureNoARM, 622 ModeThumb, 623 FeatureDB, 624 FeatureHWDivThumb, 625 FeatureMClass]>; 626 627def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, 628 FeatureThumb2, 629 FeatureNoARM, 630 ModeThumb, 631 FeatureDB, 632 FeatureHWDivThumb, 633 FeatureMClass, 634 FeatureDSP]>; 635 636def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, 637 FeatureAClass, 638 FeatureDB, 639 FeatureFPARMv8, 640 FeatureNEON, 641 FeatureDSP, 642 FeatureTrustZone, 643 FeatureMP, 644 FeatureVirtualization, 645 FeatureCrypto, 646 FeatureCRC]>; 647 648def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps, 649 FeatureAClass, 650 FeatureDB, 651 FeatureFPARMv8, 652 FeatureNEON, 653 FeatureDSP, 654 FeatureTrustZone, 655 FeatureMP, 656 FeatureVirtualization, 657 FeatureCrypto, 658 FeatureCRC]>; 659 660def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, 661 FeatureAClass, 662 FeatureDB, 663 FeatureFPARMv8, 664 FeatureNEON, 665 FeatureDSP, 666 FeatureTrustZone, 667 FeatureMP, 668 FeatureVirtualization, 669 FeatureCrypto, 670 FeatureCRC, 671 FeatureRAS]>; 672 673def ARMv83a : Architecture<"armv8.3-a", "ARMv83a", [HasV8_3aOps, 674 FeatureAClass, 675 FeatureDB, 676 FeatureFPARMv8, 677 FeatureNEON, 678 FeatureDSP, 679 FeatureTrustZone, 680 FeatureMP, 681 FeatureVirtualization, 682 FeatureCrypto, 683 FeatureCRC, 684 FeatureRAS]>; 685 686def ARMv84a : Architecture<"armv8.4-a", "ARMv84a", [HasV8_4aOps, 687 FeatureAClass, 688 FeatureDB, 689 FeatureFPARMv8, 690 FeatureNEON, 691 FeatureDSP, 692 FeatureTrustZone, 693 FeatureMP, 694 FeatureVirtualization, 695 FeatureCrypto, 696 FeatureCRC, 697 FeatureRAS, 698 FeatureDotProd]>; 699 700def ARMv85a : Architecture<"armv8.5-a", "ARMv85a", [HasV8_5aOps, 701 FeatureAClass, 702 FeatureDB, 703 FeatureFPARMv8, 704 FeatureNEON, 705 FeatureDSP, 706 FeatureTrustZone, 707 FeatureMP, 708 FeatureVirtualization, 709 FeatureCrypto, 710 FeatureCRC, 711 FeatureRAS, 712 FeatureDotProd]>; 713 714def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, 715 FeatureRClass, 716 FeatureDB, 717 FeatureDFB, 718 FeatureDSP, 719 FeatureCRC, 720 FeatureMP, 721 FeatureVirtualization, 722 FeatureFPARMv8, 723 FeatureNEON]>; 724 725def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", 726 [HasV8MBaselineOps, 727 FeatureNoARM, 728 ModeThumb, 729 FeatureDB, 730 FeatureHWDivThumb, 731 FeatureV7Clrex, 732 Feature8MSecExt, 733 FeatureAcquireRelease, 734 FeatureMClass, 735 FeatureStrictAlign]>; 736 737def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", 738 [HasV8MMainlineOps, 739 FeatureNoARM, 740 ModeThumb, 741 FeatureDB, 742 FeatureHWDivThumb, 743 Feature8MSecExt, 744 FeatureAcquireRelease, 745 FeatureMClass]>; 746 747// Aliases 748def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; 749def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; 750def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; 751def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; 752def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; 753def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; 754 755 756//===----------------------------------------------------------------------===// 757// ARM schedules. 758//===----------------------------------------------------------------------===// 759// 760include "ARMSchedule.td" 761 762//===----------------------------------------------------------------------===// 763// ARM processors 764// 765 766// Dummy CPU, used to target architectures 767def : ProcessorModel<"generic", CortexA8Model, []>; 768 769// FIXME: Several processors below are not using their own scheduler 770// model, but one of similar/previous processor. These should be fixed. 771 772def : ProcNoItin<"arm8", [ARMv4]>; 773def : ProcNoItin<"arm810", [ARMv4]>; 774def : ProcNoItin<"strongarm", [ARMv4]>; 775def : ProcNoItin<"strongarm110", [ARMv4]>; 776def : ProcNoItin<"strongarm1100", [ARMv4]>; 777def : ProcNoItin<"strongarm1110", [ARMv4]>; 778 779def : ProcNoItin<"arm7tdmi", [ARMv4t]>; 780def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>; 781def : ProcNoItin<"arm710t", [ARMv4t]>; 782def : ProcNoItin<"arm720t", [ARMv4t]>; 783def : ProcNoItin<"arm9", [ARMv4t]>; 784def : ProcNoItin<"arm9tdmi", [ARMv4t]>; 785def : ProcNoItin<"arm920", [ARMv4t]>; 786def : ProcNoItin<"arm920t", [ARMv4t]>; 787def : ProcNoItin<"arm922t", [ARMv4t]>; 788def : ProcNoItin<"arm940t", [ARMv4t]>; 789def : ProcNoItin<"ep9312", [ARMv4t]>; 790 791def : ProcNoItin<"arm10tdmi", [ARMv5t]>; 792def : ProcNoItin<"arm1020t", [ARMv5t]>; 793 794def : ProcNoItin<"arm9e", [ARMv5te]>; 795def : ProcNoItin<"arm926ej-s", [ARMv5te]>; 796def : ProcNoItin<"arm946e-s", [ARMv5te]>; 797def : ProcNoItin<"arm966e-s", [ARMv5te]>; 798def : ProcNoItin<"arm968e-s", [ARMv5te]>; 799def : ProcNoItin<"arm10e", [ARMv5te]>; 800def : ProcNoItin<"arm1020e", [ARMv5te]>; 801def : ProcNoItin<"arm1022e", [ARMv5te]>; 802def : ProcNoItin<"xscale", [ARMv5te]>; 803def : ProcNoItin<"iwmmxt", [ARMv5te]>; 804 805def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>; 806def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, 807 FeatureVFP2, 808 FeatureHasSlowFPVMLx]>; 809 810def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>; 811def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>; 812def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>; 813def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>; 814 815def : Processor<"arm1176j-s", ARMV6Itineraries, [ARMv6kz]>; 816def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; 817def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, 818 FeatureVFP2, 819 FeatureHasSlowFPVMLx]>; 820 821def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>; 822def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k, 823 FeatureVFP2, 824 FeatureHasSlowFPVMLx]>; 825 826def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>; 827def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2, 828 FeatureVFP2, 829 FeatureHasSlowFPVMLx]>; 830 831def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5, 832 FeatureHasRetAddrStack, 833 FeatureTrustZone, 834 FeatureSlowFPBrcc, 835 FeatureHasSlowFPVMLx, 836 FeatureVMLxForwarding, 837 FeatureMP, 838 FeatureVFP4]>; 839 840def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7, 841 FeatureHasRetAddrStack, 842 FeatureTrustZone, 843 FeatureSlowFPBrcc, 844 FeatureHasVMLxHazards, 845 FeatureHasSlowFPVMLx, 846 FeatureVMLxForwarding, 847 FeatureMP, 848 FeatureVFP4, 849 FeatureVirtualization]>; 850 851def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, 852 FeatureHasRetAddrStack, 853 FeatureNonpipelinedVFP, 854 FeatureTrustZone, 855 FeatureSlowFPBrcc, 856 FeatureHasVMLxHazards, 857 FeatureHasSlowFPVMLx, 858 FeatureVMLxForwarding]>; 859 860def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9, 861 FeatureHasRetAddrStack, 862 FeatureTrustZone, 863 FeatureHasVMLxHazards, 864 FeatureVMLxForwarding, 865 FeatureFP16, 866 FeatureAvoidPartialCPSR, 867 FeatureExpandMLx, 868 FeaturePreferVMOVSR, 869 FeatureMuxedUnits, 870 FeatureNEONForFPMovs, 871 FeatureCheckVLDnAlign, 872 FeatureMP]>; 873 874def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12, 875 FeatureHasRetAddrStack, 876 FeatureTrustZone, 877 FeatureVMLxForwarding, 878 FeatureVFP4, 879 FeatureAvoidPartialCPSR, 880 FeatureVirtualization, 881 FeatureMP]>; 882 883def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, 884 FeatureDontWidenVMOVS, 885 FeatureSplatVFPToNeon, 886 FeatureHasRetAddrStack, 887 FeatureMuxedUnits, 888 FeatureTrustZone, 889 FeatureVFP4, 890 FeatureMP, 891 FeatureCheckVLDnAlign, 892 FeatureAvoidPartialCPSR, 893 FeatureVirtualization]>; 894 895def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17, 896 FeatureHasRetAddrStack, 897 FeatureTrustZone, 898 FeatureMP, 899 FeatureVMLxForwarding, 900 FeatureVFP4, 901 FeatureAvoidPartialCPSR, 902 FeatureVirtualization]>; 903 904// FIXME: krait has currently the same features as A9 plus VFP4 and HWDiv 905def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, 906 FeatureHasRetAddrStack, 907 FeatureMuxedUnits, 908 FeatureCheckVLDnAlign, 909 FeatureVMLxForwarding, 910 FeatureFP16, 911 FeatureAvoidPartialCPSR, 912 FeatureVFP4, 913 FeatureHWDivThumb, 914 FeatureHWDivARM]>; 915 916def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, 917 FeatureHasRetAddrStack, 918 FeatureNEONForFP, 919 FeatureVFP4, 920 FeatureUseWideStrideVFP, 921 FeatureMP, 922 FeatureHWDivThumb, 923 FeatureHWDivARM, 924 FeatureAvoidPartialCPSR, 925 FeatureAvoidMOVsShOp, 926 FeatureHasSlowFPVMLx, 927 FeatureHasVMLxHazards, 928 FeatureProfUnpredicate, 929 FeaturePrefISHSTBarrier, 930 FeatureSlowOddRegister, 931 FeatureSlowLoadDSubreg, 932 FeatureSlowVGETLNi32, 933 FeatureSlowVDUP32, 934 FeatureUseMISched, 935 FeatureNoPostRASched]>; 936 937def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, 938 FeatureHasRetAddrStack, 939 FeatureAvoidPartialCPSR]>; 940 941def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4, 942 FeatureHasRetAddrStack, 943 FeatureSlowFPBrcc, 944 FeatureHasSlowFPVMLx, 945 FeatureVFP3, 946 FeatureD16, 947 FeatureAvoidPartialCPSR]>; 948 949def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, 950 FeatureHasRetAddrStack, 951 FeatureVFP3, 952 FeatureD16, 953 FeatureSlowFPBrcc, 954 FeatureHWDivARM, 955 FeatureHasSlowFPVMLx, 956 FeatureAvoidPartialCPSR]>; 957 958def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, 959 FeatureHasRetAddrStack, 960 FeatureVFP3, 961 FeatureD16, 962 FeatureFP16, 963 FeatureMP, 964 FeatureSlowFPBrcc, 965 FeatureHWDivARM, 966 FeatureHasSlowFPVMLx, 967 FeatureAvoidPartialCPSR]>; 968 969def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, 970 FeatureHasRetAddrStack, 971 FeatureVFP3, 972 FeatureD16, 973 FeatureFP16, 974 FeatureMP, 975 FeatureSlowFPBrcc, 976 FeatureHWDivARM, 977 FeatureHasSlowFPVMLx, 978 FeatureAvoidPartialCPSR]>; 979 980def : ProcessorModel<"cortex-m3", CortexM3Model, [ARMv7m, 981 ProcM3, 982 FeaturePrefLoopAlign32, 983 FeatureHasNoBranchPredictor]>; 984 985def : ProcessorModel<"sc300", CortexM3Model, [ARMv7m, 986 ProcM3, 987 FeatureHasNoBranchPredictor]>; 988 989def : ProcessorModel<"cortex-m4", CortexM3Model, [ARMv7em, 990 FeatureVFP4, 991 FeatureVFPOnlySP, 992 FeatureD16, 993 FeaturePrefLoopAlign32, 994 FeatureHasSlowFPVMLx, 995 FeatureHasNoBranchPredictor]>; 996 997def : ProcNoItin<"cortex-m7", [ARMv7em, 998 FeatureFPARMv8, 999 FeatureD16]>; 1000 1001def : ProcNoItin<"cortex-m23", [ARMv8mBaseline, 1002 FeatureNoMovt]>; 1003 1004def : ProcessorModel<"cortex-m33", CortexM3Model, [ARMv8mMainline, 1005 FeatureDSP, 1006 FeatureFPARMv8, 1007 FeatureD16, 1008 FeatureVFPOnlySP, 1009 FeaturePrefLoopAlign32, 1010 FeatureHasSlowFPVMLx, 1011 FeatureHasNoBranchPredictor]>; 1012 1013def : ProcNoItin<"cortex-a32", [ARMv8a, 1014 FeatureHWDivThumb, 1015 FeatureHWDivARM, 1016 FeatureCrypto, 1017 FeatureCRC]>; 1018 1019def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, 1020 FeatureHWDivThumb, 1021 FeatureHWDivARM, 1022 FeatureCrypto, 1023 FeatureCRC]>; 1024 1025def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, 1026 FeatureHWDivThumb, 1027 FeatureHWDivARM, 1028 FeatureCrypto, 1029 FeatureCRC, 1030 FeatureFPAO]>; 1031 1032def : ProcNoItin<"cortex-a55", [ARMv82a, ProcA55, 1033 FeatureHWDivThumb, 1034 FeatureHWDivARM, 1035 FeatureDotProd]>; 1036 1037def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57, 1038 FeatureHWDivThumb, 1039 FeatureHWDivARM, 1040 FeatureCrypto, 1041 FeatureCRC, 1042 FeatureFPAO, 1043 FeatureAvoidPartialCPSR, 1044 FeatureCheapPredicableCPSR]>; 1045 1046def : ProcessorModel<"cortex-a72", CortexA57Model, [ARMv8a, ProcA72, 1047 FeatureHWDivThumb, 1048 FeatureHWDivARM, 1049 FeatureCrypto, 1050 FeatureCRC]>; 1051 1052def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73, 1053 FeatureHWDivThumb, 1054 FeatureHWDivARM, 1055 FeatureCrypto, 1056 FeatureCRC]>; 1057 1058def : ProcNoItin<"cortex-a75", [ARMv82a, ProcA75, 1059 FeatureHWDivThumb, 1060 FeatureHWDivARM, 1061 FeatureDotProd]>; 1062 1063def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, 1064 FeatureHasRetAddrStack, 1065 FeatureNEONForFP, 1066 FeatureVFP4, 1067 FeatureMP, 1068 FeatureHWDivThumb, 1069 FeatureHWDivARM, 1070 FeatureAvoidPartialCPSR, 1071 FeatureAvoidMOVsShOp, 1072 FeatureHasSlowFPVMLx, 1073 FeatureCrypto, 1074 FeatureUseMISched, 1075 FeatureZCZeroing, 1076 FeatureNoPostRASched]>; 1077 1078def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynos]>; 1079def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynos]>; 1080def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynos]>; 1081def : ProcNoItin<"exynos-m4", [ARMv8a, ProcExynos]>; 1082 1083def : ProcNoItin<"kryo", [ARMv8a, ProcKryo, 1084 FeatureHWDivThumb, 1085 FeatureHWDivARM, 1086 FeatureCrypto, 1087 FeatureCRC]>; 1088 1089def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, 1090 FeatureUseMISched, 1091 FeatureFPAO, 1092 FeatureUseAA]>; 1093 1094//===----------------------------------------------------------------------===// 1095// Register File Description 1096//===----------------------------------------------------------------------===// 1097 1098include "ARMRegisterInfo.td" 1099include "ARMRegisterBanks.td" 1100include "ARMCallingConv.td" 1101 1102//===----------------------------------------------------------------------===// 1103// Instruction Descriptions 1104//===----------------------------------------------------------------------===// 1105 1106include "ARMInstrInfo.td" 1107def ARMInstrInfo : InstrInfo; 1108 1109//===----------------------------------------------------------------------===// 1110// Declare the target which we are implementing 1111//===----------------------------------------------------------------------===// 1112 1113def ARMAsmWriter : AsmWriter { 1114 string AsmWriterClassName = "InstPrinter"; 1115 int PassSubtarget = 1; 1116 int Variant = 0; 1117 bit isMCAsmWriter = 1; 1118} 1119 1120def ARMAsmParser : AsmParser { 1121 bit ReportMultipleNearMisses = 1; 1122} 1123 1124def ARMAsmParserVariant : AsmParserVariant { 1125 int Variant = 0; 1126 string Name = "ARM"; 1127 string BreakCharacters = "."; 1128} 1129 1130def ARM : Target { 1131 // Pull in Instruction Info. 1132 let InstructionSet = ARMInstrInfo; 1133 let AssemblyWriters = [ARMAsmWriter]; 1134 let AssemblyParsers = [ARMAsmParser]; 1135 let AssemblyParserVariants = [ARMAsmParserVariant]; 1136 let AllowRegisterRenaming = 1; 1137} 1138