1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// ARM Subtarget state. 20// 21 22def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", 23 "true", "Thumb mode">; 24 25def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat", 26 "true", "Use software floating " 27 "point features.">; 28 29 30//===----------------------------------------------------------------------===// 31// ARM Subtarget features. 32// 33 34// Floating Point, HW Division and Neon Support 35 36// FP loads/stores/moves, shared between VFP and MVE (even in the integer-only 37// version). 38def FeatureFPRegs : SubtargetFeature<"fpregs", "HasFPRegs", "true", 39 "Enable FP registers">; 40 41// 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16 42// extension) and MVE (even in the integer-only version). 43def FeatureFPRegs16 : SubtargetFeature<"fpregs16", "HasFPRegs16", "true", 44 "Enable 16-bit FP registers", 45 [FeatureFPRegs]>; 46 47def FeatureFPRegs64 : SubtargetFeature<"fpregs64", "HasFPRegs64", "true", 48 "Enable 64-bit FP registers", 49 [FeatureFPRegs]>; 50 51def FeatureFP64 : SubtargetFeature<"fp64", "HasFP64", "true", 52 "Floating point unit supports " 53 "double precision", 54 [FeatureFPRegs64]>; 55 56def FeatureD32 : SubtargetFeature<"d32", "HasD32", "true", 57 "Extend FP to 32 double registers">; 58 59multiclass VFPver<string name, string query, string description, 60 list<SubtargetFeature> prev, 61 list<SubtargetFeature> otherimplies, 62 list<SubtargetFeature> vfp2prev = []> { 63 def _D16_SP: SubtargetFeature< 64 name#"d16sp", query#"D16SP", "true", 65 description#" with only 16 d-registers and no double precision", 66 !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) # 67 !foreach(v, vfp2prev, !cast<SubtargetFeature>(v # "_SP")) # 68 otherimplies>; 69 def _SP: SubtargetFeature< 70 name#"sp", query#"SP", "true", 71 description#" with no double precision", 72 !foreach(v, prev, !cast<SubtargetFeature>(v # "_SP")) # 73 otherimplies # [FeatureD32, !cast<SubtargetFeature>(NAME # "_D16_SP")]>; 74 def _D16: SubtargetFeature< 75 name#"d16", query#"D16", "true", 76 description#" with only 16 d-registers", 77 !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16")) # 78 vfp2prev # 79 otherimplies # [FeatureFP64, !cast<SubtargetFeature>(NAME # "_D16_SP")]>; 80 def "": SubtargetFeature< 81 name, query, "true", description, 82 prev # otherimplies # [ 83 !cast<SubtargetFeature>(NAME # "_D16"), 84 !cast<SubtargetFeature>(NAME # "_SP")]>; 85} 86 87def FeatureVFP2_SP : SubtargetFeature<"vfp2sp", "HasVFPv2SP", "true", 88 "Enable VFP2 instructions with " 89 "no double precision", 90 [FeatureFPRegs]>; 91 92def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 93 "Enable VFP2 instructions", 94 [FeatureFP64, FeatureVFP2_SP]>; 95 96defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions", 97 [], [], [FeatureVFP2]>; 98 99def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 100 "Enable NEON instructions", 101 [FeatureVFP3]>; 102 103def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 104 "Enable half-precision " 105 "floating point">; 106 107defm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions", 108 [FeatureVFP3], [FeatureFP16]>; 109 110defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP", 111 [FeatureVFP4], []>; 112 113def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 114 "Enable full half-precision " 115 "floating point", 116 [FeatureFPARMv8_D16_SP, FeatureFPRegs16]>; 117 118def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 119 "Enable full half-precision " 120 "floating point fml instructions", 121 [FeatureFullFP16]>; 122 123def FeatureHWDivThumb : SubtargetFeature<"hwdiv", 124 "HasHardwareDivideInThumb", "true", 125 "Enable divide instructions in Thumb">; 126 127def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", 128 "HasHardwareDivideInARM", "true", 129 "Enable divide instructions in ARM mode">; 130 131// Atomic Support 132def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 133 "Has data barrier (dmb/dsb) instructions">; 134 135def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", 136 "Has v7 clrex instruction">; 137 138def FeatureDFB : SubtargetFeature<"dfb", "HasFullDataBarrier", "true", 139 "Has full data barrier (dfb) instruction">; 140 141def FeatureAcquireRelease : SubtargetFeature<"acquire-release", 142 "HasAcquireRelease", "true", 143 "Has v8 acquire/release (lda/ldaex " 144 " etc) instructions">; 145 146 147def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 148 "FP compare + branch is slow">; 149 150def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 151 "Enable support for Performance " 152 "Monitor extensions">; 153 154 155// TrustZone Security Extensions 156def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", 157 "Enable support for TrustZone " 158 "security extensions">; 159 160def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true", 161 "Enable support for ARMv8-M " 162 "Security Extensions">; 163 164def FeatureSHA2 : SubtargetFeature<"sha2", "HasSHA2", "true", 165 "Enable SHA1 and SHA256 support", [FeatureNEON]>; 166 167def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", 168 "Enable AES support", [FeatureNEON]>; 169 170def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 171 "Enable support for " 172 "Cryptography extensions", 173 [FeatureNEON, FeatureSHA2, FeatureAES]>; 174 175def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 176 "Enable support for CRC instructions">; 177 178def FeatureDotProd : SubtargetFeature<"dotprod", "HasDotProd", "true", 179 "Enable support for dot product instructions", 180 [FeatureNEON]>; 181 182// Not to be confused with FeatureHasRetAddrStack (return address stack) 183def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 184 "Enable Reliability, Availability " 185 "and Serviceability extensions">; 186 187// Fast computation of non-negative address offsets 188def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true", 189 "Enable fast computation of " 190 "positive address offsets">; 191 192// Fast execution of AES crypto operations 193def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true", 194 "CPU fuses AES crypto operations">; 195 196// Fast execution of bottom and top halves of literal generation 197def FeatureFuseLiterals : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true", 198 "CPU fuses literal generation operations">; 199 200// The way of reading thread pointer 201def FeatureReadTp : SubtargetFeature<"read-tp-hard", "ReadTPHard", "true", 202 "Reading thread pointer from register">; 203 204// Cyclone can zero VFP registers in 0 cycles. 205def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 206 "Has zero-cycle zeroing instructions">; 207 208// Whether it is profitable to unpredicate certain instructions during if-conversion 209def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr", 210 "IsProfitableToUnpredicate", "true", 211 "Is profitable to unpredicate">; 212 213// Some targets (e.g. Swift) have microcoded VGETLNi32. 214def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32", 215 "HasSlowVGETLNi32", "true", 216 "Has slow VGETLNi32 - prefer VMOV">; 217 218// Some targets (e.g. Swift) have microcoded VDUP32. 219def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", 220 "true", 221 "Has slow VDUP32 - prefer VMOV">; 222 223// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON 224// for scalar FP, as this allows more effective execution domain optimization. 225def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR", 226 "true", "Prefer VMOVSR">; 227 228// Swift has ISHST barriers compatible with Atomic Release semantics but weaker 229// than ISH 230def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST", 231 "true", "Prefer ISHST barriers">; 232 233// Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU. 234def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", 235 "true", 236 "Has muxed AGU and NEON/FPU">; 237 238// Whether VLDM/VSTM starting with odd register number need more microops 239// than single VLDRS 240def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister", 241 "true", "VLDM/VSTM starting " 242 "with an odd register is slow">; 243 244// Some targets have a renaming dependency when loading into D subregisters. 245def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg", 246 "SlowLoadDSubregister", "true", 247 "Loading into D subregs is slow">; 248 249def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp", 250 "UseWideStrideVFP", "true", 251 "Use a wide stride when allocating VFP registers">; 252 253// Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD. 254def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs", 255 "DontWidenVMOVS", "true", 256 "Don't widen VMOVS to VMOVD">; 257 258// Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different 259// VFP register widths. 260def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon", 261 "SplatVFPToNeon", "true", 262 "Splat register from VFP to NEON", 263 [FeatureDontWidenVMOVS]>; 264 265// Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions. 266def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", 267 "ExpandMLx", "true", 268 "Expand VFP/NEON MLA/MLS instructions">; 269 270// Some targets have special RAW hazards for VFP/NEON VMLA/VMLS. 271def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards", 272 "true", "Has VMLx hazards">; 273 274// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from 275// VFP to NEON, as an execution domain optimization. 276def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", 277 "UseNEONForFPMovs", "true", 278 "Convert VMOVSR, VMOVRS, " 279 "VMOVS to NEON">; 280 281// Some processors benefit from using NEON instructions for scalar 282// single-precision FP operations. This affects instruction selection and should 283// only be enabled if the handling of denormals is not important. 284def FeatureNEONForFP : SubtargetFeature<"neonfp", 285 "UseNEONForSinglePrecisionFP", 286 "true", 287 "Use NEON for single precision FP">; 288 289// On some processors, VLDn instructions that access unaligned data take one 290// extra cycle. Take that into account when computing operand latencies. 291def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign", 292 "true", 293 "Check for VLDn unaligned access">; 294 295// Some processors have a nonpipelined VFP coprocessor. 296def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp", 297 "NonpipelinedVFP", "true", 298 "VFP instructions are not pipelined">; 299 300// Some processors have FP multiply-accumulate instructions that don't 301// play nicely with other VFP / NEON instructions, and it's generally better 302// to just not use them. 303def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 304 "Disable VFP / NEON MAC instructions">; 305 306// VFPv4 added VFMA instructions that can similar be fast or slow. 307def FeatureHasSlowFPVFMx : SubtargetFeature<"slowfpvfmx", "SlowFPVFMx", "true", 308 "Disable VFP / NEON FMA instructions">; 309 310// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 311def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 312 "HasVMLxForwarding", "true", 313 "Has multiplier accumulator forwarding">; 314 315// Disable 32-bit to 16-bit narrowing for experimentation. 316def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 317 "Prefer 32-bit Thumb instrs">; 318 319def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopLogAlignment","2", 320 "Prefer 32-bit alignment for loops">; 321 322def FeatureMVEVectorCostFactor1 : SubtargetFeature<"mve1beat", "MVEVectorCostFactor", "1", 323 "Model MVE instructions as a 1 beat per tick architecture">; 324 325def FeatureMVEVectorCostFactor2 : SubtargetFeature<"mve2beat", "MVEVectorCostFactor", "2", 326 "Model MVE instructions as a 2 beats per tick architecture">; 327 328def FeatureMVEVectorCostFactor4 : SubtargetFeature<"mve4beat", "MVEVectorCostFactor", "4", 329 "Model MVE instructions as a 4 beats per tick architecture">; 330 331/// Some instructions update CPSR partially, which can add false dependency for 332/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 333/// mapped to a separate physical register. Avoid partial CPSR update for these 334/// processors. 335def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 336 "AvoidCPSRPartialUpdate", "true", 337 "Avoid CPSR partial update for OOO execution">; 338 339/// Disable +1 predication cost for instructions updating CPSR. 340/// Enabled for Cortex-A57. 341def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr", 342 "CheapPredicableCPSRDef", 343 "true", 344 "Disable +1 predication cost for instructions updating CPSR">; 345 346def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", 347 "AvoidMOVsShifterOperand", "true", 348 "Avoid movs instructions with " 349 "shifter operand">; 350 351// Some processors perform return stack prediction. CodeGen should avoid issue 352// "normal" call instructions to callees which do not return. 353def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", 354 "HasRetAddrStack", "true", 355 "Has return address stack">; 356 357// Some processors have no branch predictor, which changes the expected cost of 358// taking a branch which affects the choice of whether to use predicated 359// instructions. 360def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor", 361 "HasBranchPredictor", "false", 362 "Has no branch predictor">; 363 364/// DSP extension. 365def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", 366 "Supports DSP instructions in " 367 "ARM and/or Thumb2">; 368 369// Multiprocessing extension. 370def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 371 "Supports Multiprocessing extension">; 372 373// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). 374def FeatureVirtualization : SubtargetFeature<"virtualization", 375 "HasVirtualization", "true", 376 "Supports Virtualization extension", 377 [FeatureHWDivThumb, FeatureHWDivARM]>; 378 379// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. 380// See ARMInstrInfo.td for details. 381def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", 382 "NaCl trap">; 383 384def FeatureStrictAlign : SubtargetFeature<"strict-align", 385 "StrictAlign", "true", 386 "Disallow all unaligned memory " 387 "access">; 388 389def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", 390 "Generate calls via indirect call " 391 "instructions">; 392 393def FeatureExecuteOnly : SubtargetFeature<"execute-only", 394 "GenExecuteOnly", "true", 395 "Enable the generation of " 396 "execute only code.">; 397 398def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", 399 "Reserve R9, making it unavailable" 400 " as GPR">; 401 402def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", 403 "Don't use movt/movw pairs for " 404 "32-bit imms">; 405 406def FeatureNoNegativeImmediates 407 : SubtargetFeature<"no-neg-immediates", 408 "NegativeImmediates", "false", 409 "Convert immediates and instructions " 410 "to their negated or complemented " 411 "equivalent when the immediate does " 412 "not fit in the encoding.">; 413 414// Use the MachineScheduler for instruction scheduling for the subtarget. 415def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true", 416 "Use the MachineScheduler">; 417 418def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler", 419 "DisablePostRAScheduler", "true", 420 "Don't schedule again after register allocation">; 421 422// Armv8.5-A extensions 423 424def FeatureSB : SubtargetFeature<"sb", "HasSB", "true", 425 "Enable v8.5a Speculation Barrier" >; 426 427// Armv8.6-A extensions 428def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16", "true", 429 "Enable support for BFloat16 instructions", [FeatureNEON]>; 430 431def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8", 432 "true", "Enable Matrix Multiply Int8 Extension", [FeatureNEON]>; 433 434// Armv8.1-M extensions 435 436def FeatureLOB : SubtargetFeature<"lob", "HasLOB", "true", 437 "Enable Low Overhead Branch " 438 "extensions">; 439 440def FeatureFixCMSE_CVE_2021_35465 : SubtargetFeature<"fix-cmse-cve-2021-35465", 441 "FixCMSE_CVE_2021_35465", "true", 442 "Mitigate against the cve-2021-35465 " 443 "security vulnurability">; 444 445def FeaturePACBTI : SubtargetFeature<"pacbti", "HasPACBTI", "true", 446 "Enable Pointer Authentication and Branch " 447 "Target Identification">; 448 449def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice", 450 "NoBTIAtReturnTwice", "true", 451 "Don't place a BTI instruction " 452 "after a return-twice">; 453 454//===----------------------------------------------------------------------===// 455// ARM architecture class 456// 457 458// A-series ISA 459def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", 460 "Is application profile ('A' series)">; 461 462// R-series ISA 463def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", 464 "Is realtime profile ('R' series)">; 465 466// M-series ISA 467def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", 468 "Is microcontroller profile ('M' series)">; 469 470 471def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 472 "Enable Thumb2 instructions">; 473 474def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 475 "Does not support ARM mode execution">; 476 477//===----------------------------------------------------------------------===// 478// ARM ISAa. 479// 480 481def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 482 "Support ARM v4T instructions">; 483 484def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 485 "Support ARM v5T instructions", 486 [HasV4TOps]>; 487 488def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 489 "Support ARM v5TE, v5TEj, and " 490 "v5TExp instructions", 491 [HasV5TOps]>; 492 493def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 494 "Support ARM v6 instructions", 495 [HasV5TEOps]>; 496 497def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", 498 "Support ARM v6M instructions", 499 [HasV6Ops]>; 500 501def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true", 502 "Support ARM v8M Baseline instructions", 503 [HasV6MOps]>; 504 505def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true", 506 "Support ARM v6k instructions", 507 [HasV6Ops]>; 508 509def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 510 "Support ARM v6t2 instructions", 511 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>; 512 513def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 514 "Support ARM v7 instructions", 515 [HasV6T2Ops, FeatureV7Clrex]>; 516 517def HasV8MMainlineOps : 518 SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true", 519 "Support ARM v8M Mainline instructions", 520 [HasV7Ops]>; 521 522def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", 523 "Support ARM v8 instructions", 524 [HasV7Ops, FeaturePerfMon, FeatureAcquireRelease]>; 525 526def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 527 "Support ARM v8.1a instructions", 528 [HasV8Ops]>; 529 530def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 531 "Support ARM v8.2a instructions", 532 [HasV8_1aOps]>; 533 534def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 535 "Support ARM v8.3a instructions", 536 [HasV8_2aOps]>; 537 538def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 539 "Support ARM v8.4a instructions", 540 [HasV8_3aOps, FeatureDotProd]>; 541 542def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true", 543 "Support ARM v8.5a instructions", 544 [HasV8_4aOps, FeatureSB]>; 545 546def HasV8_6aOps : SubtargetFeature<"v8.6a", "HasV8_6aOps", "true", 547 "Support ARM v8.6a instructions", 548 [HasV8_5aOps, FeatureBF16, 549 FeatureMatMulInt8]>; 550 551def HasV8_7aOps : SubtargetFeature<"v8.7a", "HasV8_7aOps", "true", 552 "Support ARM v8.7a instructions", 553 [HasV8_6aOps]>; 554 555def HasV8_8aOps : SubtargetFeature<"v8.8a", "HasV8_8aOps", "true", 556 "Support ARM v8.8a instructions", 557 [HasV8_7aOps]>; 558 559def HasV9_0aOps : SubtargetFeature<"v9a", "HasV9_0aOps", "true", 560 "Support ARM v9a instructions", 561 [HasV8_5aOps]>; 562 563def HasV9_1aOps : SubtargetFeature<"v9.1a", "HasV9_1aOps", "true", 564 "Support ARM v9.1a instructions", 565 [HasV8_6aOps, HasV9_0aOps]>; 566 567def HasV9_2aOps : SubtargetFeature<"v9.2a", "HasV9_2aOps", "true", 568 "Support ARM v9.2a instructions", 569 [HasV8_7aOps, HasV9_1aOps]>; 570 571def HasV9_3aOps : SubtargetFeature<"v9.3a", "HasV9_3aOps", "true", 572 "Support ARM v9.3a instructions", 573 [HasV8_8aOps, HasV9_2aOps]>; 574 575def HasV8_1MMainlineOps : SubtargetFeature< 576 "v8.1m.main", "HasV8_1MMainlineOps", "true", 577 "Support ARM v8-1M Mainline instructions", 578 [HasV8MMainlineOps]>; 579def HasMVEIntegerOps : SubtargetFeature< 580 "mve", "HasMVEIntegerOps", "true", 581 "Support M-Class Vector Extension with integer ops", 582 [HasV8_1MMainlineOps, FeatureDSP, FeatureFPRegs16, FeatureFPRegs64]>; 583def HasMVEFloatOps : SubtargetFeature< 584 "mve.fp", "HasMVEFloatOps", "true", 585 "Support M-Class Vector Extension with integer and floating ops", 586 [HasMVEIntegerOps, FeatureFPARMv8_D16_SP, FeatureFullFP16]>; 587 588def HasCDEOps : SubtargetFeature<"cde", "HasCDEOps", "true", 589 "Support CDE instructions", 590 [HasV8MMainlineOps]>; 591 592foreach i = {0-7} in 593 def FeatureCoprocCDE#i : SubtargetFeature<"cdecp"#i, 594 "CoprocCDE["#i#"]", "true", 595 "Coprocessor "#i#" ISA is CDEv1", 596 [HasCDEOps]>; 597 598//===----------------------------------------------------------------------===// 599// Control codegen mitigation against Straight Line Speculation vulnerability. 600//===----------------------------------------------------------------------===// 601 602def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr", 603 "HardenSlsRetBr", "true", 604 "Harden against straight line speculation across RETurn and BranchRegister " 605 "instructions">; 606def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr", 607 "HardenSlsBlr", "true", 608 "Harden against straight line speculation across indirect calls">; 609def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat", 610 "HardenSlsNoComdat", "true", 611 "Generate thunk code for SLS mitigation in the normal text section">; 612 613//===----------------------------------------------------------------------===// 614// ARM Processor subtarget features. 615// 616 617def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", 618 "Cortex-A5 ARM processors", []>; 619def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", 620 "Cortex-A7 ARM processors", []>; 621def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 622 "Cortex-A8 ARM processors", []>; 623def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 624 "Cortex-A9 ARM processors", []>; 625def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", 626 "Cortex-A12 ARM processors", []>; 627def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", 628 "Cortex-A15 ARM processors", []>; 629def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", 630 "Cortex-A17 ARM processors", []>; 631def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32", 632 "Cortex-A32 ARM processors", []>; 633def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 634 "Cortex-A35 ARM processors", []>; 635def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 636 "Cortex-A53 ARM processors", []>; 637def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 638 "Cortex-A55 ARM processors", []>; 639def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 640 "Cortex-A57 ARM processors", []>; 641def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 642 "Cortex-A72 ARM processors", []>; 643def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 644 "Cortex-A73 ARM processors", []>; 645def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 646 "Cortex-A75 ARM processors", []>; 647def ProcA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 648 "Cortex-A76 ARM processors", []>; 649def ProcA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77", 650 "Cortex-A77 ARM processors", []>; 651def ProcA78 : SubtargetFeature<"cortex-a78", "ARMProcFamily", "CortexA78", 652 "Cortex-A78 ARM processors", []>; 653def ProcA78C : SubtargetFeature<"a78c", "ARMProcFamily", "CortexA78C", 654 "Cortex-A78C ARM processors", []>; 655def ProcA710 : SubtargetFeature<"cortex-a710", "ARMProcFamily", 656 "CortexA710", "Cortex-A710 ARM processors", []>; 657def ProcX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1", 658 "Cortex-X1 ARM processors", []>; 659 660def ProcV1 : SubtargetFeature<"neoverse-v1", "ARMProcFamily", 661 "NeoverseV1", "Neoverse-V1 ARM processors", []>; 662 663def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", 664 "Qualcomm Krait processors", []>; 665def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 666 "Qualcomm Kryo processors", []>; 667def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", 668 "Swift ARM processors", []>; 669 670def ProcExynos : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos", 671 "Samsung Exynos processors", 672 [FeatureZCZeroing, 673 FeatureUseWideStrideVFP, 674 FeatureSplatVFPToNeon, 675 FeatureSlowVGETLNi32, 676 FeatureSlowVDUP32, 677 FeatureSlowFPBrcc, 678 FeatureProfUnpredicate, 679 FeatureHWDivThumb, 680 FeatureHWDivARM, 681 FeatureHasSlowFPVMLx, 682 FeatureHasSlowFPVFMx, 683 FeatureHasRetAddrStack, 684 FeatureFuseLiterals, 685 FeatureFuseAES, 686 FeatureExpandMLx, 687 FeatureCrypto, 688 FeatureCRC]>; 689 690def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", 691 "Cortex-R4 ARM processors", []>; 692def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", 693 "Cortex-R5 ARM processors", []>; 694def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", 695 "Cortex-R7 ARM processors", []>; 696def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52", 697 "Cortex-R52 ARM processors", []>; 698 699def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", 700 "Cortex-M3 ARM processors", []>; 701def ProcM7 : SubtargetFeature<"m7", "ARMProcFamily", "CortexM7", 702 "Cortex-M7 ARM processors", []>; 703 704//===----------------------------------------------------------------------===// 705// ARM Helper classes. 706// 707 708class Architecture<string fname, string aname, list<SubtargetFeature> features> 709 : SubtargetFeature<fname, "ARMArch", aname, 710 !strconcat(aname, " architecture"), features>; 711 712class ProcNoItin<string Name, list<SubtargetFeature> Features> 713 : Processor<Name, NoItineraries, Features>; 714 715 716//===----------------------------------------------------------------------===// 717// ARM architectures 718// 719 720def ARMv2 : Architecture<"armv2", "ARMv2", []>; 721 722def ARMv2a : Architecture<"armv2a", "ARMv2a", []>; 723 724def ARMv3 : Architecture<"armv3", "ARMv3", []>; 725 726def ARMv3m : Architecture<"armv3m", "ARMv3m", []>; 727 728def ARMv4 : Architecture<"armv4", "ARMv4", []>; 729 730def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>; 731 732def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>; 733 734def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>; 735 736def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>; 737 738def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops, 739 FeatureDSP]>; 740 741def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, 742 FeatureDSP]>; 743 744def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; 745 746def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, 747 FeatureTrustZone]>; 748 749def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, 750 FeatureNoARM, 751 ModeThumb, 752 FeatureDB, 753 FeatureMClass, 754 FeatureStrictAlign]>; 755 756def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, 757 FeatureNoARM, 758 ModeThumb, 759 FeatureDB, 760 FeatureMClass, 761 FeatureStrictAlign]>; 762 763def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, 764 FeatureNEON, 765 FeatureDB, 766 FeatureDSP, 767 FeatureAClass, 768 FeaturePerfMon]>; 769 770def ARMv7ve : Architecture<"armv7ve", "ARMv7ve", [HasV7Ops, 771 FeatureNEON, 772 FeatureDB, 773 FeatureDSP, 774 FeatureTrustZone, 775 FeatureMP, 776 FeatureVirtualization, 777 FeatureAClass, 778 FeaturePerfMon]>; 779 780def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, 781 FeatureDB, 782 FeatureDSP, 783 FeatureHWDivThumb, 784 FeatureRClass, 785 FeaturePerfMon]>; 786 787def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, 788 FeatureThumb2, 789 FeatureNoARM, 790 ModeThumb, 791 FeatureDB, 792 FeatureHWDivThumb, 793 FeatureMClass]>; 794 795def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, 796 FeatureThumb2, 797 FeatureNoARM, 798 ModeThumb, 799 FeatureDB, 800 FeatureHWDivThumb, 801 FeatureMClass, 802 FeatureDSP]>; 803 804def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, 805 FeatureAClass, 806 FeatureDB, 807 FeatureFPARMv8, 808 FeatureNEON, 809 FeatureDSP, 810 FeatureTrustZone, 811 FeatureMP, 812 FeatureVirtualization, 813 FeatureCrypto, 814 FeatureCRC]>; 815 816def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps, 817 FeatureAClass, 818 FeatureDB, 819 FeatureFPARMv8, 820 FeatureNEON, 821 FeatureDSP, 822 FeatureTrustZone, 823 FeatureMP, 824 FeatureVirtualization, 825 FeatureCrypto, 826 FeatureCRC]>; 827 828def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, 829 FeatureAClass, 830 FeatureDB, 831 FeatureFPARMv8, 832 FeatureNEON, 833 FeatureDSP, 834 FeatureTrustZone, 835 FeatureMP, 836 FeatureVirtualization, 837 FeatureCrypto, 838 FeatureCRC, 839 FeatureRAS]>; 840 841def ARMv83a : Architecture<"armv8.3-a", "ARMv83a", [HasV8_3aOps, 842 FeatureAClass, 843 FeatureDB, 844 FeatureFPARMv8, 845 FeatureNEON, 846 FeatureDSP, 847 FeatureTrustZone, 848 FeatureMP, 849 FeatureVirtualization, 850 FeatureCrypto, 851 FeatureCRC, 852 FeatureRAS]>; 853 854def ARMv84a : Architecture<"armv8.4-a", "ARMv84a", [HasV8_4aOps, 855 FeatureAClass, 856 FeatureDB, 857 FeatureFPARMv8, 858 FeatureNEON, 859 FeatureDSP, 860 FeatureTrustZone, 861 FeatureMP, 862 FeatureVirtualization, 863 FeatureCrypto, 864 FeatureCRC, 865 FeatureRAS, 866 FeatureDotProd]>; 867 868def ARMv85a : Architecture<"armv8.5-a", "ARMv85a", [HasV8_5aOps, 869 FeatureAClass, 870 FeatureDB, 871 FeatureFPARMv8, 872 FeatureNEON, 873 FeatureDSP, 874 FeatureTrustZone, 875 FeatureMP, 876 FeatureVirtualization, 877 FeatureCrypto, 878 FeatureCRC, 879 FeatureRAS, 880 FeatureDotProd]>; 881def ARMv86a : Architecture<"armv8.6-a", "ARMv86a", [HasV8_6aOps, 882 FeatureAClass, 883 FeatureDB, 884 FeatureFPARMv8, 885 FeatureNEON, 886 FeatureDSP, 887 FeatureTrustZone, 888 FeatureMP, 889 FeatureVirtualization, 890 FeatureCrypto, 891 FeatureCRC, 892 FeatureRAS, 893 FeatureDotProd]>; 894def ARMv87a : Architecture<"armv8.7-a", "ARMv87a", [HasV8_7aOps, 895 FeatureAClass, 896 FeatureDB, 897 FeatureFPARMv8, 898 FeatureNEON, 899 FeatureDSP, 900 FeatureTrustZone, 901 FeatureMP, 902 FeatureVirtualization, 903 FeatureCrypto, 904 FeatureCRC, 905 FeatureRAS, 906 FeatureDotProd]>; 907def ARMv88a : Architecture<"armv8.8-a", "ARMv88a", [HasV8_8aOps, 908 FeatureAClass, 909 FeatureDB, 910 FeatureFPARMv8, 911 FeatureNEON, 912 FeatureDSP, 913 FeatureTrustZone, 914 FeatureMP, 915 FeatureVirtualization, 916 FeatureCrypto, 917 FeatureCRC, 918 FeatureRAS, 919 FeatureDotProd]>; 920 921def ARMv9a : Architecture<"armv9-a", "ARMv9a", [HasV9_0aOps, 922 FeatureAClass, 923 FeatureDB, 924 FeatureFPARMv8, 925 FeatureNEON, 926 FeatureDSP, 927 FeatureTrustZone, 928 FeatureMP, 929 FeatureVirtualization, 930 FeatureCRC, 931 FeatureRAS, 932 FeatureDotProd]>; 933def ARMv91a : Architecture<"armv9.1-a", "ARMv91a", [HasV9_1aOps, 934 FeatureAClass, 935 FeatureDB, 936 FeatureFPARMv8, 937 FeatureNEON, 938 FeatureDSP, 939 FeatureTrustZone, 940 FeatureMP, 941 FeatureVirtualization, 942 FeatureCRC, 943 FeatureRAS, 944 FeatureDotProd]>; 945def ARMv92a : Architecture<"armv9.2-a", "ARMv92a", [HasV9_2aOps, 946 FeatureAClass, 947 FeatureDB, 948 FeatureFPARMv8, 949 FeatureNEON, 950 FeatureDSP, 951 FeatureTrustZone, 952 FeatureMP, 953 FeatureVirtualization, 954 FeatureCRC, 955 FeatureRAS, 956 FeatureDotProd]>; 957def ARMv93a : Architecture<"armv9.3-a", "ARMv93a", [HasV9_3aOps, 958 FeatureAClass, 959 FeatureDB, 960 FeatureFPARMv8, 961 FeatureNEON, 962 FeatureDSP, 963 FeatureTrustZone, 964 FeatureMP, 965 FeatureVirtualization, 966 FeatureCrypto, 967 FeatureCRC, 968 FeatureRAS, 969 FeatureDotProd]>; 970 971def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, 972 FeatureRClass, 973 FeatureDB, 974 FeatureDFB, 975 FeatureDSP, 976 FeatureCRC, 977 FeatureMP, 978 FeatureVirtualization, 979 FeatureFPARMv8, 980 FeatureNEON]>; 981 982def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", 983 [HasV8MBaselineOps, 984 FeatureNoARM, 985 ModeThumb, 986 FeatureDB, 987 FeatureHWDivThumb, 988 FeatureV7Clrex, 989 Feature8MSecExt, 990 FeatureAcquireRelease, 991 FeatureMClass, 992 FeatureStrictAlign]>; 993 994def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", 995 [HasV8MMainlineOps, 996 FeatureNoARM, 997 ModeThumb, 998 FeatureDB, 999 FeatureHWDivThumb, 1000 Feature8MSecExt, 1001 FeatureAcquireRelease, 1002 FeatureMClass]>; 1003 1004def ARMv81mMainline : Architecture<"armv8.1-m.main", "ARMv81mMainline", 1005 [HasV8_1MMainlineOps, 1006 FeatureNoARM, 1007 ModeThumb, 1008 FeatureDB, 1009 FeatureHWDivThumb, 1010 Feature8MSecExt, 1011 FeatureAcquireRelease, 1012 FeatureMClass, 1013 FeatureRAS, 1014 FeatureLOB]>; 1015 1016// Aliases 1017def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; 1018def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; 1019def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; 1020def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; 1021def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; 1022def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; 1023 1024//===----------------------------------------------------------------------===// 1025// Register File Description 1026//===----------------------------------------------------------------------===// 1027 1028include "ARMRegisterInfo.td" 1029include "ARMRegisterBanks.td" 1030include "ARMCallingConv.td" 1031 1032//===----------------------------------------------------------------------===// 1033// ARM schedules. 1034//===----------------------------------------------------------------------===// 1035// 1036include "ARMPredicates.td" 1037include "ARMSchedule.td" 1038 1039//===----------------------------------------------------------------------===// 1040// Instruction Descriptions 1041//===----------------------------------------------------------------------===// 1042 1043include "ARMInstrInfo.td" 1044def ARMInstrInfo : InstrInfo; 1045 1046//===----------------------------------------------------------------------===// 1047// ARM schedules 1048// 1049include "ARMScheduleV6.td" 1050include "ARMScheduleA8.td" 1051include "ARMScheduleA9.td" 1052include "ARMScheduleSwift.td" 1053include "ARMScheduleR52.td" 1054include "ARMScheduleA57.td" 1055include "ARMScheduleM4.td" 1056include "ARMScheduleM7.td" 1057 1058//===----------------------------------------------------------------------===// 1059// ARM processors 1060// 1061// Dummy CPU, used to target architectures 1062def : ProcessorModel<"generic", CortexA8Model, []>; 1063 1064// FIXME: Several processors below are not using their own scheduler 1065// model, but one of similar/previous processor. These should be fixed. 1066 1067def : ProcNoItin<"arm8", [ARMv4]>; 1068def : ProcNoItin<"arm810", [ARMv4]>; 1069def : ProcNoItin<"strongarm", [ARMv4]>; 1070def : ProcNoItin<"strongarm110", [ARMv4]>; 1071def : ProcNoItin<"strongarm1100", [ARMv4]>; 1072def : ProcNoItin<"strongarm1110", [ARMv4]>; 1073 1074def : ProcNoItin<"arm7tdmi", [ARMv4t]>; 1075def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>; 1076def : ProcNoItin<"arm710t", [ARMv4t]>; 1077def : ProcNoItin<"arm720t", [ARMv4t]>; 1078def : ProcNoItin<"arm9", [ARMv4t]>; 1079def : ProcNoItin<"arm9tdmi", [ARMv4t]>; 1080def : ProcNoItin<"arm920", [ARMv4t]>; 1081def : ProcNoItin<"arm920t", [ARMv4t]>; 1082def : ProcNoItin<"arm922t", [ARMv4t]>; 1083def : ProcNoItin<"arm940t", [ARMv4t]>; 1084def : ProcNoItin<"ep9312", [ARMv4t]>; 1085 1086def : ProcNoItin<"arm10tdmi", [ARMv5t]>; 1087def : ProcNoItin<"arm1020t", [ARMv5t]>; 1088 1089def : ProcNoItin<"arm9e", [ARMv5te]>; 1090def : ProcNoItin<"arm926ej-s", [ARMv5te]>; 1091def : ProcNoItin<"arm946e-s", [ARMv5te]>; 1092def : ProcNoItin<"arm966e-s", [ARMv5te]>; 1093def : ProcNoItin<"arm968e-s", [ARMv5te]>; 1094def : ProcNoItin<"arm10e", [ARMv5te]>; 1095def : ProcNoItin<"arm1020e", [ARMv5te]>; 1096def : ProcNoItin<"arm1022e", [ARMv5te]>; 1097def : ProcNoItin<"xscale", [ARMv5te]>; 1098def : ProcNoItin<"iwmmxt", [ARMv5te]>; 1099 1100def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>; 1101def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, 1102 FeatureVFP2, 1103 FeatureHasSlowFPVMLx]>; 1104 1105def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m, 1106 FeatureHasNoBranchPredictor]>; 1107def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m, 1108 FeatureHasNoBranchPredictor]>; 1109def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m, 1110 FeatureHasNoBranchPredictor]>; 1111def : Processor<"sc000", ARMV6Itineraries, [ARMv6m, 1112 FeatureHasNoBranchPredictor]>; 1113 1114def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; 1115def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, 1116 FeatureVFP2, 1117 FeatureHasSlowFPVMLx]>; 1118 1119def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>; 1120def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k, 1121 FeatureVFP2, 1122 FeatureHasSlowFPVMLx]>; 1123 1124def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>; 1125def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2, 1126 FeatureVFP2, 1127 FeatureHasSlowFPVMLx]>; 1128 1129def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5, 1130 FeatureHasRetAddrStack, 1131 FeatureTrustZone, 1132 FeatureSlowFPBrcc, 1133 FeatureHasSlowFPVMLx, 1134 FeatureHasSlowFPVFMx, 1135 FeatureVMLxForwarding, 1136 FeatureMP, 1137 FeatureVFP4]>; 1138 1139def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7, 1140 FeatureHasRetAddrStack, 1141 FeatureTrustZone, 1142 FeatureSlowFPBrcc, 1143 FeatureHasVMLxHazards, 1144 FeatureHasSlowFPVMLx, 1145 FeatureHasSlowFPVFMx, 1146 FeatureVMLxForwarding, 1147 FeatureMP, 1148 FeatureVFP4, 1149 FeatureVirtualization]>; 1150 1151def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, 1152 FeatureHasRetAddrStack, 1153 FeatureNonpipelinedVFP, 1154 FeatureTrustZone, 1155 FeatureSlowFPBrcc, 1156 FeatureHasVMLxHazards, 1157 FeatureHasSlowFPVMLx, 1158 FeatureHasSlowFPVFMx, 1159 FeatureVMLxForwarding]>; 1160 1161def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9, 1162 FeatureHasRetAddrStack, 1163 FeatureTrustZone, 1164 FeatureHasVMLxHazards, 1165 FeatureVMLxForwarding, 1166 FeatureFP16, 1167 FeatureAvoidPartialCPSR, 1168 FeatureExpandMLx, 1169 FeaturePreferVMOVSR, 1170 FeatureMuxedUnits, 1171 FeatureNEONForFPMovs, 1172 FeatureCheckVLDnAlign, 1173 FeatureMP]>; 1174 1175def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12, 1176 FeatureHasRetAddrStack, 1177 FeatureTrustZone, 1178 FeatureVMLxForwarding, 1179 FeatureVFP4, 1180 FeatureAvoidPartialCPSR, 1181 FeatureVirtualization, 1182 FeatureMP]>; 1183 1184def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, 1185 FeatureDontWidenVMOVS, 1186 FeatureSplatVFPToNeon, 1187 FeatureHasRetAddrStack, 1188 FeatureMuxedUnits, 1189 FeatureTrustZone, 1190 FeatureVFP4, 1191 FeatureMP, 1192 FeatureCheckVLDnAlign, 1193 FeatureAvoidPartialCPSR, 1194 FeatureVirtualization]>; 1195 1196def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17, 1197 FeatureHasRetAddrStack, 1198 FeatureTrustZone, 1199 FeatureMP, 1200 FeatureVMLxForwarding, 1201 FeatureVFP4, 1202 FeatureAvoidPartialCPSR, 1203 FeatureVirtualization]>; 1204 1205// FIXME: krait has currently the same features as A9 plus VFP4 and HWDiv 1206def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, 1207 FeatureHasRetAddrStack, 1208 FeatureMuxedUnits, 1209 FeatureCheckVLDnAlign, 1210 FeatureVMLxForwarding, 1211 FeatureFP16, 1212 FeatureAvoidPartialCPSR, 1213 FeatureVFP4, 1214 FeatureHWDivThumb, 1215 FeatureHWDivARM]>; 1216 1217def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, 1218 FeatureHasRetAddrStack, 1219 FeatureNEONForFP, 1220 FeatureVFP4, 1221 FeatureUseWideStrideVFP, 1222 FeatureMP, 1223 FeatureHWDivThumb, 1224 FeatureHWDivARM, 1225 FeatureAvoidPartialCPSR, 1226 FeatureAvoidMOVsShOp, 1227 FeatureHasSlowFPVMLx, 1228 FeatureHasSlowFPVFMx, 1229 FeatureHasVMLxHazards, 1230 FeatureProfUnpredicate, 1231 FeaturePrefISHSTBarrier, 1232 FeatureSlowOddRegister, 1233 FeatureSlowLoadDSubreg, 1234 FeatureSlowVGETLNi32, 1235 FeatureSlowVDUP32, 1236 FeatureUseMISched, 1237 FeatureNoPostRASched]>; 1238 1239def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, 1240 FeatureHasRetAddrStack, 1241 FeatureAvoidPartialCPSR]>; 1242 1243def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4, 1244 FeatureHasRetAddrStack, 1245 FeatureSlowFPBrcc, 1246 FeatureHasSlowFPVMLx, 1247 FeatureHasSlowFPVFMx, 1248 FeatureVFP3_D16, 1249 FeatureAvoidPartialCPSR]>; 1250 1251def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, 1252 FeatureHasRetAddrStack, 1253 FeatureVFP3_D16, 1254 FeatureSlowFPBrcc, 1255 FeatureHWDivARM, 1256 FeatureHasSlowFPVMLx, 1257 FeatureHasSlowFPVFMx, 1258 FeatureAvoidPartialCPSR]>; 1259 1260def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, 1261 FeatureHasRetAddrStack, 1262 FeatureVFP3_D16, 1263 FeatureFP16, 1264 FeatureMP, 1265 FeatureSlowFPBrcc, 1266 FeatureHWDivARM, 1267 FeatureHasSlowFPVMLx, 1268 FeatureHasSlowFPVFMx, 1269 FeatureAvoidPartialCPSR]>; 1270 1271def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, 1272 FeatureHasRetAddrStack, 1273 FeatureVFP3_D16, 1274 FeatureFP16, 1275 FeatureMP, 1276 FeatureSlowFPBrcc, 1277 FeatureHWDivARM, 1278 FeatureHasSlowFPVMLx, 1279 FeatureHasSlowFPVFMx, 1280 FeatureAvoidPartialCPSR]>; 1281 1282def : ProcessorModel<"cortex-m3", CortexM4Model, [ARMv7m, 1283 ProcM3, 1284 FeaturePrefLoopAlign32, 1285 FeatureUseMISched, 1286 FeatureHasNoBranchPredictor]>; 1287 1288def : ProcessorModel<"sc300", CortexM4Model, [ARMv7m, 1289 ProcM3, 1290 FeatureUseMISched, 1291 FeatureHasNoBranchPredictor]>; 1292 1293def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em, 1294 FeatureVFP4_D16_SP, 1295 FeaturePrefLoopAlign32, 1296 FeatureHasSlowFPVMLx, 1297 FeatureHasSlowFPVFMx, 1298 FeatureUseMISched, 1299 FeatureHasNoBranchPredictor]>; 1300 1301def : ProcessorModel<"cortex-m7", CortexM7Model, [ARMv7em, 1302 ProcM7, 1303 FeatureFPARMv8_D16, 1304 FeatureUseMISched]>; 1305 1306def : ProcNoItin<"cortex-m23", [ARMv8mBaseline, 1307 FeatureNoMovt, 1308 FeatureHasNoBranchPredictor]>; 1309 1310def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline, 1311 FeatureDSP, 1312 FeatureFPARMv8_D16_SP, 1313 FeaturePrefLoopAlign32, 1314 FeatureHasSlowFPVMLx, 1315 FeatureHasSlowFPVFMx, 1316 FeatureUseMISched, 1317 FeatureHasNoBranchPredictor, 1318 FeatureFixCMSE_CVE_2021_35465]>; 1319 1320def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline, 1321 FeatureDSP, 1322 FeatureFPARMv8_D16_SP, 1323 FeaturePrefLoopAlign32, 1324 FeatureHasSlowFPVMLx, 1325 FeatureHasSlowFPVFMx, 1326 FeatureUseMISched, 1327 FeatureHasNoBranchPredictor, 1328 FeatureFixCMSE_CVE_2021_35465]>; 1329 1330def : ProcessorModel<"cortex-m55", CortexM4Model, [ARMv81mMainline, 1331 FeatureDSP, 1332 FeatureFPARMv8_D16, 1333 FeatureUseMISched, 1334 FeatureHasNoBranchPredictor, 1335 FeaturePrefLoopAlign32, 1336 FeatureHasSlowFPVMLx, 1337 HasMVEFloatOps, 1338 FeatureFixCMSE_CVE_2021_35465]>; 1339 1340def : ProcNoItin<"cortex-a32", [ARMv8a, 1341 FeatureHWDivThumb, 1342 FeatureHWDivARM, 1343 FeatureCrypto, 1344 FeatureCRC]>; 1345 1346def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, 1347 FeatureHWDivThumb, 1348 FeatureHWDivARM, 1349 FeatureCrypto, 1350 FeatureCRC]>; 1351 1352def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, 1353 FeatureHWDivThumb, 1354 FeatureHWDivARM, 1355 FeatureCrypto, 1356 FeatureCRC, 1357 FeatureFPAO]>; 1358 1359def : ProcNoItin<"cortex-a55", [ARMv82a, ProcA55, 1360 FeatureHWDivThumb, 1361 FeatureHWDivARM, 1362 FeatureDotProd]>; 1363 1364def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57, 1365 FeatureHWDivThumb, 1366 FeatureHWDivARM, 1367 FeatureCrypto, 1368 FeatureCRC, 1369 FeatureFPAO, 1370 FeatureAvoidPartialCPSR, 1371 FeatureCheapPredicableCPSR]>; 1372 1373def : ProcessorModel<"cortex-a72", CortexA57Model, [ARMv8a, ProcA72, 1374 FeatureHWDivThumb, 1375 FeatureHWDivARM, 1376 FeatureCrypto, 1377 FeatureCRC]>; 1378 1379def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73, 1380 FeatureHWDivThumb, 1381 FeatureHWDivARM, 1382 FeatureCrypto, 1383 FeatureCRC]>; 1384 1385def : ProcNoItin<"cortex-a75", [ARMv82a, ProcA75, 1386 FeatureHWDivThumb, 1387 FeatureHWDivARM, 1388 FeatureDotProd]>; 1389 1390def : ProcNoItin<"cortex-a76", [ARMv82a, ProcA76, 1391 FeatureHWDivThumb, 1392 FeatureHWDivARM, 1393 FeatureCrypto, 1394 FeatureCRC, 1395 FeatureFullFP16, 1396 FeatureDotProd]>; 1397 1398def : ProcNoItin<"cortex-a76ae", [ARMv82a, ProcA76, 1399 FeatureHWDivThumb, 1400 FeatureHWDivARM, 1401 FeatureCrypto, 1402 FeatureCRC, 1403 FeatureFullFP16, 1404 FeatureDotProd]>; 1405 1406def : ProcNoItin<"cortex-a77", [ARMv82a, ProcA77, 1407 FeatureHWDivThumb, 1408 FeatureHWDivARM, 1409 FeatureCrypto, 1410 FeatureCRC, 1411 FeatureFullFP16, 1412 FeatureDotProd]>; 1413 1414def : ProcNoItin<"cortex-a78", [ARMv82a, ProcA78, 1415 FeatureHWDivThumb, 1416 FeatureHWDivARM, 1417 FeatureCrypto, 1418 FeatureCRC, 1419 FeatureFullFP16, 1420 FeatureDotProd]>; 1421 1422def : ProcNoItin<"cortex-a78c", [ARMv82a, ProcA78C, 1423 FeatureHWDivThumb, 1424 FeatureHWDivARM, 1425 FeatureCrypto, 1426 FeatureCRC, 1427 FeatureDotProd, 1428 FeatureFullFP16]>; 1429 1430def : ProcNoItin<"cortex-a710", [ARMv9a, ProcA710, 1431 FeatureHWDivThumb, 1432 FeatureHWDivARM, 1433 FeatureFP16FML, 1434 FeatureBF16, 1435 FeatureMatMulInt8, 1436 FeatureSB]>; 1437 1438def : ProcNoItin<"cortex-x1", [ARMv82a, ProcX1, 1439 FeatureHWDivThumb, 1440 FeatureHWDivARM, 1441 FeatureCrypto, 1442 FeatureCRC, 1443 FeatureFullFP16, 1444 FeatureDotProd]>; 1445 1446def : ProcNoItin<"neoverse-v1", [ARMv84a, 1447 FeatureHWDivThumb, 1448 FeatureHWDivARM, 1449 FeatureCrypto, 1450 FeatureCRC, 1451 FeatureFullFP16, 1452 FeatureBF16, 1453 FeatureMatMulInt8]>; 1454 1455def : ProcNoItin<"neoverse-n1", [ARMv82a, 1456 FeatureHWDivThumb, 1457 FeatureHWDivARM, 1458 FeatureCrypto, 1459 FeatureCRC, 1460 FeatureDotProd]>; 1461 1462def : ProcNoItin<"neoverse-n2", [ARMv85a, 1463 FeatureBF16, 1464 FeatureMatMulInt8]>; 1465 1466def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, 1467 FeatureHasRetAddrStack, 1468 FeatureNEONForFP, 1469 FeatureVFP4, 1470 FeatureMP, 1471 FeatureHWDivThumb, 1472 FeatureHWDivARM, 1473 FeatureAvoidPartialCPSR, 1474 FeatureAvoidMOVsShOp, 1475 FeatureHasSlowFPVMLx, 1476 FeatureHasSlowFPVFMx, 1477 FeatureCrypto, 1478 FeatureUseMISched, 1479 FeatureZCZeroing, 1480 FeatureNoPostRASched]>; 1481 1482def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynos]>; 1483def : ProcNoItin<"exynos-m4", [ARMv82a, ProcExynos, 1484 FeatureFullFP16, 1485 FeatureDotProd]>; 1486def : ProcNoItin<"exynos-m5", [ARMv82a, ProcExynos, 1487 FeatureFullFP16, 1488 FeatureDotProd]>; 1489 1490def : ProcNoItin<"kryo", [ARMv8a, ProcKryo, 1491 FeatureHWDivThumb, 1492 FeatureHWDivARM, 1493 FeatureCrypto, 1494 FeatureCRC]>; 1495 1496def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, 1497 FeatureUseMISched, 1498 FeatureFPAO]>; 1499 1500//===----------------------------------------------------------------------===// 1501// Declare the target which we are implementing 1502//===----------------------------------------------------------------------===// 1503 1504def ARMAsmWriter : AsmWriter { 1505 string AsmWriterClassName = "InstPrinter"; 1506 int PassSubtarget = 1; 1507 int Variant = 0; 1508 bit isMCAsmWriter = 1; 1509} 1510 1511def ARMAsmParser : AsmParser { 1512 bit ReportMultipleNearMisses = 1; 1513} 1514 1515def ARMAsmParserVariant : AsmParserVariant { 1516 int Variant = 0; 1517 string Name = "ARM"; 1518 string BreakCharacters = "."; 1519} 1520 1521def ARM : Target { 1522 // Pull in Instruction Info. 1523 let InstructionSet = ARMInstrInfo; 1524 let AssemblyWriters = [ARMAsmWriter]; 1525 let AssemblyParsers = [ARMAsmParser]; 1526 let AssemblyParserVariants = [ARMAsmParserVariant]; 1527 let AllowRegisterRenaming = 1; 1528} 1529