1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Target-independent interfaces which we are implementing 15//===----------------------------------------------------------------------===// 16 17include "llvm/Target/Target.td" 18 19//===----------------------------------------------------------------------===// 20// ARM Helper classes. 21// 22 23class ProcNoItin<string Name, list<SubtargetFeature> Features> 24 : Processor<Name, NoItineraries, Features>; 25 26class Architecture<string fname, string aname, list<SubtargetFeature> features > 27 : SubtargetFeature<fname, "ARMArch", aname, 28 !strconcat(aname, " architecture"), features>; 29 30//===----------------------------------------------------------------------===// 31// ARM Subtarget state. 32// 33 34def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true", 35 "Thumb mode">; 36 37def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true", 38 "Use software floating point features.">; 39 40//===----------------------------------------------------------------------===// 41// ARM Subtarget features. 42// 43 44def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 45 "Enable VFP2 instructions">; 46def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true", 47 "Enable VFP3 instructions", 48 [FeatureVFP2]>; 49def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 50 "Enable NEON instructions", 51 [FeatureVFP3]>; 52def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 53 "Enable Thumb2 instructions">; 54def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 55 "Does not support ARM mode execution", 56 [ModeThumb]>; 57def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 58 "Enable half-precision floating point">; 59def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true", 60 "Enable VFP4 instructions", 61 [FeatureVFP3, FeatureFP16]>; 62def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", 63 "true", "Enable ARMv8 FP", 64 [FeatureVFP4]>; 65def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 66 "Enable full half-precision floating point", 67 [FeatureFPARMv8]>; 68def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true", 69 "Restrict FP to 16 double registers">; 70def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true", 71 "Enable divide instructions">; 72def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", 73 "HasHardwareDivideInARM", "true", 74 "Enable divide instructions in ARM mode">; 75def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true", 76 "Enable Thumb2 extract and pack instructions">; 77def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 78 "Has data barrier (dmb / dsb) instructions">; 79def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", 80 "Has v7 clrex instruction">; 81def FeatureAcquireRelease : SubtargetFeature<"acquire-release", 82 "HasAcquireRelease", "true", 83 "Has v8 acquire/release (lda/ldaex etc) instructions">; 84def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 85 "FP compare + branch is slow">; 86def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true", 87 "Floating point unit supports single precision only">; 88def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 89 "Enable support for Performance Monitor extensions">; 90def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", 91 "Enable support for TrustZone security extensions">; 92def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true", 93 "Enable support for ARMv8-M Security Extensions">; 94def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 95 "Enable support for Cryptography extensions", 96 [FeatureNEON]>; 97def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 98 "Enable support for CRC instructions">; 99 100// Cyclone has preferred instructions for zeroing VFP registers, which can 101// execute in 0 cycles. 102def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 103 "Has zero-cycle zeroing instructions">; 104 105// Some processors have FP multiply-accumulate instructions that don't 106// play nicely with other VFP / NEON instructions, and it's generally better 107// to just not use them. 108def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 109 "Disable VFP / NEON MAC instructions">; 110 111// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 112def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 113 "HasVMLxForwarding", "true", 114 "Has multiplier accumulator forwarding">; 115 116// Some processors benefit from using NEON instructions for scalar 117// single-precision FP operations. 118def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", 119 "true", 120 "Use NEON for single precision FP">; 121 122// Disable 32-bit to 16-bit narrowing for experimentation. 123def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 124 "Prefer 32-bit Thumb instrs">; 125 126/// Some instructions update CPSR partially, which can add false dependency for 127/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 128/// mapped to a separate physical register. Avoid partial CPSR update for these 129/// processors. 130def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 131 "AvoidCPSRPartialUpdate", "true", 132 "Avoid CPSR partial update for OOO execution">; 133 134def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", 135 "AvoidMOVsShifterOperand", "true", 136 "Avoid movs instructions with shifter operand">; 137 138// Some processors perform return stack prediction. CodeGen should avoid issue 139// "normal" call instructions to callees which do not return. 140def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true", 141 "Has return address stack">; 142 143/// DSP extension. 144def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", 145 "Supports DSP instructions in ARM and/or Thumb2">; 146 147// Multiprocessing extension. 148def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 149 "Supports Multiprocessing extension">; 150 151// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). 152def FeatureVirtualization : SubtargetFeature<"virtualization", 153 "HasVirtualization", "true", 154 "Supports Virtualization extension", 155 [FeatureHWDiv, FeatureHWDivARM]>; 156 157// M-series ISA 158def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", 159 "Is microcontroller profile ('M' series)">; 160 161// R-series ISA 162def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", 163 "Is realtime profile ('R' series)">; 164 165// A-series ISA 166def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", 167 "Is application profile ('A' series)">; 168 169// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. 170// See ARMInstrInfo.td for details. 171def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", 172 "NaCl trap">; 173 174def FeatureStrictAlign : SubtargetFeature<"strict-align", 175 "StrictAlign", "true", 176 "Disallow all unaligned memory " 177 "access">; 178 179def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", 180 "Generate calls via indirect call " 181 "instructions">; 182 183def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", 184 "Reserve R9, making it unavailable as " 185 "GPR">; 186 187def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", 188 "Don't use movt/movw pairs for 32-bit " 189 "imms">; 190 191 192//===----------------------------------------------------------------------===// 193// ARM ISAa. 194// 195 196def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 197 "Support ARM v4T instructions">; 198def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 199 "Support ARM v5T instructions", 200 [HasV4TOps]>; 201def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 202 "Support ARM v5TE, v5TEj, and v5TExp instructions", 203 [HasV5TOps]>; 204def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 205 "Support ARM v6 instructions", 206 [HasV5TEOps]>; 207def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", 208 "Support ARM v6M instructions", 209 [HasV6Ops]>; 210def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true", 211 "Support ARM v8M Baseline instructions", 212 [HasV6MOps]>; 213def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true", 214 "Support ARM v6k instructions", 215 [HasV6Ops]>; 216def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 217 "Support ARM v6t2 instructions", 218 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>; 219def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 220 "Support ARM v7 instructions", 221 [HasV6T2Ops, FeaturePerfMon, 222 FeatureV7Clrex]>; 223def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", 224 "Support ARM v8 instructions", 225 [HasV7Ops, FeatureAcquireRelease]>; 226def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 227 "Support ARM v8.1a instructions", 228 [HasV8Ops]>; 229def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 230 "Support ARM v8.2a instructions", 231 [HasV8_1aOps]>; 232def HasV8MMainlineOps : SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true", 233 "Support ARM v8M Mainline instructions", 234 [HasV7Ops]>; 235 236 237//===----------------------------------------------------------------------===// 238// ARM Processor subtarget features. 239// 240 241def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", 242 "Cortex-A5 ARM processors", []>; 243def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", 244 "Cortex-A7 ARM processors", []>; 245def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 246 "Cortex-A8 ARM processors", []>; 247def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 248 "Cortex-A9 ARM processors", []>; 249def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", 250 "Cortex-A12 ARM processors", []>; 251def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", 252 "Cortex-A15 ARM processors", []>; 253def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", 254 "Cortex-A17 ARM processors", []>; 255def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 256 "Cortex-A35 ARM processors", []>; 257def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 258 "Cortex-A53 ARM processors", []>; 259def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 260 "Cortex-A57 ARM processors", []>; 261def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 262 "Cortex-A72 ARM processors", []>; 263 264def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", 265 "Qualcomm ARM processors", []>; 266def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", 267 "Swift ARM processors", []>; 268 269def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1", 270 "Samsung Exynos-M1 processors", []>; 271 272def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", 273 "Cortex-R4 ARM processors", []>; 274def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", 275 "Cortex-R5 ARM processors", []>; 276def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", 277 "Cortex-R7 ARM processors", []>; 278 279 280//===----------------------------------------------------------------------===// 281// ARM schedules. 282// 283 284include "ARMSchedule.td" 285 286 287//===----------------------------------------------------------------------===// 288// ARM architectures 289// 290 291def ARMv2 : Architecture<"armv2", "ARMv2", []>; 292 293def ARMv2a : Architecture<"armv2a", "ARMv2a", []>; 294 295def ARMv3 : Architecture<"armv3", "ARMv3", []>; 296 297def ARMv3m : Architecture<"armv3m", "ARMv3m", []>; 298 299def ARMv4 : Architecture<"armv4", "ARMv4", []>; 300 301def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>; 302 303def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>; 304 305def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>; 306 307def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>; 308 309def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>; 310 311def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, 312 FeatureDSP]>; 313 314def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; 315 316def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, 317 FeatureTrustZone]>; 318 319def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, 320 FeatureNoARM, 321 FeatureDB, 322 FeatureMClass]>; 323 324def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, 325 FeatureNoARM, 326 FeatureDB, 327 FeatureMClass]>; 328 329def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, 330 FeatureNEON, 331 FeatureDB, 332 FeatureDSP, 333 FeatureAClass]>; 334 335def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, 336 FeatureDB, 337 FeatureDSP, 338 FeatureHWDiv, 339 FeatureRClass]>; 340 341def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, 342 FeatureThumb2, 343 FeatureNoARM, 344 FeatureDB, 345 FeatureHWDiv, 346 FeatureMClass]>; 347 348def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, 349 FeatureThumb2, 350 FeatureNoARM, 351 FeatureDB, 352 FeatureHWDiv, 353 FeatureMClass, 354 FeatureDSP, 355 FeatureT2XtPk]>; 356 357def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, 358 FeatureAClass, 359 FeatureDB, 360 FeatureFPARMv8, 361 FeatureNEON, 362 FeatureDSP, 363 FeatureTrustZone, 364 FeatureMP, 365 FeatureVirtualization, 366 FeatureCrypto, 367 FeatureCRC]>; 368 369def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps, 370 FeatureAClass, 371 FeatureDB, 372 FeatureFPARMv8, 373 FeatureNEON, 374 FeatureDSP, 375 FeatureTrustZone, 376 FeatureMP, 377 FeatureVirtualization, 378 FeatureCrypto, 379 FeatureCRC]>; 380 381def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, 382 FeatureAClass, 383 FeatureDB, 384 FeatureFPARMv8, 385 FeatureNEON, 386 FeatureDSP, 387 FeatureTrustZone, 388 FeatureMP, 389 FeatureVirtualization, 390 FeatureCrypto, 391 FeatureCRC]>; 392 393def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", 394 [HasV8MBaselineOps, 395 FeatureNoARM, 396 FeatureDB, 397 FeatureHWDiv, 398 FeatureV7Clrex, 399 Feature8MSecExt, 400 FeatureAcquireRelease, 401 FeatureMClass]>; 402 403def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", 404 [HasV8MMainlineOps, 405 FeatureNoARM, 406 FeatureDB, 407 FeatureHWDiv, 408 Feature8MSecExt, 409 FeatureAcquireRelease, 410 FeatureMClass]>; 411 412// Aliases 413def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; 414def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; 415def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; 416def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; 417def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; 418def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; 419 420 421//===----------------------------------------------------------------------===// 422// ARM processors 423// 424 425// Dummy CPU, used to target architectures 426def : ProcNoItin<"generic", []>; 427 428def : ProcNoItin<"arm8", [ARMv4]>; 429def : ProcNoItin<"arm810", [ARMv4]>; 430def : ProcNoItin<"strongarm", [ARMv4]>; 431def : ProcNoItin<"strongarm110", [ARMv4]>; 432def : ProcNoItin<"strongarm1100", [ARMv4]>; 433def : ProcNoItin<"strongarm1110", [ARMv4]>; 434 435def : ProcNoItin<"arm7tdmi", [ARMv4t]>; 436def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>; 437def : ProcNoItin<"arm710t", [ARMv4t]>; 438def : ProcNoItin<"arm720t", [ARMv4t]>; 439def : ProcNoItin<"arm9", [ARMv4t]>; 440def : ProcNoItin<"arm9tdmi", [ARMv4t]>; 441def : ProcNoItin<"arm920", [ARMv4t]>; 442def : ProcNoItin<"arm920t", [ARMv4t]>; 443def : ProcNoItin<"arm922t", [ARMv4t]>; 444def : ProcNoItin<"arm940t", [ARMv4t]>; 445def : ProcNoItin<"ep9312", [ARMv4t]>; 446 447def : ProcNoItin<"arm10tdmi", [ARMv5t]>; 448def : ProcNoItin<"arm1020t", [ARMv5t]>; 449 450def : ProcNoItin<"arm9e", [ARMv5te]>; 451def : ProcNoItin<"arm926ej-s", [ARMv5te]>; 452def : ProcNoItin<"arm946e-s", [ARMv5te]>; 453def : ProcNoItin<"arm966e-s", [ARMv5te]>; 454def : ProcNoItin<"arm968e-s", [ARMv5te]>; 455def : ProcNoItin<"arm10e", [ARMv5te]>; 456def : ProcNoItin<"arm1020e", [ARMv5te]>; 457def : ProcNoItin<"arm1022e", [ARMv5te]>; 458def : ProcNoItin<"xscale", [ARMv5te]>; 459def : ProcNoItin<"iwmmxt", [ARMv5te]>; 460 461def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>; 462def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, 463 FeatureVFP2, 464 FeatureHasSlowFPVMLx]>; 465 466def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>; 467def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>; 468def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>; 469def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>; 470 471def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; 472def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, 473 FeatureVFP2, 474 FeatureHasSlowFPVMLx]>; 475 476def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>; 477def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k, 478 FeatureVFP2, 479 FeatureHasSlowFPVMLx]>; 480 481def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>; 482def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2, 483 FeatureVFP2, 484 FeatureHasSlowFPVMLx]>; 485 486// FIXME: A5 has currently the same Schedule model as A8 487def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5, 488 FeatureHasRAS, 489 FeatureTrustZone, 490 FeatureSlowFPBrcc, 491 FeatureHasSlowFPVMLx, 492 FeatureVMLxForwarding, 493 FeatureT2XtPk, 494 FeatureMP, 495 FeatureVFP4]>; 496 497def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7, 498 FeatureHasRAS, 499 FeatureTrustZone, 500 FeatureSlowFPBrcc, 501 FeatureHasSlowFPVMLx, 502 FeatureVMLxForwarding, 503 FeatureT2XtPk, 504 FeatureMP, 505 FeatureVFP4, 506 FeatureHWDiv, 507 FeatureHWDivARM, 508 FeatureVirtualization]>; 509 510def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, 511 FeatureHasRAS, 512 FeatureTrustZone, 513 FeatureSlowFPBrcc, 514 FeatureHasSlowFPVMLx, 515 FeatureVMLxForwarding, 516 FeatureT2XtPk]>; 517 518def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9, 519 FeatureHasRAS, 520 FeatureTrustZone, 521 FeatureVMLxForwarding, 522 FeatureT2XtPk, 523 FeatureFP16, 524 FeatureAvoidPartialCPSR, 525 FeatureMP]>; 526 527// FIXME: A12 has currently the same Schedule model as A9 528def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12, 529 FeatureHasRAS, 530 FeatureTrustZone, 531 FeatureVMLxForwarding, 532 FeatureT2XtPk, 533 FeatureVFP4, 534 FeatureHWDiv, 535 FeatureHWDivARM, 536 FeatureAvoidPartialCPSR, 537 FeatureVirtualization, 538 FeatureMP]>; 539 540// FIXME: A15 has currently the same Schedule model as A9. 541def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, 542 FeatureHasRAS, 543 FeatureTrustZone, 544 FeatureT2XtPk, 545 FeatureVFP4, 546 FeatureMP, 547 FeatureHWDiv, 548 FeatureHWDivARM, 549 FeatureAvoidPartialCPSR, 550 FeatureVirtualization]>; 551 552// FIXME: A17 has currently the same Schedule model as A9 553def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17, 554 FeatureHasRAS, 555 FeatureTrustZone, 556 FeatureMP, 557 FeatureVMLxForwarding, 558 FeatureT2XtPk, 559 FeatureVFP4, 560 FeatureHWDiv, 561 FeatureHWDivARM, 562 FeatureAvoidPartialCPSR, 563 FeatureVirtualization]>; 564 565// FIXME: krait has currently the same Schedule model as A9 566// FIXME: krait has currently the same features as A9 plus VFP4 and hardware 567// division features. 568def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, 569 FeatureHasRAS, 570 FeatureVMLxForwarding, 571 FeatureT2XtPk, 572 FeatureFP16, 573 FeatureAvoidPartialCPSR, 574 FeatureVFP4, 575 FeatureHWDiv, 576 FeatureHWDivARM]>; 577 578def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, 579 FeatureHasRAS, 580 FeatureNEONForFP, 581 FeatureT2XtPk, 582 FeatureVFP4, 583 FeatureMP, 584 FeatureHWDiv, 585 FeatureHWDivARM, 586 FeatureAvoidPartialCPSR, 587 FeatureAvoidMOVsShOp, 588 FeatureHasSlowFPVMLx]>; 589 590// FIXME: R4 has currently the same ProcessorModel as A8. 591def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, 592 FeatureHasRAS, 593 FeatureAvoidPartialCPSR, 594 FeatureT2XtPk]>; 595 596// FIXME: R4F has currently the same ProcessorModel as A8. 597def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4, 598 FeatureHasRAS, 599 FeatureSlowFPBrcc, 600 FeatureHasSlowFPVMLx, 601 FeatureVFP3, 602 FeatureD16, 603 FeatureAvoidPartialCPSR, 604 FeatureT2XtPk]>; 605 606// FIXME: R5 has currently the same ProcessorModel as A8. 607def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, 608 FeatureHasRAS, 609 FeatureVFP3, 610 FeatureD16, 611 FeatureSlowFPBrcc, 612 FeatureHWDivARM, 613 FeatureHasSlowFPVMLx, 614 FeatureAvoidPartialCPSR, 615 FeatureT2XtPk]>; 616 617// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5. 618def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, 619 FeatureHasRAS, 620 FeatureVFP3, 621 FeatureD16, 622 FeatureFP16, 623 FeatureMP, 624 FeatureSlowFPBrcc, 625 FeatureHWDivARM, 626 FeatureHasSlowFPVMLx, 627 FeatureAvoidPartialCPSR, 628 FeatureT2XtPk]>; 629 630def : ProcNoItin<"cortex-m3", [ARMv7m]>; 631def : ProcNoItin<"sc300", [ARMv7m]>; 632 633def : ProcNoItin<"cortex-m4", [ARMv7em, 634 FeatureVFP4, 635 FeatureVFPOnlySP, 636 FeatureD16]>; 637 638def : ProcNoItin<"cortex-m7", [ARMv7em, 639 FeatureFPARMv8, 640 FeatureD16]>; 641 642 643def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, 644 FeatureHWDiv, 645 FeatureHWDivARM, 646 FeatureT2XtPk, 647 FeatureCrypto, 648 FeatureCRC]>; 649 650def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, 651 FeatureHWDiv, 652 FeatureHWDivARM, 653 FeatureT2XtPk, 654 FeatureCrypto, 655 FeatureCRC]>; 656 657def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57, 658 FeatureHWDiv, 659 FeatureHWDivARM, 660 FeatureT2XtPk, 661 FeatureCrypto, 662 FeatureCRC]>; 663 664def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72, 665 FeatureHWDiv, 666 FeatureHWDivARM, 667 FeatureT2XtPk, 668 FeatureCrypto, 669 FeatureCRC]>; 670 671// Cyclone is very similar to swift 672def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, 673 FeatureHasRAS, 674 FeatureNEONForFP, 675 FeatureT2XtPk, 676 FeatureVFP4, 677 FeatureMP, 678 FeatureHWDiv, 679 FeatureHWDivARM, 680 FeatureAvoidPartialCPSR, 681 FeatureAvoidMOVsShOp, 682 FeatureHasSlowFPVMLx, 683 FeatureCrypto, 684 FeatureZCZeroing]>; 685 686def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1, 687 FeatureHWDiv, 688 FeatureHWDivARM, 689 FeatureT2XtPk, 690 FeatureCrypto, 691 FeatureCRC]>; 692 693//===----------------------------------------------------------------------===// 694// Register File Description 695//===----------------------------------------------------------------------===// 696 697include "ARMRegisterInfo.td" 698 699include "ARMCallingConv.td" 700 701//===----------------------------------------------------------------------===// 702// Instruction Descriptions 703//===----------------------------------------------------------------------===// 704 705include "ARMInstrInfo.td" 706 707def ARMInstrInfo : InstrInfo; 708 709//===----------------------------------------------------------------------===// 710// Declare the target which we are implementing 711//===----------------------------------------------------------------------===// 712 713def ARMAsmWriter : AsmWriter { 714 string AsmWriterClassName = "InstPrinter"; 715 int PassSubtarget = 1; 716 int Variant = 0; 717 bit isMCAsmWriter = 1; 718} 719 720def ARMAsmParserVariant : AsmParserVariant { 721 int Variant = 0; 722 string Name = "ARM"; 723 string BreakCharacters = "."; 724} 725 726def ARM : Target { 727 // Pull in Instruction Info: 728 let InstructionSet = ARMInstrInfo; 729 let AssemblyWriters = [ARMAsmWriter]; 730 let AssemblyParserVariants = [ARMAsmParserVariant]; 731} 732