1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Target-independent interfaces which we are implementing 15//===----------------------------------------------------------------------===// 16 17include "llvm/Target/Target.td" 18 19//===----------------------------------------------------------------------===// 20// ARM Helper classes. 21// 22 23class ProcNoItin<string Name, list<SubtargetFeature> Features> 24 : Processor<Name, NoItineraries, Features>; 25 26class Architecture<string fname, string aname, list<SubtargetFeature> features > 27 : SubtargetFeature<fname, "ARMArch", aname, 28 !strconcat(aname, " architecture"), features>; 29 30//===----------------------------------------------------------------------===// 31// ARM Subtarget state. 32// 33 34def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true", 35 "Thumb mode">; 36 37def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true", 38 "Use software floating point features.">; 39 40//===----------------------------------------------------------------------===// 41// ARM Subtarget features. 42// 43 44def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 45 "Enable VFP2 instructions">; 46def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true", 47 "Enable VFP3 instructions", 48 [FeatureVFP2]>; 49def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 50 "Enable NEON instructions", 51 [FeatureVFP3]>; 52def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 53 "Enable Thumb2 instructions">; 54def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 55 "Does not support ARM mode execution", 56 [ModeThumb]>; 57def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 58 "Enable half-precision floating point">; 59def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true", 60 "Enable VFP4 instructions", 61 [FeatureVFP3, FeatureFP16]>; 62def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", 63 "true", "Enable ARMv8 FP", 64 [FeatureVFP4]>; 65def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 66 "Enable full half-precision floating point", 67 [FeatureFPARMv8]>; 68def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true", 69 "Restrict FP to 16 double registers">; 70def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true", 71 "Enable divide instructions">; 72def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", 73 "HasHardwareDivideInARM", "true", 74 "Enable divide instructions in ARM mode">; 75def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true", 76 "Enable Thumb2 extract and pack instructions">; 77def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 78 "Has data barrier (dmb / dsb) instructions">; 79def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", 80 "Has v7 clrex instruction">; 81def FeatureAcquireRelease : SubtargetFeature<"acquire-release", 82 "HasAcquireRelease", "true", 83 "Has v8 acquire/release (lda/ldaex etc) instructions">; 84def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 85 "FP compare + branch is slow">; 86def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true", 87 "Floating point unit supports single precision only">; 88def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 89 "Enable support for Performance Monitor extensions">; 90def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", 91 "Enable support for TrustZone security extensions">; 92def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true", 93 "Enable support for ARMv8-M Security Extensions">; 94def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 95 "Enable support for Cryptography extensions", 96 [FeatureNEON]>; 97def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 98 "Enable support for CRC instructions">; 99// Not to be confused with FeatureHasRetAddrStack (return address stack) 100def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 101 "Enable Reliability, Availability and Serviceability extensions">; 102def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true", 103 "Enable fast computation of positive address offsets">; 104 105 106// Cyclone has preferred instructions for zeroing VFP registers, which can 107// execute in 0 cycles. 108def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 109 "Has zero-cycle zeroing instructions">; 110 111// Whether or not it may be profitable to unpredicate certain instructions 112// during if conversion. 113def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr", 114 "IsProfitableToUnpredicate", 115 "true", 116 "Is profitable to unpredicate">; 117 118// Some targets (e.g. Swift) have microcoded VGETLNi32. 119def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32", 120 "HasSlowVGETLNi32", "true", 121 "Has slow VGETLNi32 - prefer VMOV">; 122 123// Some targets (e.g. Swift) have microcoded VDUP32. 124def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", "true", 125 "Has slow VDUP32 - prefer VMOV">; 126 127// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON 128// for scalar FP, as this allows more effective execution domain optimization. 129def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR", 130 "true", "Prefer VMOVSR">; 131 132// Swift has ISHST barriers compatible with Atomic Release semantics but weaker 133// than ISH 134def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST", 135 "true", "Prefer ISHST barriers">; 136 137// Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU. 138def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", "true", 139 "Has muxed AGU and NEON/FPU">; 140 141// On some targets, a VLDM/VSTM starting with an odd register number needs more 142// microops than single VLDRS. 143def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister", 144 "true", "VLDM/VSTM starting with an odd register is slow">; 145 146// Some targets have a renaming dependency when loading into D subregisters. 147def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg", 148 "SlowLoadDSubregister", "true", 149 "Loading into D subregs is slow">; 150// Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD. 151def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs", 152 "DontWidenVMOVS", "true", 153 "Don't widen VMOVS to VMOVD">; 154 155// Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions. 156def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", "ExpandMLx", "true", 157 "Expand VFP/NEON MLA/MLS instructions">; 158 159// Some targets have special RAW hazards for VFP/NEON VMLA/VMLS. 160def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards", 161 "true", "Has VMLx hazards">; 162 163// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from 164// VFP to NEON, as an execution domain optimization. 165def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", "UseNEONForFPMovs", 166 "true", "Convert VMOVSR, VMOVRS, VMOVS to NEON">; 167 168// Some processors benefit from using NEON instructions for scalar 169// single-precision FP operations. This affects instruction selection and should 170// only be enabled if the handling of denormals is not important. 171def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", 172 "true", 173 "Use NEON for single precision FP">; 174 175// On some processors, VLDn instructions that access unaligned data take one 176// extra cycle. Take that into account when computing operand latencies. 177def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign", 178 "true", 179 "Check for VLDn unaligned access">; 180 181// Some processors have a nonpipelined VFP coprocessor. 182def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp", 183 "NonpipelinedVFP", "true", 184 "VFP instructions are not pipelined">; 185 186// Some processors have FP multiply-accumulate instructions that don't 187// play nicely with other VFP / NEON instructions, and it's generally better 188// to just not use them. 189def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 190 "Disable VFP / NEON MAC instructions">; 191 192// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 193def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 194 "HasVMLxForwarding", "true", 195 "Has multiplier accumulator forwarding">; 196 197// Disable 32-bit to 16-bit narrowing for experimentation. 198def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 199 "Prefer 32-bit Thumb instrs">; 200 201/// Some instructions update CPSR partially, which can add false dependency for 202/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 203/// mapped to a separate physical register. Avoid partial CPSR update for these 204/// processors. 205def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 206 "AvoidCPSRPartialUpdate", "true", 207 "Avoid CPSR partial update for OOO execution">; 208 209def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", 210 "AvoidMOVsShifterOperand", "true", 211 "Avoid movs instructions with shifter operand">; 212 213// Some processors perform return stack prediction. CodeGen should avoid issue 214// "normal" call instructions to callees which do not return. 215def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", "HasRetAddrStack", "true", 216 "Has return address stack">; 217 218/// DSP extension. 219def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", 220 "Supports DSP instructions in ARM and/or Thumb2">; 221 222// Multiprocessing extension. 223def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 224 "Supports Multiprocessing extension">; 225 226// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). 227def FeatureVirtualization : SubtargetFeature<"virtualization", 228 "HasVirtualization", "true", 229 "Supports Virtualization extension", 230 [FeatureHWDiv, FeatureHWDivARM]>; 231 232// M-series ISA 233def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", 234 "Is microcontroller profile ('M' series)">; 235 236// R-series ISA 237def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", 238 "Is realtime profile ('R' series)">; 239 240// A-series ISA 241def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", 242 "Is application profile ('A' series)">; 243 244// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. 245// See ARMInstrInfo.td for details. 246def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", 247 "NaCl trap">; 248 249def FeatureStrictAlign : SubtargetFeature<"strict-align", 250 "StrictAlign", "true", 251 "Disallow all unaligned memory " 252 "access">; 253 254def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", 255 "Generate calls via indirect call " 256 "instructions">; 257 258def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", 259 "Reserve R9, making it unavailable as " 260 "GPR">; 261 262def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", 263 "Don't use movt/movw pairs for 32-bit " 264 "imms">; 265 266 267//===----------------------------------------------------------------------===// 268// ARM ISAa. 269// 270 271def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 272 "Support ARM v4T instructions">; 273def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 274 "Support ARM v5T instructions", 275 [HasV4TOps]>; 276def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 277 "Support ARM v5TE, v5TEj, and v5TExp instructions", 278 [HasV5TOps]>; 279def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 280 "Support ARM v6 instructions", 281 [HasV5TEOps]>; 282def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", 283 "Support ARM v6M instructions", 284 [HasV6Ops]>; 285def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true", 286 "Support ARM v8M Baseline instructions", 287 [HasV6MOps]>; 288def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true", 289 "Support ARM v6k instructions", 290 [HasV6Ops]>; 291def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 292 "Support ARM v6t2 instructions", 293 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>; 294def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 295 "Support ARM v7 instructions", 296 [HasV6T2Ops, FeaturePerfMon, 297 FeatureV7Clrex]>; 298def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", 299 "Support ARM v8 instructions", 300 [HasV7Ops, FeatureAcquireRelease, 301 FeatureT2XtPk]>; 302def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 303 "Support ARM v8.1a instructions", 304 [HasV8Ops]>; 305def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 306 "Support ARM v8.2a instructions", 307 [HasV8_1aOps]>; 308def HasV8MMainlineOps : SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true", 309 "Support ARM v8M Mainline instructions", 310 [HasV7Ops]>; 311 312 313//===----------------------------------------------------------------------===// 314// ARM Processor subtarget features. 315// 316 317def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", 318 "Cortex-A5 ARM processors", []>; 319def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", 320 "Cortex-A7 ARM processors", []>; 321def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 322 "Cortex-A8 ARM processors", []>; 323def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 324 "Cortex-A9 ARM processors", []>; 325def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", 326 "Cortex-A12 ARM processors", []>; 327def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", 328 "Cortex-A15 ARM processors", []>; 329def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", 330 "Cortex-A17 ARM processors", []>; 331def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32", 332 "Cortex-A32 ARM processors", []>; 333def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 334 "Cortex-A35 ARM processors", []>; 335def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 336 "Cortex-A53 ARM processors", []>; 337def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 338 "Cortex-A57 ARM processors", []>; 339def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 340 "Cortex-A72 ARM processors", []>; 341def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 342 "Cortex-A73 ARM processors", []>; 343 344def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", 345 "Qualcomm ARM processors", []>; 346def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", 347 "Swift ARM processors", []>; 348 349def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1", 350 "Samsung Exynos-M1 processors", []>; 351 352def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", 353 "Cortex-R4 ARM processors", []>; 354def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", 355 "Cortex-R5 ARM processors", []>; 356def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", 357 "Cortex-R7 ARM processors", []>; 358def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52", 359 "Cortex-R52 ARM processors", []>; 360 361def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", 362 "Cortex-M3 ARM processors", []>; 363 364//===----------------------------------------------------------------------===// 365// ARM schedules. 366// 367 368include "ARMSchedule.td" 369 370 371//===----------------------------------------------------------------------===// 372// ARM architectures 373// 374 375def ARMv2 : Architecture<"armv2", "ARMv2", []>; 376 377def ARMv2a : Architecture<"armv2a", "ARMv2a", []>; 378 379def ARMv3 : Architecture<"armv3", "ARMv3", []>; 380 381def ARMv3m : Architecture<"armv3m", "ARMv3m", []>; 382 383def ARMv4 : Architecture<"armv4", "ARMv4", []>; 384 385def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>; 386 387def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>; 388 389def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>; 390 391def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>; 392 393def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>; 394 395def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, 396 FeatureDSP, 397 FeatureT2XtPk]>; 398 399def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; 400 401def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, 402 FeatureTrustZone]>; 403 404def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, 405 FeatureNoARM, 406 FeatureDB, 407 FeatureMClass]>; 408 409def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, 410 FeatureNoARM, 411 FeatureDB, 412 FeatureMClass]>; 413 414def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, 415 FeatureNEON, 416 FeatureDB, 417 FeatureDSP, 418 FeatureAClass, 419 FeatureT2XtPk]>; 420 421def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, 422 FeatureDB, 423 FeatureDSP, 424 FeatureHWDiv, 425 FeatureRClass, 426 FeatureT2XtPk]>; 427 428def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, 429 FeatureThumb2, 430 FeatureNoARM, 431 FeatureDB, 432 FeatureHWDiv, 433 FeatureMClass]>; 434 435def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, 436 FeatureThumb2, 437 FeatureNoARM, 438 FeatureDB, 439 FeatureHWDiv, 440 FeatureMClass, 441 FeatureDSP, 442 FeatureT2XtPk]>; 443 444def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, 445 FeatureAClass, 446 FeatureDB, 447 FeatureFPARMv8, 448 FeatureNEON, 449 FeatureDSP, 450 FeatureTrustZone, 451 FeatureMP, 452 FeatureVirtualization, 453 FeatureCrypto, 454 FeatureCRC]>; 455 456def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps, 457 FeatureAClass, 458 FeatureDB, 459 FeatureFPARMv8, 460 FeatureNEON, 461 FeatureDSP, 462 FeatureTrustZone, 463 FeatureMP, 464 FeatureVirtualization, 465 FeatureCrypto, 466 FeatureCRC]>; 467 468def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, 469 FeatureAClass, 470 FeatureDB, 471 FeatureFPARMv8, 472 FeatureNEON, 473 FeatureDSP, 474 FeatureTrustZone, 475 FeatureMP, 476 FeatureVirtualization, 477 FeatureCrypto, 478 FeatureCRC, 479 FeatureRAS]>; 480 481def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, 482 FeatureRClass, 483 FeatureDB, 484 FeatureHWDiv, 485 FeatureHWDivARM, 486 FeatureT2XtPk, 487 FeatureDSP, 488 FeatureCRC, 489 FeatureMP, 490 FeatureVirtualization, 491 FeatureFPARMv8, 492 FeatureNEON]>; 493 494def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", 495 [HasV8MBaselineOps, 496 FeatureNoARM, 497 FeatureDB, 498 FeatureHWDiv, 499 FeatureV7Clrex, 500 Feature8MSecExt, 501 FeatureAcquireRelease, 502 FeatureMClass]>; 503 504def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", 505 [HasV8MMainlineOps, 506 FeatureNoARM, 507 FeatureDB, 508 FeatureHWDiv, 509 Feature8MSecExt, 510 FeatureAcquireRelease, 511 FeatureMClass]>; 512 513// Aliases 514def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; 515def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; 516def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; 517def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; 518def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; 519def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; 520 521 522//===----------------------------------------------------------------------===// 523// ARM processors 524// 525 526// Dummy CPU, used to target architectures 527def : ProcNoItin<"generic", []>; 528 529def : ProcNoItin<"arm8", [ARMv4]>; 530def : ProcNoItin<"arm810", [ARMv4]>; 531def : ProcNoItin<"strongarm", [ARMv4]>; 532def : ProcNoItin<"strongarm110", [ARMv4]>; 533def : ProcNoItin<"strongarm1100", [ARMv4]>; 534def : ProcNoItin<"strongarm1110", [ARMv4]>; 535 536def : ProcNoItin<"arm7tdmi", [ARMv4t]>; 537def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>; 538def : ProcNoItin<"arm710t", [ARMv4t]>; 539def : ProcNoItin<"arm720t", [ARMv4t]>; 540def : ProcNoItin<"arm9", [ARMv4t]>; 541def : ProcNoItin<"arm9tdmi", [ARMv4t]>; 542def : ProcNoItin<"arm920", [ARMv4t]>; 543def : ProcNoItin<"arm920t", [ARMv4t]>; 544def : ProcNoItin<"arm922t", [ARMv4t]>; 545def : ProcNoItin<"arm940t", [ARMv4t]>; 546def : ProcNoItin<"ep9312", [ARMv4t]>; 547 548def : ProcNoItin<"arm10tdmi", [ARMv5t]>; 549def : ProcNoItin<"arm1020t", [ARMv5t]>; 550 551def : ProcNoItin<"arm9e", [ARMv5te]>; 552def : ProcNoItin<"arm926ej-s", [ARMv5te]>; 553def : ProcNoItin<"arm946e-s", [ARMv5te]>; 554def : ProcNoItin<"arm966e-s", [ARMv5te]>; 555def : ProcNoItin<"arm968e-s", [ARMv5te]>; 556def : ProcNoItin<"arm10e", [ARMv5te]>; 557def : ProcNoItin<"arm1020e", [ARMv5te]>; 558def : ProcNoItin<"arm1022e", [ARMv5te]>; 559def : ProcNoItin<"xscale", [ARMv5te]>; 560def : ProcNoItin<"iwmmxt", [ARMv5te]>; 561 562def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>; 563def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, 564 FeatureVFP2, 565 FeatureHasSlowFPVMLx]>; 566 567def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>; 568def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>; 569def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>; 570def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>; 571 572def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; 573def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, 574 FeatureVFP2, 575 FeatureHasSlowFPVMLx]>; 576 577def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>; 578def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k, 579 FeatureVFP2, 580 FeatureHasSlowFPVMLx]>; 581 582def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>; 583def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2, 584 FeatureVFP2, 585 FeatureHasSlowFPVMLx]>; 586 587// FIXME: A5 has currently the same Schedule model as A8 588def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5, 589 FeatureHasRetAddrStack, 590 FeatureTrustZone, 591 FeatureSlowFPBrcc, 592 FeatureHasSlowFPVMLx, 593 FeatureVMLxForwarding, 594 FeatureMP, 595 FeatureVFP4]>; 596 597def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7, 598 FeatureHasRetAddrStack, 599 FeatureTrustZone, 600 FeatureSlowFPBrcc, 601 FeatureHasVMLxHazards, 602 FeatureHasSlowFPVMLx, 603 FeatureVMLxForwarding, 604 FeatureMP, 605 FeatureVFP4, 606 FeatureHWDiv, 607 FeatureHWDivARM, 608 FeatureVirtualization]>; 609 610def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, 611 FeatureHasRetAddrStack, 612 FeatureNonpipelinedVFP, 613 FeatureTrustZone, 614 FeatureSlowFPBrcc, 615 FeatureHasVMLxHazards, 616 FeatureHasSlowFPVMLx, 617 FeatureVMLxForwarding]>; 618 619def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9, 620 FeatureHasRetAddrStack, 621 FeatureTrustZone, 622 FeatureHasVMLxHazards, 623 FeatureVMLxForwarding, 624 FeatureFP16, 625 FeatureAvoidPartialCPSR, 626 FeatureExpandMLx, 627 FeaturePreferVMOVSR, 628 FeatureMuxedUnits, 629 FeatureNEONForFPMovs, 630 FeatureCheckVLDnAlign, 631 FeatureMP]>; 632 633// FIXME: A12 has currently the same Schedule model as A9 634def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12, 635 FeatureHasRetAddrStack, 636 FeatureTrustZone, 637 FeatureVMLxForwarding, 638 FeatureVFP4, 639 FeatureHWDiv, 640 FeatureHWDivARM, 641 FeatureAvoidPartialCPSR, 642 FeatureVirtualization, 643 FeatureMP]>; 644 645// FIXME: A15 has currently the same Schedule model as A9. 646def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, 647 FeatureDontWidenVMOVS, 648 FeatureHasRetAddrStack, 649 FeatureMuxedUnits, 650 FeatureTrustZone, 651 FeatureVFP4, 652 FeatureMP, 653 FeatureCheckVLDnAlign, 654 FeatureHWDiv, 655 FeatureHWDivARM, 656 FeatureAvoidPartialCPSR, 657 FeatureVirtualization]>; 658 659// FIXME: A17 has currently the same Schedule model as A9 660def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17, 661 FeatureHasRetAddrStack, 662 FeatureTrustZone, 663 FeatureMP, 664 FeatureVMLxForwarding, 665 FeatureVFP4, 666 FeatureHWDiv, 667 FeatureHWDivARM, 668 FeatureAvoidPartialCPSR, 669 FeatureVirtualization]>; 670 671// FIXME: krait has currently the same Schedule model as A9 672// FIXME: krait has currently the same features as A9 plus VFP4 and hardware 673// division features. 674def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, 675 FeatureHasRetAddrStack, 676 FeatureMuxedUnits, 677 FeatureCheckVLDnAlign, 678 FeatureVMLxForwarding, 679 FeatureFP16, 680 FeatureAvoidPartialCPSR, 681 FeatureVFP4, 682 FeatureHWDiv, 683 FeatureHWDivARM]>; 684 685def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, 686 FeatureHasRetAddrStack, 687 FeatureNEONForFP, 688 FeatureVFP4, 689 FeatureMP, 690 FeatureHWDiv, 691 FeatureHWDivARM, 692 FeatureAvoidPartialCPSR, 693 FeatureAvoidMOVsShOp, 694 FeatureHasSlowFPVMLx, 695 FeatureHasVMLxHazards, 696 FeatureProfUnpredicate, 697 FeaturePrefISHSTBarrier, 698 FeatureSlowOddRegister, 699 FeatureSlowLoadDSubreg, 700 FeatureSlowVGETLNi32, 701 FeatureSlowVDUP32]>; 702 703// FIXME: R4 has currently the same ProcessorModel as A8. 704def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, 705 FeatureHasRetAddrStack, 706 FeatureAvoidPartialCPSR]>; 707 708// FIXME: R4F has currently the same ProcessorModel as A8. 709def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4, 710 FeatureHasRetAddrStack, 711 FeatureSlowFPBrcc, 712 FeatureHasSlowFPVMLx, 713 FeatureVFP3, 714 FeatureD16, 715 FeatureAvoidPartialCPSR]>; 716 717// FIXME: R5 has currently the same ProcessorModel as A8. 718def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, 719 FeatureHasRetAddrStack, 720 FeatureVFP3, 721 FeatureD16, 722 FeatureSlowFPBrcc, 723 FeatureHWDivARM, 724 FeatureHasSlowFPVMLx, 725 FeatureAvoidPartialCPSR]>; 726 727// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5. 728def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, 729 FeatureHasRetAddrStack, 730 FeatureVFP3, 731 FeatureD16, 732 FeatureFP16, 733 FeatureMP, 734 FeatureSlowFPBrcc, 735 FeatureHWDivARM, 736 FeatureHasSlowFPVMLx, 737 FeatureAvoidPartialCPSR]>; 738 739def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, 740 FeatureHasRetAddrStack, 741 FeatureVFP3, 742 FeatureD16, 743 FeatureFP16, 744 FeatureMP, 745 FeatureSlowFPBrcc, 746 FeatureHWDivARM, 747 FeatureHasSlowFPVMLx, 748 FeatureAvoidPartialCPSR]>; 749 750def : ProcNoItin<"cortex-m3", [ARMv7m, ProcM3]>; 751def : ProcNoItin<"sc300", [ARMv7m, ProcM3]>; 752 753def : ProcNoItin<"cortex-m4", [ARMv7em, 754 FeatureVFP4, 755 FeatureVFPOnlySP, 756 FeatureD16]>; 757 758def : ProcNoItin<"cortex-m7", [ARMv7em, 759 FeatureFPARMv8, 760 FeatureD16]>; 761 762def : ProcNoItin<"cortex-a32", [ARMv8a, 763 FeatureHWDiv, 764 FeatureHWDivARM, 765 FeatureCrypto, 766 FeatureCRC]>; 767 768def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, 769 FeatureHWDiv, 770 FeatureHWDivARM, 771 FeatureCrypto, 772 FeatureCRC]>; 773 774def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, 775 FeatureHWDiv, 776 FeatureHWDivARM, 777 FeatureCrypto, 778 FeatureCRC, 779 FeatureFPAO]>; 780 781def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57, 782 FeatureHWDiv, 783 FeatureHWDivARM, 784 FeatureCrypto, 785 FeatureCRC, 786 FeatureFPAO]>; 787 788def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72, 789 FeatureHWDiv, 790 FeatureHWDivARM, 791 FeatureCrypto, 792 FeatureCRC]>; 793 794def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73, 795 FeatureHWDiv, 796 FeatureHWDivARM, 797 FeatureCrypto, 798 FeatureCRC]>; 799 800// Cyclone is very similar to swift 801def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, 802 FeatureHasRetAddrStack, 803 FeatureNEONForFP, 804 FeatureVFP4, 805 FeatureMP, 806 FeatureHWDiv, 807 FeatureHWDivARM, 808 FeatureAvoidPartialCPSR, 809 FeatureAvoidMOVsShOp, 810 FeatureHasSlowFPVMLx, 811 FeatureCrypto, 812 FeatureZCZeroing]>; 813 814def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1, 815 FeatureHWDiv, 816 FeatureHWDivARM, 817 FeatureCrypto, 818 FeatureCRC]>; 819 820def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynosM1, 821 FeatureHWDiv, 822 FeatureHWDivARM, 823 FeatureCrypto, 824 FeatureCRC]>; 825 826def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynosM1, 827 FeatureHWDiv, 828 FeatureHWDivARM, 829 FeatureCrypto, 830 FeatureCRC]>; 831 832def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, 833 FeatureFPAO]>; 834 835//===----------------------------------------------------------------------===// 836// Register File Description 837//===----------------------------------------------------------------------===// 838 839include "ARMRegisterInfo.td" 840 841include "ARMCallingConv.td" 842 843//===----------------------------------------------------------------------===// 844// Instruction Descriptions 845//===----------------------------------------------------------------------===// 846 847include "ARMInstrInfo.td" 848 849def ARMInstrInfo : InstrInfo; 850 851//===----------------------------------------------------------------------===// 852// Declare the target which we are implementing 853//===----------------------------------------------------------------------===// 854 855def ARMAsmWriter : AsmWriter { 856 string AsmWriterClassName = "InstPrinter"; 857 int PassSubtarget = 1; 858 int Variant = 0; 859 bit isMCAsmWriter = 1; 860} 861 862def ARMAsmParserVariant : AsmParserVariant { 863 int Variant = 0; 864 string Name = "ARM"; 865 string BreakCharacters = "."; 866} 867 868def ARM : Target { 869 // Pull in Instruction Info: 870 let InstructionSet = ARMInstrInfo; 871 let AssemblyWriters = [ARMAsmWriter]; 872 let AssemblyParserVariants = [ARMAsmParserVariant]; 873} 874