1 //===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the entry points for global functions defined in the LLVM 11 // ARM back-end. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef TARGET_ARM_H 16 #define TARGET_ARM_H 17 18 #include "llvm/Support/ErrorHandling.h" 19 #include "llvm/Target/TargetMachine.h" 20 #include <cassert> 21 22 namespace llvm { 23 24 class ARMBaseTargetMachine; 25 class FunctionPass; 26 class MachineCodeEmitter; 27 class JITCodeEmitter; 28 class ObjectCodeEmitter; 29 class formatted_raw_ostream; 30 31 // Enums corresponding to ARM condition codes 32 namespace ARMCC { 33 // The CondCodes constants map directly to the 4-bit encoding of the 34 // condition field for predicated instructions. 35 enum CondCodes { 36 EQ, 37 NE, 38 HS, 39 LO, 40 MI, 41 PL, 42 VS, 43 VC, 44 HI, 45 LS, 46 GE, 47 LT, 48 GT, 49 LE, 50 AL 51 }; 52 53 inline static CondCodes getOppositeCondition(CondCodes CC){ 54 switch (CC) { 55 default: llvm_unreachable("Unknown condition code"); 56 case EQ: return NE; 57 case NE: return EQ; 58 case HS: return LO; 59 case LO: return HS; 60 case MI: return PL; 61 case PL: return MI; 62 case VS: return VC; 63 case VC: return VS; 64 case HI: return LS; 65 case LS: return HI; 66 case GE: return LT; 67 case LT: return GE; 68 case GT: return LE; 69 case LE: return GT; 70 } 71 } 72 } 73 74 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { 75 switch (CC) { 76 default: llvm_unreachable("Unknown condition code"); 77 case ARMCC::EQ: return "eq"; 78 case ARMCC::NE: return "ne"; 79 case ARMCC::HS: return "hs"; 80 case ARMCC::LO: return "lo"; 81 case ARMCC::MI: return "mi"; 82 case ARMCC::PL: return "pl"; 83 case ARMCC::VS: return "vs"; 84 case ARMCC::VC: return "vc"; 85 case ARMCC::HI: return "hi"; 86 case ARMCC::LS: return "ls"; 87 case ARMCC::GE: return "ge"; 88 case ARMCC::LT: return "lt"; 89 case ARMCC::GT: return "gt"; 90 case ARMCC::LE: return "le"; 91 case ARMCC::AL: return "al"; 92 } 93 } 94 95 FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM); 96 FunctionPass *createARMCodeEmitterPass(ARMBaseTargetMachine &TM, 97 MachineCodeEmitter &MCE); 98 99 FunctionPass *createARMCodeEmitterPass(ARMBaseTargetMachine &TM, 100 MachineCodeEmitter &MCE); 101 FunctionPass *createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, 102 JITCodeEmitter &JCE); 103 FunctionPass *createARMObjectCodeEmitterPass(ARMBaseTargetMachine &TM, 104 ObjectCodeEmitter &OCE); 105 106 FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false); 107 FunctionPass *createARMConstantIslandPass(); 108 109 FunctionPass *createThumb2ITBlockPass(); 110 111 extern Target TheARMTarget, TheThumbTarget; 112 113 } // end namespace llvm; 114 115 // Defines symbolic names for ARM registers. This defines a mapping from 116 // register name to register number. 117 // 118 #include "ARMGenRegisterNames.inc" 119 120 // Defines symbolic names for the ARM instructions. 121 // 122 #include "ARMGenInstrNames.inc" 123 124 125 #endif 126