1 //===- ARCRegisterInfo.cpp - ARC Register Information -----------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the ARC implementation of the MRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARCRegisterInfo.h"
15 #include "ARC.h"
16 #include "ARCInstrInfo.h"
17 #include "ARCMachineFunctionInfo.h"
18 #include "ARCSubtarget.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/CodeGen/TargetFrameLowering.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "arc-reg-info"
35 
36 #define GET_REGINFO_TARGET_DESC
37 #include "ARCGenRegisterInfo.inc"
38 
39 static void ReplaceFrameIndex(MachineBasicBlock::iterator II,
40                               const ARCInstrInfo &TII, unsigned Reg,
41                               unsigned FrameReg, int Offset, int StackSize,
42                               int ObjSize, RegScavenger *RS, int SPAdj) {
43   assert(RS && "Need register scavenger.");
44   MachineInstr &MI = *II;
45   MachineBasicBlock &MBB = *MI.getParent();
46   DebugLoc dl = MI.getDebugLoc();
47   unsigned BaseReg = FrameReg;
48   unsigned KillState = 0;
49   if (MI.getOpcode() == ARC::LD_rs9 && (Offset >= 256 || Offset < -256)) {
50     // Loads can always be reached with LD_rlimm.
51     BuildMI(MBB, II, dl, TII.get(ARC::LD_rlimm), Reg)
52         .addReg(BaseReg)
53         .addImm(Offset)
54         .addMemOperand(*MI.memoperands_begin());
55     MBB.erase(II);
56     return;
57   }
58 
59   if (MI.getOpcode() != ARC::GETFI && (Offset >= 256 || Offset < -256)) {
60     // We need to use a scratch register to reach the far-away frame indexes.
61     BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass);
62     if (!BaseReg) {
63       // We can be sure that the scavenged-register slot is within the range
64       // of the load offset.
65       const TargetRegisterInfo *TRI =
66           MBB.getParent()->getSubtarget().getRegisterInfo();
67       BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj);
68       assert(BaseReg && "Register scavenging failed.");
69       DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI)
70                    << " for FrameReg=" << printReg(FrameReg, TRI)
71                    << "+Offset=" << Offset << "\n");
72       (void)TRI;
73       RS->setRegUsed(BaseReg);
74     }
75     unsigned AddOpc = isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm;
76     BuildMI(MBB, II, dl, TII.get(AddOpc))
77         .addReg(BaseReg, RegState::Define)
78         .addReg(FrameReg)
79         .addImm(Offset);
80     Offset = 0;
81     KillState = RegState::Kill;
82   }
83   switch (MI.getOpcode()) {
84   case ARC::LD_rs9:
85     assert((Offset % 4 == 0) && "LD needs 4 byte alignment.");
86   case ARC::LDH_rs9:
87   case ARC::LDH_X_rs9:
88     assert((Offset % 2 == 0) && "LDH needs 2 byte alignment.");
89   case ARC::LDB_rs9:
90   case ARC::LDB_X_rs9:
91     DEBUG(dbgs() << "Building LDFI\n");
92     BuildMI(MBB, II, dl, TII.get(MI.getOpcode()), Reg)
93         .addReg(BaseReg, KillState)
94         .addImm(Offset)
95         .addMemOperand(*MI.memoperands_begin());
96     break;
97   case ARC::ST_rs9:
98     assert((Offset % 4 == 0) && "ST needs 4 byte alignment.");
99   case ARC::STH_rs9:
100     assert((Offset % 2 == 0) && "STH needs 2 byte alignment.");
101   case ARC::STB_rs9:
102     DEBUG(dbgs() << "Building STFI\n");
103     BuildMI(MBB, II, dl, TII.get(MI.getOpcode()))
104         .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
105         .addReg(BaseReg, KillState)
106         .addImm(Offset)
107         .addMemOperand(*MI.memoperands_begin());
108     break;
109   case ARC::GETFI:
110     DEBUG(dbgs() << "Building GETFI\n");
111     BuildMI(MBB, II, dl,
112             TII.get(isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm))
113         .addReg(Reg, RegState::Define)
114         .addReg(FrameReg)
115         .addImm(Offset);
116     break;
117   default:
118     llvm_unreachable("Unhandled opcode.");
119   }
120 
121   // Erase old instruction.
122   MBB.erase(II);
123 }
124 
125 ARCRegisterInfo::ARCRegisterInfo() : ARCGenRegisterInfo(ARC::BLINK) {}
126 
127 bool ARCRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
128   return MF.getMMI().hasDebugInfo() || MF.getFunction().needsUnwindTableEntry();
129 }
130 
131 const MCPhysReg *
132 ARCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
133   return CSR_ARC_SaveList;
134 }
135 
136 BitVector ARCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
137   BitVector Reserved(getNumRegs());
138 
139   Reserved.set(ARC::ILINK);
140   Reserved.set(ARC::SP);
141   Reserved.set(ARC::GP);
142   Reserved.set(ARC::R25);
143   Reserved.set(ARC::BLINK);
144   Reserved.set(ARC::FP);
145   return Reserved;
146 }
147 
148 bool ARCRegisterInfo::requiresRegisterScavenging(
149     const MachineFunction &MF) const {
150   return true;
151 }
152 
153 bool ARCRegisterInfo::trackLivenessAfterRegAlloc(
154     const MachineFunction &MF) const {
155   return true;
156 }
157 
158 bool ARCRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
159   return true;
160 }
161 
162 void ARCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
163                                           int SPAdj, unsigned FIOperandNum,
164                                           RegScavenger *RS) const {
165   assert(SPAdj == 0 && "Unexpected");
166   MachineInstr &MI = *II;
167   MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
168   int FrameIndex = FrameOp.getIndex();
169 
170   MachineFunction &MF = *MI.getParent()->getParent();
171   const ARCInstrInfo &TII = *MF.getSubtarget<ARCSubtarget>().getInstrInfo();
172   const ARCFrameLowering *TFI = getFrameLowering(MF);
173   int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex);
174   int ObjSize = MF.getFrameInfo().getObjectSize(FrameIndex);
175   int StackSize = MF.getFrameInfo().getStackSize();
176   int LocalFrameSize = MF.getFrameInfo().getLocalFrameSize();
177 
178   DEBUG(dbgs() << "\nFunction         : " << MF.getName() << "\n");
179   DEBUG(dbgs() << "<--------->\n");
180   DEBUG(dbgs() << MI << "\n");
181   DEBUG(dbgs() << "FrameIndex         : " << FrameIndex << "\n");
182   DEBUG(dbgs() << "ObjSize            : " << ObjSize << "\n");
183   DEBUG(dbgs() << "FrameOffset        : " << Offset << "\n");
184   DEBUG(dbgs() << "StackSize          : " << StackSize << "\n");
185   DEBUG(dbgs() << "LocalFrameSize     : " << LocalFrameSize << "\n");
186   (void)LocalFrameSize;
187 
188   // Special handling of DBG_VALUE instructions.
189   if (MI.isDebugValue()) {
190     unsigned FrameReg = getFrameRegister(MF);
191     MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
192     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
193     return;
194   }
195 
196   // fold constant into offset.
197   Offset += MI.getOperand(FIOperandNum + 1).getImm();
198 
199   // TODO: assert based on the load type:
200   // ldb needs no alignment,
201   // ldh needs 2 byte alignment
202   // ld needs 4 byte alignment
203   DEBUG(dbgs() << "Offset             : " << Offset << "\n"
204                << "<--------->\n");
205 
206   unsigned Reg = MI.getOperand(0).getReg();
207   assert(ARC::GPR32RegClass.contains(Reg) && "Unexpected register operand");
208 
209   if (!TFI->hasFP(MF)) {
210     Offset = StackSize + Offset;
211     if (FrameIndex >= 0)
212       assert((Offset >= 0 && Offset < StackSize) && "SP Offset not in bounds.");
213   } else {
214     if (FrameIndex >= 0) {
215       assert((Offset < 0 && -Offset <= StackSize) &&
216              "FP Offset not in bounds.");
217     }
218   }
219   ReplaceFrameIndex(II, TII, Reg, getFrameRegister(MF), Offset, StackSize,
220                     ObjSize, RS, SPAdj);
221 }
222 
223 unsigned ARCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
224   const ARCFrameLowering *TFI = getFrameLowering(MF);
225   return TFI->hasFP(MF) ? ARC::FP : ARC::SP;
226 }
227 
228 const uint32_t *
229 ARCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
230                                       CallingConv::ID CC) const {
231   return CSR_ARC_RegMask;
232 }
233