1//===-- VOPInstructions.td - Vector Instruction Definitions ---------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// dummies for outer let 10class LetDummies { 11 bit TRANS; 12 bit ReadsModeReg; 13 bit mayRaiseFPException; 14 bit isCommutable; 15 bit isConvertibleToThreeAddress; 16 bit isMoveImm; 17 bit isReMaterializable; 18 bit isAsCheapAsAMove; 19 bit VOPAsmPrefer32Bit; 20 bit FPDPRounding; 21 Predicate SubtargetPredicate; 22 string Constraints; 23 string DisableEncoding; 24 list<SchedReadWrite> SchedRW; 25 list<Register> Uses; 26 list<Register> Defs; 27} 28 29class VOP <string opName> { 30 string OpName = opName; 31} 32 33class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> : 34 InstSI <outs, ins, asm, pattern> { 35 36 let mayLoad = 0; 37 let mayStore = 0; 38 let hasSideEffects = 0; 39 let UseNamedOperandTable = 1; 40 let VALU = 1; 41 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 42} 43 44class VOP_Pseudo <string opName, string suffix, VOPProfile P, dag outs, dag ins, 45 string asm, list<dag> pattern> : 46 InstSI <outs, ins, asm, pattern>, 47 VOP <opName>, 48 SIMCInstr <opName#suffix, SIEncodingFamily.NONE> { 49 let isPseudo = 1; 50 let isCodeGenOnly = 1; 51 let UseNamedOperandTable = 1; 52 53 string Mnemonic = opName; 54 VOPProfile Pfl = P; 55 56 string AsmOperands; 57} 58 59class VOP3Common <dag outs, dag ins, string asm = "", 60 list<dag> pattern = [], bit HasMods = 0> : 61 VOPAnyCommon <outs, ins, asm, pattern> { 62 63 // Using complex patterns gives VOP3 patterns a very high complexity rating, 64 // but standalone patterns are almost always preferred, so we need to adjust the 65 // priority lower. The goal is to use a high number to reduce complexity to 66 // zero (or less than zero). 67 let AddedComplexity = -1000; 68 69 let VOP3 = 1; 70 71 let AsmVariantName = AMDGPUAsmVariants.VOP3; 72 let AsmMatchConverter = !if(HasMods, "cvtVOP3", ""); 73 74 let isCodeGenOnly = 0; 75 76 int Size = 8; 77 78 // Because SGPRs may be allowed if there are multiple operands, we 79 // need a post-isel hook to insert copies in order to avoid 80 // violating constant bus requirements. 81 let hasPostISelHook = 1; 82} 83 84class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [], 85 bit isVOP3P = 0, bit isVop3OpSel = 0> : 86 VOP_Pseudo <opName, "_e64", P, P.Outs64, 87 !if(isVop3OpSel, 88 P.InsVOP3OpSel, 89 !if(!and(isVOP3P, P.IsPacked), P.InsVOP3P, P.Ins64)), 90 "", pattern> { 91 92 let VOP3_OPSEL = isVop3OpSel; 93 let IsPacked = P.IsPacked; 94 let IsMAI = P.IsMAI; 95 96 let AsmOperands = !if(isVop3OpSel, 97 P.AsmVOP3OpSel, 98 !if(!and(isVOP3P, P.IsPacked), P.AsmVOP3P, P.Asm64)); 99 100 let Size = 8; 101 let mayLoad = 0; 102 let mayStore = 0; 103 let hasSideEffects = 0; 104 105 // Because SGPRs may be allowed if there are multiple operands, we 106 // need a post-isel hook to insert copies in order to avoid 107 // violating constant bus requirements. 108 let hasPostISelHook = 1; 109 110 // Using complex patterns gives VOP3 patterns a very high complexity rating, 111 // but standalone patterns are almost always preferred, so we need to adjust the 112 // priority lower. The goal is to use a high number to reduce complexity to 113 // zero (or less than zero). 114 let AddedComplexity = -1000; 115 116 let VOP3 = 1; 117 let VALU = 1; 118 let FPClamp = P.HasFPClamp; 119 let IntClamp = P.HasIntClamp; 120 let ClampLo = P.HasClampLo; 121 let ClampHi = P.HasClampHi; 122 123 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 124 125 let mayRaiseFPException = ReadsModeReg; 126 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 127 128 let AsmVariantName = AMDGPUAsmVariants.VOP3; 129 let AsmMatchConverter = 130 !if(isVOP3P, 131 "cvtVOP3P", 132 !if(!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), 133 "cvtVOP3", 134 "")); 135} 136 137class VOP3P_Pseudo <string opName, VOPProfile P, list<dag> pattern = []> : 138 VOP3_Pseudo<opName, P, pattern, 1> { 139 let VOP3P = 1; 140} 141 142class VOP_Real<VOP_Pseudo ps> { 143 Instruction Opcode = !cast<Instruction>(NAME); 144 bit IsSingle = ps.Pfl.IsSingle; 145} 146 147class VOP3_Real <VOP_Pseudo ps, int EncodingFamily, string asm_name = ps.Mnemonic> : 148 VOP_Real <ps>, 149 InstSI <ps.OutOperandList, ps.InOperandList, asm_name # ps.AsmOperands, []>, 150 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 151 152 let VALU = 1; 153 let VOP3 = 1; 154 let isPseudo = 0; 155 let isCodeGenOnly = 0; 156 let UseNamedOperandTable = 1; 157 158 // copy relevant pseudo op flags 159 let SubtargetPredicate = ps.SubtargetPredicate; 160 let OtherPredicates = ps.OtherPredicates; 161 let AsmMatchConverter = ps.AsmMatchConverter; 162 let AsmVariantName = ps.AsmVariantName; 163 let Constraints = ps.Constraints; 164 let DisableEncoding = ps.DisableEncoding; 165 let TSFlags = ps.TSFlags; 166 let UseNamedOperandTable = ps.UseNamedOperandTable; 167 let Uses = ps.Uses; 168 let Defs = ps.Defs; 169 let SchedRW = ps.SchedRW; 170 let mayLoad = ps.mayLoad; 171 let mayStore = ps.mayStore; 172 let TRANS = ps.TRANS; 173 174 VOPProfile Pfl = ps.Pfl; 175} 176 177// XXX - Is there any reason to distinguish this from regular VOP3 178// here? 179class VOP3P_Real<VOP_Pseudo ps, int EncodingFamily, string asm_name = ps.Mnemonic> : 180 VOP3_Real<ps, EncodingFamily, asm_name>; 181 182class VOP3a<VOPProfile P> : Enc64 { 183 bits<4> src0_modifiers; 184 bits<9> src0; 185 bits<3> src1_modifiers; 186 bits<9> src1; 187 bits<3> src2_modifiers; 188 bits<9> src2; 189 bits<1> clamp; 190 bits<2> omod; 191 192 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 193 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); 194 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); 195 196 let Inst{31-26} = 0x34; //encoding 197 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 198 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 199 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 200 let Inst{60-59} = !if(P.HasOMod, omod, 0); 201 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 202 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 203 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 204} 205 206class VOP3a_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a<p> { 207 let Inst{11} = !if(p.HasClamp, clamp{0}, 0); 208 let Inst{25-17} = op; 209} 210 211class VOP3a_gfx10<bits<10> op, VOPProfile p> : VOP3a<p> { 212 let Inst{15} = !if(p.HasClamp, clamp{0}, 0); 213 let Inst{25-16} = op; 214 let Inst{31-26} = 0x35; 215} 216 217class VOP3a_gfx11<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p>; 218 219class VOP3a_vi <bits<10> op, VOPProfile P> : VOP3a<P> { 220 let Inst{25-16} = op; 221 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 222} 223 224class VOP3e_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a_gfx6_gfx7<op, p> { 225 bits<8> vdst; 226 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0); 227} 228 229class VOP3e_gfx10<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p> { 230 bits<8> vdst; 231 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0); 232} 233 234class VOP3e_gfx11<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p>; 235 236class VOP3e_vi <bits<10> op, VOPProfile P> : VOP3a_vi <op, P> { 237 bits<8> vdst; 238 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0); 239} 240 241class VOP3OpSel_gfx9 <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> { 242 let Inst{11} = !if(P.HasSrc0, src0_modifiers{2}, 0); 243 let Inst{12} = !if(P.HasSrc1, src1_modifiers{2}, 0); 244 let Inst{13} = !if(P.HasSrc2, src2_modifiers{2}, 0); 245 let Inst{14} = !if(P.HasDst, src0_modifiers{3}, 0); 246} 247 248class VOP3OpSel_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> { 249 let Inst{11} = !if(p.HasSrc0, src0_modifiers{2}, 0); 250 let Inst{12} = !if(p.HasSrc1, src1_modifiers{2}, 0); 251 let Inst{13} = !if(p.HasSrc2, src2_modifiers{2}, 0); 252 let Inst{14} = !if(p.HasDst, src0_modifiers{3}, 0); 253} 254 255class VOP3OpSel_gfx11<bits<10> op, VOPProfile p> : VOP3OpSel_gfx10<op, p>; 256 257 258// NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa 259class VOP3Interp_vi <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> { 260 bits<2> attrchan; 261 bits<6> attr; 262 bits<1> high; 263 264 let Inst{8} = 0; // No modifiers for src0 265 let Inst{61} = 0; 266 267 let Inst{9} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 268 let Inst{62} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 269 270 let Inst{37-32} = attr; 271 let Inst{39-38} = attrchan; 272 let Inst{40} = !if(P.HasHigh, high, 0); 273 274 let Inst{49-41} = src0; 275} 276 277class VOP3Interp_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> { 278 bits<6> attr; 279 bits<2> attrchan; 280 bits<1> high; 281 282 let Inst{8} = 0; 283 let Inst{9} = !if(p.HasSrc0Mods, src0_modifiers{1}, 0); 284 let Inst{37-32} = attr; 285 let Inst{39-38} = attrchan; 286 let Inst{40} = !if(p.HasHigh, high, 0); 287 let Inst{49-41} = src0; 288 let Inst{61} = 0; 289 let Inst{62} = !if(p.HasSrc0Mods, src0_modifiers{0}, 0); 290} 291 292class VOP3Interp_gfx11<bits<10> op, VOPProfile p> : VOP3Interp_gfx10<op, p>; 293 294class VOP3be <VOPProfile P> : Enc64 { 295 bits<8> vdst; 296 bits<2> src0_modifiers; 297 bits<9> src0; 298 bits<2> src1_modifiers; 299 bits<9> src1; 300 bits<2> src2_modifiers; 301 bits<9> src2; 302 bits<7> sdst; 303 bits<2> omod; 304 305 let Inst{7-0} = vdst; 306 let Inst{14-8} = sdst; 307 let Inst{31-26} = 0x34; //encoding 308 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 309 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 310 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 311 let Inst{60-59} = !if(P.HasOMod, omod, 0); 312 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 313 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 314 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 315} 316 317class VOP3Pe <bits<7> op, VOPProfile P> : Enc64 { 318 bits<8> vdst; 319 // neg, neg_hi, op_sel put in srcN_modifiers 320 bits<4> src0_modifiers; 321 bits<9> src0; 322 bits<4> src1_modifiers; 323 bits<9> src1; 324 bits<4> src2_modifiers; 325 bits<9> src2; 326 bits<1> clamp; 327 328 let Inst{7-0} = vdst; 329 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0 330 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // neg_hi src1 331 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); // neg_hi src2 332 333 let Inst{11} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{2}, 0); // op_sel(0) 334 let Inst{12} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{2}, 0); // op_sel(1) 335 let Inst{13} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{2}, 0); // op_sel(2) 336 337 let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, ?); // op_sel_hi(2) 338 339 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 340 341 let Inst{22-16} = op; 342 let Inst{31-23} = 0x1a7; //encoding 343 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 344 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 345 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 346 let Inst{59} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, ?); // op_sel_hi(0) 347 let Inst{60} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, ?); // op_sel_hi(1) 348 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // neg (lo) 349 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // neg (lo) 350 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo) 351} 352 353class VOP3Pe_MAI <bits<7> op, VOPProfile P, bit acc_cd = 0> : Enc64 { 354 bits<8> vdst; 355 bits<10> src0; 356 bits<10> src1; 357 bits<9> src2; 358 bits<3> blgp; 359 bits<3> cbsz; 360 bits<4> abid; 361 362 let Inst{7-0} = vdst; 363 364 let Inst{10-8} = !if(P.HasSrc1, cbsz, 0); 365 let Inst{14-11} = !if(P.HasSrc1, abid, 0); 366 367 let Inst{15} = acc_cd; 368 369 let Inst{22-16} = op; 370 let Inst{31-23} = 0x1a7; //encoding 371 let Inst{40-32} = !if(P.HasSrc0, src0{8-0}, 0); 372 let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, 0); 373 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 374 375 let Inst{59} = !if(P.HasSrc0, src0{9}, 0); // acc(0) 376 let Inst{60} = !if(P.HasSrc1, src1{9}, 0); // acc(1) 377 378 let Inst{63-61} = !if(P.HasSrc1, blgp, 0); 379} 380 381class VOP3Pe_SMFMAC <bits<7> op> : Enc64 { 382 bits<10> vdst; // VGPR or AGPR, but not SGPR. vdst{8} is not encoded in the instruction. 383 bits<10> src0; 384 bits<10> src1; 385 bits<9> idx; 386 bits<3> blgp; 387 bits<3> cbsz; 388 bits<4> abid; 389 390 let blgp = 0; 391 392 let Inst{7-0} = vdst{7-0}; 393 394 let Inst{10-8} = cbsz; 395 let Inst{14-11} = abid; 396 397 let Inst{15} = vdst{9}; // acc(vdst) 398 399 let Inst{22-16} = op; 400 let Inst{31-23} = 0x1a7; // encoding 401 let Inst{40-32} = src0{8-0}; 402 let Inst{49-41} = src1{8-0}; 403 let Inst{58-50} = idx; 404 405 let Inst{59} = src0{9}; // acc(0) 406 let Inst{60} = src1{9}; // acc(1) 407 408 let Inst{63-61} = blgp; 409} 410 411class VOP3Pe_gfx10 <bits<7> op, VOPProfile P> : VOP3Pe<op, P> { 412 let Inst{31-23} = 0x198; //encoding 413} 414 415class VOP3be_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3be<p> { 416 let Inst{25-17} = op; 417} 418 419class VOP3be_gfx10<bits<10> op, VOPProfile p> : VOP3be<p> { 420 bits<1> clamp; 421 let Inst{15} = !if(p.HasClamp, clamp{0}, 0); 422 let Inst{25-16} = op; 423 let Inst{31-26} = 0x35; 424} 425 426class VOP3be_gfx11<bits<10> op, VOPProfile p> : VOP3be_gfx10<op, p>; 427 428class VOP3be_vi <bits<10> op, VOPProfile P> : VOP3be<P> { 429 bits<1> clamp; 430 let Inst{25-16} = op; 431 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 432} 433 434def SDWA { 435 // sdwa_sel 436 int BYTE_0 = 0; 437 int BYTE_1 = 1; 438 int BYTE_2 = 2; 439 int BYTE_3 = 3; 440 int WORD_0 = 4; 441 int WORD_1 = 5; 442 int DWORD = 6; 443 444 // dst_unused 445 int UNUSED_PAD = 0; 446 int UNUSED_SEXT = 1; 447 int UNUSED_PRESERVE = 2; 448} 449 450class VOP_SDWAe<VOPProfile P> : Enc64 { 451 bits<8> src0; 452 bits<3> src0_sel; 453 bits<2> src0_modifiers; // float: {abs,neg}, int {sext} 454 bits<3> src1_sel; 455 bits<2> src1_modifiers; 456 bits<3> dst_sel; 457 bits<2> dst_unused; 458 bits<1> clamp; 459 460 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 461 let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?); 462 let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?); 463 let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); 464 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0); 465 let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0); 466 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0); 467 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0); 468 let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0); 469 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0); 470} 471 472// GFX9 adds two features to SDWA: 473// 1. Add 3 fields to the SDWA microcode word: S0, S1 and OMOD. 474// a. S0 and S1 indicate that source 0 and 1 respectively are SGPRs rather 475// than VGPRs (at most 1 can be an SGPR); 476// b. OMOD is the standard output modifier (result *2, *4, /2) 477// 2. Add a new version of the SDWA microcode word for VOPC: SDWAB. This 478// replaces OMOD and the dest fields with SD and SDST (SGPR destination) 479// field. 480// a. When SD=1, the SDST is used as the destination for the compare result; 481// b. When SD=0, VCC is used. 482// 483// In GFX9, V_MAC_F16, V_MAC_F32 opcodes cannot be used with SDWA 484 485// gfx9 SDWA basic encoding 486class VOP_SDWA9e<VOPProfile P> : Enc64 { 487 bits<9> src0; // {src0_sgpr{0}, src0{7-0}} 488 bits<3> src0_sel; 489 bits<2> src0_modifiers; // float: {abs,neg}, int {sext} 490 bits<3> src1_sel; 491 bits<2> src1_modifiers; 492 bits<1> src1_sgpr; 493 494 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 495 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0); 496 let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0); 497 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0); 498 let Inst{55} = !if(P.HasSrc0, src0{8}, 0); 499 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0); 500 let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0); 501 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0); 502 let Inst{63} = 0; // src1_sgpr - should be specified in subclass 503} 504 505// gfx9 SDWA-A 506class VOP_SDWA9Ae<VOPProfile P> : VOP_SDWA9e<P> { 507 bits<3> dst_sel; 508 bits<2> dst_unused; 509 bits<1> clamp; 510 bits<2> omod; 511 512 let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?); 513 let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?); 514 let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); 515 let Inst{47-46} = !if(P.HasSDWAOMod, omod{1-0}, 0); 516} 517 518// gfx9 SDWA-B 519class VOP_SDWA9Be<VOPProfile P> : VOP_SDWA9e<P> { 520 bits<8> sdst; // {vcc_sdst{0}, sdst{6-0}} 521 522 let Inst{46-40} = !if(P.EmitDst, sdst{6-0}, ?); 523 let Inst{47} = !if(P.EmitDst, sdst{7}, 0); 524} 525 526class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> : 527 InstSI <P.OutsSDWA, P.InsSDWA, "", pattern>, 528 VOP <opName>, 529 SIMCInstr <opName#"_sdwa", SIEncodingFamily.NONE> { 530 531 let isPseudo = 1; 532 let isCodeGenOnly = 1; 533 let UseNamedOperandTable = 1; 534 535 string Mnemonic = opName; 536 string AsmOperands = P.AsmSDWA; 537 string AsmOperands9 = P.AsmSDWA9; 538 539 let Size = 8; 540 let mayLoad = 0; 541 let mayStore = 0; 542 let hasSideEffects = 0; 543 544 let VALU = 1; 545 let SDWA = 1; 546 547 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 548 549 let mayRaiseFPException = ReadsModeReg; 550 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 551 552 let SubtargetPredicate = HasSDWA; 553 let AssemblerPredicate = HasSDWA; 554 let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA, 555 AMDGPUAsmVariants.Disable); 556 let DecoderNamespace = "SDWA"; 557 558 VOPProfile Pfl = P; 559} 560 561class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> : 562 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 563 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA> { 564 565 let VALU = 1; 566 let SDWA = 1; 567 let isPseudo = 0; 568 let isCodeGenOnly = 0; 569 570 let Defs = ps.Defs; 571 let Uses = ps.Uses; 572 let hasSideEffects = ps.hasSideEffects; 573 574 let Constraints = ps.Constraints; 575 let DisableEncoding = ps.DisableEncoding; 576 577 // Copy relevant pseudo op flags 578 let SubtargetPredicate = ps.SubtargetPredicate; 579 let AssemblerPredicate = ps.AssemblerPredicate; 580 let AsmMatchConverter = ps.AsmMatchConverter; 581 let AsmVariantName = ps.AsmVariantName; 582 let UseNamedOperandTable = ps.UseNamedOperandTable; 583 let DecoderNamespace = ps.DecoderNamespace; 584 let Constraints = ps.Constraints; 585 let DisableEncoding = ps.DisableEncoding; 586 let TSFlags = ps.TSFlags; 587 let SchedRW = ps.SchedRW; 588 let mayLoad = ps.mayLoad; 589 let mayStore = ps.mayStore; 590 let TRANS = ps.TRANS; 591} 592 593class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> : 594 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands9, []> { 595 596 let VALU = 1; 597 let SDWA = 1; 598 let isPseudo = 0; 599 let isCodeGenOnly = 0; 600 601 let Defs = ps.Defs; 602 let Uses = ps.Uses; 603 let hasSideEffects = ps.hasSideEffects; 604 605 let Constraints = ps.Constraints; 606 let DisableEncoding = ps.DisableEncoding; 607 608 let SubtargetPredicate = HasSDWA9; 609 let AssemblerPredicate = HasSDWA9; 610 let AsmVariantName = !if(ps.Pfl.HasExtSDWA9, AMDGPUAsmVariants.SDWA9, 611 AMDGPUAsmVariants.Disable); 612 let DecoderNamespace = "SDWA9"; 613 614 // Copy relevant pseudo op flags 615 let AsmMatchConverter = ps.AsmMatchConverter; 616 let UseNamedOperandTable = ps.UseNamedOperandTable; 617 let Constraints = ps.Constraints; 618 let DisableEncoding = ps.DisableEncoding; 619 let TSFlags = ps.TSFlags; 620 let SchedRW = ps.SchedRW; 621 let mayLoad = ps.mayLoad; 622 let mayStore = ps.mayStore; 623 let TRANS = ps.TRANS; 624} 625 626class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> : 627 Base_VOP_SDWA9_Real <ps >, 628 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA9>; 629 630class Base_VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : Base_VOP_SDWA9_Real<ps> { 631 let SubtargetPredicate = HasSDWA10; 632 let AssemblerPredicate = HasSDWA10; 633 let DecoderNamespace = "SDWA10"; 634} 635 636class VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : 637 Base_VOP_SDWA10_Real<ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SDWA10>; 638 639class VOP_DPPe<VOPProfile P, bit IsDPP16=0> : Enc64 { 640 bits<2> src0_modifiers; 641 bits<8> src0; 642 bits<2> src1_modifiers; 643 bits<9> dpp_ctrl; 644 bits<1> bound_ctrl; 645 bits<4> bank_mask; 646 bits<4> row_mask; 647 bit fi; 648 649 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 650 let Inst{48-40} = dpp_ctrl; 651 let Inst{50} = !if(IsDPP16, fi, ?); 652 let Inst{51} = bound_ctrl; 653 let Inst{52} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg 654 let Inst{53} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // src0_abs 655 let Inst{54} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg 656 let Inst{55} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // src1_abs 657 let Inst{59-56} = bank_mask; 658 let Inst{63-60} = row_mask; 659} 660 661class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : 662 InstSI <P.OutsDPP, P.InsDPP, OpName#P.AsmDPP, pattern>, 663 VOP <OpName>, 664 SIMCInstr <OpName#"_dpp", SIEncodingFamily.NONE> { 665 666 let isPseudo = 1; 667 let isCodeGenOnly = 1; 668 669 let mayLoad = 0; 670 let mayStore = 0; 671 let hasSideEffects = 0; 672 let UseNamedOperandTable = 1; 673 674 let VALU = 1; 675 let DPP = 1; 676 let Size = 8; 677 678 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 679 680 let mayRaiseFPException = ReadsModeReg; 681 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 682 let isConvergent = 1; 683 684 string Mnemonic = OpName; 685 string AsmOperands = P.AsmDPP; 686 687 let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", ""); 688 let SubtargetPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 689 let AssemblerPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 690 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, 691 AMDGPUAsmVariants.Disable); 692 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 693 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 694 let DecoderNamespace = "DPP"; 695 696 VOPProfile Pfl = P; 697} 698 699class VOP_DPP_Real <VOP_DPP_Pseudo ps, int EncodingFamily> : 700 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 701 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 702 703 let VALU = 1; 704 let DPP = 1; 705 let isPseudo = 0; 706 let isCodeGenOnly = 0; 707 708 let Defs = ps.Defs; 709 let Uses = ps.Uses; 710 let hasSideEffects = ps.hasSideEffects; 711 712 let Constraints = ps.Constraints; 713 let DisableEncoding = ps.DisableEncoding; 714 715 // Copy relevant pseudo op flags 716 let isConvergent = ps.isConvergent; 717 let SubtargetPredicate = ps.SubtargetPredicate; 718 let AssemblerPredicate = ps.AssemblerPredicate; 719 let OtherPredicates = ps.OtherPredicates; 720 let AsmMatchConverter = ps.AsmMatchConverter; 721 let AsmVariantName = ps.AsmVariantName; 722 let UseNamedOperandTable = ps.UseNamedOperandTable; 723 let DecoderNamespace = ps.DecoderNamespace; 724 let Constraints = ps.Constraints; 725 let DisableEncoding = ps.DisableEncoding; 726 let TSFlags = ps.TSFlags; 727 let SchedRW = ps.SchedRW; 728 let mayLoad = ps.mayLoad; 729 let mayStore = ps.mayStore; 730 let TRANS = ps.TRANS; 731} 732 733class VOP_DPP <string OpName, VOPProfile P, bit IsDPP16, 734 dag InsDPP = !if(IsDPP16, P.InsDPP16, P.InsDPP), 735 string AsmDPP = !if(IsDPP16, P.AsmDPP16, P.AsmDPP)> : 736 InstSI <P.OutsDPP, InsDPP, OpName#AsmDPP, []>, 737 VOP_DPPe<P, IsDPP16> { 738 739 let mayLoad = 0; 740 let mayStore = 0; 741 let hasSideEffects = 0; 742 let UseNamedOperandTable = 1; 743 744 let VALU = 1; 745 let DPP = 1; 746 let Size = 8; 747 748 let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", ""); 749 let SubtargetPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 750 let AssemblerPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 751 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, 752 AMDGPUAsmVariants.Disable); 753 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 754 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 755 let DecoderNamespace = "DPP"; 756} 757 758class VOP_DPP8e<VOPProfile P> : Enc64 { 759 bits<8> src0; 760 bits<24> dpp8; 761 bits<9> fi; 762 763 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 764 let Inst{63-40} = dpp8{23-0}; 765} 766 767class VOP_DPP8<string OpName, VOPProfile P> : 768 InstSI<P.OutsDPP8, P.InsDPP8, OpName#P.AsmDPP8, []>, 769 VOP_DPP8e<P> { 770 771 let mayLoad = 0; 772 let mayStore = 0; 773 let hasSideEffects = 0; 774 let UseNamedOperandTable = 1; 775 776 let VALU = 1; 777 let DPP = 1; 778 let Size = 8; 779 780 let AsmMatchConverter = "cvtDPP8"; 781 let SubtargetPredicate = HasDPP8; 782 let AssemblerPredicate = HasDPP8; 783 let AsmVariantName = !if(P.HasExt, AMDGPUAsmVariants.DPP, 784 AMDGPUAsmVariants.Disable); 785 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 786 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 787} 788 789def DPP8Mode { 790 int FI_0 = 0xE9; 791 int FI_1 = 0xEA; 792} 793 794class getNumNodeArgs<SDPatternOperator Op> { 795 SDNode N = !cast<SDNode>(Op); 796 SDTypeProfile TP = N.TypeProfile; 797 int ret = TP.NumOperands; 798} 799 800class getDivergentFrag<SDPatternOperator Op> { 801 assert !or(!isa<SDNode>(Op), !isa<PatFrags>(Op)), "Expected SDNode or PatFrags"; 802 803 int NumSrcArgs = !if(!isa<SDNode>(Op), getNumNodeArgs<Op>.ret, 804 !size(!cast<PatFrags>(Op).Operands)); 805 PatFrag ret = PatFrag < 806 !if(!eq(NumSrcArgs, 1), 807 (ops node:$src0), 808 !if(!eq(NumSrcArgs, 2), 809 (ops node:$src0, node:$src1), 810 (ops node:$src0, node:$src1, node:$src2))), 811 !if(!eq(NumSrcArgs, 1), 812 (Op $src0), 813 !if(!eq(NumSrcArgs, 2), 814 (Op $src0, $src1), 815 (Op $src0, $src1, $src2))), 816 [{ return N->isDivergent(); }] 817 >; 818} 819 820class VOPPatGen<SDPatternOperator Op, VOPProfile P> { 821 PatFrag Operator = getDivergentFrag < Op >.ret; 822 823 dag Ins = !foreach(tmp, P.Ins32, !subst(ins, Operator, 824 !subst(P.Src0RC32, P.Src0VT, 825 !subst(P.Src1RC32, P.Src1VT, tmp)))); 826 827 dag Outs = !foreach(tmp, P.Outs32, !subst(outs, set, 828 !subst(P.DstRC, P.DstVT, tmp))); 829 830 list<dag> ret = [!con(Outs, (set Ins))]; 831} 832 833class DivergentUnaryFrag<SDPatternOperator Op> : PatFrag < 834 (ops node:$src0), 835 (Op $src0), 836 [{ return N->isDivergent(); }]> { 837 // This check is unnecessary as it's captured by the result register 838 // bank constraint. 839 // 840 // FIXME: Should add a way for the emitter to recognize this is a 841 // trivially true predicate to eliminate the check. 842 let GISelPredicateCode = [{return true;}]; 843} 844 845class VOPPatOrNull<SDPatternOperator Op, VOPProfile P> { 846 list<dag> ret = !if(!ne(P.NeedPatGen,PatGenMode.NoPattern), VOPPatGen<Op, P>.ret, []); 847} 848 849class DivergentFragOrOp<SDPatternOperator Op, VOPProfile P> { 850 SDPatternOperator ret = !if(!eq(P.NeedPatGen,PatGenMode.Pattern), 851 !if(!isa<SDNode>(Op), getDivergentFrag<Op>.ret, Op), Op); 852} 853 854class getVSrcOp<ValueType vt> { 855 RegisterOperand ret = !if(!eq(vt.Size, 32), VSrc_b32, VSrc_b16); 856} 857 858// Class for binary integer operations with the clamp bit set for saturation 859// TODO: Add sub with negated inline constant pattern. 860class VOPBinOpClampPat<SDPatternOperator node, Instruction inst, ValueType vt> : 861 GCNPat<(node vt:$src0, vt:$src1), 862 (inst getVSrcOp<vt>.ret:$src0, getVSrcOp<vt>.ret:$src1, 863 DSTCLAMP.ENABLE) 864>; 865 866//===----------------------------------------------------------------------===// 867// VOP3 Classes 868//===----------------------------------------------------------------------===// 869 870class getVOP3ModPat<VOPProfile P, SDPatternOperator node> { 871 dag src0 = !if(P.HasOMod, 872 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 873 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)); 874 875 list<dag> ret3 = [(set P.DstVT:$vdst, 876 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 877 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), 878 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))]; 879 880 list<dag> ret2 = [(set P.DstVT:$vdst, 881 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 882 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))]; 883 884 list<dag> ret1 = [(set P.DstVT:$vdst, 885 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))]; 886 887 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 888 !if(!eq(P.NumSrcArgs, 2), ret2, 889 ret1)); 890} 891 892class getVOP3PModPat<VOPProfile P, SDPatternOperator node, bit HasExplicitClamp, 893 bit IsDOT = 0, 894 ComplexPattern SrcPat = !if(IsDOT, VOP3PModsDOT, VOP3PMods)> { 895 dag src0_dag = (P.Src0VT (SrcPat P.Src0VT:$src0, i32:$src0_modifiers)); 896 dag src1_dag = (P.Src1VT (SrcPat P.Src1VT:$src1, i32:$src1_modifiers)); 897 dag src2_dag = (P.Src2VT (SrcPat P.Src2VT:$src2, i32:$src2_modifiers)); 898 dag clamp_dag = (i1 timm:$clamp); 899 900 list<dag> ret3 = [(set P.DstVT:$vdst, 901 !if(HasExplicitClamp, 902 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, src2_dag, clamp_dag), 903 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, src2_dag)))]; 904 905 list<dag> ret2 = [(set P.DstVT:$vdst, 906 !if(HasExplicitClamp, 907 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, clamp_dag), 908 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag)))]; 909 910 list<dag> ret1 = [(set P.DstVT:$vdst, 911 !if(HasExplicitClamp, 912 (DivergentFragOrOp<node, P>.ret src0_dag, clamp_dag), 913 (DivergentFragOrOp<node, P>.ret src0_dag)))]; 914 915 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 916 !if(!eq(P.NumSrcArgs, 2), ret2, 917 ret1)); 918} 919 920class getVOP3OpSelPat<VOPProfile P, SDPatternOperator node> { 921 list<dag> ret3 = [(set P.DstVT:$vdst, 922 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)), 923 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)), 924 (P.Src2VT (VOP3OpSel P.Src2VT:$src2, i32:$src2_modifiers))))]; 925 926 list<dag> ret2 = [(set P.DstVT:$vdst, 927 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)), 928 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))]; 929 930 list<dag> ret1 = [(set P.DstVT:$vdst, 931 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))))]; 932 933 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 934 !if(!eq(P.NumSrcArgs, 2), ret2, 935 ret1)); 936} 937 938class getVOP3OpSelModPat<VOPProfile P, SDPatternOperator node> { 939 list<dag> ret3 = [(set P.DstVT:$vdst, 940 (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers), 941 (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 942 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)), 943 (P.Src2VT (VOP3OpSelMods P.Src2VT:$src2, i32:$src2_modifiers))))]; 944 945 list<dag> ret2 = [(set P.DstVT:$vdst, 946 (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers)), 947 (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 948 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))]; 949 950 list<dag> ret1 = [(set P.DstVT:$vdst, 951 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))))]; 952 953 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 954 !if(!eq(P.NumSrcArgs, 2), ret2, 955 ret1)); 956} 957 958class getVOP3FromVOP2Pat<VOPProfile P, SDPatternOperator node> { 959 list<dag> ret = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]; 960} 961// In VOP1, we can have clamp and omod even if !HasModifiers 962class getVOP3Pat<VOPProfile P, SDPatternOperator node> { 963 dag src0 = 964 !if(P.HasOMod, 965 !if(P.HasClamp, 966 (VOP3Mods0 P.Src0VT:$src0, i1:$clamp, i32:$omod), 967 (VOP3Mods0 P.Src0VT:$src0, i32:$omod)), // impossible? 968 !if(P.HasClamp, 969 (VOP3Mods0 P.Src0VT:$src0, i1:$clamp), 970 (VOP3Mods0 P.Src0VT:$src0)) 971 ); 972 list<dag> ret3 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), P.Src1VT:$src1, P.Src2VT:$src2))]; 973 974 list<dag> ret2 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), P.Src1VT:$src1))]; 975 976 list<dag> ret1 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))]; 977 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 978 !if(!eq(P.NumSrcArgs, 2), ret2, 979 ret1)); 980} 981 982class getVOP3ClampPat<VOPProfile P, SDPatternOperator node> { 983 list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i1:$clamp))]; 984 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))]; 985 list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, i1:$clamp))]; 986 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 987 !if(!eq(P.NumSrcArgs, 2), ret2, 988 ret1)); 989} 990 991class getVOP3MAIPat<VOPProfile P, SDPatternOperator node> { 992 list<dag> ret = !if(!eq(P.Src0VT, P.Src1VT), 993 // mfma 994 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, 995 timm:$cbsz, timm:$abid, timm:$blgp))], 996 // smfmac 997 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i32:$idx, 998 timm:$cbsz, timm:$abid))]); 999} 1000 1001class VOP3Features<bit Clamp, bit OpSel, bit Packed, bit MAI> { 1002 bit HasClamp = Clamp; 1003 bit HasOpSel = OpSel; 1004 bit IsPacked = Packed; 1005 bit IsMAI = MAI; 1006} 1007 1008def VOP3_REGULAR : VOP3Features<0, 0, 0, 0>; 1009def VOP3_CLAMP : VOP3Features<1, 0, 0, 0>; 1010def VOP3_OPSEL : VOP3Features<1, 1, 0, 0>; 1011def VOP3_PACKED : VOP3Features<1, 1, 1, 0>; 1012def VOP3_MAI : VOP3Features<0, 0, 0, 1>; 1013 1014class VOP3_Profile_Base<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOPProfile<P.ArgVT> { 1015 1016 let HasClamp = !if(Features.HasClamp, 1, P.HasClamp); 1017 let HasOpSel = !if(Features.HasOpSel, 1, P.HasOpSel); 1018 let IsMAI = !if(Features.IsMAI, 1, P.IsMAI); 1019 let IsPacked = !if(Features.IsPacked, 1, P.IsPacked); 1020 1021 let HasModifiers = !if(Features.IsMAI, 0, !or(Features.IsPacked, P.HasModifiers)); 1022} 1023 1024class VOP3_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOP3_Profile_Base<P, Features> { 1025 let IsSingle = 1; 1026 1027} 1028 1029// consistently gives instructions a _e64 suffix 1030multiclass VOP3Inst_Pseudo_Wrapper<string opName, VOPProfile P, list<dag> pattern = [], bit VOP3Only = 0> { 1031 def _e64 : VOP3_Pseudo<opName, P, pattern, VOP3Only>; 1032} 1033 1034class VOP3InstBase<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit IsVOP2 = 0> : 1035 VOP3_Pseudo<OpName, P, 1036 !if(P.HasOpSel, 1037 !if(P.HasModifiers, 1038 getVOP3OpSelModPat<P, node>.ret, 1039 getVOP3OpSelPat<P, node>.ret), 1040 !if(P.HasModifiers, 1041 getVOP3ModPat<P, node>.ret, 1042 !if(IsVOP2, 1043 getVOP3FromVOP2Pat<P, node>.ret, 1044 !if(P.HasIntClamp, 1045 getVOP3ClampPat<P, node>.ret, 1046 !if (P.IsMAI, 1047 getVOP3MAIPat<P, node>.ret, 1048 getVOP3Pat<P, node>.ret))))), 1049 0, P.HasOpSel> { 1050 1051 let IntClamp = P.HasIntClamp; 1052 let AsmMatchConverter = 1053 !if(P.HasOpSel, 1054 "cvtVOP3OpSel", 1055 !if(!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), 1056 "cvtVOP3", 1057 "")); 1058} 1059 1060multiclass VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> { 1061 def _e64 : VOP3InstBase<OpName, P, node>; 1062} 1063 1064//===----------------------------------------------------------------------===// 1065// VOP3 GFX11 1066//===----------------------------------------------------------------------===// 1067 1068let AssemblerPredicate = isGFX11Only, 1069 DecoderNamespace = "GFX11" in { 1070 multiclass VOP3_Real_Base_gfx11<bits<10> op, string opName = NAME, 1071 bit isSingle = 0> { 1072 defvar ps = !cast<VOP_Pseudo>(opName#"_e64"); 1073 let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in { 1074 foreach _ = BoolToList<ps.Pfl.HasOpSel>.ret in 1075 def _e64_gfx11 : 1076 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1077 VOP3OpSel_gfx11<op, ps.Pfl>; 1078 foreach _ = BoolToList<!not(ps.Pfl.HasOpSel)>.ret in 1079 def _e64_gfx11 : 1080 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1081 VOP3e_gfx11<op, ps.Pfl>; 1082 } 1083 } 1084 multiclass VOP3_Real_with_name_gfx11<bits<10> op, string opName, 1085 string asmName, bit isSingle = 0> { 1086 defvar ps = !cast<VOP_Pseudo>(opName#"_e64"); 1087 let AsmString = asmName # ps.AsmOperands, 1088 IsSingle = !or(isSingle, ps.Pfl.IsSingle) in { 1089 foreach _ = BoolToList<ps.Pfl.HasOpSel>.ret in 1090 def _e64_gfx11 : 1091 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1092 VOP3OpSel_gfx11<op, ps.Pfl>, 1093 MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX11Plus]>; 1094 foreach _ = BoolToList<!not(ps.Pfl.HasOpSel)>.ret in 1095 def _e64_gfx11 : 1096 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1097 VOP3e_gfx11<op, ps.Pfl>, 1098 MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX11Plus]>; 1099 } 1100 } 1101 // for READLANE/WRITELANE 1102 multiclass VOP3_Real_No_Suffix_gfx11<bits<10> op, string opName = NAME> { 1103 defvar ps = !cast<VOP_Pseudo>(opName); 1104 def _e64_gfx11 : 1105 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1106 VOP3e_gfx11<op, ps.Pfl>; 1107 } 1108 multiclass VOP3be_Real_gfx11<bits<10> op, string opName, string asmName, 1109 bit isSingle = 0> { 1110 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1111 let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in 1112 def _e64_gfx11 : 1113 VOP3_Real<ps, SIEncodingFamily.GFX11, asmName>, 1114 VOP3be_gfx11<op, ps.Pfl> ; 1115 } 1116} // End AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" 1117 1118// VOP1 and VOP2 depend on these triple defs 1119multiclass VOP3_Realtriple_gfx11<bits<10> op, 1120 bit isSingle = 0, string opName = NAME> : 1121 VOP3_Real_Base_gfx11<op, opName, isSingle>; 1122 1123multiclass VOP3Only_Realtriple_gfx11<bits<10> op> : 1124 VOP3_Realtriple_gfx11<op, 1>; 1125 1126multiclass VOP3_Realtriple_with_name_gfx11<bits<10> op, string opName, 1127 string asmName, bit isSingle = 0> : 1128 VOP3_Real_with_name_gfx11<op, opName, asmName, isSingle>; 1129 1130multiclass VOP3Only_Realtriple_with_name_gfx11<bits<10> op, string opName, 1131 string asmName> : 1132 VOP3_Realtriple_with_name_gfx11<op, opName, asmName, 1>; 1133 1134multiclass VOP3be_Realtriple_gfx11< 1135 bits<10> op, bit isSingle = 0, string opName = NAME, 1136 string asmName = !cast<VOP_Pseudo>(opName#"_e64").Mnemonic> : 1137 VOP3be_Real_gfx11<op, opName, asmName, isSingle>; 1138 1139multiclass VOP3beOnly_Realtriple_gfx11<bits<10> op> : 1140 VOP3be_Realtriple_gfx11<op, 1>; 1141 1142include "VOPCInstructions.td" 1143include "VOP1Instructions.td" 1144include "VOP2Instructions.td" 1145include "VOP3Instructions.td" 1146include "VOP3PInstructions.td" 1147 1148 1149class VOPInfoTable <string Format> : GenericTable { 1150 let FilterClass = Format # "_Real"; 1151 let CppTypeName = "VOPInfo"; 1152 let Fields = ["Opcode", "IsSingle"]; 1153 1154 let PrimaryKey = ["Opcode"]; 1155 let PrimaryKeyName = "get" # Format # "OpcodeHelper"; 1156} 1157 1158def VOP1InfoTable : VOPInfoTable<"VOP1">; 1159def VOP2InfoTable : VOPInfoTable<"VOP2">; 1160def VOP3InfoTable : VOPInfoTable<"VOP3">; 1161