1//===-- VOPInstructions.td - Vector Instruction Definitions ---------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// dummies for outer let 10class LetDummies { 11 bit TRANS; 12 bit ReadsModeReg; 13 bit mayRaiseFPException; 14 bit isCommutable; 15 bit isConvertibleToThreeAddress; 16 bit isMoveImm; 17 bit isReMaterializable; 18 bit isAsCheapAsAMove; 19 bit VOPAsmPrefer32Bit; 20 bit FPDPRounding; 21 Predicate SubtargetPredicate; 22 string Constraints; 23 string DisableEncoding; 24 list<SchedReadWrite> SchedRW; 25 list<Register> Uses; 26 list<Register> Defs; 27} 28 29class VOP <string opName> { 30 string OpName = opName; 31} 32 33// First 13 insts from VOPDY are also VOPDX. DOT2ACC_F32_BF16 is omitted 34defvar VOPDX_Max_Index = 12; 35 36class VOPD_Component<bits<5> OpIn, string vOPDName> { 37 Instruction BaseVOP = !cast<Instruction>(NAME); 38 string VOPDName = "v_dual_" # !substr(vOPDName, 2); 39 bits<5> VOPDOp = OpIn; 40 bit CanBeVOPDX = !le(VOPDOp, VOPDX_Max_Index); 41} 42 43class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> : 44 InstSI <outs, ins, asm, pattern> { 45 46 let mayLoad = 0; 47 let mayStore = 0; 48 let hasSideEffects = 0; 49 let UseNamedOperandTable = 1; 50 let VALU = 1; 51 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 52} 53 54class VOP_Pseudo <string opName, string suffix, VOPProfile P, dag outs, dag ins, 55 string asm, list<dag> pattern> : 56 InstSI <outs, ins, asm, pattern>, 57 VOP <opName>, 58 SIMCInstr <opName#suffix, SIEncodingFamily.NONE> { 59 let isPseudo = 1; 60 let isCodeGenOnly = 1; 61 let UseNamedOperandTable = 1; 62 63 string Mnemonic = opName; 64 VOPProfile Pfl = P; 65 66 string AsmOperands; 67} 68 69class VOP3Common <dag outs, dag ins, string asm = "", 70 list<dag> pattern = [], bit HasMods = 0> : 71 VOPAnyCommon <outs, ins, asm, pattern> { 72 73 // Using complex patterns gives VOP3 patterns a very high complexity rating, 74 // but standalone patterns are almost always preferred, so we need to adjust the 75 // priority lower. The goal is to use a high number to reduce complexity to 76 // zero (or less than zero). 77 let AddedComplexity = -1000; 78 79 let VOP3 = 1; 80 81 let AsmVariantName = AMDGPUAsmVariants.VOP3; 82 let AsmMatchConverter = !if(HasMods, "cvtVOP3", ""); 83 84 let isCodeGenOnly = 0; 85 86 int Size = 8; 87 88 // Because SGPRs may be allowed if there are multiple operands, we 89 // need a post-isel hook to insert copies in order to avoid 90 // violating constant bus requirements. 91 let hasPostISelHook = 1; 92} 93 94class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [], 95 bit isVOP3P = 0, bit isVop3OpSel = 0> : 96 VOP_Pseudo <opName, "_e64", P, P.Outs64, 97 !if(isVop3OpSel, 98 P.InsVOP3OpSel, 99 !if(!and(isVOP3P, P.IsPacked), P.InsVOP3P, P.Ins64)), 100 "", pattern> { 101 102 let VOP3_OPSEL = isVop3OpSel; 103 let IsPacked = P.IsPacked; 104 let IsMAI = P.IsMAI; 105 106 let AsmOperands = !if(isVop3OpSel, 107 P.AsmVOP3OpSel, 108 !if(!and(isVOP3P, P.IsPacked), P.AsmVOP3P, P.Asm64)); 109 110 let Size = 8; 111 let mayLoad = 0; 112 let mayStore = 0; 113 let hasSideEffects = 0; 114 115 // Because SGPRs may be allowed if there are multiple operands, we 116 // need a post-isel hook to insert copies in order to avoid 117 // violating constant bus requirements. 118 let hasPostISelHook = 1; 119 120 // Using complex patterns gives VOP3 patterns a very high complexity rating, 121 // but standalone patterns are almost always preferred, so we need to adjust the 122 // priority lower. The goal is to use a high number to reduce complexity to 123 // zero (or less than zero). 124 let AddedComplexity = -1000; 125 126 let VOP3 = 1; 127 let VALU = 1; 128 let FPClamp = P.HasFPClamp; 129 let IntClamp = P.HasIntClamp; 130 let ClampLo = P.HasClampLo; 131 let ClampHi = P.HasClampHi; 132 133 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 134 135 let mayRaiseFPException = ReadsModeReg; 136 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 137 138 let AsmVariantName = AMDGPUAsmVariants.VOP3; 139 let AsmMatchConverter = 140 !if(isVOP3P, 141 "cvtVOP3P", 142 !if(!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), 143 "cvtVOP3", 144 "")); 145} 146 147class VOP3P_Pseudo <string opName, VOPProfile P, list<dag> pattern = []> : 148 VOP3_Pseudo<opName, P, pattern, 1> { 149 let VOP3P = 1; 150} 151 152class VOP_Real<VOP_Pseudo ps> { 153 Instruction Opcode = !cast<Instruction>(NAME); 154 bit IsSingle = ps.Pfl.IsSingle; 155} 156 157class VOP3_Real <VOP_Pseudo ps, int EncodingFamily, string asm_name = ps.Mnemonic> : 158 VOP_Real <ps>, 159 InstSI <ps.OutOperandList, ps.InOperandList, asm_name # ps.AsmOperands, []>, 160 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 161 162 let VALU = 1; 163 let VOP3 = 1; 164 let isPseudo = 0; 165 let isCodeGenOnly = 0; 166 let UseNamedOperandTable = 1; 167 168 // copy relevant pseudo op flags 169 let SubtargetPredicate = ps.SubtargetPredicate; 170 let OtherPredicates = ps.OtherPredicates; 171 let AsmMatchConverter = ps.AsmMatchConverter; 172 let AsmVariantName = ps.AsmVariantName; 173 let Constraints = ps.Constraints; 174 let DisableEncoding = ps.DisableEncoding; 175 let TSFlags = ps.TSFlags; 176 let UseNamedOperandTable = ps.UseNamedOperandTable; 177 let Uses = ps.Uses; 178 let Defs = ps.Defs; 179 let SchedRW = ps.SchedRW; 180 let mayLoad = ps.mayLoad; 181 let mayStore = ps.mayStore; 182 let TRANS = ps.TRANS; 183 184 VOPProfile Pfl = ps.Pfl; 185} 186 187// XXX - Is there any reason to distinguish this from regular VOP3 188// here? 189class VOP3P_Real<VOP_Pseudo ps, int EncodingFamily, string asm_name = ps.Mnemonic> : 190 VOP3_Real<ps, EncodingFamily, asm_name>; 191 192class VOP3a<VOPProfile P> : Enc64 { 193 bits<4> src0_modifiers; 194 bits<9> src0; 195 bits<3> src1_modifiers; 196 bits<9> src1; 197 bits<3> src2_modifiers; 198 bits<9> src2; 199 bits<1> clamp; 200 bits<2> omod; 201 202 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 203 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); 204 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); 205 206 let Inst{31-26} = 0x34; //encoding 207 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 208 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 209 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 210 let Inst{60-59} = !if(P.HasOMod, omod, 0); 211 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 212 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 213 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 214} 215 216class VOP3a_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a<p> { 217 let Inst{11} = !if(p.HasClamp, clamp{0}, 0); 218 let Inst{25-17} = op; 219} 220 221class VOP3a_gfx10<bits<10> op, VOPProfile p> : VOP3a<p> { 222 let Inst{15} = !if(p.HasClamp, clamp{0}, 0); 223 let Inst{25-16} = op; 224 let Inst{31-26} = 0x35; 225} 226 227class VOP3a_gfx11<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p>; 228 229class VOP3a_vi <bits<10> op, VOPProfile P> : VOP3a<P> { 230 let Inst{25-16} = op; 231 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 232} 233 234class VOP3e_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a_gfx6_gfx7<op, p> { 235 bits<8> vdst; 236 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0); 237} 238 239class VOP3e_gfx10<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p> { 240 bits<8> vdst; 241 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0); 242} 243 244class VOP3e_gfx11<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p>; 245 246class VOP3e_vi <bits<10> op, VOPProfile P> : VOP3a_vi <op, P> { 247 bits<8> vdst; 248 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0); 249} 250 251class VOP3OpSel_gfx9 <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> { 252 let Inst{11} = !if(P.HasSrc0, src0_modifiers{2}, 0); 253 let Inst{12} = !if(P.HasSrc1, src1_modifiers{2}, 0); 254 let Inst{13} = !if(P.HasSrc2, src2_modifiers{2}, 0); 255 let Inst{14} = !if(P.HasDst, src0_modifiers{3}, 0); 256} 257 258class VOP3OpSel_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> { 259 let Inst{11} = !if(p.HasSrc0, src0_modifiers{2}, 0); 260 let Inst{12} = !if(p.HasSrc1, src1_modifiers{2}, 0); 261 let Inst{13} = !if(p.HasSrc2, src2_modifiers{2}, 0); 262 let Inst{14} = !if(p.HasDst, src0_modifiers{3}, 0); 263} 264 265class VOP3OpSel_gfx11<bits<10> op, VOPProfile p> : VOP3OpSel_gfx10<op, p>; 266 267 268// NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa 269class VOP3Interp_vi <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> { 270 bits<2> attrchan; 271 bits<6> attr; 272 bits<1> high; 273 274 let Inst{8} = 0; // No modifiers for src0 275 let Inst{61} = 0; 276 277 let Inst{9} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 278 let Inst{62} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 279 280 let Inst{37-32} = attr; 281 let Inst{39-38} = attrchan; 282 let Inst{40} = !if(P.HasHigh, high, 0); 283 284 let Inst{49-41} = src0; 285} 286 287class VOP3Interp_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> { 288 bits<6> attr; 289 bits<2> attrchan; 290 bits<1> high; 291 292 let Inst{8} = 0; 293 let Inst{9} = !if(p.HasSrc0Mods, src0_modifiers{1}, 0); 294 let Inst{37-32} = attr; 295 let Inst{39-38} = attrchan; 296 let Inst{40} = !if(p.HasHigh, high, 0); 297 let Inst{49-41} = src0; 298 let Inst{61} = 0; 299 let Inst{62} = !if(p.HasSrc0Mods, src0_modifiers{0}, 0); 300} 301 302class VOP3Interp_gfx11<bits<10> op, VOPProfile p> : VOP3Interp_gfx10<op, p>; 303 304class VOP3be <VOPProfile P> : Enc64 { 305 bits<8> vdst; 306 bits<2> src0_modifiers; 307 bits<9> src0; 308 bits<2> src1_modifiers; 309 bits<9> src1; 310 bits<2> src2_modifiers; 311 bits<9> src2; 312 bits<7> sdst; 313 bits<2> omod; 314 315 let Inst{7-0} = vdst; 316 let Inst{14-8} = sdst; 317 let Inst{31-26} = 0x34; //encoding 318 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 319 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 320 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 321 let Inst{60-59} = !if(P.HasOMod, omod, 0); 322 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 323 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 324 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 325} 326 327class VOP3Pe <bits<7> op, VOPProfile P> : Enc64 { 328 bits<8> vdst; 329 bits<4> src0_modifiers; 330 bits<9> src0; 331 bits<4> src1_modifiers; 332 bits<9> src1; 333 bits<4> src2_modifiers; 334 bits<9> src2; 335 bits<1> clamp; 336 337 let Inst{7-0} = vdst; 338 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0 339 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // neg_hi src1 340 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); // neg_hi src2 341 342 let Inst{11} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{2}, 0); // op_sel(0) 343 let Inst{12} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{2}, 0); // op_sel(1) 344 let Inst{13} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{2}, 0); // op_sel(2) 345 346 let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, ?); // op_sel_hi(2) 347 348 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 349 350 let Inst{22-16} = op; 351 let Inst{31-23} = 0x1a7; //encoding 352 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 353 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 354 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 355 let Inst{59} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, ?); // op_sel_hi(0) 356 let Inst{60} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, ?); // op_sel_hi(1) 357 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // neg (lo) 358 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // neg (lo) 359 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo) 360} 361 362class VOP3Pe_MAI <bits<7> op, VOPProfile P, bit acc_cd = 0> : Enc64 { 363 bits<8> vdst; 364 bits<10> src0; 365 bits<10> src1; 366 bits<9> src2; 367 bits<3> blgp; 368 bits<3> cbsz; 369 bits<4> abid; 370 371 let Inst{7-0} = vdst; 372 373 let Inst{10-8} = !if(P.HasSrc1, cbsz, 0); 374 let Inst{14-11} = !if(P.HasSrc1, abid, 0); 375 376 let Inst{15} = acc_cd; 377 378 let Inst{22-16} = op; 379 let Inst{31-23} = 0x1a7; //encoding 380 let Inst{40-32} = !if(P.HasSrc0, src0{8-0}, 0); 381 let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, 0); 382 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 383 384 let Inst{59} = !if(P.HasSrc0, src0{9}, 0); // acc(0) 385 let Inst{60} = !if(P.HasSrc1, src1{9}, 0); // acc(1) 386 387 let Inst{63-61} = !if(P.HasSrc1, blgp, 0); 388} 389 390class VOP3Pe_SMFMAC <bits<7> op> : Enc64 { 391 bits<10> vdst; // VGPR or AGPR, but not SGPR. vdst{8} is not encoded in the instruction. 392 bits<10> src0; 393 bits<10> src1; 394 bits<9> idx; 395 bits<3> blgp; 396 bits<3> cbsz; 397 bits<4> abid; 398 399 let blgp = 0; 400 401 let Inst{7-0} = vdst{7-0}; 402 403 let Inst{10-8} = cbsz; 404 let Inst{14-11} = abid; 405 406 let Inst{15} = vdst{9}; // acc(vdst) 407 408 let Inst{22-16} = op; 409 let Inst{31-23} = 0x1a7; // encoding 410 let Inst{40-32} = src0{8-0}; 411 let Inst{49-41} = src1{8-0}; 412 let Inst{58-50} = idx; 413 414 let Inst{59} = src0{9}; // acc(0) 415 let Inst{60} = src1{9}; // acc(1) 416 417 let Inst{63-61} = blgp; 418} 419 420class VOP3Pe_gfx10 <bits<7> op, VOPProfile P> : VOP3Pe<op, P> { 421 let Inst{31-23} = 0x198; //encoding 422} 423 424class VOP3Pe_gfx11<bits<7> op, VOPProfile P> : VOP3Pe_gfx10<op, P>; 425 426class VOP3be_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3be<p> { 427 let Inst{25-17} = op; 428} 429 430class VOP3be_gfx10<bits<10> op, VOPProfile p> : VOP3be<p> { 431 bits<1> clamp; 432 let Inst{15} = !if(p.HasClamp, clamp{0}, 0); 433 let Inst{25-16} = op; 434 let Inst{31-26} = 0x35; 435} 436 437class VOP3be_gfx11<bits<10> op, VOPProfile p> : VOP3be_gfx10<op, p>; 438 439class VOP3be_vi <bits<10> op, VOPProfile P> : VOP3be<P> { 440 bits<1> clamp; 441 let Inst{25-16} = op; 442 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 443} 444 445def SDWA { 446 // sdwa_sel 447 int BYTE_0 = 0; 448 int BYTE_1 = 1; 449 int BYTE_2 = 2; 450 int BYTE_3 = 3; 451 int WORD_0 = 4; 452 int WORD_1 = 5; 453 int DWORD = 6; 454 455 // dst_unused 456 int UNUSED_PAD = 0; 457 int UNUSED_SEXT = 1; 458 int UNUSED_PRESERVE = 2; 459} 460 461class VOP_SDWAe<VOPProfile P> : Enc64 { 462 bits<8> src0; 463 bits<3> src0_sel; 464 bits<2> src0_modifiers; // float: {abs,neg}, int {sext} 465 bits<3> src1_sel; 466 bits<2> src1_modifiers; 467 bits<3> dst_sel; 468 bits<2> dst_unused; 469 bits<1> clamp; 470 471 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 472 let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?); 473 let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?); 474 let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); 475 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0); 476 let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0); 477 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0); 478 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0); 479 let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0); 480 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0); 481} 482 483// GFX9 adds two features to SDWA: 484// 1. Add 3 fields to the SDWA microcode word: S0, S1 and OMOD. 485// a. S0 and S1 indicate that source 0 and 1 respectively are SGPRs rather 486// than VGPRs (at most 1 can be an SGPR); 487// b. OMOD is the standard output modifier (result *2, *4, /2) 488// 2. Add a new version of the SDWA microcode word for VOPC: SDWAB. This 489// replaces OMOD and the dest fields with SD and SDST (SGPR destination) 490// field. 491// a. When SD=1, the SDST is used as the destination for the compare result; 492// b. When SD=0, VCC is used. 493// 494// In GFX9, V_MAC_F16, V_MAC_F32 opcodes cannot be used with SDWA 495 496// gfx9 SDWA basic encoding 497class VOP_SDWA9e<VOPProfile P> : Enc64 { 498 bits<9> src0; // {src0_sgpr{0}, src0{7-0}} 499 bits<3> src0_sel; 500 bits<2> src0_modifiers; // float: {abs,neg}, int {sext} 501 bits<3> src1_sel; 502 bits<2> src1_modifiers; 503 bits<1> src1_sgpr; 504 505 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 506 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0); 507 let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0); 508 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0); 509 let Inst{55} = !if(P.HasSrc0, src0{8}, 0); 510 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0); 511 let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0); 512 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0); 513 let Inst{63} = 0; // src1_sgpr - should be specified in subclass 514} 515 516// gfx9 SDWA-A 517class VOP_SDWA9Ae<VOPProfile P> : VOP_SDWA9e<P> { 518 bits<3> dst_sel; 519 bits<2> dst_unused; 520 bits<1> clamp; 521 bits<2> omod; 522 523 let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?); 524 let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?); 525 let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); 526 let Inst{47-46} = !if(P.HasSDWAOMod, omod{1-0}, 0); 527} 528 529// gfx9 SDWA-B 530class VOP_SDWA9Be<VOPProfile P> : VOP_SDWA9e<P> { 531 bits<8> sdst; // {vcc_sdst{0}, sdst{6-0}} 532 533 let Inst{46-40} = !if(P.EmitDst, sdst{6-0}, ?); 534 let Inst{47} = !if(P.EmitDst, sdst{7}, 0); 535} 536 537class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> : 538 InstSI <P.OutsSDWA, P.InsSDWA, "", pattern>, 539 VOP <opName>, 540 SIMCInstr <opName#"_sdwa", SIEncodingFamily.NONE> { 541 542 let isPseudo = 1; 543 let isCodeGenOnly = 1; 544 let UseNamedOperandTable = 1; 545 546 string Mnemonic = opName; 547 string AsmOperands = P.AsmSDWA; 548 string AsmOperands9 = P.AsmSDWA9; 549 550 let Size = 8; 551 let mayLoad = 0; 552 let mayStore = 0; 553 let hasSideEffects = 0; 554 555 let VALU = 1; 556 let SDWA = 1; 557 558 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 559 560 let mayRaiseFPException = ReadsModeReg; 561 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 562 563 let SubtargetPredicate = HasSDWA; 564 let AssemblerPredicate = HasSDWA; 565 let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA, 566 AMDGPUAsmVariants.Disable); 567 let DecoderNamespace = "SDWA"; 568 569 VOPProfile Pfl = P; 570} 571 572class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> : 573 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 574 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA> { 575 576 let VALU = 1; 577 let SDWA = 1; 578 let isPseudo = 0; 579 let isCodeGenOnly = 0; 580 581 let Defs = ps.Defs; 582 let Uses = ps.Uses; 583 let hasSideEffects = ps.hasSideEffects; 584 585 let Constraints = ps.Constraints; 586 let DisableEncoding = ps.DisableEncoding; 587 588 // Copy relevant pseudo op flags 589 let SubtargetPredicate = ps.SubtargetPredicate; 590 let AssemblerPredicate = ps.AssemblerPredicate; 591 let AsmMatchConverter = ps.AsmMatchConverter; 592 let AsmVariantName = ps.AsmVariantName; 593 let UseNamedOperandTable = ps.UseNamedOperandTable; 594 let DecoderNamespace = ps.DecoderNamespace; 595 let Constraints = ps.Constraints; 596 let DisableEncoding = ps.DisableEncoding; 597 let TSFlags = ps.TSFlags; 598 let SchedRW = ps.SchedRW; 599 let mayLoad = ps.mayLoad; 600 let mayStore = ps.mayStore; 601 let TRANS = ps.TRANS; 602} 603 604class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> : 605 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands9, []> { 606 607 let VALU = 1; 608 let SDWA = 1; 609 let isPseudo = 0; 610 let isCodeGenOnly = 0; 611 612 let Defs = ps.Defs; 613 let Uses = ps.Uses; 614 let hasSideEffects = ps.hasSideEffects; 615 616 let Constraints = ps.Constraints; 617 let DisableEncoding = ps.DisableEncoding; 618 619 let SubtargetPredicate = HasSDWA9; 620 let AssemblerPredicate = HasSDWA9; 621 let AsmVariantName = !if(ps.Pfl.HasExtSDWA9, AMDGPUAsmVariants.SDWA9, 622 AMDGPUAsmVariants.Disable); 623 let DecoderNamespace = "SDWA9"; 624 625 // Copy relevant pseudo op flags 626 let AsmMatchConverter = ps.AsmMatchConverter; 627 let UseNamedOperandTable = ps.UseNamedOperandTable; 628 let Constraints = ps.Constraints; 629 let DisableEncoding = ps.DisableEncoding; 630 let TSFlags = ps.TSFlags; 631 let SchedRW = ps.SchedRW; 632 let mayLoad = ps.mayLoad; 633 let mayStore = ps.mayStore; 634 let TRANS = ps.TRANS; 635} 636 637class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> : 638 Base_VOP_SDWA9_Real <ps >, 639 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA9>; 640 641class Base_VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : Base_VOP_SDWA9_Real<ps> { 642 let SubtargetPredicate = HasSDWA10; 643 let AssemblerPredicate = HasSDWA10; 644 let DecoderNamespace = "SDWA10"; 645} 646 647class VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : 648 Base_VOP_SDWA10_Real<ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SDWA10>; 649 650class VOP_DPPe<VOPProfile P, bit IsDPP16=0> : Enc64 { 651 bits<2> src0_modifiers; 652 bits<8> src0; 653 bits<2> src1_modifiers; 654 bits<9> dpp_ctrl; 655 bits<1> bound_ctrl; 656 bits<4> bank_mask; 657 bits<4> row_mask; 658 bit fi; 659 660 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 661 let Inst{48-40} = dpp_ctrl; 662 let Inst{50} = !if(IsDPP16, fi, ?); 663 let Inst{51} = bound_ctrl; 664 let Inst{52} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg 665 let Inst{53} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // src0_abs 666 let Inst{54} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg 667 let Inst{55} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // src1_abs 668 let Inst{59-56} = bank_mask; 669 let Inst{63-60} = row_mask; 670} 671 672class VOP3_DPPe_Fields_Base { 673 bits<9> dpp_ctrl; 674 bits<1> bound_ctrl; 675 bits<4> bank_mask; 676 bits<4> row_mask; 677 bit fi; 678} 679class VOP3_DPPe_Fields : VOP3_DPPe_Fields_Base { 680 bits<8> src0; 681} 682 683// Common refers to common between DPP and DPP8 684class VOP3_DPPe_Common_Base<bits<10> op, VOPProfile P> : Enc96 { 685 bits<4> src0_modifiers; 686 bits<3> src1_modifiers; 687 bits<3> src2_modifiers; 688 bits<1> clamp; 689 bits<2> omod; 690 691 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 692 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); 693 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); 694 // OPSEL must be set such that the low result only uses low inputs, and the high result only uses high inputs. 695 let Inst{11} = !if(P.HasOpSel,!if(P.HasSrc0Mods, src0_modifiers{2}, 0),?); 696 let Inst{12} = !if(P.HasOpSel,!if(P.HasSrc1Mods, src1_modifiers{2}, 0),?); 697 let Inst{13} = !if(P.HasOpSel,!if(P.HasSrc2Mods, src2_modifiers{2}, 0),?); 698 let Inst{14} = !if(P.HasOpSel,!if(P.HasSrc0Mods, src0_modifiers{3}, 0),?); 699 let Inst{15} = !if(P.HasClamp, clamp, 0); 700 let Inst{25-16} = op; 701 let Inst{31-26} = 0x35; 702 703 let Inst{60-59} = !if(P.HasOMod, omod, 0); 704 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 705 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 706 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 707} 708 709class VOP3_DPPe_Common<bits<10> op, VOPProfile P> : VOP3_DPPe_Common_Base<op, P> { 710 bits<8> vdst; 711 bits<9> src1; 712 bits<9> src2; 713 714 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0); 715 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 716 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 717} 718 719class VOP3P_DPPe_Common_Base<bits<7> op, VOPProfile P> : Enc96 { 720 bits<4> src0_modifiers; 721 bits<4> src1_modifiers; 722 bits<4> src2_modifiers; 723 bits<1> clamp; 724 725 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0 726 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // neg_hi src1 727 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); // neg_hi src2 728 let Inst{11} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{2}, 0); // op_sel(0) 729 let Inst{12} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{2}, 0); // op_sel(1) 730 let Inst{13} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{2}, 0); // op_sel(2) 731 let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, ?); // op_sel_hi(2) 732 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 733 let Inst{22-16} = op; 734 let Inst{31-23} = 0x198; // encoding 735 let Inst{59} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, ?); // op_sel_hi(0) 736 let Inst{60} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, ?); // op_sel_hi(1) 737 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // neg (lo) 738 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // neg (lo) 739 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo) 740} 741 742class VOP3P_DPPe_Common<bits<7> op, VOPProfile P> : VOP3P_DPPe_Common_Base<op, P> { 743 bits<8> vdst; 744 bits<9> src1; 745 bits<9> src2; 746 747 let Inst{7-0} = vdst; 748 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 749 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 750} 751 752class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[], 753 dag Ins = P.InsDPP, string asmOps = P.AsmDPP> : 754 InstSI <P.OutsDPP, Ins, OpName#asmOps, pattern>, 755 VOP <OpName>, 756 SIMCInstr <OpName#"_dpp", SIEncodingFamily.NONE> { 757 758 let isPseudo = 1; 759 let isCodeGenOnly = 1; 760 761 let mayLoad = 0; 762 let mayStore = 0; 763 let hasSideEffects = 0; 764 let UseNamedOperandTable = 1; 765 766 let VALU = 1; 767 let DPP = 1; 768 let Size = 8; 769 770 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 771 772 let mayRaiseFPException = ReadsModeReg; 773 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 774 let isConvergent = 1; 775 776 string Mnemonic = OpName; 777 string AsmOperands = asmOps; 778 779 let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", ""); 780 let SubtargetPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 781 let AssemblerPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 782 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, 783 AMDGPUAsmVariants.Disable); 784 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 785 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 786 let DecoderNamespace = "DPP"; 787 788 VOPProfile Pfl = P; 789} 790 791class VOP3_DPP_Pseudo <string OpName, VOPProfile P> : 792 VOP_DPP_Pseudo <OpName, P, [], P.InsVOP3DPP, P.AsmVOP3DPP> { 793 let PseudoInstr = OpName#"_e64"#"_dpp"; 794 let OutOperandList = P.OutsVOP3DPP; 795 let Size = 12; 796 let VOP3 = 1; 797 let AsmMatchConverter = "cvtVOP3DPP"; 798 let AsmVariantName = !if(P.HasExtVOP3DPP, AMDGPUAsmVariants.VOP3_DPP, 799 AMDGPUAsmVariants.Disable); 800} 801 802class VOP_DPP_Real <VOP_DPP_Pseudo ps, int EncodingFamily> : 803 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 804 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 805 806 let VALU = 1; 807 let DPP = 1; 808 let isPseudo = 0; 809 let isCodeGenOnly = 0; 810 811 let Defs = ps.Defs; 812 let Uses = ps.Uses; 813 let hasSideEffects = ps.hasSideEffects; 814 815 let Constraints = ps.Constraints; 816 let DisableEncoding = ps.DisableEncoding; 817 818 // Copy relevant pseudo op flags 819 let isConvergent = ps.isConvergent; 820 let SubtargetPredicate = ps.SubtargetPredicate; 821 let AssemblerPredicate = ps.AssemblerPredicate; 822 let OtherPredicates = ps.OtherPredicates; 823 let AsmMatchConverter = ps.AsmMatchConverter; 824 let AsmVariantName = ps.AsmVariantName; 825 let UseNamedOperandTable = ps.UseNamedOperandTable; 826 let DecoderNamespace = ps.DecoderNamespace; 827 let Constraints = ps.Constraints; 828 let DisableEncoding = ps.DisableEncoding; 829 let TSFlags = ps.TSFlags; 830 let SchedRW = ps.SchedRW; 831 let mayLoad = ps.mayLoad; 832 let mayStore = ps.mayStore; 833 let TRANS = ps.TRANS; 834} 835 836class VOP_DPP_Base <string OpName, VOPProfile P, 837 dag InsDPP, 838 string AsmDPP > : 839 InstSI <P.OutsDPP, InsDPP, OpName#AsmDPP, []> { 840 841 let mayLoad = 0; 842 let mayStore = 0; 843 let hasSideEffects = 0; 844 let UseNamedOperandTable = 1; 845 846 let VALU = 1; 847 let DPP = 1; 848 let Size = 8; 849 850 let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", ""); 851 let SubtargetPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 852 let AssemblerPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 853 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, 854 AMDGPUAsmVariants.Disable); 855 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 856 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 857 let DecoderNamespace = "DPP"; 858} 859 860class VOP_DPP <string OpName, VOPProfile P, bit IsDPP16, 861 dag InsDPP = !if(IsDPP16, P.InsDPP16, P.InsDPP), 862 string AsmDPP = !if(IsDPP16, P.AsmDPP16, P.AsmDPP)> : 863 VOP_DPP_Base<OpName, P, InsDPP, AsmDPP>, VOP_DPPe<P, IsDPP16>; 864 865class VOP3_DPP_Base <string OpName, VOPProfile P, bit IsDPP16, 866 dag InsDPP = !if(IsDPP16, P.InsVOP3DPP16, P.InsVOP3DPP), 867 string AsmDPP = !if(IsDPP16, P.AsmVOP3DPP16, P.AsmVOP3DPP)> : 868 VOP_DPP_Base<OpName, P, InsDPP, AsmDPP> { 869 let OutOperandList = P.OutsVOP3DPP; 870 let AsmMatchConverter = "cvtVOP3DPP"; 871 let VOP3 = 1; 872 let AsmVariantName = !if(P.HasExtVOP3DPP, AMDGPUAsmVariants.VOP3_DPP, 873 AMDGPUAsmVariants.Disable); 874 let Size = 12; 875} 876 877class VOP3_DPP <bits<10> op, string OpName, VOPProfile P, bit IsDPP16, 878 dag InsDPP = !if(IsDPP16, P.InsVOP3DPP16, P.InsVOP3DPP), 879 string AsmDPP = !if(IsDPP16, P.AsmVOP3DPP16, P.AsmVOP3DPP)> : 880 VOP3_DPP_Base<OpName, P, IsDPP16, InsDPP, AsmDPP>, VOP3_DPPe_Common<op, P>, 881 VOP3_DPPe_Fields { 882 883 let Inst{40-32} = 0xfa; 884 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 885 let Inst{80-72} = dpp_ctrl; 886 let Inst{82} = !if(IsDPP16, fi, ?); 887 let Inst{83} = bound_ctrl; 888 889 // Inst{87-84} ignored by hw 890 let Inst{91-88} = bank_mask; 891 let Inst{95-92} = row_mask; 892} 893 894class VOP3P_DPP <bits<7> op, string OpName, VOPProfile P, bit IsDPP16, 895 dag InsDPP = !if(IsDPP16, P.InsVOP3DPP16, P.InsVOP3DPP), 896 string AsmDPP = !if(IsDPP16, P.AsmVOP3DPP16, P.AsmVOP3DPP)> : 897 VOP3_DPP_Base<OpName, P, IsDPP16, InsDPP, AsmDPP>, VOP3P_DPPe_Common<op, P>, 898 VOP3_DPPe_Fields { 899 900 let VOP3P = 1; 901 902 let Inst{40-32} = 0xfa; 903 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 904 let Inst{80-72} = dpp_ctrl; 905 let Inst{82} = !if(IsDPP16, fi, ?); 906 let Inst{83} = bound_ctrl; 907 908 // Inst{87-84} ignored by hw 909 let Inst{91-88} = bank_mask; 910 let Inst{95-92} = row_mask; 911} 912 913class VOP_DPP8e<VOPProfile P> : Enc64 { 914 bits<8> src0; 915 bits<24> dpp8; 916 bits<9> fi; 917 918 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 919 let Inst{63-40} = dpp8{23-0}; 920} 921 922class VOP3_DPP8e_Fields { 923 bits<8> src0; 924 bits<24> dpp8; 925 bits<9> fi; 926} 927 928class VOP_DPP8_Base<string OpName, VOPProfile P, dag InsDPP8 = P.InsDPP8, string AsmDPP8 = P.AsmDPP8> : 929 InstSI<P.OutsDPP8, InsDPP8, OpName#AsmDPP8, []> { 930 931 let mayLoad = 0; 932 let mayStore = 0; 933 let hasSideEffects = 0; 934 let UseNamedOperandTable = 1; 935 936 let VALU = 1; 937 let DPP = 1; 938 let Size = 8; 939 940 let AsmMatchConverter = "cvtDPP8"; 941 let SubtargetPredicate = HasDPP8; 942 let AssemblerPredicate = HasDPP8; 943 let AsmVariantName = AMDGPUAsmVariants.DPP; 944 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 945 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 946} 947 948class VOP_DPP8<string OpName, VOPProfile P> : 949 VOP_DPP8_Base<OpName, P>, VOP_DPP8e<P>; 950 951class VOP3_DPP8_Base<string OpName, VOPProfile P> : 952 VOP_DPP8_Base<OpName, P, P.InsVOP3DPP8, P.AsmVOP3DPP8> { 953 let OutOperandList = P.OutsVOP3DPP8; 954 let AsmMatchConverter = "cvtVOP3DPP8"; 955 let AsmVariantName = !if(P.HasExtVOP3DPP, AMDGPUAsmVariants.VOP3_DPP, 956 AMDGPUAsmVariants.Disable); 957 let VOP3 = 1; 958 let Size = 12; 959} 960 961 962class VOP3_DPP8<bits<10> op, string OpName, VOPProfile P> : 963 VOP3_DPP8_Base<OpName, P>, VOP3_DPPe_Common<op, P>, 964 VOP3_DPP8e_Fields { 965 966 let Inst{40-32} = fi; 967 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 968 let Inst{95-72} = dpp8{23-0}; 969} 970 971class VOP3P_DPP8<bits<7> op, string OpName, VOPProfile P> : 972 VOP3_DPP8_Base<OpName, P>, VOP3P_DPPe_Common<op, P>, 973 VOP3_DPP8e_Fields { 974 975 let VOP3P = 1; 976 let Inst{40-32} = fi; 977 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 978 let Inst{95-72} = dpp8{23-0}; 979} 980 981def DPP8Mode { 982 int FI_0 = 0xE9; 983 int FI_1 = 0xEA; 984} 985 986class getNumNodeArgs<SDPatternOperator Op> { 987 SDNode N = !cast<SDNode>(Op); 988 SDTypeProfile TP = N.TypeProfile; 989 int ret = TP.NumOperands; 990} 991 992class getDivergentFrag<SDPatternOperator Op> { 993 assert !or(!isa<SDNode>(Op), !isa<PatFrags>(Op)), "Expected SDNode or PatFrags"; 994 995 int NumSrcArgs = !if(!isa<SDNode>(Op), getNumNodeArgs<Op>.ret, 996 !size(!cast<PatFrags>(Op).Operands)); 997 PatFrag ret = PatFrag < 998 !if(!eq(NumSrcArgs, 1), 999 (ops node:$src0), 1000 !if(!eq(NumSrcArgs, 2), 1001 (ops node:$src0, node:$src1), 1002 (ops node:$src0, node:$src1, node:$src2))), 1003 !if(!eq(NumSrcArgs, 1), 1004 (Op $src0), 1005 !if(!eq(NumSrcArgs, 2), 1006 (Op $src0, $src1), 1007 (Op $src0, $src1, $src2))), 1008 [{ return N->isDivergent(); }] 1009 >; 1010} 1011 1012class VOPPatGen<SDPatternOperator Op, VOPProfile P> { 1013 PatFrag Operator = getDivergentFrag < Op >.ret; 1014 1015 dag Ins = !foreach(tmp, P.Ins32, !subst(ins, Operator, 1016 !subst(P.Src0RC32, P.Src0VT, 1017 !subst(P.Src1RC32, P.Src1VT, tmp)))); 1018 1019 dag Outs = !foreach(tmp, P.Outs32, !subst(outs, set, 1020 !subst(P.DstRC, P.DstVT, tmp))); 1021 1022 list<dag> ret = [!con(Outs, (set Ins))]; 1023} 1024 1025class DivergentUnaryFrag<SDPatternOperator Op> : PatFrag < 1026 (ops node:$src0), 1027 (Op $src0), 1028 [{ return N->isDivergent(); }]> { 1029 // This check is unnecessary as it's captured by the result register 1030 // bank constraint. 1031 // 1032 // FIXME: Should add a way for the emitter to recognize this is a 1033 // trivially true predicate to eliminate the check. 1034 let GISelPredicateCode = [{return true;}]; 1035} 1036 1037class VOPPatOrNull<SDPatternOperator Op, VOPProfile P> { 1038 list<dag> ret = !if(!ne(P.NeedPatGen,PatGenMode.NoPattern), VOPPatGen<Op, P>.ret, []); 1039} 1040 1041class DivergentFragOrOp<SDPatternOperator Op, VOPProfile P> { 1042 SDPatternOperator ret = !if(!eq(P.NeedPatGen,PatGenMode.Pattern), 1043 !if(!isa<SDNode>(Op), getDivergentFrag<Op>.ret, Op), Op); 1044} 1045 1046class getVSrcOp<ValueType vt> { 1047 RegisterOperand ret = !if(!eq(vt.Size, 32), VSrc_b32, VSrc_b16); 1048} 1049 1050// Class for binary integer operations with the clamp bit set for saturation 1051// TODO: Add sub with negated inline constant pattern. 1052class VOPBinOpClampPat<SDPatternOperator node, Instruction inst, ValueType vt> : 1053 GCNPat<(node vt:$src0, vt:$src1), 1054 (inst getVSrcOp<vt>.ret:$src0, getVSrcOp<vt>.ret:$src1, 1055 DSTCLAMP.ENABLE) 1056>; 1057 1058//===----------------------------------------------------------------------===// 1059// VOP3 Classes 1060//===----------------------------------------------------------------------===// 1061 1062class getVOP3ModPat<VOPProfile P, SDPatternOperator node> { 1063 dag src0 = !if(P.HasOMod, 1064 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 1065 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)); 1066 1067 list<dag> ret3 = [(set P.DstVT:$vdst, 1068 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 1069 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), 1070 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))]; 1071 1072 list<dag> ret2 = [(set P.DstVT:$vdst, 1073 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 1074 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))]; 1075 1076 list<dag> ret1 = [(set P.DstVT:$vdst, 1077 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))]; 1078 1079 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1080 !if(!eq(P.NumSrcArgs, 2), ret2, 1081 ret1)); 1082} 1083 1084class getVOP3PModPat<VOPProfile P, SDPatternOperator node, bit HasExplicitClamp, 1085 bit IsDOT = 0, 1086 ComplexPattern SrcPat = !if(IsDOT, VOP3PModsDOT, VOP3PMods)> { 1087 dag src0_dag = (P.Src0VT (SrcPat P.Src0VT:$src0, i32:$src0_modifiers)); 1088 dag src1_dag = (P.Src1VT (SrcPat P.Src1VT:$src1, i32:$src1_modifiers)); 1089 dag src2_dag = (P.Src2VT (SrcPat P.Src2VT:$src2, i32:$src2_modifiers)); 1090 dag clamp_dag = (i1 timm:$clamp); 1091 1092 list<dag> ret3 = [(set P.DstVT:$vdst, 1093 !if(HasExplicitClamp, 1094 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, src2_dag, clamp_dag), 1095 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, src2_dag)))]; 1096 1097 list<dag> ret2 = [(set P.DstVT:$vdst, 1098 !if(HasExplicitClamp, 1099 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, clamp_dag), 1100 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag)))]; 1101 1102 list<dag> ret1 = [(set P.DstVT:$vdst, 1103 !if(HasExplicitClamp, 1104 (DivergentFragOrOp<node, P>.ret src0_dag, clamp_dag), 1105 (DivergentFragOrOp<node, P>.ret src0_dag)))]; 1106 1107 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1108 !if(!eq(P.NumSrcArgs, 2), ret2, 1109 ret1)); 1110} 1111 1112class getVOP3OpSelPat<VOPProfile P, SDPatternOperator node> { 1113 list<dag> ret3 = [(set P.DstVT:$vdst, 1114 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)), 1115 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)), 1116 (P.Src2VT (VOP3OpSel P.Src2VT:$src2, i32:$src2_modifiers))))]; 1117 1118 list<dag> ret2 = [(set P.DstVT:$vdst, 1119 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)), 1120 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))]; 1121 1122 list<dag> ret1 = [(set P.DstVT:$vdst, 1123 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))))]; 1124 1125 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1126 !if(!eq(P.NumSrcArgs, 2), ret2, 1127 ret1)); 1128} 1129 1130class getVOP3OpSelModPat<VOPProfile P, SDPatternOperator node> { 1131 list<dag> ret3 = [(set P.DstVT:$vdst, 1132 (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers), 1133 (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 1134 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)), 1135 (P.Src2VT (VOP3OpSelMods P.Src2VT:$src2, i32:$src2_modifiers))))]; 1136 1137 list<dag> ret2 = [(set P.DstVT:$vdst, 1138 (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers)), 1139 (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 1140 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))]; 1141 1142 list<dag> ret1 = [(set P.DstVT:$vdst, 1143 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))))]; 1144 1145 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1146 !if(!eq(P.NumSrcArgs, 2), ret2, 1147 ret1)); 1148} 1149 1150class getVOP3FromVOP2Pat<VOPProfile P, SDPatternOperator node> { 1151 list<dag> ret = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]; 1152} 1153// In VOP1, we can have clamp and omod even if !HasModifiers 1154class getVOP3Pat<VOPProfile P, SDPatternOperator node> { 1155 dag src0 = 1156 !if(P.HasOMod, 1157 !if(P.HasClamp, 1158 (VOP3Mods0 P.Src0VT:$src0, i1:$clamp, i32:$omod), 1159 (VOP3Mods0 P.Src0VT:$src0, i32:$omod)), // impossible? 1160 !if(P.HasClamp, 1161 (VOP3Mods0 P.Src0VT:$src0, i1:$clamp), 1162 (VOP3Mods0 P.Src0VT:$src0)) 1163 ); 1164 list<dag> ret3 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), P.Src1VT:$src1, P.Src2VT:$src2))]; 1165 1166 list<dag> ret2 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), P.Src1VT:$src1))]; 1167 1168 list<dag> ret1 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))]; 1169 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1170 !if(!eq(P.NumSrcArgs, 2), ret2, 1171 ret1)); 1172} 1173 1174class getVOP3ClampPat<VOPProfile P, SDPatternOperator node> { 1175 list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i1:$clamp))]; 1176 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))]; 1177 list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, i1:$clamp))]; 1178 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1179 !if(!eq(P.NumSrcArgs, 2), ret2, 1180 ret1)); 1181} 1182 1183class getVOP3MAIPat<VOPProfile P, SDPatternOperator node> { 1184 list<dag> ret = !if(!eq(P.Src0VT, P.Src1VT), 1185 // mfma 1186 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, 1187 timm:$cbsz, timm:$abid, timm:$blgp))], 1188 // smfmac 1189 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i32:$idx, 1190 timm:$cbsz, timm:$abid))]); 1191} 1192 1193class VOP3Features<bit Clamp, bit OpSel, bit Packed, bit MAI> { 1194 bit HasClamp = Clamp; 1195 bit HasOpSel = OpSel; 1196 bit IsPacked = Packed; 1197 bit IsMAI = MAI; 1198} 1199 1200def VOP3_REGULAR : VOP3Features<0, 0, 0, 0>; 1201def VOP3_CLAMP : VOP3Features<1, 0, 0, 0>; 1202def VOP3_OPSEL : VOP3Features<1, 1, 0, 0>; 1203def VOP3_PACKED : VOP3Features<1, 1, 1, 0>; 1204def VOP3_MAI : VOP3Features<0, 0, 0, 1>; 1205 1206class VOP3_Profile_Base<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOPProfile<P.ArgVT> { 1207 1208 let HasClamp = !if(Features.HasClamp, 1, P.HasClamp); 1209 let HasOpSel = !if(Features.HasOpSel, 1, P.HasOpSel); 1210 let IsMAI = !if(Features.IsMAI, 1, P.IsMAI); 1211 let IsPacked = !if(Features.IsPacked, 1, P.IsPacked); 1212 1213 let HasModifiers = !if(Features.IsMAI, 0, !or(Features.IsPacked, P.HasModifiers)); 1214} 1215 1216class VOP3_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOP3_Profile_Base<P, Features> { 1217 let IsSingle = 1; 1218 1219} 1220 1221// consistently gives instructions a _e64 suffix 1222multiclass VOP3Inst_Pseudo_Wrapper<string opName, VOPProfile P, list<dag> pattern = [], bit VOP3Only = 0> { 1223 def _e64 : VOP3_Pseudo<opName, P, pattern, VOP3Only>; 1224} 1225 1226class VOP3InstBase<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit IsVOP2 = 0> : 1227 VOP3_Pseudo<OpName, P, 1228 !if(P.HasOpSel, 1229 !if(P.HasModifiers, 1230 getVOP3OpSelModPat<P, node>.ret, 1231 getVOP3OpSelPat<P, node>.ret), 1232 !if(P.HasModifiers, 1233 getVOP3ModPat<P, node>.ret, 1234 !if(IsVOP2, 1235 getVOP3FromVOP2Pat<P, node>.ret, 1236 !if(P.HasIntClamp, 1237 getVOP3ClampPat<P, node>.ret, 1238 !if (P.IsMAI, 1239 getVOP3MAIPat<P, node>.ret, 1240 getVOP3Pat<P, node>.ret))))), 1241 0, P.HasOpSel> { 1242 1243 let IntClamp = P.HasIntClamp; 1244 let AsmMatchConverter = 1245 !if(P.HasOpSel, 1246 "cvtVOP3OpSel", 1247 !if(!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), 1248 "cvtVOP3", 1249 "")); 1250} 1251 1252multiclass VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> { 1253 def _e64 : VOP3InstBase<OpName, P, node>; 1254 let SubtargetPredicate = isGFX11Plus in { 1255 foreach _ = BoolToList<P.HasExtVOP3DPP>.ret in 1256 def _e64_dpp : VOP3_DPP_Pseudo <OpName, P>; 1257 } // end SubtargetPredicate = isGFX11Plus 1258} 1259 1260//===----------------------------------------------------------------------===// 1261// VOP3 DPP 1262//===----------------------------------------------------------------------===// 1263 1264class Base_VOP3_DPP16<bits<10> op, VOP_DPP_Pseudo ps, string opName = ps.OpName> 1265 : VOP3_DPP<op, opName, ps.Pfl, 1> { 1266 let hasSideEffects = ps.hasSideEffects; 1267 let Defs = ps.Defs; 1268 let SchedRW = ps.SchedRW; 1269 let Uses = ps.Uses; 1270 let AssemblerPredicate = HasDPP16; 1271 let SubtargetPredicate = HasDPP16; 1272 let OtherPredicates = ps.OtherPredicates; 1273} 1274 1275class VOP3_DPP16<bits<10> op, VOP_DPP_Pseudo ps, int subtarget, 1276 string opName = ps.OpName> 1277 : Base_VOP3_DPP16<op, ps, opName>, SIMCInstr<ps.PseudoInstr, subtarget>; 1278 1279class Base_VOP3_DPP8<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName> 1280 : VOP3_DPP8<op, opName, ps.Pfl> { 1281 let hasSideEffects = ps.hasSideEffects; 1282 let Defs = ps.Defs; 1283 let SchedRW = ps.SchedRW; 1284 let Uses = ps.Uses; 1285 1286 let OtherPredicates = ps.OtherPredicates; 1287} 1288 1289class Base_VOP3b_DPP16<bits<10> op, VOP_DPP_Pseudo ps, 1290 string opName = ps.OpName> 1291 : Base_VOP3_DPP16<op, ps, opName> { 1292 bits<7> sdst; 1293 let Inst{14 - 8} = sdst; 1294} 1295 1296class VOP3b_DPP8_Base<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName> 1297 : Base_VOP3_DPP8<op, ps, opName> { 1298 bits<7> sdst; 1299 let Inst{14 - 8} = sdst; 1300} 1301 1302//===----------------------------------------------------------------------===// 1303// VOP3 GFX11 1304//===----------------------------------------------------------------------===// 1305 1306let AssemblerPredicate = isGFX11Only, 1307 DecoderNamespace = "GFX11" in { 1308 multiclass VOP3_Real_Base_gfx11<bits<10> op, string opName = NAME, 1309 bit isSingle = 0> { 1310 defvar ps = !cast<VOP_Pseudo>(opName#"_e64"); 1311 let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in { 1312 foreach _ = BoolToList<ps.Pfl.HasOpSel>.ret in 1313 def _e64_gfx11 : 1314 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1315 VOP3OpSel_gfx11<op, ps.Pfl>; 1316 foreach _ = BoolToList<!not(ps.Pfl.HasOpSel)>.ret in 1317 def _e64_gfx11 : 1318 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1319 VOP3e_gfx11<op, ps.Pfl>; 1320 } 1321 } 1322 multiclass VOP3_Real_with_name_gfx11<bits<10> op, string opName, 1323 string asmName, bit isSingle = 0> { 1324 defvar ps = !cast<VOP_Pseudo>(opName#"_e64"); 1325 let AsmString = asmName # ps.AsmOperands, 1326 IsSingle = !or(isSingle, ps.Pfl.IsSingle) in { 1327 foreach _ = BoolToList<ps.Pfl.HasOpSel>.ret in 1328 def _e64_gfx11 : 1329 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1330 VOP3OpSel_gfx11<op, ps.Pfl>, 1331 MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX11Plus]>; 1332 foreach _ = BoolToList<!not(ps.Pfl.HasOpSel)>.ret in 1333 def _e64_gfx11 : 1334 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1335 VOP3e_gfx11<op, ps.Pfl>, 1336 MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX11Plus]>; 1337 } 1338 } 1339 // for READLANE/WRITELANE 1340 multiclass VOP3_Real_No_Suffix_gfx11<bits<10> op, string opName = NAME> { 1341 defvar ps = !cast<VOP_Pseudo>(opName); 1342 def _e64_gfx11 : 1343 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1344 VOP3e_gfx11<op, ps.Pfl>; 1345 } 1346 multiclass VOP3_Real_dpp_Base_gfx11<bits<10> op, string opName = NAME> { 1347 def _e64_dpp_gfx11 : VOP3_DPP16<op, !cast<VOP_DPP_Pseudo>(opName#"_e64"#"_dpp"), SIEncodingFamily.GFX11> { 1348 let DecoderNamespace = "DPPGFX11"; 1349 } 1350 } 1351 multiclass VOP3_Real_dpp_with_name_gfx11<bits<10> op, string opName, 1352 string asmName> { 1353 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1354 let AsmString = asmName # ps.Pfl.AsmVOP3DPP16, DecoderNamespace = "DPPGFX11" in { 1355 defm NAME : VOP3_Real_dpp_Base_gfx11<op, opName>; 1356 } 1357 } 1358 multiclass VOP3_Real_dpp8_Base_gfx11<bits<10> op, string opName = NAME> { 1359 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1360 def _e64_dpp8_gfx11 : Base_VOP3_DPP8<op, ps> { 1361 let DecoderNamespace = "DPP8GFX11"; 1362 } 1363 } 1364 multiclass VOP3_Real_dpp8_with_name_gfx11<bits<10> op, string opName, 1365 string asmName> { 1366 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1367 let AsmString = asmName # ps.Pfl.AsmVOP3DPP8, DecoderNamespace = "DPP8GFX11" in { 1368 defm NAME : VOP3_Real_dpp8_Base_gfx11<op, opName>; 1369 } 1370 } 1371 multiclass VOP3be_Real_gfx11<bits<10> op, string opName, string asmName, 1372 bit isSingle = 0> { 1373 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1374 let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in 1375 def _e64_gfx11 : 1376 VOP3_Real<ps, SIEncodingFamily.GFX11, asmName>, 1377 VOP3be_gfx11<op, ps.Pfl> ; 1378 } 1379 multiclass VOP3be_Real_dpp_gfx11<bits<10> op, string opName, string asmName> { 1380 defvar ps = !cast<VOP3_Pseudo>(opName #"_e64"); 1381 defvar dpp_ps = !cast<VOP_DPP_Pseudo>(opName #"_e64" #"_dpp"); 1382 def _e64_dpp_gfx11 : Base_VOP3b_DPP16<op, dpp_ps, asmName>, 1383 SIMCInstr<dpp_ps.PseudoInstr, SIEncodingFamily.GFX11> { 1384 let DecoderNamespace = "DPPGFX11"; 1385 } 1386 } 1387 multiclass VOP3be_Real_dpp8_gfx11<bits<10> op, string opName, string asmName> { 1388 defvar ps = !cast<VOP3_Pseudo>(opName #"_e64"); 1389 def _e64_dpp8_gfx11 : VOP3b_DPP8_Base<op, ps, asmName> { 1390 let DecoderNamespace = "DPP8GFX11"; 1391 } 1392 } 1393} // End AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" 1394 1395// VOP1 and VOP2 depend on these triple defs 1396multiclass VOP3_Realtriple_gfx11<bits<10> op, 1397 bit isSingle = 0, string opName = NAME> : 1398 VOP3_Real_Base_gfx11<op, opName, isSingle>, 1399 VOP3_Real_dpp_Base_gfx11<op, opName>, 1400 VOP3_Real_dpp8_Base_gfx11<op, opName>; 1401 1402multiclass VOP3Only_Realtriple_gfx11<bits<10> op> : 1403 VOP3_Realtriple_gfx11<op, 1>; 1404 1405multiclass VOP3_Realtriple_with_name_gfx11<bits<10> op, string opName, 1406 string asmName, bit isSingle = 0> : 1407 VOP3_Real_with_name_gfx11<op, opName, asmName, isSingle>, 1408 VOP3_Real_dpp_with_name_gfx11<op, opName, asmName>, 1409 VOP3_Real_dpp8_with_name_gfx11<op, opName, asmName>; 1410 1411multiclass VOP3Only_Realtriple_with_name_gfx11<bits<10> op, string opName, 1412 string asmName> : 1413 VOP3_Realtriple_with_name_gfx11<op, opName, asmName, 1>; 1414 1415multiclass VOP3be_Realtriple_gfx11< 1416 bits<10> op, bit isSingle = 0, string opName = NAME, 1417 string asmName = !cast<VOP_Pseudo>(opName#"_e64").Mnemonic> : 1418 VOP3be_Real_gfx11<op, opName, asmName, isSingle>, 1419 VOP3be_Real_dpp_gfx11<op, opName, asmName>, 1420 VOP3be_Real_dpp8_gfx11<op, opName, asmName>; 1421 1422multiclass VOP3beOnly_Realtriple_gfx11<bits<10> op> : 1423 VOP3be_Realtriple_gfx11<op, 1>; 1424 1425include "VOPCInstructions.td" 1426include "VOP1Instructions.td" 1427include "VOP2Instructions.td" 1428include "VOP3Instructions.td" 1429include "VOP3PInstructions.td" 1430include "VOPDInstructions.td" 1431 1432 1433class VOPInfoTable <string Format> : GenericTable { 1434 let FilterClass = Format # "_Real"; 1435 let CppTypeName = "VOPInfo"; 1436 let Fields = ["Opcode", "IsSingle"]; 1437 1438 let PrimaryKey = ["Opcode"]; 1439 let PrimaryKeyName = "get" # Format # "OpcodeHelper"; 1440} 1441 1442def VOP1InfoTable : VOPInfoTable<"VOP1">; 1443def VOP2InfoTable : VOPInfoTable<"VOP2">; 1444def VOP3InfoTable : VOPInfoTable<"VOP3">; 1445 1446class VOPC64Table <string Format> : GenericTable { 1447 let FilterClass = "VOPC64_" # Format # "_Base"; 1448 let CppTypeName = "VOPC64DPPInfo"; 1449 let Fields = ["Opcode"]; 1450 1451 let PrimaryKey = ["Opcode"]; 1452 let PrimaryKeyName = "isVOPC64" # Format # "OpcodeHelper"; 1453} 1454 1455def VOPC64DPPTable : VOPC64Table<"DPP">; 1456def VOPC64DPP8Table : VOPC64Table<"DPP8">; 1457