1//===-- VOPInstructions.td - Vector Instruction Definitions ---------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// dummies for outer let 10class LetDummies { 11 bit TRANS; 12 bit ReadsModeReg; 13 bit mayRaiseFPException; 14 bit isCommutable; 15 bit isConvertibleToThreeAddress; 16 bit isMoveImm; 17 bit isReMaterializable; 18 bit isAsCheapAsAMove; 19 bit VOPAsmPrefer32Bit; 20 bit FPDPRounding; 21 Predicate SubtargetPredicate; 22 string Constraints; 23 string DisableEncoding; 24 list<SchedReadWrite> SchedRW; 25 list<Register> Uses; 26 list<Register> Defs; 27} 28 29class VOP <string opName> { 30 string OpName = opName; 31} 32 33// First 13 insts from VOPDY are also VOPDX. DOT2ACC_F32_BF16 is omitted 34defvar VOPDX_Max_Index = 12; 35 36class VOPD_Component<bits<5> OpIn, string vOPDName> { 37 Instruction BaseVOP = !cast<Instruction>(NAME); 38 string VOPDName = "v_dual_" # !substr(vOPDName, 2); 39 bits<5> VOPDOp = OpIn; 40 bit CanBeVOPDX = !le(VOPDOp, VOPDX_Max_Index); 41} 42 43class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> : 44 InstSI <outs, ins, asm, pattern> { 45 46 let mayLoad = 0; 47 let mayStore = 0; 48 let hasSideEffects = 0; 49 let UseNamedOperandTable = 1; 50 let VALU = 1; 51 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 52} 53 54class VOP_Pseudo <string opName, string suffix, VOPProfile P, dag outs, dag ins, 55 string asm, list<dag> pattern> : 56 InstSI <outs, ins, asm, pattern>, 57 VOP <opName>, 58 SIMCInstr <opName#suffix, SIEncodingFamily.NONE> { 59 let isPseudo = 1; 60 let isCodeGenOnly = 1; 61 let UseNamedOperandTable = 1; 62 63 string Mnemonic = opName; 64 VOPProfile Pfl = P; 65 66 string AsmOperands; 67} 68 69class VOP3Common <dag outs, dag ins, string asm = "", 70 list<dag> pattern = [], bit HasMods = 0> : 71 VOPAnyCommon <outs, ins, asm, pattern> { 72 73 // Using complex patterns gives VOP3 patterns a very high complexity rating, 74 // but standalone patterns are almost always preferred, so we need to adjust the 75 // priority lower. The goal is to use a high number to reduce complexity to 76 // zero (or less than zero). 77 let AddedComplexity = -1000; 78 79 let VOP3 = 1; 80 81 let AsmVariantName = AMDGPUAsmVariants.VOP3; 82 let AsmMatchConverter = !if(HasMods, "cvtVOP3", ""); 83 84 let isCodeGenOnly = 0; 85 86 int Size = 8; 87 88 // Because SGPRs may be allowed if there are multiple operands, we 89 // need a post-isel hook to insert copies in order to avoid 90 // violating constant bus requirements. 91 let hasPostISelHook = 1; 92} 93 94class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [], 95 bit isVOP3P = 0, bit isVop3OpSel = 0> : 96 VOP_Pseudo <opName, "_e64", P, P.Outs64, 97 !if(isVop3OpSel, 98 P.InsVOP3OpSel, 99 !if(!and(isVOP3P, P.IsPacked), P.InsVOP3P, P.Ins64)), 100 "", pattern> { 101 102 let VOP3_OPSEL = isVop3OpSel; 103 let IsPacked = P.IsPacked; 104 let IsMAI = P.IsMAI; 105 let IsWMMA = P.IsWMMA; 106 107 let AsmOperands = !if(isVop3OpSel, 108 P.AsmVOP3OpSel, 109 !if(!and(isVOP3P, P.IsPacked), P.AsmVOP3P, P.Asm64)); 110 111 let Size = 8; 112 let mayLoad = 0; 113 let mayStore = 0; 114 let hasSideEffects = 0; 115 116 // Because SGPRs may be allowed if there are multiple operands, we 117 // need a post-isel hook to insert copies in order to avoid 118 // violating constant bus requirements. 119 let hasPostISelHook = 1; 120 121 // Using complex patterns gives VOP3 patterns a very high complexity rating, 122 // but standalone patterns are almost always preferred, so we need to adjust the 123 // priority lower. The goal is to use a high number to reduce complexity to 124 // zero (or less than zero). 125 let AddedComplexity = -1000; 126 127 let VOP3 = 1; 128 let VALU = 1; 129 let FPClamp = P.HasFPClamp; 130 let IntClamp = P.HasIntClamp; 131 let ClampLo = P.HasClampLo; 132 let ClampHi = P.HasClampHi; 133 134 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 135 136 let mayRaiseFPException = ReadsModeReg; 137 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 138 139 let AsmVariantName = AMDGPUAsmVariants.VOP3; 140 let AsmMatchConverter = 141 !if(isVOP3P, 142 "cvtVOP3P", 143 !if(!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), 144 "cvtVOP3", 145 "")); 146} 147 148class VOP3P_Pseudo <string opName, VOPProfile P, list<dag> pattern = []> : 149 VOP3_Pseudo<opName, P, pattern, 1> { 150 let VOP3P = 1; 151} 152 153class VOP_Real<VOP_Pseudo ps> { 154 Instruction Opcode = !cast<Instruction>(NAME); 155 bit IsSingle = ps.Pfl.IsSingle; 156} 157 158class VOP3_Real <VOP_Pseudo ps, int EncodingFamily, string asm_name = ps.Mnemonic> : 159 VOP_Real <ps>, 160 InstSI <ps.OutOperandList, ps.InOperandList, asm_name # ps.AsmOperands, []>, 161 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 162 163 let VALU = 1; 164 let VOP3 = 1; 165 let isPseudo = 0; 166 let isCodeGenOnly = 0; 167 let UseNamedOperandTable = 1; 168 169 // copy relevant pseudo op flags 170 let SubtargetPredicate = ps.SubtargetPredicate; 171 let OtherPredicates = ps.OtherPredicates; 172 let AsmMatchConverter = ps.AsmMatchConverter; 173 let AsmVariantName = ps.AsmVariantName; 174 let Constraints = ps.Constraints; 175 let DisableEncoding = ps.DisableEncoding; 176 let TSFlags = ps.TSFlags; 177 let UseNamedOperandTable = ps.UseNamedOperandTable; 178 let Uses = ps.Uses; 179 let Defs = ps.Defs; 180 let SchedRW = ps.SchedRW; 181 let mayLoad = ps.mayLoad; 182 let mayStore = ps.mayStore; 183 let TRANS = ps.TRANS; 184 185 VOPProfile Pfl = ps.Pfl; 186} 187 188// XXX - Is there any reason to distinguish this from regular VOP3 189// here? 190class VOP3P_Real<VOP_Pseudo ps, int EncodingFamily, string asm_name = ps.Mnemonic> : 191 VOP3_Real<ps, EncodingFamily, asm_name> { 192 193 // The v_wmma pseudos have extra constraints that we do not want to impose on the real instruction. 194 let Constraints = !if(!eq(!substr(ps.Mnemonic,0,6), "v_wmma"), "", ps.Constraints); 195} 196 197class VOP3a<VOPProfile P> : Enc64 { 198 bits<4> src0_modifiers; 199 bits<9> src0; 200 bits<3> src1_modifiers; 201 bits<9> src1; 202 bits<3> src2_modifiers; 203 bits<9> src2; 204 bits<1> clamp; 205 bits<2> omod; 206 207 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 208 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); 209 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); 210 211 let Inst{31-26} = 0x34; //encoding 212 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 213 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 214 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 215 let Inst{60-59} = !if(P.HasOMod, omod, 0); 216 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 217 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 218 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 219} 220 221class VOP3a_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a<p> { 222 let Inst{11} = !if(p.HasClamp, clamp{0}, 0); 223 let Inst{25-17} = op; 224} 225 226class VOP3a_gfx10<bits<10> op, VOPProfile p> : VOP3a<p> { 227 let Inst{15} = !if(p.HasClamp, clamp{0}, 0); 228 let Inst{25-16} = op; 229 let Inst{31-26} = 0x35; 230} 231 232class VOP3a_gfx11<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p>; 233 234class VOP3a_vi <bits<10> op, VOPProfile P> : VOP3a<P> { 235 let Inst{25-16} = op; 236 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 237} 238 239class VOP3e_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a_gfx6_gfx7<op, p> { 240 bits<8> vdst; 241 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0); 242} 243 244class VOP3e_gfx10<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p> { 245 bits<8> vdst; 246 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0); 247} 248 249class VOP3e_gfx11<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p>; 250 251class VOP3e_vi <bits<10> op, VOPProfile P> : VOP3a_vi <op, P> { 252 bits<8> vdst; 253 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0); 254} 255 256class VOP3OpSel_gfx9 <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> { 257 let Inst{11} = !if(P.HasSrc0, src0_modifiers{2}, 0); 258 let Inst{12} = !if(P.HasSrc1, src1_modifiers{2}, 0); 259 let Inst{13} = !if(P.HasSrc2, src2_modifiers{2}, 0); 260 let Inst{14} = !if(P.HasDst, src0_modifiers{3}, 0); 261} 262 263class VOP3OpSel_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> { 264 let Inst{11} = !if(p.HasSrc0, src0_modifiers{2}, 0); 265 let Inst{12} = !if(p.HasSrc1, src1_modifiers{2}, 0); 266 let Inst{13} = !if(p.HasSrc2, src2_modifiers{2}, 0); 267 let Inst{14} = !if(p.HasDst, src0_modifiers{3}, 0); 268} 269 270class VOP3OpSel_gfx11<bits<10> op, VOPProfile p> : VOP3OpSel_gfx10<op, p>; 271 272 273// NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa 274class VOP3Interp_vi <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> { 275 bits<2> attrchan; 276 bits<6> attr; 277 bits<1> high; 278 279 let Inst{8} = 0; // No modifiers for src0 280 let Inst{61} = 0; 281 282 let Inst{9} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 283 let Inst{62} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 284 285 let Inst{37-32} = attr; 286 let Inst{39-38} = attrchan; 287 let Inst{40} = !if(P.HasHigh, high, 0); 288 289 let Inst{49-41} = src0; 290} 291 292class VOP3Interp_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> { 293 bits<6> attr; 294 bits<2> attrchan; 295 bits<1> high; 296 297 let Inst{8} = 0; 298 let Inst{9} = !if(p.HasSrc0Mods, src0_modifiers{1}, 0); 299 let Inst{37-32} = attr; 300 let Inst{39-38} = attrchan; 301 let Inst{40} = !if(p.HasHigh, high, 0); 302 let Inst{49-41} = src0; 303 let Inst{61} = 0; 304 let Inst{62} = !if(p.HasSrc0Mods, src0_modifiers{0}, 0); 305} 306 307class VOP3Interp_gfx11<bits<10> op, VOPProfile p> : VOP3Interp_gfx10<op, p>; 308 309class VOP3be <VOPProfile P> : Enc64 { 310 bits<8> vdst; 311 bits<2> src0_modifiers; 312 bits<9> src0; 313 bits<2> src1_modifiers; 314 bits<9> src1; 315 bits<2> src2_modifiers; 316 bits<9> src2; 317 bits<7> sdst; 318 bits<2> omod; 319 320 let Inst{7-0} = vdst; 321 let Inst{14-8} = sdst; 322 let Inst{31-26} = 0x34; //encoding 323 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 324 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 325 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 326 let Inst{60-59} = !if(P.HasOMod, omod, 0); 327 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 328 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 329 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 330} 331 332class VOP3Pe <bits<7> op, VOPProfile P> : Enc64 { 333 bits<8> vdst; 334 bits<4> src0_modifiers; 335 bits<9> src0; 336 bits<4> src1_modifiers; 337 bits<9> src1; 338 bits<4> src2_modifiers; 339 bits<9> src2; 340 bits<1> clamp; 341 342 let Inst{7-0} = vdst; 343 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0 344 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // neg_hi src1 345 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); // neg_hi src2 346 347 let Inst{11} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{2}, 0); // op_sel(0) 348 let Inst{12} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{2}, 0); // op_sel(1) 349 let Inst{13} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{2}, 0); // op_sel(2) 350 351 let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, ?); // op_sel_hi(2) 352 353 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 354 355 let Inst{22-16} = op; 356 let Inst{31-23} = 0x1a7; //encoding 357 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 358 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 359 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 360 let Inst{59} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, ?); // op_sel_hi(0) 361 let Inst{60} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, ?); // op_sel_hi(1) 362 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // neg (lo) 363 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // neg (lo) 364 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo) 365} 366 367class VOP3Pe_MAI <bits<7> op, VOPProfile P, bit acc_cd = 0> : Enc64 { 368 bits<8> vdst; 369 bits<10> src0; 370 bits<10> src1; 371 bits<9> src2; 372 bits<3> blgp; 373 bits<3> cbsz; 374 bits<4> abid; 375 376 let Inst{7-0} = vdst; 377 378 let Inst{10-8} = !if(P.HasSrc1, cbsz, 0); 379 let Inst{14-11} = !if(P.HasSrc1, abid, 0); 380 381 let Inst{15} = acc_cd; 382 383 let Inst{22-16} = op; 384 let Inst{31-23} = 0x1a7; //encoding 385 let Inst{40-32} = !if(P.HasSrc0, src0{8-0}, 0); 386 let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, 0); 387 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 388 389 let Inst{59} = !if(P.HasSrc0, src0{9}, 0); // acc(0) 390 let Inst{60} = !if(P.HasSrc1, src1{9}, 0); // acc(1) 391 392 let Inst{63-61} = !if(P.HasSrc1, blgp, 0); 393} 394 395class VOP3Pe_SMFMAC <bits<7> op> : Enc64 { 396 bits<10> vdst; // VGPR or AGPR, but not SGPR. vdst{8} is not encoded in the instruction. 397 bits<10> src0; 398 bits<10> src1; 399 bits<9> idx; 400 bits<3> blgp; 401 bits<3> cbsz; 402 bits<4> abid; 403 404 let blgp = 0; 405 406 let Inst{7-0} = vdst{7-0}; 407 408 let Inst{10-8} = cbsz; 409 let Inst{14-11} = abid; 410 411 let Inst{15} = vdst{9}; // acc(vdst) 412 413 let Inst{22-16} = op; 414 let Inst{31-23} = 0x1a7; // encoding 415 let Inst{40-32} = src0{8-0}; 416 let Inst{49-41} = src1{8-0}; 417 let Inst{58-50} = idx; 418 419 let Inst{59} = src0{9}; // acc(0) 420 let Inst{60} = src1{9}; // acc(1) 421 422 let Inst{63-61} = blgp; 423} 424 425class VOP3Pe_gfx10 <bits<7> op, VOPProfile P> : VOP3Pe<op, P> { 426 let Inst{31-23} = 0x198; //encoding 427} 428 429class VOP3Pe_gfx11<bits<7> op, VOPProfile P> : VOP3Pe_gfx10<op, P>; 430 431class VOP3be_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3be<p> { 432 let Inst{25-17} = op; 433} 434 435class VOP3be_gfx10<bits<10> op, VOPProfile p> : VOP3be<p> { 436 bits<1> clamp; 437 let Inst{15} = !if(p.HasClamp, clamp{0}, 0); 438 let Inst{25-16} = op; 439 let Inst{31-26} = 0x35; 440} 441 442class VOP3be_gfx11<bits<10> op, VOPProfile p> : VOP3be_gfx10<op, p>; 443 444class VOP3be_vi <bits<10> op, VOPProfile P> : VOP3be<P> { 445 bits<1> clamp; 446 let Inst{25-16} = op; 447 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 448} 449 450def SDWA { 451 // sdwa_sel 452 int BYTE_0 = 0; 453 int BYTE_1 = 1; 454 int BYTE_2 = 2; 455 int BYTE_3 = 3; 456 int WORD_0 = 4; 457 int WORD_1 = 5; 458 int DWORD = 6; 459 460 // dst_unused 461 int UNUSED_PAD = 0; 462 int UNUSED_SEXT = 1; 463 int UNUSED_PRESERVE = 2; 464} 465 466class VOP_SDWAe<VOPProfile P> : Enc64 { 467 bits<8> src0; 468 bits<3> src0_sel; 469 bits<2> src0_modifiers; // float: {abs,neg}, int {sext} 470 bits<3> src1_sel; 471 bits<2> src1_modifiers; 472 bits<3> dst_sel; 473 bits<2> dst_unused; 474 bits<1> clamp; 475 476 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 477 let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?); 478 let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?); 479 let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); 480 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0); 481 let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0); 482 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0); 483 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0); 484 let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0); 485 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0); 486} 487 488// GFX9 adds two features to SDWA: 489// 1. Add 3 fields to the SDWA microcode word: S0, S1 and OMOD. 490// a. S0 and S1 indicate that source 0 and 1 respectively are SGPRs rather 491// than VGPRs (at most 1 can be an SGPR); 492// b. OMOD is the standard output modifier (result *2, *4, /2) 493// 2. Add a new version of the SDWA microcode word for VOPC: SDWAB. This 494// replaces OMOD and the dest fields with SD and SDST (SGPR destination) 495// field. 496// a. When SD=1, the SDST is used as the destination for the compare result; 497// b. When SD=0, VCC is used. 498// 499// In GFX9, V_MAC_F16, V_MAC_F32 opcodes cannot be used with SDWA 500 501// gfx9 SDWA basic encoding 502class VOP_SDWA9e<VOPProfile P> : Enc64 { 503 bits<9> src0; // {src0_sgpr{0}, src0{7-0}} 504 bits<3> src0_sel; 505 bits<2> src0_modifiers; // float: {abs,neg}, int {sext} 506 bits<3> src1_sel; 507 bits<2> src1_modifiers; 508 bits<1> src1_sgpr; 509 510 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 511 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0); 512 let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0); 513 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0); 514 let Inst{55} = !if(P.HasSrc0, src0{8}, 0); 515 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0); 516 let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0); 517 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0); 518 let Inst{63} = 0; // src1_sgpr - should be specified in subclass 519} 520 521// gfx9 SDWA-A 522class VOP_SDWA9Ae<VOPProfile P> : VOP_SDWA9e<P> { 523 bits<3> dst_sel; 524 bits<2> dst_unused; 525 bits<1> clamp; 526 bits<2> omod; 527 528 let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?); 529 let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?); 530 let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); 531 let Inst{47-46} = !if(P.HasSDWAOMod, omod{1-0}, 0); 532} 533 534// gfx9 SDWA-B 535class VOP_SDWA9Be<VOPProfile P> : VOP_SDWA9e<P> { 536 bits<8> sdst; // {vcc_sdst{0}, sdst{6-0}} 537 538 let Inst{46-40} = !if(P.EmitDst, sdst{6-0}, ?); 539 let Inst{47} = !if(P.EmitDst, sdst{7}, 0); 540} 541 542class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> : 543 InstSI <P.OutsSDWA, P.InsSDWA, "", pattern>, 544 VOP <opName>, 545 SIMCInstr <opName#"_sdwa", SIEncodingFamily.NONE> { 546 547 let isPseudo = 1; 548 let isCodeGenOnly = 1; 549 let UseNamedOperandTable = 1; 550 551 string Mnemonic = opName; 552 string AsmOperands = P.AsmSDWA; 553 string AsmOperands9 = P.AsmSDWA9; 554 555 let Size = 8; 556 let mayLoad = 0; 557 let mayStore = 0; 558 let hasSideEffects = 0; 559 560 let VALU = 1; 561 let SDWA = 1; 562 563 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 564 565 let mayRaiseFPException = ReadsModeReg; 566 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 567 568 let SubtargetPredicate = HasSDWA; 569 let AssemblerPredicate = HasSDWA; 570 let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA, 571 AMDGPUAsmVariants.Disable); 572 let DecoderNamespace = "SDWA"; 573 574 VOPProfile Pfl = P; 575} 576 577class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> : 578 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 579 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA> { 580 581 let VALU = 1; 582 let SDWA = 1; 583 let isPseudo = 0; 584 let isCodeGenOnly = 0; 585 586 let Defs = ps.Defs; 587 let Uses = ps.Uses; 588 let hasSideEffects = ps.hasSideEffects; 589 590 let Constraints = ps.Constraints; 591 let DisableEncoding = ps.DisableEncoding; 592 593 // Copy relevant pseudo op flags 594 let SubtargetPredicate = ps.SubtargetPredicate; 595 let AssemblerPredicate = ps.AssemblerPredicate; 596 let AsmMatchConverter = ps.AsmMatchConverter; 597 let AsmVariantName = ps.AsmVariantName; 598 let UseNamedOperandTable = ps.UseNamedOperandTable; 599 let DecoderNamespace = ps.DecoderNamespace; 600 let Constraints = ps.Constraints; 601 let DisableEncoding = ps.DisableEncoding; 602 let TSFlags = ps.TSFlags; 603 let SchedRW = ps.SchedRW; 604 let mayLoad = ps.mayLoad; 605 let mayStore = ps.mayStore; 606 let TRANS = ps.TRANS; 607} 608 609class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> : 610 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands9, []> { 611 612 let VALU = 1; 613 let SDWA = 1; 614 let isPseudo = 0; 615 let isCodeGenOnly = 0; 616 617 let Defs = ps.Defs; 618 let Uses = ps.Uses; 619 let hasSideEffects = ps.hasSideEffects; 620 621 let Constraints = ps.Constraints; 622 let DisableEncoding = ps.DisableEncoding; 623 624 let SubtargetPredicate = HasSDWA9; 625 let AssemblerPredicate = HasSDWA9; 626 let AsmVariantName = !if(ps.Pfl.HasExtSDWA9, AMDGPUAsmVariants.SDWA9, 627 AMDGPUAsmVariants.Disable); 628 let DecoderNamespace = "SDWA9"; 629 630 // Copy relevant pseudo op flags 631 let AsmMatchConverter = ps.AsmMatchConverter; 632 let UseNamedOperandTable = ps.UseNamedOperandTable; 633 let Constraints = ps.Constraints; 634 let DisableEncoding = ps.DisableEncoding; 635 let TSFlags = ps.TSFlags; 636 let SchedRW = ps.SchedRW; 637 let mayLoad = ps.mayLoad; 638 let mayStore = ps.mayStore; 639 let TRANS = ps.TRANS; 640} 641 642class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> : 643 Base_VOP_SDWA9_Real <ps >, 644 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA9>; 645 646class Base_VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : Base_VOP_SDWA9_Real<ps> { 647 let SubtargetPredicate = HasSDWA10; 648 let AssemblerPredicate = HasSDWA10; 649 let DecoderNamespace = "SDWA10"; 650} 651 652class VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : 653 Base_VOP_SDWA10_Real<ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SDWA10>; 654 655class VOP_DPPe<VOPProfile P, bit IsDPP16=0> : Enc64 { 656 bits<2> src0_modifiers; 657 bits<8> src0; 658 bits<2> src1_modifiers; 659 bits<9> dpp_ctrl; 660 bits<1> bound_ctrl; 661 bits<4> bank_mask; 662 bits<4> row_mask; 663 bit fi; 664 665 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 666 let Inst{48-40} = dpp_ctrl; 667 let Inst{50} = !if(IsDPP16, fi, ?); 668 let Inst{51} = bound_ctrl; 669 let Inst{52} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg 670 let Inst{53} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // src0_abs 671 let Inst{54} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg 672 let Inst{55} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // src1_abs 673 let Inst{59-56} = bank_mask; 674 let Inst{63-60} = row_mask; 675} 676 677class VOP3_DPPe_Fields_Base { 678 bits<9> dpp_ctrl; 679 bits<1> bound_ctrl; 680 bits<4> bank_mask; 681 bits<4> row_mask; 682 bit fi; 683} 684class VOP3_DPPe_Fields : VOP3_DPPe_Fields_Base { 685 bits<8> src0; 686} 687 688// Common refers to common between DPP and DPP8 689class VOP3_DPPe_Common_Base<bits<10> op, VOPProfile P> : Enc96 { 690 bits<4> src0_modifiers; 691 bits<3> src1_modifiers; 692 bits<3> src2_modifiers; 693 bits<1> clamp; 694 bits<2> omod; 695 696 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 697 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); 698 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); 699 // OPSEL must be set such that the low result only uses low inputs, and the high result only uses high inputs. 700 let Inst{11} = !if(P.HasOpSel,!if(P.HasSrc0Mods, src0_modifiers{2}, 0),?); 701 let Inst{12} = !if(P.HasOpSel,!if(P.HasSrc1Mods, src1_modifiers{2}, 0),?); 702 let Inst{13} = !if(P.HasOpSel,!if(P.HasSrc2Mods, src2_modifiers{2}, 0),?); 703 let Inst{14} = !if(P.HasOpSel,!if(P.HasSrc0Mods, src0_modifiers{3}, 0),?); 704 let Inst{15} = !if(P.HasClamp, clamp, 0); 705 let Inst{25-16} = op; 706 let Inst{31-26} = 0x35; 707 708 let Inst{60-59} = !if(P.HasOMod, omod, 0); 709 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 710 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 711 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 712} 713 714class VOP3_DPPe_Common<bits<10> op, VOPProfile P> : VOP3_DPPe_Common_Base<op, P> { 715 bits<8> vdst; 716 bits<9> src1; 717 bits<9> src2; 718 719 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0); 720 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 721 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 722} 723 724class VOP3P_DPPe_Common_Base<bits<7> op, VOPProfile P> : Enc96 { 725 bits<4> src0_modifiers; 726 bits<4> src1_modifiers; 727 bits<4> src2_modifiers; 728 bits<1> clamp; 729 730 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0 731 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // neg_hi src1 732 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); // neg_hi src2 733 let Inst{11} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{2}, 0); // op_sel(0) 734 let Inst{12} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{2}, 0); // op_sel(1) 735 let Inst{13} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{2}, 0); // op_sel(2) 736 let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, ?); // op_sel_hi(2) 737 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 738 let Inst{22-16} = op; 739 let Inst{31-23} = 0x198; // encoding 740 let Inst{59} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, ?); // op_sel_hi(0) 741 let Inst{60} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, ?); // op_sel_hi(1) 742 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // neg (lo) 743 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // neg (lo) 744 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo) 745} 746 747class VOP3P_DPPe_Common<bits<7> op, VOPProfile P> : VOP3P_DPPe_Common_Base<op, P> { 748 bits<8> vdst; 749 bits<9> src1; 750 bits<9> src2; 751 752 let Inst{7-0} = vdst; 753 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 754 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 755} 756 757class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[], 758 dag Ins = P.InsDPP, string asmOps = P.AsmDPP> : 759 InstSI <P.OutsDPP, Ins, OpName#asmOps, pattern>, 760 VOP <OpName>, 761 SIMCInstr <OpName#"_dpp", SIEncodingFamily.NONE> { 762 763 let isPseudo = 1; 764 let isCodeGenOnly = 1; 765 766 let mayLoad = 0; 767 let mayStore = 0; 768 let hasSideEffects = 0; 769 let UseNamedOperandTable = 1; 770 771 let VALU = 1; 772 let DPP = 1; 773 let Size = 8; 774 775 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 776 777 let mayRaiseFPException = ReadsModeReg; 778 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 779 let isConvergent = 1; 780 781 string Mnemonic = OpName; 782 string AsmOperands = asmOps; 783 784 let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", ""); 785 let SubtargetPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 786 let AssemblerPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 787 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, 788 AMDGPUAsmVariants.Disable); 789 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 790 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 791 let DecoderNamespace = "DPP"; 792 793 VOPProfile Pfl = P; 794} 795 796class VOP3_DPP_Pseudo <string OpName, VOPProfile P> : 797 VOP_DPP_Pseudo <OpName, P, [], P.InsVOP3DPP, P.AsmVOP3DPP> { 798 let PseudoInstr = OpName#"_e64"#"_dpp"; 799 let OutOperandList = P.OutsVOP3DPP; 800 let Size = 12; 801 let VOP3 = 1; 802 let AsmMatchConverter = "cvtVOP3DPP"; 803 let AsmVariantName = !if(P.HasExtVOP3DPP, AMDGPUAsmVariants.VOP3_DPP, 804 AMDGPUAsmVariants.Disable); 805} 806 807class VOP_DPP_Real <VOP_DPP_Pseudo ps, int EncodingFamily> : 808 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 809 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 810 811 let VALU = 1; 812 let DPP = 1; 813 let isPseudo = 0; 814 let isCodeGenOnly = 0; 815 816 let Defs = ps.Defs; 817 let Uses = ps.Uses; 818 let hasSideEffects = ps.hasSideEffects; 819 820 let Constraints = ps.Constraints; 821 let DisableEncoding = ps.DisableEncoding; 822 823 // Copy relevant pseudo op flags 824 let isConvergent = ps.isConvergent; 825 let SubtargetPredicate = ps.SubtargetPredicate; 826 let AssemblerPredicate = ps.AssemblerPredicate; 827 let OtherPredicates = ps.OtherPredicates; 828 let AsmMatchConverter = ps.AsmMatchConverter; 829 let AsmVariantName = ps.AsmVariantName; 830 let UseNamedOperandTable = ps.UseNamedOperandTable; 831 let DecoderNamespace = ps.DecoderNamespace; 832 let Constraints = ps.Constraints; 833 let DisableEncoding = ps.DisableEncoding; 834 let TSFlags = ps.TSFlags; 835 let SchedRW = ps.SchedRW; 836 let mayLoad = ps.mayLoad; 837 let mayStore = ps.mayStore; 838 let TRANS = ps.TRANS; 839} 840 841class VOP_DPP_Base <string OpName, VOPProfile P, 842 dag InsDPP, 843 string AsmDPP > : 844 InstSI <P.OutsDPP, InsDPP, OpName#AsmDPP, []> { 845 846 let mayLoad = 0; 847 let mayStore = 0; 848 let hasSideEffects = 0; 849 let UseNamedOperandTable = 1; 850 851 let VALU = 1; 852 let DPP = 1; 853 let Size = 8; 854 855 let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", ""); 856 let SubtargetPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 857 let AssemblerPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 858 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, 859 AMDGPUAsmVariants.Disable); 860 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 861 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 862 let DecoderNamespace = "DPP"; 863} 864 865class VOP_DPP <string OpName, VOPProfile P, bit IsDPP16, 866 dag InsDPP = !if(IsDPP16, P.InsDPP16, P.InsDPP), 867 string AsmDPP = !if(IsDPP16, P.AsmDPP16, P.AsmDPP)> : 868 VOP_DPP_Base<OpName, P, InsDPP, AsmDPP>, VOP_DPPe<P, IsDPP16>; 869 870class VOP3_DPP_Base <string OpName, VOPProfile P, bit IsDPP16, 871 dag InsDPP = !if(IsDPP16, P.InsVOP3DPP16, P.InsVOP3DPP), 872 string AsmDPP = !if(IsDPP16, P.AsmVOP3DPP16, P.AsmVOP3DPP)> : 873 VOP_DPP_Base<OpName, P, InsDPP, AsmDPP> { 874 let OutOperandList = P.OutsVOP3DPP; 875 let AsmMatchConverter = "cvtVOP3DPP"; 876 let VOP3 = 1; 877 let AsmVariantName = !if(P.HasExtVOP3DPP, AMDGPUAsmVariants.VOP3_DPP, 878 AMDGPUAsmVariants.Disable); 879 let Size = 12; 880} 881 882class VOP3_DPP <bits<10> op, string OpName, VOPProfile P, bit IsDPP16, 883 dag InsDPP = !if(IsDPP16, P.InsVOP3DPP16, P.InsVOP3DPP), 884 string AsmDPP = !if(IsDPP16, P.AsmVOP3DPP16, P.AsmVOP3DPP)> : 885 VOP3_DPP_Base<OpName, P, IsDPP16, InsDPP, AsmDPP>, VOP3_DPPe_Common<op, P>, 886 VOP3_DPPe_Fields { 887 888 let Inst{40-32} = 0xfa; 889 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 890 let Inst{80-72} = dpp_ctrl; 891 let Inst{82} = !if(IsDPP16, fi, ?); 892 let Inst{83} = bound_ctrl; 893 894 // Inst{87-84} ignored by hw 895 let Inst{91-88} = bank_mask; 896 let Inst{95-92} = row_mask; 897} 898 899class VOP3P_DPP <bits<7> op, string OpName, VOPProfile P, bit IsDPP16, 900 dag InsDPP = !if(IsDPP16, P.InsVOP3DPP16, P.InsVOP3DPP), 901 string AsmDPP = !if(IsDPP16, P.AsmVOP3DPP16, P.AsmVOP3DPP)> : 902 VOP3_DPP_Base<OpName, P, IsDPP16, InsDPP, AsmDPP>, VOP3P_DPPe_Common<op, P>, 903 VOP3_DPPe_Fields { 904 905 let VOP3P = 1; 906 907 let Inst{40-32} = 0xfa; 908 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 909 let Inst{80-72} = dpp_ctrl; 910 let Inst{82} = !if(IsDPP16, fi, ?); 911 let Inst{83} = bound_ctrl; 912 913 // Inst{87-84} ignored by hw 914 let Inst{91-88} = bank_mask; 915 let Inst{95-92} = row_mask; 916} 917 918class VOP_DPP8e<VOPProfile P> : Enc64 { 919 bits<8> src0; 920 bits<24> dpp8; 921 bits<9> fi; 922 923 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 924 let Inst{63-40} = dpp8{23-0}; 925} 926 927class VOP3_DPP8e_Fields { 928 bits<8> src0; 929 bits<24> dpp8; 930 bits<9> fi; 931} 932 933class VOP_DPP8_Base<string OpName, VOPProfile P, dag InsDPP8 = P.InsDPP8, string AsmDPP8 = P.AsmDPP8> : 934 InstSI<P.OutsDPP8, InsDPP8, OpName#AsmDPP8, []> { 935 936 let mayLoad = 0; 937 let mayStore = 0; 938 let hasSideEffects = 0; 939 let UseNamedOperandTable = 1; 940 941 let VALU = 1; 942 let DPP = 1; 943 let Size = 8; 944 945 let AsmMatchConverter = "cvtDPP8"; 946 let SubtargetPredicate = HasDPP8; 947 let AssemblerPredicate = HasDPP8; 948 let AsmVariantName = AMDGPUAsmVariants.DPP; 949 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 950 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 951} 952 953class VOP_DPP8<string OpName, VOPProfile P> : 954 VOP_DPP8_Base<OpName, P>, VOP_DPP8e<P>; 955 956class VOP3_DPP8_Base<string OpName, VOPProfile P> : 957 VOP_DPP8_Base<OpName, P, P.InsVOP3DPP8, P.AsmVOP3DPP8> { 958 let OutOperandList = P.OutsVOP3DPP8; 959 let AsmMatchConverter = "cvtVOP3DPP8"; 960 let AsmVariantName = !if(P.HasExtVOP3DPP, AMDGPUAsmVariants.VOP3_DPP, 961 AMDGPUAsmVariants.Disable); 962 let VOP3 = 1; 963 let Size = 12; 964} 965 966 967class VOP3_DPP8<bits<10> op, string OpName, VOPProfile P> : 968 VOP3_DPP8_Base<OpName, P>, VOP3_DPPe_Common<op, P>, 969 VOP3_DPP8e_Fields { 970 971 let Inst{40-32} = fi; 972 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 973 let Inst{95-72} = dpp8{23-0}; 974} 975 976class VOP3P_DPP8<bits<7> op, string OpName, VOPProfile P> : 977 VOP3_DPP8_Base<OpName, P>, VOP3P_DPPe_Common<op, P>, 978 VOP3_DPP8e_Fields { 979 980 let VOP3P = 1; 981 let Inst{40-32} = fi; 982 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 983 let Inst{95-72} = dpp8{23-0}; 984} 985 986def DPP8Mode { 987 int FI_0 = 0xE9; 988 int FI_1 = 0xEA; 989} 990 991class getNumNodeArgs<SDPatternOperator Op> { 992 SDNode N = !cast<SDNode>(Op); 993 SDTypeProfile TP = N.TypeProfile; 994 int ret = TP.NumOperands; 995} 996 997class getDivergentFrag<SDPatternOperator Op> { 998 assert !or(!isa<SDNode>(Op), !isa<PatFrags>(Op)), "Expected SDNode or PatFrags"; 999 1000 int NumSrcArgs = !if(!isa<SDNode>(Op), getNumNodeArgs<Op>.ret, 1001 !size(!cast<PatFrags>(Op).Operands)); 1002 PatFrag ret = PatFrag < 1003 !if(!eq(NumSrcArgs, 1), 1004 (ops node:$src0), 1005 !if(!eq(NumSrcArgs, 2), 1006 (ops node:$src0, node:$src1), 1007 (ops node:$src0, node:$src1, node:$src2))), 1008 !if(!eq(NumSrcArgs, 1), 1009 (Op $src0), 1010 !if(!eq(NumSrcArgs, 2), 1011 (Op $src0, $src1), 1012 (Op $src0, $src1, $src2))), 1013 [{ return N->isDivergent(); }] 1014 >; 1015} 1016 1017class VOPPatGen<SDPatternOperator Op, VOPProfile P> { 1018 PatFrag Operator = getDivergentFrag < Op >.ret; 1019 1020 dag Ins = !foreach(tmp, P.Ins32, !subst(ins, Operator, 1021 !subst(P.Src0RC32, P.Src0VT, 1022 !subst(P.Src1RC32, P.Src1VT, tmp)))); 1023 1024 dag Outs = !foreach(tmp, P.Outs32, !subst(outs, set, 1025 !subst(P.DstRC, P.DstVT, tmp))); 1026 1027 list<dag> ret = [!con(Outs, (set Ins))]; 1028} 1029 1030class DivergentUnaryFrag<SDPatternOperator Op> : PatFrag < 1031 (ops node:$src0), 1032 (Op $src0), 1033 [{ return N->isDivergent(); }]> { 1034 // This check is unnecessary as it's captured by the result register 1035 // bank constraint. 1036 // 1037 // FIXME: Should add a way for the emitter to recognize this is a 1038 // trivially true predicate to eliminate the check. 1039 let GISelPredicateCode = [{return true;}]; 1040} 1041 1042class VOPPatOrNull<SDPatternOperator Op, VOPProfile P> { 1043 list<dag> ret = !if(!ne(P.NeedPatGen,PatGenMode.NoPattern), VOPPatGen<Op, P>.ret, []); 1044} 1045 1046class DivergentFragOrOp<SDPatternOperator Op, VOPProfile P> { 1047 SDPatternOperator ret = !if(!eq(P.NeedPatGen,PatGenMode.Pattern), 1048 !if(!isa<SDNode>(Op), getDivergentFrag<Op>.ret, Op), Op); 1049} 1050 1051class getVSrcOp<ValueType vt> { 1052 RegisterOperand ret = !if(!eq(vt.Size, 32), VSrc_b32, VSrc_b16); 1053} 1054 1055// Class for binary integer operations with the clamp bit set for saturation 1056// TODO: Add sub with negated inline constant pattern. 1057class VOPBinOpClampPat<SDPatternOperator node, Instruction inst, ValueType vt> : 1058 GCNPat<(node vt:$src0, vt:$src1), 1059 (inst getVSrcOp<vt>.ret:$src0, getVSrcOp<vt>.ret:$src1, 1060 DSTCLAMP.ENABLE) 1061>; 1062 1063//===----------------------------------------------------------------------===// 1064// VOP3 Classes 1065//===----------------------------------------------------------------------===// 1066 1067class getVOP3ModPat<VOPProfile P, SDPatternOperator node> { 1068 dag src0 = !if(P.HasOMod, 1069 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 1070 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)); 1071 1072 list<dag> ret3 = [(set P.DstVT:$vdst, 1073 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 1074 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), 1075 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))]; 1076 1077 list<dag> ret2 = [(set P.DstVT:$vdst, 1078 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 1079 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))]; 1080 1081 list<dag> ret1 = [(set P.DstVT:$vdst, 1082 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))]; 1083 1084 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1085 !if(!eq(P.NumSrcArgs, 2), ret2, 1086 ret1)); 1087} 1088 1089class getVOP3PModPat<VOPProfile P, SDPatternOperator node, bit HasExplicitClamp, 1090 bit IsDOT = 0, 1091 ComplexPattern SrcPat = !if(IsDOT, VOP3PModsDOT, VOP3PMods)> { 1092 dag src0_dag = (P.Src0VT (SrcPat P.Src0VT:$src0, i32:$src0_modifiers)); 1093 dag src1_dag = (P.Src1VT (SrcPat P.Src1VT:$src1, i32:$src1_modifiers)); 1094 dag src2_dag = (P.Src2VT (SrcPat P.Src2VT:$src2, i32:$src2_modifiers)); 1095 dag clamp_dag = (i1 timm:$clamp); 1096 1097 list<dag> ret3 = [(set P.DstVT:$vdst, 1098 !if(HasExplicitClamp, 1099 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, src2_dag, clamp_dag), 1100 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, src2_dag)))]; 1101 1102 list<dag> ret2 = [(set P.DstVT:$vdst, 1103 !if(HasExplicitClamp, 1104 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, clamp_dag), 1105 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag)))]; 1106 1107 list<dag> ret1 = [(set P.DstVT:$vdst, 1108 !if(HasExplicitClamp, 1109 (DivergentFragOrOp<node, P>.ret src0_dag, clamp_dag), 1110 (DivergentFragOrOp<node, P>.ret src0_dag)))]; 1111 1112 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1113 !if(!eq(P.NumSrcArgs, 2), ret2, 1114 ret1)); 1115} 1116 1117class getVOP3OpSelPat<VOPProfile P, SDPatternOperator node> { 1118 list<dag> ret3 = [(set P.DstVT:$vdst, 1119 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)), 1120 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)), 1121 (P.Src2VT (VOP3OpSel P.Src2VT:$src2, i32:$src2_modifiers))))]; 1122 1123 list<dag> ret2 = [(set P.DstVT:$vdst, 1124 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)), 1125 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))]; 1126 1127 list<dag> ret1 = [(set P.DstVT:$vdst, 1128 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))))]; 1129 1130 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1131 !if(!eq(P.NumSrcArgs, 2), ret2, 1132 ret1)); 1133} 1134 1135class getVOP3OpSelModPat<VOPProfile P, SDPatternOperator node> { 1136 list<dag> ret3 = [(set P.DstVT:$vdst, 1137 (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers), 1138 (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 1139 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)), 1140 (P.Src2VT (VOP3OpSelMods P.Src2VT:$src2, i32:$src2_modifiers))))]; 1141 1142 list<dag> ret2 = [(set P.DstVT:$vdst, 1143 (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers)), 1144 (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 1145 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))]; 1146 1147 list<dag> ret1 = [(set P.DstVT:$vdst, 1148 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))))]; 1149 1150 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1151 !if(!eq(P.NumSrcArgs, 2), ret2, 1152 ret1)); 1153} 1154 1155class getVOP3FromVOP2Pat<VOPProfile P, SDPatternOperator node> { 1156 list<dag> ret = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]; 1157} 1158// In VOP1, we can have clamp and omod even if !HasModifiers 1159class getVOP3Pat<VOPProfile P, SDPatternOperator node> { 1160 dag src0 = 1161 !if(P.HasOMod, 1162 !if(P.HasClamp, 1163 (VOP3Mods0 P.Src0VT:$src0, i1:$clamp, i32:$omod), 1164 (VOP3Mods0 P.Src0VT:$src0, i32:$omod)), // impossible? 1165 !if(P.HasClamp, 1166 (VOP3Mods0 P.Src0VT:$src0, i1:$clamp), 1167 (VOP3Mods0 P.Src0VT:$src0)) 1168 ); 1169 list<dag> ret3 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), P.Src1VT:$src1, P.Src2VT:$src2))]; 1170 1171 list<dag> ret2 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), P.Src1VT:$src1))]; 1172 1173 list<dag> ret1 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))]; 1174 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1175 !if(!eq(P.NumSrcArgs, 2), ret2, 1176 ret1)); 1177} 1178 1179class getVOP3ClampPat<VOPProfile P, SDPatternOperator node> { 1180 list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i1:$clamp))]; 1181 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))]; 1182 list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, i1:$clamp))]; 1183 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1184 !if(!eq(P.NumSrcArgs, 2), ret2, 1185 ret1)); 1186} 1187 1188class getVOP3MAIPat<VOPProfile P, SDPatternOperator node> { 1189 list<dag> ret = !if(!eq(P.Src0VT, P.Src1VT), 1190 // mfma 1191 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, 1192 timm:$cbsz, timm:$abid, timm:$blgp))], 1193 // smfmac 1194 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i32:$idx, 1195 timm:$cbsz, timm:$abid))]); 1196} 1197 1198class VOP3Features<bit Clamp, bit OpSel, bit Packed, bit MAI> { 1199 bit HasClamp = Clamp; 1200 bit HasOpSel = OpSel; 1201 bit IsPacked = Packed; 1202 bit IsMAI = MAI; 1203} 1204 1205def VOP3_REGULAR : VOP3Features<0, 0, 0, 0>; 1206def VOP3_CLAMP : VOP3Features<1, 0, 0, 0>; 1207def VOP3_OPSEL : VOP3Features<1, 1, 0, 0>; 1208def VOP3_PACKED : VOP3Features<1, 1, 1, 0>; 1209def VOP3_MAI : VOP3Features<0, 0, 0, 1>; 1210 1211class VOP3_Profile_Base<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOPProfile<P.ArgVT> { 1212 1213 let HasClamp = !if(Features.HasClamp, 1, P.HasClamp); 1214 let HasOpSel = !if(Features.HasOpSel, 1, P.HasOpSel); 1215 let IsMAI = !if(Features.IsMAI, 1, P.IsMAI); 1216 let IsPacked = !if(Features.IsPacked, 1, P.IsPacked); 1217 1218 let HasModifiers = 1219 !if (Features.IsMAI, 0, 1220 !or(Features.IsPacked, Features.HasOpSel, P.HasModifiers)); 1221} 1222 1223class VOP3_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOP3_Profile_Base<P, Features> { 1224 let IsSingle = 1; 1225 1226} 1227 1228// consistently gives instructions a _e64 suffix 1229multiclass VOP3Inst_Pseudo_Wrapper<string opName, VOPProfile P, list<dag> pattern = [], bit VOP3Only = 0> { 1230 def _e64 : VOP3_Pseudo<opName, P, pattern, VOP3Only>; 1231} 1232 1233class VOP3InstBase<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit IsVOP2 = 0> : 1234 VOP3_Pseudo<OpName, P, 1235 !if(P.HasOpSel, 1236 !if(P.HasModifiers, 1237 getVOP3OpSelModPat<P, node>.ret, 1238 getVOP3OpSelPat<P, node>.ret), 1239 !if(P.HasModifiers, 1240 getVOP3ModPat<P, node>.ret, 1241 !if(IsVOP2, 1242 getVOP3FromVOP2Pat<P, node>.ret, 1243 !if(P.HasIntClamp, 1244 getVOP3ClampPat<P, node>.ret, 1245 !if (P.IsMAI, 1246 getVOP3MAIPat<P, node>.ret, 1247 getVOP3Pat<P, node>.ret))))), 1248 0, P.HasOpSel> { 1249 1250 let IntClamp = P.HasIntClamp; 1251 let AsmMatchConverter = 1252 !if(P.HasOpSel, 1253 "cvtVOP3OpSel", 1254 !if(!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), 1255 "cvtVOP3", 1256 "")); 1257} 1258 1259multiclass VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> { 1260 def _e64 : VOP3InstBase<OpName, P, node>; 1261 let SubtargetPredicate = isGFX11Plus in { 1262 foreach _ = BoolToList<P.HasExtVOP3DPP>.ret in 1263 def _e64_dpp : VOP3_DPP_Pseudo <OpName, P>; 1264 } // end SubtargetPredicate = isGFX11Plus 1265} 1266 1267//===----------------------------------------------------------------------===// 1268// VOP3 DPP 1269//===----------------------------------------------------------------------===// 1270 1271class Base_VOP3_DPP16<bits<10> op, VOP_DPP_Pseudo ps, string opName = ps.OpName> 1272 : VOP3_DPP<op, opName, ps.Pfl, 1> { 1273 let hasSideEffects = ps.hasSideEffects; 1274 let Defs = ps.Defs; 1275 let SchedRW = ps.SchedRW; 1276 let Uses = ps.Uses; 1277 let AssemblerPredicate = HasDPP16; 1278 let SubtargetPredicate = HasDPP16; 1279 let OtherPredicates = ps.OtherPredicates; 1280} 1281 1282class VOP3_DPP16<bits<10> op, VOP_DPP_Pseudo ps, int subtarget, 1283 string opName = ps.OpName> 1284 : Base_VOP3_DPP16<op, ps, opName>, SIMCInstr<ps.PseudoInstr, subtarget>; 1285 1286class Base_VOP3_DPP8<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName> 1287 : VOP3_DPP8<op, opName, ps.Pfl> { 1288 let hasSideEffects = ps.hasSideEffects; 1289 let Defs = ps.Defs; 1290 let SchedRW = ps.SchedRW; 1291 let Uses = ps.Uses; 1292 1293 let OtherPredicates = ps.OtherPredicates; 1294} 1295 1296class Base_VOP3b_DPP16<bits<10> op, VOP_DPP_Pseudo ps, 1297 string opName = ps.OpName> 1298 : Base_VOP3_DPP16<op, ps, opName> { 1299 bits<7> sdst; 1300 let Inst{14 - 8} = sdst; 1301} 1302 1303class VOP3b_DPP8_Base<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName> 1304 : Base_VOP3_DPP8<op, ps, opName> { 1305 bits<7> sdst; 1306 let Inst{14 - 8} = sdst; 1307} 1308 1309//===----------------------------------------------------------------------===// 1310// VOP3 GFX11 1311//===----------------------------------------------------------------------===// 1312 1313let AssemblerPredicate = isGFX11Only, 1314 DecoderNamespace = "GFX11" in { 1315 multiclass VOP3_Real_Base_gfx11<bits<10> op, string opName = NAME, 1316 bit isSingle = 0> { 1317 defvar ps = !cast<VOP_Pseudo>(opName#"_e64"); 1318 let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in { 1319 foreach _ = BoolToList<ps.Pfl.HasOpSel>.ret in 1320 def _e64_gfx11 : 1321 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1322 VOP3OpSel_gfx11<op, ps.Pfl>; 1323 foreach _ = BoolToList<!not(ps.Pfl.HasOpSel)>.ret in 1324 def _e64_gfx11 : 1325 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1326 VOP3e_gfx11<op, ps.Pfl>; 1327 } 1328 } 1329 multiclass VOP3_Real_with_name_gfx11<bits<10> op, string opName, 1330 string asmName, bit isSingle = 0> { 1331 defvar ps = !cast<VOP_Pseudo>(opName#"_e64"); 1332 let AsmString = asmName # ps.AsmOperands, 1333 IsSingle = !or(isSingle, ps.Pfl.IsSingle) in { 1334 foreach _ = BoolToList<ps.Pfl.HasOpSel>.ret in 1335 def _e64_gfx11 : 1336 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1337 VOP3OpSel_gfx11<op, ps.Pfl>, 1338 MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX11Plus]>; 1339 foreach _ = BoolToList<!not(ps.Pfl.HasOpSel)>.ret in 1340 def _e64_gfx11 : 1341 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1342 VOP3e_gfx11<op, ps.Pfl>, 1343 MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX11Plus]>; 1344 } 1345 } 1346 // for READLANE/WRITELANE 1347 multiclass VOP3_Real_No_Suffix_gfx11<bits<10> op, string opName = NAME> { 1348 defvar ps = !cast<VOP_Pseudo>(opName); 1349 def _e64_gfx11 : 1350 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1351 VOP3e_gfx11<op, ps.Pfl>; 1352 } 1353 multiclass VOP3_Real_dpp_Base_gfx11<bits<10> op, string opName = NAME> { 1354 def _e64_dpp_gfx11 : VOP3_DPP16<op, !cast<VOP_DPP_Pseudo>(opName#"_e64"#"_dpp"), SIEncodingFamily.GFX11> { 1355 let DecoderNamespace = "DPPGFX11"; 1356 } 1357 } 1358 multiclass VOP3_Real_dpp_with_name_gfx11<bits<10> op, string opName, 1359 string asmName> { 1360 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1361 let AsmString = asmName # ps.Pfl.AsmVOP3DPP16, DecoderNamespace = "DPPGFX11" in { 1362 defm NAME : VOP3_Real_dpp_Base_gfx11<op, opName>; 1363 } 1364 } 1365 multiclass VOP3_Real_dpp8_Base_gfx11<bits<10> op, string opName = NAME> { 1366 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1367 def _e64_dpp8_gfx11 : Base_VOP3_DPP8<op, ps> { 1368 let DecoderNamespace = "DPP8GFX11"; 1369 } 1370 } 1371 multiclass VOP3_Real_dpp8_with_name_gfx11<bits<10> op, string opName, 1372 string asmName> { 1373 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1374 let AsmString = asmName # ps.Pfl.AsmVOP3DPP8, DecoderNamespace = "DPP8GFX11" in { 1375 defm NAME : VOP3_Real_dpp8_Base_gfx11<op, opName>; 1376 } 1377 } 1378 multiclass VOP3be_Real_gfx11<bits<10> op, string opName, string asmName, 1379 bit isSingle = 0> { 1380 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1381 let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in 1382 def _e64_gfx11 : 1383 VOP3_Real<ps, SIEncodingFamily.GFX11, asmName>, 1384 VOP3be_gfx11<op, ps.Pfl> ; 1385 } 1386 multiclass VOP3be_Real_dpp_gfx11<bits<10> op, string opName, string asmName> { 1387 defvar ps = !cast<VOP3_Pseudo>(opName #"_e64"); 1388 defvar dpp_ps = !cast<VOP_DPP_Pseudo>(opName #"_e64" #"_dpp"); 1389 def _e64_dpp_gfx11 : Base_VOP3b_DPP16<op, dpp_ps, asmName>, 1390 SIMCInstr<dpp_ps.PseudoInstr, SIEncodingFamily.GFX11> { 1391 let DecoderNamespace = "DPPGFX11"; 1392 } 1393 } 1394 multiclass VOP3be_Real_dpp8_gfx11<bits<10> op, string opName, string asmName> { 1395 defvar ps = !cast<VOP3_Pseudo>(opName #"_e64"); 1396 def _e64_dpp8_gfx11 : VOP3b_DPP8_Base<op, ps, asmName> { 1397 let DecoderNamespace = "DPP8GFX11"; 1398 } 1399 } 1400} // End AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" 1401 1402// VOP1 and VOP2 depend on these triple defs 1403multiclass VOP3_Realtriple_gfx11<bits<10> op, 1404 bit isSingle = 0, string opName = NAME> : 1405 VOP3_Real_Base_gfx11<op, opName, isSingle>, 1406 VOP3_Real_dpp_Base_gfx11<op, opName>, 1407 VOP3_Real_dpp8_Base_gfx11<op, opName>; 1408 1409multiclass VOP3Only_Realtriple_gfx11<bits<10> op> : 1410 VOP3_Realtriple_gfx11<op, 1>; 1411 1412multiclass VOP3_Realtriple_with_name_gfx11<bits<10> op, string opName, 1413 string asmName, bit isSingle = 0> : 1414 VOP3_Real_with_name_gfx11<op, opName, asmName, isSingle>, 1415 VOP3_Real_dpp_with_name_gfx11<op, opName, asmName>, 1416 VOP3_Real_dpp8_with_name_gfx11<op, opName, asmName>; 1417 1418multiclass VOP3Only_Realtriple_with_name_gfx11<bits<10> op, string opName, 1419 string asmName> : 1420 VOP3_Realtriple_with_name_gfx11<op, opName, asmName, 1>; 1421 1422multiclass VOP3be_Realtriple_gfx11< 1423 bits<10> op, bit isSingle = 0, string opName = NAME, 1424 string asmName = !cast<VOP_Pseudo>(opName#"_e64").Mnemonic> : 1425 VOP3be_Real_gfx11<op, opName, asmName, isSingle>, 1426 VOP3be_Real_dpp_gfx11<op, opName, asmName>, 1427 VOP3be_Real_dpp8_gfx11<op, opName, asmName>; 1428 1429multiclass VOP3beOnly_Realtriple_gfx11<bits<10> op> : 1430 VOP3be_Realtriple_gfx11<op, 1>; 1431 1432include "VOPCInstructions.td" 1433include "VOP1Instructions.td" 1434include "VOP2Instructions.td" 1435include "VOP3Instructions.td" 1436include "VOP3PInstructions.td" 1437include "VOPDInstructions.td" 1438 1439 1440class VOPInfoTable <string Format> : GenericTable { 1441 let FilterClass = Format # "_Real"; 1442 let CppTypeName = "VOPInfo"; 1443 let Fields = ["Opcode", "IsSingle"]; 1444 1445 let PrimaryKey = ["Opcode"]; 1446 let PrimaryKeyName = "get" # Format # "OpcodeHelper"; 1447} 1448 1449def VOP1InfoTable : VOPInfoTable<"VOP1">; 1450def VOP2InfoTable : VOPInfoTable<"VOP2">; 1451def VOP3InfoTable : VOPInfoTable<"VOP3">; 1452 1453class VOPC64Table <string Format> : GenericTable { 1454 let FilterClass = "VOPC64_" # Format # "_Base"; 1455 let CppTypeName = "VOPC64DPPInfo"; 1456 let Fields = ["Opcode"]; 1457 1458 let PrimaryKey = ["Opcode"]; 1459 let PrimaryKeyName = "isVOPC64" # Format # "OpcodeHelper"; 1460} 1461 1462def VOPC64DPPTable : VOPC64Table<"DPP">; 1463def VOPC64DPP8Table : VOPC64Table<"DPP8">; 1464