1//===-- VOP3PInstructions.td - Vector Instruction Defintions --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// VOP3P Classes 12//===----------------------------------------------------------------------===// 13 14class VOP3PInst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> : 15 VOP3P_Pseudo<OpName, P, 16 !if(P.HasModifiers, getVOP3PModPat<P, node>.ret, getVOP3Pat<P, node>.ret) 17>; 18 19// Non-packed instructions that use the VOP3P encoding. 20// VOP3 neg/abs and VOP3P opsel/opsel_hi modifiers are allowed. 21class VOP3_VOP3PInst<string OpName, VOPProfile P, bit UseTiedOutput = 0, 22 SDPatternOperator node = null_frag> : 23 VOP3P_Pseudo<OpName, P> { 24 // These operands are only sort of f16 operands. Depending on 25 // op_sel_hi, these may be interpreted as f32. The inline immediate 26 // values are really f16 converted to f32, so we treat these as f16 27 // operands. 28 let InOperandList = 29 !con( 30 !con( 31 (ins FP16InputMods:$src0_modifiers, VCSrc_f16:$src0, 32 FP16InputMods:$src1_modifiers, VCSrc_f16:$src1, 33 FP16InputMods:$src2_modifiers, VCSrc_f16:$src2, 34 clampmod:$clamp), 35 !if(UseTiedOutput, (ins VGPR_32:$vdst_in), (ins))), 36 (ins op_sel:$op_sel, op_sel_hi:$op_sel_hi)); 37 38 let Constraints = !if(UseTiedOutput, "$vdst = $vdst_in", ""); 39 let DisableEncoding = !if(UseTiedOutput, "$vdst_in", ""); 40 let AsmOperands = 41 " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$op_sel$op_sel_hi$clamp"; 42} 43 44let isCommutable = 1 in { 45def V_PK_MAD_I16 : VOP3PInst<"v_pk_mad_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16_V2I16>>; 46def V_PK_MAD_U16 : VOP3PInst<"v_pk_mad_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16_V2I16>>; 47 48let FPDPRounding = 1 in { 49def V_PK_FMA_F16 : VOP3PInst<"v_pk_fma_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16_V2F16>, fma>; 50def V_PK_ADD_F16 : VOP3PInst<"v_pk_add_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16>, fadd>; 51def V_PK_MUL_F16 : VOP3PInst<"v_pk_mul_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16>, fmul>; 52} // End FPDPRounding = 1 53def V_PK_MAX_F16 : VOP3PInst<"v_pk_max_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16>, fmaxnum_like>; 54def V_PK_MIN_F16 : VOP3PInst<"v_pk_min_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16>, fminnum_like>; 55 56def V_PK_ADD_U16 : VOP3PInst<"v_pk_add_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, add>; 57def V_PK_ADD_I16 : VOP3PInst<"v_pk_add_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>>; 58def V_PK_MUL_LO_U16 : VOP3PInst<"v_pk_mul_lo_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, mul>; 59 60def V_PK_MIN_I16 : VOP3PInst<"v_pk_min_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, smin>; 61def V_PK_MIN_U16 : VOP3PInst<"v_pk_min_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, umin>; 62def V_PK_MAX_I16 : VOP3PInst<"v_pk_max_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, smax>; 63def V_PK_MAX_U16 : VOP3PInst<"v_pk_max_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, umax>; 64} 65 66def V_PK_SUB_U16 : VOP3PInst<"v_pk_sub_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>>; 67def V_PK_SUB_I16 : VOP3PInst<"v_pk_sub_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, sub>; 68 69def V_PK_LSHLREV_B16 : VOP3PInst<"v_pk_lshlrev_b16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, lshl_rev>; 70def V_PK_ASHRREV_I16 : VOP3PInst<"v_pk_ashrrev_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, ashr_rev>; 71def V_PK_LSHRREV_B16 : VOP3PInst<"v_pk_lshrrev_b16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, lshr_rev>; 72 73multiclass MadFmaMixPats<SDPatternOperator fma_like, 74 Instruction mix_inst, 75 Instruction mixlo_inst, 76 Instruction mixhi_inst> { 77 def : GCNPat < 78 (f16 (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)), 79 (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)), 80 (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_modifiers))))), 81 (mixlo_inst $src0_modifiers, $src0, 82 $src1_modifiers, $src1, 83 $src2_modifiers, $src2, 84 DSTCLAMP.NONE, 85 (i32 (IMPLICIT_DEF))) 86 >; 87 88 // FIXME: Special case handling for maxhi (especially for clamp) 89 // because dealing with the write to high half of the register is 90 // difficult. 91 def : GCNPat < 92 (build_vector f16:$elt0, (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)), 93 (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)), 94 (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_modifiers))))), 95 (v2f16 (mixhi_inst $src0_modifiers, $src0, 96 $src1_modifiers, $src1, 97 $src2_modifiers, $src2, 98 DSTCLAMP.NONE, 99 $elt0)) 100 >; 101 102 def : GCNPat < 103 (build_vector 104 f16:$elt0, 105 (AMDGPUclamp (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)), 106 (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)), 107 (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_modifiers)))))), 108 (v2f16 (mixhi_inst $src0_modifiers, $src0, 109 $src1_modifiers, $src1, 110 $src2_modifiers, $src2, 111 DSTCLAMP.ENABLE, 112 $elt0)) 113 >; 114 115 def : GCNPat < 116 (AMDGPUclamp (build_vector 117 (fpround (fma_like (f32 (VOP3PMadMixMods f16:$lo_src0, i32:$lo_src0_modifiers)), 118 (f32 (VOP3PMadMixMods f16:$lo_src1, i32:$lo_src1_modifiers)), 119 (f32 (VOP3PMadMixMods f16:$lo_src2, i32:$lo_src2_modifiers)))), 120 (fpround (fma_like (f32 (VOP3PMadMixMods f16:$hi_src0, i32:$hi_src0_modifiers)), 121 (f32 (VOP3PMadMixMods f16:$hi_src1, i32:$hi_src1_modifiers)), 122 (f32 (VOP3PMadMixMods f16:$hi_src2, i32:$hi_src2_modifiers)))))), 123 (v2f16 (mixhi_inst $hi_src0_modifiers, $hi_src0, 124 $hi_src1_modifiers, $hi_src1, 125 $hi_src2_modifiers, $hi_src2, 126 DSTCLAMP.ENABLE, 127 (mixlo_inst $lo_src0_modifiers, $lo_src0, 128 $lo_src1_modifiers, $lo_src1, 129 $lo_src2_modifiers, $lo_src2, 130 DSTCLAMP.ENABLE, 131 (i32 (IMPLICIT_DEF))))) 132 >; 133} 134 135let SubtargetPredicate = HasMadMixInsts in { 136// These are VOP3a-like opcodes which accept no omod. 137// Size of src arguments (16/32) is controlled by op_sel. 138// For 16-bit src arguments their location (hi/lo) are controlled by op_sel_hi. 139let isCommutable = 1 in { 140def V_MAD_MIX_F32 : VOP3_VOP3PInst<"v_mad_mix_f32", VOP3_Profile<VOP_F32_F16_F16_F16, VOP3_OPSEL>>; 141 142let FPDPRounding = 1 in { 143// Clamp modifier is applied after conversion to f16. 144def V_MAD_MIXLO_F16 : VOP3_VOP3PInst<"v_mad_mixlo_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, 1>; 145 146let ClampLo = 0, ClampHi = 1 in { 147def V_MAD_MIXHI_F16 : VOP3_VOP3PInst<"v_mad_mixhi_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, 1>; 148} 149} // End FPDPRounding = 1 150} 151 152defm : MadFmaMixPats<fmad, V_MAD_MIX_F32, V_MAD_MIXLO_F16, V_MAD_MIXHI_F16>; 153} // End SubtargetPredicate = HasMadMixInsts 154 155 156// Essentially the same as the mad_mix versions 157let SubtargetPredicate = HasFmaMixInsts in { 158let isCommutable = 1 in { 159def V_FMA_MIX_F32 : VOP3_VOP3PInst<"v_fma_mix_f32", VOP3_Profile<VOP_F32_F16_F16_F16, VOP3_OPSEL>>; 160 161let FPDPRounding = 1 in { 162// Clamp modifier is applied after conversion to f16. 163def V_FMA_MIXLO_F16 : VOP3_VOP3PInst<"v_fma_mixlo_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, 1>; 164 165let ClampLo = 0, ClampHi = 1 in { 166def V_FMA_MIXHI_F16 : VOP3_VOP3PInst<"v_fma_mixhi_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, 1>; 167} 168} // End FPDPRounding = 1 169} 170 171defm : MadFmaMixPats<fma, V_FMA_MIX_F32, V_FMA_MIXLO_F16, V_FMA_MIXHI_F16>; 172} 173 174// Defines patterns that extract signed 4bit from each Idx[0]. 175foreach Idx = [[0,28],[4,24],[8,20],[12,16],[16,12],[20,8],[24,4]] in 176 def ExtractSigned4bit_#Idx[0] : PatFrag<(ops node:$src), 177 (sra (shl node:$src, (i32 Idx[1])), (i32 28))>; 178 179// Defines code pattern that extracts U(unsigned/signed) 4/8bit from FromBitIndex. 180class Extract<int FromBitIndex, int BitMask, bit U>: PatFrag< 181 (ops node:$src), 182 !if (!or (!and (!eq (BitMask, 255), !eq (FromBitIndex, 24)), !eq (FromBitIndex, 28)), // last element 183 !if (U, (srl node:$src, (i32 FromBitIndex)), (sra node:$src, (i32 FromBitIndex))), 184 !if (!eq (FromBitIndex, 0), // first element 185 !if (U, (and node:$src, (i32 BitMask)), 186 !if (!eq (BitMask, 15), (!cast<PatFrag>("ExtractSigned4bit_"#FromBitIndex) node:$src), 187 (sext_inreg node:$src, i8))), 188 !if (U, (and (srl node:$src, (i32 FromBitIndex)), (i32 BitMask)), 189 !if (!eq (BitMask, 15), (!cast<PatFrag>("ExtractSigned4bit_"#FromBitIndex) node:$src), 190 (sext_inreg (srl node:$src, (i32 FromBitIndex)), i8)))))>; 191 192 193foreach Type = ["I", "U"] in 194 foreach Index = 0-3 in { 195 // Defines patterns that extract each Index'ed 8bit from an unsigned 196 // 32bit scalar value; 197 def #Type#Index#"_8bit" : Extract<!shl(Index, 3), 255, !if (!eq (Type, "U"), 1, 0)>; 198 199 // Defines multiplication patterns where the multiplication is happening on each 200 // Index'ed 8bit of a 32bit scalar value. 201 202 def Mul#Type#_Elt#Index : PatFrag< 203 (ops node:$src0, node:$src1), 204 (!cast<HasOneUseBinOp>(!if (!eq (Type, "I"), AMDGPUmul_i24_oneuse, AMDGPUmul_u24_oneuse)) 205 (!cast<Extract>(#Type#Index#"_8bit") node:$src0), 206 (!cast<Extract>(#Type#Index#"_8bit") node:$src1))>; 207 } 208 209// Different variants of dot8 patterns cause a huge increase in the compile time. 210// Define non-associative/commutative add/mul to prevent permutation in the dot8 211// pattern. 212def NonACAdd : SDNode<"ISD::ADD" , SDTIntBinOp>; 213def NonACAdd_oneuse : HasOneUseBinOp<NonACAdd>; 214 215def NonACAMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24" , SDTIntBinOp>; 216def NonACAMDGPUmul_u24_oneuse : HasOneUseBinOp<NonACAMDGPUmul_u24>; 217 218def NonACAMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24" , SDTIntBinOp>; 219def NonACAMDGPUmul_i24_oneuse : HasOneUseBinOp<NonACAMDGPUmul_i24>; 220 221foreach Type = ["I", "U"] in 222 foreach Index = 0-7 in { 223 // Defines patterns that extract each Index'ed 4bit from an unsigned 224 // 32bit scalar value; 225 def #Type#Index#"_4bit" : Extract<!shl(Index, 2), 15, !if (!eq (Type, "U"), 1, 0)>; 226 227 // Defines multiplication patterns where the multiplication is happening on each 228 // Index'ed 8bit of a 32bit scalar value. 229 def Mul#Type#Index#"_4bit" : PatFrag< 230 (ops node:$src0, node:$src1), 231 (!cast<HasOneUseBinOp>(!if (!eq (Type, "I"), NonACAMDGPUmul_i24_oneuse, NonACAMDGPUmul_u24_oneuse)) 232 (!cast<Extract>(#Type#Index#"_4bit") node:$src0), 233 (!cast<Extract>(#Type#Index#"_4bit") node:$src1))>; 234 } 235 236class UDot2Pat<Instruction Inst> : GCNPat < 237 (add (add_oneuse (AMDGPUmul_u24_oneuse (srl i32:$src0, (i32 16)), 238 (srl i32:$src1, (i32 16))), i32:$src2), 239 (AMDGPUmul_u24_oneuse (and i32:$src0, (i32 65535)), 240 (and i32:$src1, (i32 65535))) 241 ), 242 (Inst (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0)) 243>; 244 245class SDot2Pat<Instruction Inst> : GCNPat < 246 (add (add_oneuse (AMDGPUmul_i24_oneuse (sra i32:$src0, (i32 16)), 247 (sra i32:$src1, (i32 16))), i32:$src2), 248 (AMDGPUmul_i24_oneuse (sext_inreg i32:$src0, i16), 249 (sext_inreg i32:$src1, i16))), 250 (Inst (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0)) 251>; 252 253let SubtargetPredicate = HasDLInsts in { 254 255def V_DOT2_F32_F16 : VOP3PInst<"v_dot2_f32_f16", VOP3_Profile<VOP_F32_V2F16_V2F16_F32>>; 256def V_DOT2_I32_I16 : VOP3PInst<"v_dot2_i32_i16", VOP3_Profile<VOP_I32_V2I16_V2I16_I32>>; 257def V_DOT2_U32_U16 : VOP3PInst<"v_dot2_u32_u16", VOP3_Profile<VOP_I32_V2I16_V2I16_I32>>; 258def V_DOT4_I32_I8 : VOP3PInst<"v_dot4_i32_i8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>>; 259def V_DOT4_U32_U8 : VOP3PInst<"v_dot4_u32_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>>; 260def V_DOT8_I32_I4 : VOP3PInst<"v_dot8_i32_i4", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>>; 261def V_DOT8_U32_U4 : VOP3PInst<"v_dot8_u32_u4", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>>; 262 263multiclass DotPats<SDPatternOperator dot_op, 264 VOP3PInst dot_inst> { 265 def : GCNPat < 266 (dot_op (dot_inst.Pfl.Src0VT (VOP3PMods0 dot_inst.Pfl.Src0VT:$src0, i32:$src0_modifiers)), 267 (dot_inst.Pfl.Src1VT (VOP3PMods dot_inst.Pfl.Src1VT:$src1, i32:$src1_modifiers)), 268 (dot_inst.Pfl.Src2VT (VOP3PMods dot_inst.Pfl.Src2VT:$src2, i32:$src2_modifiers)), i1:$clamp), 269 (dot_inst $src0_modifiers, $src0, $src1_modifiers, $src1, $src2_modifiers, $src2, (as_i1imm $clamp))>; 270} 271 272defm : DotPats<AMDGPUfdot2, V_DOT2_F32_F16>; 273defm : DotPats<int_amdgcn_sdot2, V_DOT2_I32_I16>; 274defm : DotPats<int_amdgcn_udot2, V_DOT2_U32_U16>; 275defm : DotPats<int_amdgcn_sdot4, V_DOT4_I32_I8>; 276defm : DotPats<int_amdgcn_udot4, V_DOT4_U32_U8>; 277defm : DotPats<int_amdgcn_sdot8, V_DOT8_I32_I4>; 278defm : DotPats<int_amdgcn_udot8, V_DOT8_U32_U4>; 279 280def : UDot2Pat<V_DOT2_U32_U16>; 281def : SDot2Pat<V_DOT2_I32_I16>; 282 283foreach Type = ["U", "I"] in 284 def : GCNPat < 285 !cast<dag>(!foldl((i32 i32:$src2), [0, 1, 2, 3], lhs, y, 286 (add_oneuse lhs, (!cast<PatFrag>("Mul"#Type#"_Elt"#y) i32:$src0, i32:$src1)))), 287 (!cast<VOP3PInst>("V_DOT4_"#Type#"32_"#Type#8) (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))>; 288 289foreach Type = ["U", "I"] in 290 def : GCNPat < 291 !cast<dag>(!foldl((add_oneuse i32:$src2, (!cast<PatFrag>("Mul"#Type#"0_4bit") i32:$src0, i32:$src1)), 292 [1, 2, 3, 4, 5, 6, 7], lhs, y, 293 (NonACAdd_oneuse lhs, (!cast<PatFrag>("Mul"#Type#y#"_4bit") i32:$src0, i32:$src1)))), 294 (!cast<VOP3PInst>("V_DOT8_"#Type#"32_"#Type#4) (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))>; 295 296// Different variants of dot8 code-gen dag patterns are not generated through table-gen due to a huge increase 297// in the compile time. Directly handle the pattern generated by the FE here. 298foreach Type = ["U", "I"] in 299 def : GCNPat < 300 !cast<dag>(!foldl((add_oneuse i32:$src2, (!cast<PatFrag>("Mul"#Type#"0_4bit") i32:$src0, i32:$src1)), 301 [7, 1, 2, 3, 4, 5, 6], lhs, y, 302 (NonACAdd_oneuse lhs, (!cast<PatFrag>("Mul"#Type#y#"_4bit") i32:$src0, i32:$src1)))), 303 (!cast<VOP3PInst>("V_DOT8_"#Type#"32_"#Type#4) (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))>; 304 305} // End SubtargetPredicate = HasDLInsts 306 307multiclass VOP3P_Real_vi<bits<10> op> { 308 def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>, 309 VOP3Pe <op, !cast<VOP3_Pseudo>(NAME).Pfl> { 310 let AssemblerPredicates = [HasVOP3PInsts]; 311 let DecoderNamespace = "VI"; 312 } 313} 314 315defm V_PK_MAD_I16 : VOP3P_Real_vi <0x380>; 316defm V_PK_MUL_LO_U16 : VOP3P_Real_vi <0x381>; 317defm V_PK_ADD_I16 : VOP3P_Real_vi <0x382>; 318defm V_PK_SUB_I16 : VOP3P_Real_vi <0x383>; 319defm V_PK_LSHLREV_B16 : VOP3P_Real_vi <0x384>; 320defm V_PK_LSHRREV_B16 : VOP3P_Real_vi <0x385>; 321defm V_PK_ASHRREV_I16 : VOP3P_Real_vi <0x386>; 322defm V_PK_MAX_I16 : VOP3P_Real_vi <0x387>; 323defm V_PK_MIN_I16 : VOP3P_Real_vi <0x388>; 324defm V_PK_MAD_U16 : VOP3P_Real_vi <0x389>; 325 326defm V_PK_ADD_U16 : VOP3P_Real_vi <0x38a>; 327defm V_PK_SUB_U16 : VOP3P_Real_vi <0x38b>; 328defm V_PK_MAX_U16 : VOP3P_Real_vi <0x38c>; 329defm V_PK_MIN_U16 : VOP3P_Real_vi <0x38d>; 330defm V_PK_FMA_F16 : VOP3P_Real_vi <0x38e>; 331defm V_PK_ADD_F16 : VOP3P_Real_vi <0x38f>; 332defm V_PK_MUL_F16 : VOP3P_Real_vi <0x390>; 333defm V_PK_MIN_F16 : VOP3P_Real_vi <0x391>; 334defm V_PK_MAX_F16 : VOP3P_Real_vi <0x392>; 335 336 337let SubtargetPredicate = HasMadMixInsts in { 338defm V_MAD_MIX_F32 : VOP3P_Real_vi <0x3a0>; 339defm V_MAD_MIXLO_F16 : VOP3P_Real_vi <0x3a1>; 340defm V_MAD_MIXHI_F16 : VOP3P_Real_vi <0x3a2>; 341} 342 343let SubtargetPredicate = HasFmaMixInsts in { 344let DecoderNamespace = "GFX9_DL" in { 345// The mad_mix instructions were renamed and their behaviors changed, 346// but the opcode stayed the same so we need to put these in a 347// different DecoderNamespace to avoid the ambiguity. 348defm V_FMA_MIX_F32 : VOP3P_Real_vi <0x3a0>; 349defm V_FMA_MIXLO_F16 : VOP3P_Real_vi <0x3a1>; 350defm V_FMA_MIXHI_F16 : VOP3P_Real_vi <0x3a2>; 351} 352} 353 354 355let SubtargetPredicate = HasDLInsts in { 356 357defm V_DOT2_F32_F16 : VOP3P_Real_vi <0x3a3>; 358defm V_DOT2_I32_I16 : VOP3P_Real_vi <0x3a6>; 359defm V_DOT2_U32_U16 : VOP3P_Real_vi <0x3a7>; 360defm V_DOT4_I32_I8 : VOP3P_Real_vi <0x3a8>; 361defm V_DOT4_U32_U8 : VOP3P_Real_vi <0x3a9>; 362defm V_DOT8_I32_I4 : VOP3P_Real_vi <0x3aa>; 363defm V_DOT8_U32_U4 : VOP3P_Real_vi <0x3ab>; 364 365} // End SubtargetPredicate = HasDLInsts 366