1//===-- VOP3Instructions.td - Vector Instruction Definitions --------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// VOP3 Classes 11//===----------------------------------------------------------------------===// 12 13class getVOP3ModPat<VOPProfile P, SDPatternOperator node> { 14 dag src0 = !if(P.HasOMod, 15 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 16 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)); 17 18 list<dag> ret3 = [(set P.DstVT:$vdst, 19 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 20 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), 21 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))]; 22 23 list<dag> ret2 = [(set P.DstVT:$vdst, 24 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 25 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))]; 26 27 list<dag> ret1 = [(set P.DstVT:$vdst, 28 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))]; 29 30 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 31 !if(!eq(P.NumSrcArgs, 2), ret2, 32 ret1)); 33} 34 35class getVOP3PModPat<VOPProfile P, SDPatternOperator node, bit HasExplicitClamp> { 36 dag src0_dag = (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers)); 37 dag src1_dag = (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers)); 38 dag src2_dag = (P.Src2VT (VOP3PMods P.Src2VT:$src2, i32:$src2_modifiers)); 39 dag clamp_dag = (i1 timm:$clamp); 40 41 list<dag> ret3 = [(set P.DstVT:$vdst, 42 !if(HasExplicitClamp, 43 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, src2_dag, clamp_dag), 44 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, src2_dag)))]; 45 46 list<dag> ret2 = [(set P.DstVT:$vdst, 47 !if(HasExplicitClamp, 48 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, clamp_dag), 49 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag)))]; 50 51 list<dag> ret1 = [(set P.DstVT:$vdst, 52 !if(HasExplicitClamp, 53 (DivergentFragOrOp<node, P>.ret src0_dag, clamp_dag), 54 (DivergentFragOrOp<node, P>.ret src0_dag)))]; 55 56 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 57 !if(!eq(P.NumSrcArgs, 2), ret2, 58 ret1)); 59} 60 61class getVOP3OpSelPat<VOPProfile P, SDPatternOperator node> { 62 list<dag> ret3 = [(set P.DstVT:$vdst, 63 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)), 64 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)), 65 (P.Src2VT (VOP3OpSel P.Src2VT:$src2, i32:$src2_modifiers))))]; 66 67 list<dag> ret2 = [(set P.DstVT:$vdst, 68 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)), 69 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))]; 70 71 list<dag> ret1 = [(set P.DstVT:$vdst, 72 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))))]; 73 74 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 75 !if(!eq(P.NumSrcArgs, 2), ret2, 76 ret1)); 77} 78 79class getVOP3OpSelModPat<VOPProfile P, SDPatternOperator node> { 80 list<dag> ret3 = [(set P.DstVT:$vdst, 81 (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers), 82 (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 83 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)), 84 (P.Src2VT (VOP3OpSelMods P.Src2VT:$src2, i32:$src2_modifiers))))]; 85 86 list<dag> ret2 = [(set P.DstVT:$vdst, 87 (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers)), 88 (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 89 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))]; 90 91 list<dag> ret1 = [(set P.DstVT:$vdst, 92 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))))]; 93 94 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 95 !if(!eq(P.NumSrcArgs, 2), ret2, 96 ret1)); 97} 98 99class getVOP3Pat<VOPProfile P, SDPatternOperator node> { 100 list<dag> ret3 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))]; 101 list<dag> ret2 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$src1))]; 102 list<dag> ret1 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0))]; 103 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 104 !if(!eq(P.NumSrcArgs, 2), ret2, 105 ret1)); 106} 107 108class getVOP3ClampPat<VOPProfile P, SDPatternOperator node> { 109 list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i1:$clamp))]; 110 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))]; 111 list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, i1:$clamp))]; 112 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 113 !if(!eq(P.NumSrcArgs, 2), ret2, 114 ret1)); 115} 116 117class getVOP3MAIPat<VOPProfile P, SDPatternOperator node> { 118 list<dag> ret = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, 119 timm:$cbsz, timm:$abid, timm:$blgp))]; 120} 121 122// Consistently gives instructions a _e64 suffix. 123multiclass VOP3Inst_Pseudo_Wrapper<string opName, VOPProfile P, list<dag> pattern = [], bit VOP3Only = 0> { 124 def _e64 : VOP3_Pseudo<opName, P, pattern, VOP3Only>; 125} 126 127class VOP3InstBase<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit VOP3Only = 0> : 128 VOP3_Pseudo<OpName, P, 129 !if(P.HasOpSel, 130 !if(P.HasModifiers, 131 getVOP3OpSelModPat<P, node>.ret, 132 getVOP3OpSelPat<P, node>.ret), 133 !if(P.HasModifiers, 134 getVOP3ModPat<P, node>.ret, 135 !if(P.HasIntClamp, 136 getVOP3ClampPat<P, node>.ret, 137 !if (P.IsMAI, 138 getVOP3MAIPat<P, node>.ret, 139 getVOP3Pat<P, node>.ret)))), 140 VOP3Only, 0, P.HasOpSel> { 141 142 let IntClamp = P.HasIntClamp; 143 let AsmMatchConverter = 144 !if(P.HasOpSel, 145 "cvtVOP3OpSel", 146 !if(!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), 147 "cvtVOP3", 148 "")); 149} 150 151multiclass VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit VOP3Only = 0> { 152 def _e64 : VOP3InstBase<OpName, P, node, VOP3Only>; 153} 154 155// Special case for v_div_fmas_{f32|f64}, since it seems to be the 156// only VOP instruction that implicitly reads VCC. 157let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in { 158def VOP_F32_F32_F32_F32_VCC : VOPProfile<[f32, f32, f32, f32]> { 159 let Outs64 = (outs DstRC.RegClass:$vdst); 160} 161def VOP_F64_F64_F64_F64_VCC : VOPProfile<[f64, f64, f64, f64]> { 162 let Outs64 = (outs DstRC.RegClass:$vdst); 163} 164} 165 166class VOP3Features<bit Clamp, bit OpSel, bit Packed, bit MAI> { 167 bit HasClamp = Clamp; 168 bit HasOpSel = OpSel; 169 bit IsPacked = Packed; 170 bit IsMAI = MAI; 171} 172 173def VOP3_REGULAR : VOP3Features<0, 0, 0, 0>; 174def VOP3_CLAMP : VOP3Features<1, 0, 0, 0>; 175def VOP3_OPSEL : VOP3Features<1, 1, 0, 0>; 176def VOP3_PACKED : VOP3Features<1, 1, 1, 0>; 177def VOP3_MAI : VOP3Features<0, 0, 0, 1>; 178 179class VOP3_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOPProfile<P.ArgVT> { 180 181 let HasClamp = !if(Features.HasClamp, 1, P.HasClamp); 182 let HasOpSel = !if(Features.HasOpSel, 1, P.HasOpSel); 183 let IsMAI = !if(Features.IsMAI, 1, P.IsMAI); 184 let IsPacked = !if(Features.IsPacked, 1, P.IsPacked); 185 186 let HasModifiers = !if(Features.IsMAI, 0, !or(Features.IsPacked, P.HasModifiers)); 187 188 // FIXME: Hack to stop printing _e64 189 let Outs64 = (outs DstRC.RegClass:$vdst); 190 let Asm64 = 191 " " # !if(Features.HasOpSel, 192 getAsmVOP3OpSel<NumSrcArgs, 193 HasIntClamp, 194 P.HasOMod, 195 HasSrc0FloatMods, 196 HasSrc1FloatMods, 197 HasSrc2FloatMods>.ret, 198 !if(Features.HasClamp, 199 getAsm64<HasDst, NumSrcArgs, HasIntClamp, 200 HasModifiers, HasOMod, DstVT>.ret, 201 P.Asm64)); 202 let NeedPatGen = P.NeedPatGen; 203} 204 205class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> { 206 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 207 let Asm64 = " $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod"; 208} 209 210def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32> { 211 // FIXME: Hack to stop printing _e64 212 let DstRC = RegisterOperand<VGPR_32>; 213} 214 215def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> { 216 // FIXME: Hack to stop printing _e64 217 let DstRC = RegisterOperand<VReg_64>; 218} 219 220def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> { 221 let HasClamp = 1; 222 223 // FIXME: Hack to stop printing _e64 224 let DstRC = RegisterOperand<VReg_64>; 225 226 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 227 let Asm64 = " $vdst, $sdst, $src0, $src1, $src2$clamp"; 228} 229 230//===----------------------------------------------------------------------===// 231// VOP3 INTERP 232//===----------------------------------------------------------------------===// 233 234class VOP3Interp<string OpName, VOPProfile P, list<dag> pattern = []> : 235 VOP3_Pseudo<OpName, P, pattern> { 236 let AsmMatchConverter = "cvtVOP3Interp"; 237 let mayRaiseFPException = 0; 238} 239 240def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> { 241 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 242 Attr:$attr, AttrChan:$attrchan, 243 clampmod0:$clamp, omod0:$omod); 244 245 let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod"; 246} 247 248def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> { 249 let Ins64 = (ins InterpSlot:$src0, 250 Attr:$attr, AttrChan:$attrchan, 251 clampmod0:$clamp, omod0:$omod); 252 253 let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod"; 254 255 let HasClamp = 1; 256 let HasSrc0Mods = 0; 257} 258 259class getInterp16Asm <bit HasSrc2, bit HasOMod> { 260 string src2 = !if(HasSrc2, ", $src2_modifiers", ""); 261 string omod = !if(HasOMod, "$omod", ""); 262 string ret = 263 " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod; 264} 265 266class getInterp16Ins <bit HasSrc2, bit HasOMod, 267 Operand Src0Mod, Operand Src2Mod> { 268 dag ret = !if(HasSrc2, 269 !if(HasOMod, 270 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 271 Attr:$attr, AttrChan:$attrchan, 272 Src2Mod:$src2_modifiers, VRegSrc_32:$src2, 273 highmod:$high, clampmod0:$clamp, omod0:$omod), 274 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 275 Attr:$attr, AttrChan:$attrchan, 276 Src2Mod:$src2_modifiers, VRegSrc_32:$src2, 277 highmod:$high, clampmod0:$clamp) 278 ), 279 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 280 Attr:$attr, AttrChan:$attrchan, 281 highmod:$high, clampmod0:$clamp, omod0:$omod) 282 ); 283} 284 285class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> { 286 287 let HasOMod = !ne(DstVT.Value, f16.Value); 288 let HasHigh = 1; 289 290 let Outs64 = (outs VGPR_32:$vdst); 291 let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret; 292 let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret; 293} 294 295//===----------------------------------------------------------------------===// 296// VOP3 Instructions 297//===----------------------------------------------------------------------===// 298 299let isCommutable = 1 in { 300 301let mayRaiseFPException = 0 in { 302let SubtargetPredicate = HasMadMacF32Insts in { 303defm V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 304defm V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fmad>; 305} // End SubtargetPredicate = HasMadMacInsts 306 307let SubtargetPredicate = HasFmaLegacy32 in 308defm V_FMA_LEGACY_F32 : VOP3Inst <"v_fma_legacy_f32", 309 VOP3_Profile<VOP_F32_F32_F32_F32>, 310 int_amdgcn_fma_legacy>; 311} 312 313defm V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 314defm V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 315defm V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, any_fma>; 316defm V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>; 317 318let SchedRW = [WriteDoubleAdd] in { 319let FPDPRounding = 1 in { 320defm V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, any_fma>; 321defm V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, any_fadd, 1>; 322defm V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, fmul, 1>; 323} // End FPDPRounding = 1 324defm V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum_like, 1>; 325defm V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum_like, 1>; 326} // End SchedRW = [WriteDoubleAdd] 327 328let SchedRW = [WriteIntMul] in { 329defm V_MUL_LO_U32 : VOP3Inst <"v_mul_lo_u32", VOP3_Profile<VOP_I32_I32_I32>, mul>; 330defm V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", VOP3_Profile<VOP_I32_I32_I32>, mulhu>; 331defm V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", VOP3_Profile<VOP_I32_I32_I32>>; 332defm V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", VOP3_Profile<VOP_I32_I32_I32>, mulhs>; 333} // End SchedRW = [WriteIntMul] 334 335let Uses = [MODE, VCC, EXEC] in { 336// v_div_fmas_f32: 337// result = src0 * src1 + src2 338// if (vcc) 339// result *= 2^32 340// 341let SchedRW = [WriteFloatFMA] in 342defm V_DIV_FMAS_F32 : VOP3Inst_Pseudo_Wrapper <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC, []>; 343// v_div_fmas_f64: 344// result = src0 * src1 + src2 345// if (vcc) 346// result *= 2^64 347// 348let SchedRW = [WriteDouble], FPDPRounding = 1 in 349defm V_DIV_FMAS_F64 : VOP3Inst_Pseudo_Wrapper <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC, []>; 350} // End Uses = [MODE, VCC, EXEC] 351 352} // End isCommutable = 1 353 354let mayRaiseFPException = 0 in { 355defm V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubeid>; 356defm V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubesc>; 357defm V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubetc>; 358defm V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubema>; 359} // End mayRaiseFPException 360 361defm V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>; 362defm V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>; 363defm V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>; 364defm V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, fshr>; 365defm V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>; 366 367let mayRaiseFPException = 0 in { // XXX - Seems suspect but manual doesn't say it does 368defm V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmin3>; 369defm V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>; 370defm V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>; 371defm V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>; 372defm V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>; 373defm V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>; 374defm V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>; 375defm V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>; 376defm V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>; 377} // End mayRaiseFPException = 0 378 379defm V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 380defm V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 381defm V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 382defm V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 383defm V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>; 384 385defm V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUdiv_fixup>; 386 387let SchedRW = [WriteDoubleAdd], FPDPRounding = 1 in { 388 defm V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>; 389 defm V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp, 1>; 390} // End SchedRW = [WriteDoubleAdd], FPDPRounding = 1 391 392 393let mayRaiseFPException = 0 in { // Seems suspicious but manual doesn't say it does. 394 let SchedRW = [WriteFloatFMA, WriteSALU] in 395 defm V_DIV_SCALE_F32 : VOP3Inst_Pseudo_Wrapper <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> ; 396 397 // Double precision division pre-scale. 398 let SchedRW = [WriteDouble, WriteSALU], FPDPRounding = 1 in 399 defm V_DIV_SCALE_F64 : VOP3Inst_Pseudo_Wrapper <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1>; 400} // End mayRaiseFPException = 0 401 402defm V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 403 404let Constraints = "@earlyclobber $vdst" in { 405defm V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>; 406} // End Constraints = "@earlyclobber $vdst" 407 408 409let SchedRW = [WriteDouble] in { 410defm V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, int_amdgcn_trig_preop>; 411} // End SchedRW = [WriteDouble] 412 413let SchedRW = [Write64Bit] in { 414 let SubtargetPredicate = isGFX6GFX7 in { 415 defm V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>, shl>; 416 defm V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>, srl>; 417 defm V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>, sra>; 418 } // End SubtargetPredicate = isGFX6GFX7 419 420 let SubtargetPredicate = isGFX8Plus in { 421 defm V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshl_rev>; 422 defm V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshr_rev>; 423 defm V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, ashr_rev>; 424 } // End SubtargetPredicate = isGFX8Plus 425} // End SchedRW = [Write64Bit] 426 427def : GCNPat< 428 (i32 (getDivergentFrag<sext>.ret i16:$src)), 429 (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))) 430>; 431 432let SubtargetPredicate = isGFX6GFX7GFX10 in { 433defm V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 434} // End SubtargetPredicate = isGFX6GFX7GFX10 435 436let SchedRW = [Write32Bit] in { 437let SubtargetPredicate = isGFX8Plus in { 438defm V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUperm>; 439} // End SubtargetPredicate = isGFX8Plus 440} // End SchedRW = [Write32Bit] 441 442let SubtargetPredicate = isGFX7Plus in { 443 444let Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] in { 445defm V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>; 446defm V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_V4I32, VOP3_CLAMP>>; 447} // End Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] 448 449let isCommutable = 1 in { 450let SchedRW = [WriteIntMul, WriteSALU] in { 451defm V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>; 452defm V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>; 453} // End SchedRW = [WriteIntMul, WriteSALU] 454} // End isCommutable = 1 455 456} // End SubtargetPredicate = isGFX7Plus 457 458let FPDPRounding = 1 in { 459 let Predicates = [Has16BitInsts, isGFX8Only] in { 460 defm V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>; 461 defm V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, any_fma>; 462 } // End Predicates = [Has16BitInsts, isGFX8Only] 463 464 let renamedInGFX9 = 1, Predicates = [Has16BitInsts, isGFX9Plus] in { 465 defm V_DIV_FIXUP_F16_gfx9 : VOP3Inst <"v_div_fixup_f16_gfx9", 466 VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUdiv_fixup>; 467 defm V_FMA_F16_gfx9 : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, any_fma>; 468 } // End renamedInGFX9 = 1, Predicates = [Has16BitInsts, isGFX9Plus] 469} // End FPDPRounding = 1 470 471let SubtargetPredicate = Has16BitInsts, isCommutable = 1 in { 472 473let renamedInGFX9 = 1 in { 474 defm V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>; 475 defm V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>; 476 let FPDPRounding = 1 in { 477 defm V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>; 478 let Uses = [MODE, M0, EXEC] in { 479 let OtherPredicates = [isNotGFX90APlus] in 480 // For some reason the intrinsic operands are in a different order 481 // from the instruction operands. 482 def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>, 483 [(set f16:$vdst, 484 (int_amdgcn_interp_p2_f16 (VOP3Mods f32:$src2, i32:$src2_modifiers), 485 (VOP3Mods f32:$src0, i32:$src0_modifiers), 486 (i32 timm:$attrchan), 487 (i32 timm:$attr), 488 (i1 timm:$high), 489 M0))]>; 490 } // End Uses = [M0, MODE, EXEC] 491 } // End FPDPRounding = 1 492} // End renamedInGFX9 = 1 493 494let SubtargetPredicate = isGFX9Only, FPDPRounding = 1 in { 495 defm V_MAD_F16_gfx9 : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>> ; 496} // End SubtargetPredicate = isGFX9Only, FPDPRounding = 1 497 498let SubtargetPredicate = isGFX9Plus in { 499defm V_MAD_U16_gfx9 : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>; 500defm V_MAD_I16_gfx9 : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>; 501let OtherPredicates = [isNotGFX90APlus] in 502def V_INTERP_P2_F16_gfx9 : VOP3Interp <"v_interp_p2_f16_gfx9", VOP3_INTERP16<[f16, f32, i32, f32]>>; 503} // End SubtargetPredicate = isGFX9Plus 504 505// This predicate should only apply to the selection pattern. The 506// instruction still exists and should decode on subtargets with 507// other bank counts. 508let OtherPredicates = [isNotGFX90APlus, has32BankLDS], Uses = [MODE, M0, EXEC], FPDPRounding = 1 in { 509def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>, 510 [(set f32:$vdst, (int_amdgcn_interp_p1_f16 (VOP3Mods f32:$src0, i32:$src0_modifiers), 511 (i32 timm:$attrchan), 512 (i32 timm:$attr), 513 (i1 timm:$high), M0))]>; 514} // End OtherPredicates = [isNotGFX90APlus, has32BankLDS], Uses = [MODE, M0, EXEC], FPDPRounding = 1 515 516let OtherPredicates = [isNotGFX90APlus], Uses = [MODE, M0, EXEC], FPDPRounding = 1 in { 517def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>; 518} // End OtherPredicates = [isNotGFX90APlus], Uses = [MODE, M0, EXEC], FPDPRounding = 1 519 520} // End SubtargetPredicate = Has16BitInsts, isCommutable = 1 521 522def : GCNPat< 523 (i64 (getDivergentFrag<sext>.ret i16:$src)), 524 (REG_SEQUENCE VReg_64, 525 (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))), sub0, 526 (i32 (COPY_TO_REGCLASS 527 (V_ASHRREV_I32_e32 (S_MOV_B32 (i32 0x1f)), (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))) 528 ), VGPR_32)), sub1) 529>; 530 531let SubtargetPredicate = isGFX8Plus, Uses = [MODE, M0, EXEC], OtherPredicates = [isNotGFX90APlus] in { 532def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>; 533def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>; 534def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>; 535} // End SubtargetPredicate = isGFX8Plus, Uses = [MODE, M0, EXEC], OtherPredicates = [isNotGFX90APlus] 536 537let Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] in { 538 539multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2, 540 Instruction inst, SDPatternOperator op3> { 541def : GCNPat < 542 (op2 (op1 i16:$src0, i16:$src1), i16:$src2), 543 (inst i16:$src0, i16:$src1, i16:$src2, (i1 0)) 544>; 545 546} 547 548defm: Ternary_i16_Pats<mul, add, V_MAD_U16_e64, zext>; 549defm: Ternary_i16_Pats<mul, add, V_MAD_I16_e64, sext>; 550 551} // End Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] 552 553let Predicates = [Has16BitInsts, isGFX10Plus] in { 554 555multiclass Ternary_i16_Pats_gfx9<SDPatternOperator op1, SDPatternOperator op2, 556 Instruction inst, SDPatternOperator op3> { 557def : GCNPat < 558 (op2 (op1 i16:$src0, i16:$src1), i16:$src2), 559 (inst SRCMODS.NONE, $src0, SRCMODS.NONE, $src1, SRCMODS.NONE, $src2, DSTCLAMP.NONE) 560>; 561 562} 563 564defm: Ternary_i16_Pats_gfx9<mul, add, V_MAD_U16_gfx9_e64, zext>; 565defm: Ternary_i16_Pats_gfx9<mul, add, V_MAD_I16_gfx9_e64, sext>; 566 567} // End Predicates = [Has16BitInsts, isGFX10Plus] 568 569class ThreeOpFrag<SDPatternOperator op1, SDPatternOperator op2> : PatFrag< 570 (ops node:$x, node:$y, node:$z), 571 // When the inner operation is used multiple times, selecting 3-op 572 // instructions may still be beneficial -- if the other users can be 573 // combined similarly. Let's be conservative for now. 574 (op2 (HasOneUseBinOp<op1> node:$x, node:$y), node:$z), 575 [{ 576 // Only use VALU ops when the result is divergent. 577 if (!N->isDivergent()) 578 return false; 579 580 // Check constant bus limitations. 581 // 582 // Note: Use !isDivergent as a conservative proxy for whether the value 583 // is in an SGPR (uniform values can end up in VGPRs as well). 584 unsigned ConstantBusUses = 0; 585 for (unsigned i = 0; i < 3; ++i) { 586 if (!Operands[i]->isDivergent() && 587 !isInlineImmediate(Operands[i].getNode())) { 588 ConstantBusUses++; 589 // This uses AMDGPU::V_ADD3_U32_e64, but all three operand instructions 590 // have the same constant bus limit. 591 if (ConstantBusUses > Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64)) 592 return false; 593 } 594 } 595 596 return true; 597 }]> { 598 let PredicateCodeUsesOperands = 1; 599 600 // The divergence predicate is irrelevant in GlobalISel, as we have 601 // proper register bank checks. We just need to verify the constant 602 // bus restriction when all the sources are considered. 603 // 604 // FIXME: With unlucky SGPR operands, we could penalize code by 605 // blocking folding SGPR->VGPR copies later. 606 // FIXME: There's no register bank verifier 607 let GISelPredicateCode = [{ 608 const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64); 609 int ConstantBusUses = 0; 610 for (unsigned i = 0; i < 3; ++i) { 611 const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI); 612 if (RegBank->getID() == AMDGPU::SGPRRegBankID) { 613 if (++ConstantBusUses > ConstantBusLimit) 614 return false; 615 } 616 } 617 return true; 618 }]; 619} 620 621let SubtargetPredicate = isGFX9Plus in { 622defm V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 623defm V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 624defm V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 625defm V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 626defm V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 627defm V_AND_OR_B32 : VOP3Inst <"v_and_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 628defm V_OR3_B32 : VOP3Inst <"v_or3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 629 630defm V_XAD_U32 : VOP3Inst <"v_xad_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 631 632defm V_MED3_F16 : VOP3Inst <"v_med3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmed3>; 633defm V_MED3_I16 : VOP3Inst <"v_med3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmed3>; 634defm V_MED3_U16 : VOP3Inst <"v_med3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumed3>; 635 636defm V_MIN3_F16 : VOP3Inst <"v_min3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmin3>; 637defm V_MIN3_I16 : VOP3Inst <"v_min3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmin3>; 638defm V_MIN3_U16 : VOP3Inst <"v_min3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumin3>; 639 640defm V_MAX3_F16 : VOP3Inst <"v_max3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmax3>; 641defm V_MAX3_I16 : VOP3Inst <"v_max3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmax3>; 642defm V_MAX3_U16 : VOP3Inst <"v_max3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumax3>; 643 644defm V_ADD_I16 : VOP3Inst <"v_add_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>; 645defm V_SUB_I16 : VOP3Inst <"v_sub_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>; 646 647defm V_MAD_U32_U16 : VOP3Inst <"v_mad_u32_u16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>; 648defm V_MAD_I32_I16 : VOP3Inst <"v_mad_i32_i16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>; 649 650defm V_CVT_PKNORM_I16_F16 : VOP3Inst <"v_cvt_pknorm_i16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 651defm V_CVT_PKNORM_U16_F16 : VOP3Inst <"v_cvt_pknorm_u16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 652 653defm V_ADD_I32 : VOP3Inst <"v_add_i32", VOP3_Profile<VOP_I32_I32_I32_ARITH>>; 654defm V_SUB_I32 : VOP3Inst <"v_sub_i32", VOP3_Profile<VOP_I32_I32_I32_ARITH>>; 655 656 657class ThreeOp_i32_Pats <SDPatternOperator op1, SDPatternOperator op2, Instruction inst> : GCNPat < 658 // This matches (op2 (op1 i32:$src0, i32:$src1), i32:$src2) with conditions. 659 (ThreeOpFrag<op1, op2> i32:$src0, i32:$src1, i32:$src2), 660 (inst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2) 661>; 662 663def : ThreeOp_i32_Pats<shl, add, V_LSHL_ADD_U32_e64>; 664def : ThreeOp_i32_Pats<add, shl, V_ADD_LSHL_U32_e64>; 665def : ThreeOp_i32_Pats<add, add, V_ADD3_U32_e64>; 666def : ThreeOp_i32_Pats<shl, or, V_LSHL_OR_B32_e64>; 667def : ThreeOp_i32_Pats<and, or, V_AND_OR_B32_e64>; 668def : ThreeOp_i32_Pats<or, or, V_OR3_B32_e64>; 669def : ThreeOp_i32_Pats<xor, add, V_XAD_U32_e64>; 670 671def : VOPBinOpClampPat<saddsat, V_ADD_I32_e64, i32>; 672def : VOPBinOpClampPat<ssubsat, V_SUB_I32_e64, i32>; 673 674 675// FIXME: Probably should hardcode clamp bit in pseudo and avoid this. 676class OpSelBinOpClampPat<SDPatternOperator node, 677 Instruction inst> : GCNPat< 678 (node (i16 (VOP3OpSel i16:$src0, i32:$src0_modifiers)), 679 (i16 (VOP3OpSel i16:$src1, i32:$src1_modifiers))), 680 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, DSTCLAMP.ENABLE, 0) 681>; 682 683def : OpSelBinOpClampPat<saddsat, V_ADD_I16_e64>; 684def : OpSelBinOpClampPat<ssubsat, V_SUB_I16_e64>; 685} // End SubtargetPredicate = isGFX9Plus 686 687def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3_OPSEL> { 688 let Src0RC64 = VRegSrc_32; 689 let Src1RC64 = SCSrc_b32; 690 let Src2RC64 = SCSrc_b32; 691 let InsVOP3OpSel = (ins IntOpSelMods:$src0_modifiers, VRegSrc_32:$src0, 692 IntOpSelMods:$src1_modifiers, SCSrc_b32:$src1, 693 IntOpSelMods:$src2_modifiers, SCSrc_b32:$src2, 694 VGPR_32:$vdst_in, op_sel0:$op_sel); 695 let HasClamp = 0; 696} 697 698class PermlanePat<SDPatternOperator permlane, 699 Instruction inst> : GCNPat< 700 (permlane i32:$vdst_in, i32:$src0, i32:$src1, i32:$src2, 701 timm:$fi, timm:$bc), 702 (inst (as_i1timm $fi), VGPR_32:$src0, (as_i1timm $bc), 703 SCSrc_b32:$src1, 0, SCSrc_b32:$src2, VGPR_32:$vdst_in) 704>; 705 706// Permlane intrinsic that has either fetch invalid or bound control 707// fields enabled. 708class BoundControlOrFetchInvalidPermlane<SDPatternOperator permlane> : 709 PatFrag<(ops node:$vdst_in, node:$src0, node:$src1, node:$src2, 710 node:$fi, node:$bc), 711 (permlane node:$vdst_in, node:$src0, node: 712 $src1, node:$src2, node:$fi, node:$bc)> { 713 let PredicateCode = [{ return N->getConstantOperandVal(5) != 0 || 714 N->getConstantOperandVal(6) != 0; }]; 715 let GISelPredicateCode = [{ 716 return MI.getOperand(6).getImm() != 0 || 717 MI.getOperand(7).getImm() != 0; 718 }]; 719} 720 721// Drop the input value if it won't be read. 722class PermlaneDiscardVDstIn<SDPatternOperator permlane, 723 Instruction inst> : GCNPat< 724 (permlane srcvalue, i32:$src0, i32:$src1, i32:$src2, 725 timm:$fi, timm:$bc), 726 (inst (as_i1timm $fi), VGPR_32:$src0, (as_i1timm $bc), 727 SCSrc_b32:$src1, 0, SCSrc_b32:$src2, 728 (IMPLICIT_DEF)) 729>; 730 731 732let SubtargetPredicate = isGFX10Plus in { 733 defm V_XOR3_B32 : VOP3Inst <"v_xor3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 734 def : ThreeOp_i32_Pats<xor, xor, V_XOR3_B32_e64>; 735 736 let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in { 737 defm V_PERMLANE16_B32 : VOP3Inst<"v_permlane16_b32", VOP3_PERMLANE_Profile>; 738 defm V_PERMLANEX16_B32 : VOP3Inst<"v_permlanex16_b32", VOP3_PERMLANE_Profile>; 739 } // End $vdst = $vdst_in, DisableEncoding $vdst_in 740 741 def : PermlanePat<int_amdgcn_permlane16, V_PERMLANE16_B32_e64>; 742 def : PermlanePat<int_amdgcn_permlanex16, V_PERMLANEX16_B32_e64>; 743 744 def : PermlaneDiscardVDstIn< 745 BoundControlOrFetchInvalidPermlane<int_amdgcn_permlane16>, 746 V_PERMLANE16_B32_e64>; 747 def : PermlaneDiscardVDstIn< 748 BoundControlOrFetchInvalidPermlane<int_amdgcn_permlanex16>, 749 V_PERMLANEX16_B32_e64>; 750} // End SubtargetPredicate = isGFX10Plus 751 752class DivFmasPat<ValueType vt, Instruction inst, Register CondReg> : GCNPat< 753 (AMDGPUdiv_fmas (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)), 754 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), 755 (vt (VOP3Mods vt:$src2, i32:$src2_modifiers)), 756 (i1 CondReg)), 757 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, $src2_modifiers, $src2) 758>; 759 760let WaveSizePredicate = isWave64 in { 761def : DivFmasPat<f32, V_DIV_FMAS_F32_e64, VCC>; 762def : DivFmasPat<f64, V_DIV_FMAS_F64_e64, VCC>; 763} 764 765let WaveSizePredicate = isWave32 in { 766def : DivFmasPat<f32, V_DIV_FMAS_F32_e64, VCC_LO>; 767def : DivFmasPat<f64, V_DIV_FMAS_F64_e64, VCC_LO>; 768} 769 770//===----------------------------------------------------------------------===// 771// Integer Clamp Patterns 772//===----------------------------------------------------------------------===// 773 774class getClampPat<VOPProfile P, SDPatternOperator node> { 775 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2)); 776 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1)); 777 dag ret1 = (P.DstVT (node P.Src0VT:$src0)); 778 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3, 779 !if(!eq(P.NumSrcArgs, 2), ret2, 780 ret1)); 781} 782 783class getClampRes<VOPProfile P, Instruction inst> { 784 dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0)); 785 dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0)); 786 dag ret1 = (inst P.Src0VT:$src0, (i1 0)); 787 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3, 788 !if(!eq(P.NumSrcArgs, 2), ret2, 789 ret1)); 790} 791 792class IntClampPat<VOP3InstBase inst, SDPatternOperator node> : GCNPat< 793 getClampPat<inst.Pfl, node>.ret, 794 getClampRes<inst.Pfl, inst>.ret 795>; 796 797def : IntClampPat<V_MAD_I32_I24_e64, AMDGPUmad_i24>; 798def : IntClampPat<V_MAD_U32_U24_e64, AMDGPUmad_u24>; 799 800def : IntClampPat<V_SAD_U8_e64, int_amdgcn_sad_u8>; 801def : IntClampPat<V_SAD_HI_U8_e64, int_amdgcn_sad_hi_u8>; 802def : IntClampPat<V_SAD_U16_e64, int_amdgcn_sad_u16>; 803 804def : IntClampPat<V_MSAD_U8_e64, int_amdgcn_msad_u8>; 805def : IntClampPat<V_MQSAD_PK_U16_U8_e64, int_amdgcn_mqsad_pk_u16_u8>; 806 807def : IntClampPat<V_QSAD_PK_U16_U8_e64, int_amdgcn_qsad_pk_u16_u8>; 808def : IntClampPat<V_MQSAD_U32_U8_e64, int_amdgcn_mqsad_u32_u8>; 809 810 811//===----------------------------------------------------------------------===// 812// Target-specific instruction encodings. 813//===----------------------------------------------------------------------===// 814 815//===----------------------------------------------------------------------===// 816// GFX10. 817//===----------------------------------------------------------------------===// 818 819let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in { 820 multiclass VOP3_Real_gfx10<bits<10> op> { 821 def _gfx10 : 822 VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 823 VOP3e_gfx10<op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 824 } 825 multiclass VOP3_Real_No_Suffix_gfx10<bits<10> op> { 826 def _gfx10 : 827 VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX10>, 828 VOP3e_gfx10<op, !cast<VOP_Pseudo>(NAME).Pfl>; 829 } 830 multiclass VOP3_Real_gfx10_with_name<bits<10> op, string opName, 831 string asmName> { 832 def _gfx10 : 833 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>, 834 VOP3e_gfx10<op, !cast<VOP3_Pseudo>(opName#"_e64").Pfl> { 835 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64"); 836 let AsmString = asmName # ps.AsmOperands; 837 } 838 } 839 multiclass VOP3be_Real_gfx10<bits<10> op> { 840 def _gfx10 : 841 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 842 VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 843 } 844 multiclass VOP3Interp_Real_gfx10<bits<10> op> { 845 def _gfx10 : 846 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>, 847 VOP3Interp_gfx10<op, !cast<VOP3_Pseudo>(NAME).Pfl>; 848 } 849 multiclass VOP3OpSel_Real_gfx10<bits<10> op> { 850 def _gfx10 : 851 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 852 VOP3OpSel_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 853 } 854 multiclass VOP3OpSel_Real_gfx10_with_name<bits<10> op, string opName, 855 string asmName> { 856 def _gfx10 : 857 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>, 858 VOP3OpSel_gfx10<op, !cast<VOP3_Pseudo>(opName#"_e64").Pfl> { 859 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64"); 860 let AsmString = asmName # ps.AsmOperands; 861 } 862 } 863} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" 864 865defm V_READLANE_B32 : VOP3_Real_No_Suffix_gfx10<0x360>; 866 867let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in { 868 defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_gfx10<0x361>; 869} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) 870 871let SubtargetPredicate = isGFX10Before1030 in { 872 defm V_MUL_LO_I32 : VOP3_Real_gfx10<0x16b>; 873} 874 875defm V_XOR3_B32 : VOP3_Real_gfx10<0x178>; 876defm V_LSHLREV_B64 : VOP3_Real_gfx10<0x2ff>; 877defm V_LSHRREV_B64 : VOP3_Real_gfx10<0x300>; 878defm V_ASHRREV_I64 : VOP3_Real_gfx10<0x301>; 879defm V_PERM_B32 : VOP3_Real_gfx10<0x344>; 880defm V_XAD_U32 : VOP3_Real_gfx10<0x345>; 881defm V_LSHL_ADD_U32 : VOP3_Real_gfx10<0x346>; 882defm V_ADD_LSHL_U32 : VOP3_Real_gfx10<0x347>; 883defm V_ADD3_U32 : VOP3_Real_gfx10<0x36d>; 884defm V_LSHL_OR_B32 : VOP3_Real_gfx10<0x36f>; 885defm V_AND_OR_B32 : VOP3_Real_gfx10<0x371>; 886defm V_OR3_B32 : VOP3_Real_gfx10<0x372>; 887 888// TODO-GFX10: add MC tests for v_add/sub_nc_i16 889defm V_ADD_NC_I16 : 890 VOP3OpSel_Real_gfx10_with_name<0x30d, "V_ADD_I16", "v_add_nc_i16">; 891defm V_SUB_NC_I16 : 892 VOP3OpSel_Real_gfx10_with_name<0x30e, "V_SUB_I16", "v_sub_nc_i16">; 893defm V_SUB_NC_I32 : 894 VOP3_Real_gfx10_with_name<0x376, "V_SUB_I32", "v_sub_nc_i32">; 895defm V_ADD_NC_I32 : 896 VOP3_Real_gfx10_with_name<0x37f, "V_ADD_I32", "v_add_nc_i32">; 897 898defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_gfx10<0x200>; 899defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_gfx10<0x201>; 900defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_gfx10<0x202>; 901 902defm V_INTERP_P1LL_F16 : VOP3Interp_Real_gfx10<0x342>; 903defm V_INTERP_P1LV_F16 : VOP3Interp_Real_gfx10<0x343>; 904defm V_INTERP_P2_F16 : VOP3Interp_Real_gfx10<0x35a>; 905 906defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx10<0x311>; 907defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx10<0x312>; 908defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx10<0x313>; 909 910defm V_MIN3_F16 : VOP3OpSel_Real_gfx10<0x351>; 911defm V_MIN3_I16 : VOP3OpSel_Real_gfx10<0x352>; 912defm V_MIN3_U16 : VOP3OpSel_Real_gfx10<0x353>; 913defm V_MAX3_F16 : VOP3OpSel_Real_gfx10<0x354>; 914defm V_MAX3_I16 : VOP3OpSel_Real_gfx10<0x355>; 915defm V_MAX3_U16 : VOP3OpSel_Real_gfx10<0x356>; 916defm V_MED3_F16 : VOP3OpSel_Real_gfx10<0x357>; 917defm V_MED3_I16 : VOP3OpSel_Real_gfx10<0x358>; 918defm V_MED3_U16 : VOP3OpSel_Real_gfx10<0x359>; 919defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx10<0x373>; 920defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx10<0x375>; 921 922defm V_MAD_U16 : 923 VOP3OpSel_Real_gfx10_with_name<0x340, "V_MAD_U16_gfx9", "v_mad_u16">; 924defm V_FMA_F16 : 925 VOP3OpSel_Real_gfx10_with_name<0x34b, "V_FMA_F16_gfx9", "v_fma_f16">; 926defm V_MAD_I16 : 927 VOP3OpSel_Real_gfx10_with_name<0x35e, "V_MAD_I16_gfx9", "v_mad_i16">; 928defm V_DIV_FIXUP_F16 : 929 VOP3OpSel_Real_gfx10_with_name<0x35f, "V_DIV_FIXUP_F16_gfx9", "v_div_fixup_f16">; 930 931// FIXME-GFX10-OPSEL: Need to add "selective" opsel support to some of these 932// (they do not support SDWA or DPP). 933defm V_ADD_NC_U16 : VOP3_Real_gfx10_with_name<0x303, "V_ADD_U16", "v_add_nc_u16">; 934defm V_SUB_NC_U16 : VOP3_Real_gfx10_with_name<0x304, "V_SUB_U16", "v_sub_nc_u16">; 935defm V_MUL_LO_U16 : VOP3_Real_gfx10_with_name<0x305, "V_MUL_LO_U16", "v_mul_lo_u16">; 936defm V_LSHRREV_B16 : VOP3_Real_gfx10_with_name<0x307, "V_LSHRREV_B16", "v_lshrrev_b16">; 937defm V_ASHRREV_I16 : VOP3_Real_gfx10_with_name<0x308, "V_ASHRREV_I16", "v_ashrrev_i16">; 938defm V_MAX_U16 : VOP3_Real_gfx10_with_name<0x309, "V_MAX_U16", "v_max_u16">; 939defm V_MAX_I16 : VOP3_Real_gfx10_with_name<0x30a, "V_MAX_I16", "v_max_i16">; 940defm V_MIN_U16 : VOP3_Real_gfx10_with_name<0x30b, "V_MIN_U16", "v_min_u16">; 941defm V_MIN_I16 : VOP3_Real_gfx10_with_name<0x30c, "V_MIN_I16", "v_min_i16">; 942defm V_LSHLREV_B16 : VOP3_Real_gfx10_with_name<0x314, "V_LSHLREV_B16", "v_lshlrev_b16">; 943defm V_PERMLANE16_B32 : VOP3OpSel_Real_gfx10<0x377>; 944defm V_PERMLANEX16_B32 : VOP3OpSel_Real_gfx10<0x378>; 945 946//===----------------------------------------------------------------------===// 947// GFX7, GFX10. 948//===----------------------------------------------------------------------===// 949 950let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in { 951 multiclass VOP3_Real_gfx7<bits<10> op> { 952 def _gfx7 : 953 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 954 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 955 } 956 multiclass VOP3be_Real_gfx7<bits<10> op> { 957 def _gfx7 : 958 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 959 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 960 } 961} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" 962 963multiclass VOP3_Real_gfx7_gfx10<bits<10> op> : 964 VOP3_Real_gfx7<op>, VOP3_Real_gfx10<op>; 965 966multiclass VOP3be_Real_gfx7_gfx10<bits<10> op> : 967 VOP3be_Real_gfx7<op>, VOP3be_Real_gfx10<op>; 968 969defm V_QSAD_PK_U16_U8 : VOP3_Real_gfx7_gfx10<0x172>; 970defm V_MQSAD_U32_U8 : VOP3_Real_gfx7_gfx10<0x175>; 971defm V_MAD_U64_U32 : VOP3be_Real_gfx7_gfx10<0x176>; 972defm V_MAD_I64_I32 : VOP3be_Real_gfx7_gfx10<0x177>; 973 974//===----------------------------------------------------------------------===// 975// GFX6, GFX7, GFX10. 976//===----------------------------------------------------------------------===// 977 978let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in { 979 multiclass VOP3_Real_gfx6_gfx7<bits<10> op> { 980 def _gfx6_gfx7 : 981 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 982 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 983 } 984 multiclass VOP3be_Real_gfx6_gfx7<bits<10> op> { 985 def _gfx6_gfx7 : 986 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 987 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 988 } 989} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" 990 991multiclass VOP3_Real_gfx6_gfx7_gfx10<bits<10> op> : 992 VOP3_Real_gfx6_gfx7<op>, VOP3_Real_gfx10<op>; 993 994multiclass VOP3be_Real_gfx6_gfx7_gfx10<bits<10> op> : 995 VOP3be_Real_gfx6_gfx7<op>, VOP3be_Real_gfx10<op>; 996 997defm V_LSHL_B64 : VOP3_Real_gfx6_gfx7<0x161>; 998defm V_LSHR_B64 : VOP3_Real_gfx6_gfx7<0x162>; 999defm V_ASHR_I64 : VOP3_Real_gfx6_gfx7<0x163>; 1000defm V_MUL_LO_I32 : VOP3_Real_gfx6_gfx7<0x16b>; 1001 1002defm V_MAD_LEGACY_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x140>; 1003defm V_MAD_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x141>; 1004defm V_MAD_I32_I24 : VOP3_Real_gfx6_gfx7_gfx10<0x142>; 1005defm V_MAD_U32_U24 : VOP3_Real_gfx6_gfx7_gfx10<0x143>; 1006defm V_CUBEID_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x144>; 1007defm V_CUBESC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x145>; 1008defm V_CUBETC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x146>; 1009defm V_CUBEMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x147>; 1010defm V_BFE_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x148>; 1011defm V_BFE_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x149>; 1012defm V_BFI_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14a>; 1013defm V_FMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x14b>; 1014defm V_FMA_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x14c>; 1015defm V_LERP_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x14d>; 1016defm V_ALIGNBIT_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14e>; 1017defm V_ALIGNBYTE_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14f>; 1018defm V_MULLIT_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x150>; 1019defm V_MIN3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x151>; 1020defm V_MIN3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x152>; 1021defm V_MIN3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x153>; 1022defm V_MAX3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x154>; 1023defm V_MAX3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x155>; 1024defm V_MAX3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x156>; 1025defm V_MED3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x157>; 1026defm V_MED3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x158>; 1027defm V_MED3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x159>; 1028defm V_SAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15a>; 1029defm V_SAD_HI_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15b>; 1030defm V_SAD_U16 : VOP3_Real_gfx6_gfx7_gfx10<0x15c>; 1031defm V_SAD_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x15d>; 1032defm V_CVT_PK_U8_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15e>; 1033defm V_DIV_FIXUP_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15f>; 1034defm V_DIV_FIXUP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x160>; 1035defm V_ADD_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x164>; 1036defm V_MUL_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x165>; 1037defm V_MIN_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x166>; 1038defm V_MAX_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x167>; 1039defm V_LDEXP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x168>; 1040defm V_MUL_LO_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x169>; 1041defm V_MUL_HI_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x16a>; 1042defm V_MUL_HI_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x16c>; 1043defm V_DIV_FMAS_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x16f>; 1044defm V_DIV_FMAS_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x170>; 1045defm V_MSAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x171>; 1046defm V_MQSAD_PK_U16_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x173>; 1047defm V_TRIG_PREOP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x174>; 1048defm V_DIV_SCALE_F32 : VOP3be_Real_gfx6_gfx7_gfx10<0x16d>; 1049defm V_DIV_SCALE_F64 : VOP3be_Real_gfx6_gfx7_gfx10<0x16e>; 1050 1051// NB: Same opcode as v_mad_legacy_f32 1052let DecoderNamespace = "GFX10_B" in 1053defm V_FMA_LEGACY_F32 : VOP3_Real_gfx10<0x140>; 1054 1055//===----------------------------------------------------------------------===// 1056// GFX8, GFX9 (VI). 1057//===----------------------------------------------------------------------===// 1058 1059let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in { 1060 1061multiclass VOP3_Real_vi<bits<10> op> { 1062 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1063 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 1064} 1065multiclass VOP3_Real_No_Suffix_vi<bits<10> op> { 1066 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 1067 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>; 1068} 1069 1070multiclass VOP3be_Real_vi<bits<10> op> { 1071 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1072 VOP3be_vi <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 1073} 1074 1075multiclass VOP3OpSel_Real_gfx9<bits<10> op> { 1076 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1077 VOP3OpSel_gfx9 <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 1078} 1079 1080multiclass VOP3Interp_Real_vi<bits<10> op> { 1081 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 1082 VOP3Interp_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>; 1083} 1084 1085} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" 1086 1087let AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" in { 1088 1089multiclass VOP3_F16_Real_vi<bits<10> op> { 1090 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1091 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1092} 1093 1094multiclass VOP3Interp_F16_Real_vi<bits<10> op> { 1095 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>, 1096 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>; 1097} 1098 1099} // End AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" 1100 1101let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in { 1102 1103multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> { 1104 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>, 1105 VOP3e_vi <op, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> { 1106 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64"); 1107 let AsmString = AsmName # ps.AsmOperands; 1108 } 1109} 1110 1111multiclass VOP3OpSel_F16_Real_gfx9<bits<10> op, string AsmName> { 1112 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>, 1113 VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1114 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME#"_e64"); 1115 let AsmString = AsmName # ps.AsmOperands; 1116 } 1117} 1118 1119multiclass VOP3Interp_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> { 1120 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>, 1121 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> { 1122 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName); 1123 let AsmString = AsmName # ps.AsmOperands; 1124 } 1125} 1126 1127multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> { 1128 def _gfx9 : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>, 1129 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl> { 1130 VOP_Pseudo ps = !cast<VOP_Pseudo>(NAME#"_e64"); 1131 let AsmString = AsmName # ps.AsmOperands; 1132 } 1133} 1134 1135} // End AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" 1136 1137defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>; 1138defm V_MAD_I64_I32 : VOP3be_Real_vi <0x1E9>; 1139 1140defm V_MAD_LEGACY_F32 : VOP3_Real_vi <0x1c0>; 1141defm V_MAD_F32 : VOP3_Real_vi <0x1c1>; 1142defm V_MAD_I32_I24 : VOP3_Real_vi <0x1c2>; 1143defm V_MAD_U32_U24 : VOP3_Real_vi <0x1c3>; 1144defm V_CUBEID_F32 : VOP3_Real_vi <0x1c4>; 1145defm V_CUBESC_F32 : VOP3_Real_vi <0x1c5>; 1146defm V_CUBETC_F32 : VOP3_Real_vi <0x1c6>; 1147defm V_CUBEMA_F32 : VOP3_Real_vi <0x1c7>; 1148defm V_BFE_U32 : VOP3_Real_vi <0x1c8>; 1149defm V_BFE_I32 : VOP3_Real_vi <0x1c9>; 1150defm V_BFI_B32 : VOP3_Real_vi <0x1ca>; 1151defm V_FMA_F32 : VOP3_Real_vi <0x1cb>; 1152defm V_FMA_F64 : VOP3_Real_vi <0x1cc>; 1153defm V_LERP_U8 : VOP3_Real_vi <0x1cd>; 1154defm V_ALIGNBIT_B32 : VOP3_Real_vi <0x1ce>; 1155defm V_ALIGNBYTE_B32 : VOP3_Real_vi <0x1cf>; 1156defm V_MIN3_F32 : VOP3_Real_vi <0x1d0>; 1157defm V_MIN3_I32 : VOP3_Real_vi <0x1d1>; 1158defm V_MIN3_U32 : VOP3_Real_vi <0x1d2>; 1159defm V_MAX3_F32 : VOP3_Real_vi <0x1d3>; 1160defm V_MAX3_I32 : VOP3_Real_vi <0x1d4>; 1161defm V_MAX3_U32 : VOP3_Real_vi <0x1d5>; 1162defm V_MED3_F32 : VOP3_Real_vi <0x1d6>; 1163defm V_MED3_I32 : VOP3_Real_vi <0x1d7>; 1164defm V_MED3_U32 : VOP3_Real_vi <0x1d8>; 1165defm V_SAD_U8 : VOP3_Real_vi <0x1d9>; 1166defm V_SAD_HI_U8 : VOP3_Real_vi <0x1da>; 1167defm V_SAD_U16 : VOP3_Real_vi <0x1db>; 1168defm V_SAD_U32 : VOP3_Real_vi <0x1dc>; 1169defm V_CVT_PK_U8_F32 : VOP3_Real_vi <0x1dd>; 1170defm V_DIV_FIXUP_F32 : VOP3_Real_vi <0x1de>; 1171defm V_DIV_FIXUP_F64 : VOP3_Real_vi <0x1df>; 1172defm V_DIV_SCALE_F32 : VOP3be_Real_vi <0x1e0>; 1173defm V_DIV_SCALE_F64 : VOP3be_Real_vi <0x1e1>; 1174defm V_DIV_FMAS_F32 : VOP3_Real_vi <0x1e2>; 1175defm V_DIV_FMAS_F64 : VOP3_Real_vi <0x1e3>; 1176defm V_MSAD_U8 : VOP3_Real_vi <0x1e4>; 1177defm V_QSAD_PK_U16_U8 : VOP3_Real_vi <0x1e5>; 1178defm V_MQSAD_PK_U16_U8 : VOP3_Real_vi <0x1e6>; 1179defm V_MQSAD_U32_U8 : VOP3_Real_vi <0x1e7>; 1180 1181defm V_PERM_B32 : VOP3_Real_vi <0x1ed>; 1182 1183defm V_MAD_F16 : VOP3_F16_Real_vi <0x1ea>; 1184defm V_MAD_U16 : VOP3_F16_Real_vi <0x1eb>; 1185defm V_MAD_I16 : VOP3_F16_Real_vi <0x1ec>; 1186defm V_FMA_F16 : VOP3_F16_Real_vi <0x1ee>; 1187defm V_DIV_FIXUP_F16 : VOP3_F16_Real_vi <0x1ef>; 1188defm V_INTERP_P2_F16 : VOP3Interp_F16_Real_vi <0x276>; 1189 1190let FPDPRounding = 1 in { 1191defm V_MAD_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16", "v_mad_legacy_f16">; 1192defm V_FMA_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16", "v_fma_legacy_f16">; 1193defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16">; 1194defm V_INTERP_P2_LEGACY_F16 : VOP3Interp_F16_Real_gfx9 <0x276, "V_INTERP_P2_F16", "v_interp_p2_legacy_f16">; 1195} // End FPDPRounding = 1 1196 1197defm V_MAD_LEGACY_U16 : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16", "v_mad_legacy_u16">; 1198defm V_MAD_LEGACY_I16 : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16", "v_mad_legacy_i16">; 1199 1200defm V_MAD_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">; 1201defm V_MAD_U16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">; 1202defm V_MAD_I16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">; 1203defm V_FMA_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x206, "v_fma_f16">; 1204defm V_DIV_FIXUP_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">; 1205defm V_INTERP_P2_F16_gfx9 : VOP3Interp_F16_Real_gfx9 <0x277, "V_INTERP_P2_F16_gfx9", "v_interp_p2_f16">; 1206 1207defm V_ADD_I32 : VOP3_Real_vi <0x29c>; 1208defm V_SUB_I32 : VOP3_Real_vi <0x29d>; 1209 1210defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_vi <0x270>; 1211defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_vi <0x271>; 1212defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>; 1213 1214defm V_INTERP_P1LL_F16 : VOP3Interp_Real_vi <0x274>; 1215defm V_INTERP_P1LV_F16 : VOP3Interp_Real_vi <0x275>; 1216defm V_ADD_F64 : VOP3_Real_vi <0x280>; 1217defm V_MUL_F64 : VOP3_Real_vi <0x281>; 1218defm V_MIN_F64 : VOP3_Real_vi <0x282>; 1219defm V_MAX_F64 : VOP3_Real_vi <0x283>; 1220defm V_LDEXP_F64 : VOP3_Real_vi <0x284>; 1221defm V_MUL_LO_U32 : VOP3_Real_vi <0x285>; 1222 1223// removed from VI as identical to V_MUL_LO_U32 1224let isAsmParserOnly = 1 in { 1225defm V_MUL_LO_I32 : VOP3_Real_vi <0x285>; 1226} 1227 1228defm V_MUL_HI_U32 : VOP3_Real_vi <0x286>; 1229defm V_MUL_HI_I32 : VOP3_Real_vi <0x287>; 1230 1231defm V_READLANE_B32 : VOP3_Real_No_Suffix_vi <0x289>; 1232defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_vi <0x28a>; 1233 1234defm V_LSHLREV_B64 : VOP3_Real_vi <0x28f>; 1235defm V_LSHRREV_B64 : VOP3_Real_vi <0x290>; 1236defm V_ASHRREV_I64 : VOP3_Real_vi <0x291>; 1237defm V_TRIG_PREOP_F64 : VOP3_Real_vi <0x292>; 1238 1239defm V_LSHL_ADD_U32 : VOP3_Real_vi <0x1fd>; 1240defm V_ADD_LSHL_U32 : VOP3_Real_vi <0x1fe>; 1241defm V_ADD3_U32 : VOP3_Real_vi <0x1ff>; 1242defm V_LSHL_OR_B32 : VOP3_Real_vi <0x200>; 1243defm V_AND_OR_B32 : VOP3_Real_vi <0x201>; 1244defm V_OR3_B32 : VOP3_Real_vi <0x202>; 1245defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx9 <0x2a0>; 1246 1247defm V_XAD_U32 : VOP3_Real_vi <0x1f3>; 1248 1249defm V_MIN3_F16 : VOP3OpSel_Real_gfx9 <0x1f4>; 1250defm V_MIN3_I16 : VOP3OpSel_Real_gfx9 <0x1f5>; 1251defm V_MIN3_U16 : VOP3OpSel_Real_gfx9 <0x1f6>; 1252 1253defm V_MAX3_F16 : VOP3OpSel_Real_gfx9 <0x1f7>; 1254defm V_MAX3_I16 : VOP3OpSel_Real_gfx9 <0x1f8>; 1255defm V_MAX3_U16 : VOP3OpSel_Real_gfx9 <0x1f9>; 1256 1257defm V_MED3_F16 : VOP3OpSel_Real_gfx9 <0x1fa>; 1258defm V_MED3_I16 : VOP3OpSel_Real_gfx9 <0x1fb>; 1259defm V_MED3_U16 : VOP3OpSel_Real_gfx9 <0x1fc>; 1260 1261defm V_ADD_I16 : VOP3OpSel_Real_gfx9 <0x29e>; 1262defm V_SUB_I16 : VOP3OpSel_Real_gfx9 <0x29f>; 1263 1264defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx9 <0x1f1>; 1265defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx9 <0x1f2>; 1266 1267defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx9 <0x299>; 1268defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx9 <0x29a>; 1269