1//===-- VOP3Instructions.td - Vector Instruction Defintions ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// VOP3 Classes
12//===----------------------------------------------------------------------===//
13
14class getVOP3ModPat<VOPProfile P, SDPatternOperator node> {
15  dag src0 = !if(P.HasOMod,
16    (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
17    (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp));
18
19  list<dag> ret3 = [(set P.DstVT:$vdst,
20    (DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
21          (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
22          (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))];
23
24  list<dag> ret2 = [(set P.DstVT:$vdst,
25    (DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
26          (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))];
27
28  list<dag> ret1 = [(set P.DstVT:$vdst,
29    (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))];
30
31  list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
32                  !if(!eq(P.NumSrcArgs, 2), ret2,
33                  ret1));
34}
35
36class getVOP3PModPat<VOPProfile P, SDPatternOperator node> {
37  list<dag> ret3 = [(set P.DstVT:$vdst,
38    (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
39                                    (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers))),
40          (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers)),
41          (P.Src2VT (VOP3PMods P.Src2VT:$src2, i32:$src2_modifiers))))];
42
43  list<dag> ret2 = [(set P.DstVT:$vdst,
44    (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
45                          (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers))),
46          (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers))))];
47
48  list<dag> ret1 = [(set P.DstVT:$vdst,
49    (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
50
51  list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
52                  !if(!eq(P.NumSrcArgs, 2), ret2,
53                  ret1));
54}
55
56class getVOP3OpSelPat<VOPProfile P, SDPatternOperator node> {
57  list<dag> ret3 = [(set P.DstVT:$vdst,
58    (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
59                                    (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))),
60          (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)),
61          (P.Src2VT (VOP3OpSel P.Src2VT:$src2, i32:$src2_modifiers))))];
62
63  list<dag> ret2 = [(set P.DstVT:$vdst,
64    (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
65                          (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))),
66          (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))];
67
68  list<dag> ret1 = [(set P.DstVT:$vdst,
69    (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
70
71  list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
72                  !if(!eq(P.NumSrcArgs, 2), ret2,
73                  ret1));
74}
75
76class getVOP3OpSelModPat<VOPProfile P, SDPatternOperator node> {
77  list<dag> ret3 = [(set P.DstVT:$vdst,
78    (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
79                                    (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
80          (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)),
81          (P.Src2VT (VOP3OpSelMods P.Src2VT:$src2, i32:$src2_modifiers))))];
82
83  list<dag> ret2 = [(set P.DstVT:$vdst,
84    (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
85                          (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
86          (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))];
87
88  list<dag> ret1 = [(set P.DstVT:$vdst,
89    (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
90
91  list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
92                  !if(!eq(P.NumSrcArgs, 2), ret2,
93                  ret1));
94}
95
96class getVOP3Pat<VOPProfile P, SDPatternOperator node> {
97  list<dag> ret3 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))];
98  list<dag> ret2 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$src1))];
99  list<dag> ret1 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0))];
100  list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
101                  !if(!eq(P.NumSrcArgs, 2), ret2,
102                  ret1));
103}
104
105class getVOP3ClampPat<VOPProfile P, SDPatternOperator node> {
106  list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i1:$clamp))];
107  list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))];
108  list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, i1:$clamp))];
109  list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
110                  !if(!eq(P.NumSrcArgs, 2), ret2,
111                  ret1));
112}
113
114class VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit VOP3Only = 0> :
115  VOP3_Pseudo<OpName, P,
116    !if(P.HasOpSel,
117        !if(P.HasModifiers,
118            getVOP3OpSelModPat<P, node>.ret,
119            getVOP3OpSelPat<P, node>.ret),
120        !if(P.HasModifiers,
121            getVOP3ModPat<P, node>.ret,
122            !if(P.HasIntClamp,
123                getVOP3ClampPat<P, node>.ret,
124                getVOP3Pat<P, node>.ret))),
125    VOP3Only, 0, P.HasOpSel> {
126
127  let IntClamp = P.HasIntClamp;
128  let AsmMatchConverter =
129    !if(P.HasOpSel,
130        "cvtVOP3OpSel",
131        !if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)),
132            "cvtVOP3",
133            ""));
134}
135
136// Special case for v_div_fmas_{f32|f64}, since it seems to be the
137// only VOP instruction that implicitly reads VCC.
138let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in {
139def VOP_F32_F32_F32_F32_VCC : VOPProfile<[f32, f32, f32, f32]> {
140  let Outs64 = (outs DstRC.RegClass:$vdst);
141}
142def VOP_F64_F64_F64_F64_VCC : VOPProfile<[f64, f64, f64, f64]> {
143  let Outs64 = (outs DstRC.RegClass:$vdst);
144}
145}
146
147class getVOP3VCC<VOPProfile P, SDPatternOperator node> {
148  list<dag> ret =
149    [(set P.DstVT:$vdst,
150      (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
151            (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
152            (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
153            (i1 VCC)))];
154}
155
156class VOP3Features<bit Clamp, bit OpSel, bit Packed> {
157  bit HasClamp = Clamp;
158  bit HasOpSel = OpSel;
159  bit IsPacked = Packed;
160}
161
162def VOP3_REGULAR : VOP3Features<0, 0, 0>;
163def VOP3_CLAMP   : VOP3Features<1, 0, 0>;
164def VOP3_OPSEL   : VOP3Features<1, 1, 0>;
165def VOP3_PACKED  : VOP3Features<1, 1, 1>;
166
167class VOP3_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOPProfile<P.ArgVT> {
168
169  let HasClamp = !if(Features.HasClamp, 1, P.HasClamp);
170  let HasOpSel = !if(Features.HasOpSel, 1, P.HasOpSel);
171  let IsPacked = !if(Features.IsPacked, 1, P.IsPacked);
172
173  let HasModifiers = !if(Features.IsPacked, 1, P.HasModifiers);
174
175  // FIXME: Hack to stop printing _e64
176  let Outs64 = (outs DstRC.RegClass:$vdst);
177  let Asm64 =
178    " " # !if(Features.HasOpSel,
179              getAsmVOP3OpSel<NumSrcArgs,
180                              HasIntClamp,
181                              HasSrc0FloatMods,
182                              HasSrc1FloatMods,
183                              HasSrc2FloatMods>.ret,
184              !if(Features.HasClamp,
185                  getAsm64<HasDst, NumSrcArgs, HasIntClamp,
186                           HasModifiers, HasOMod, DstVT>.ret,
187                  P.Asm64));
188  let NeedPatGen = P.NeedPatGen;
189}
190
191class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> {
192  // v_div_scale_{f32|f64} do not support input modifiers.
193  let HasModifiers = 0;
194  let HasOMod = 0;
195  let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
196  let Asm64 = " $vdst, $sdst, $src0, $src1, $src2";
197}
198
199def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32> {
200  // FIXME: Hack to stop printing _e64
201  let DstRC = RegisterOperand<VGPR_32>;
202}
203
204def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> {
205  // FIXME: Hack to stop printing _e64
206  let DstRC = RegisterOperand<VReg_64>;
207}
208
209def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> {
210  let HasClamp = 1;
211
212  // FIXME: Hack to stop printing _e64
213  let DstRC = RegisterOperand<VReg_64>;
214
215  let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
216  let Asm64 = " $vdst, $sdst, $src0, $src1, $src2$clamp";
217}
218
219//===----------------------------------------------------------------------===//
220// VOP3 INTERP
221//===----------------------------------------------------------------------===//
222
223class VOP3Interp<string OpName, VOPProfile P> : VOP3_Pseudo<OpName, P> {
224  let AsmMatchConverter = "cvtVOP3Interp";
225}
226
227def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> {
228  let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
229                   Attr:$attr, AttrChan:$attrchan,
230                   clampmod:$clamp, omod:$omod);
231
232  let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod";
233}
234
235def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> {
236  let Ins64 = (ins InterpSlot:$src0,
237                   Attr:$attr, AttrChan:$attrchan,
238                   clampmod:$clamp, omod:$omod);
239
240  let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
241
242  let HasClamp = 1;
243}
244
245class getInterp16Asm <bit HasSrc2, bit HasOMod> {
246  string src2 = !if(HasSrc2, ", $src2_modifiers", "");
247  string omod = !if(HasOMod, "$omod", "");
248  string ret =
249    " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod;
250}
251
252class getInterp16Ins <bit HasSrc2, bit HasOMod,
253                      Operand Src0Mod, Operand Src2Mod> {
254  dag ret = !if(HasSrc2,
255                !if(HasOMod,
256                    (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
257                         Attr:$attr, AttrChan:$attrchan,
258                         Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
259                         highmod:$high, clampmod:$clamp, omod:$omod),
260                    (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
261                         Attr:$attr, AttrChan:$attrchan,
262                         Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
263                         highmod:$high, clampmod:$clamp)
264                ),
265                (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
266                     Attr:$attr, AttrChan:$attrchan,
267                     highmod:$high, clampmod:$clamp, omod:$omod)
268            );
269}
270
271class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
272
273  let HasOMod = !if(!eq(DstVT.Value, f16.Value), 0, 1);
274  let HasHigh = 1;
275
276  let Outs64 = (outs VGPR_32:$vdst);
277  let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret;
278  let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret;
279}
280
281//===----------------------------------------------------------------------===//
282// VOP3 Instructions
283//===----------------------------------------------------------------------===//
284
285let isCommutable = 1 in {
286
287def V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
288def V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fmad>;
289def V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
290def V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
291def V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fma>;
292def V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>;
293
294let SchedRW = [WriteDoubleAdd] in {
295def V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, fma>;
296def V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, fadd, 1>;
297def V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, fmul, 1>;
298def V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum_like, 1>;
299def V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum_like, 1>;
300} // End SchedRW = [WriteDoubleAdd]
301
302let SchedRW = [WriteQuarterRate32] in {
303def V_MUL_LO_U32 : VOP3Inst <"v_mul_lo_u32", VOP3_Profile<VOP_I32_I32_I32>>;
304def V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", VOP3_Profile<VOP_I32_I32_I32>, mulhu>;
305def V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", VOP3_Profile<VOP_I32_I32_I32>>;
306def V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", VOP3_Profile<VOP_I32_I32_I32>, mulhs>;
307} // End SchedRW = [WriteQuarterRate32]
308
309let Uses = [VCC, EXEC] in {
310// v_div_fmas_f32:
311//   result = src0 * src1 + src2
312//   if (vcc)
313//     result *= 2^32
314//
315def V_DIV_FMAS_F32 : VOP3_Pseudo <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC,
316  getVOP3VCC<VOP_F32_F32_F32_F32_VCC, AMDGPUdiv_fmas>.ret> {
317  let SchedRW = [WriteFloatFMA];
318}
319// v_div_fmas_f64:
320//   result = src0 * src1 + src2
321//   if (vcc)
322//     result *= 2^64
323//
324def V_DIV_FMAS_F64 : VOP3_Pseudo <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC,
325  getVOP3VCC<VOP_F64_F64_F64_F64_VCC, AMDGPUdiv_fmas>.ret> {
326  let SchedRW = [WriteDouble];
327}
328} // End Uses = [VCC, EXEC]
329
330} // End isCommutable = 1
331
332def V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubeid>;
333def V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubesc>;
334def V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubetc>;
335def V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubema>;
336def V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>;
337def V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>;
338def V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>;
339def V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbit>;
340def V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>;
341def V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmin3>;
342def V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>;
343def V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>;
344def V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>;
345def V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>;
346def V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>;
347def V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>;
348def V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>;
349def V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>;
350def V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
351def V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
352def V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
353def V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
354def V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>;
355def V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUdiv_fixup>;
356
357let SchedRW = [WriteDoubleAdd] in {
358def V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>;
359def V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp, 1>;
360} // End SchedRW = [WriteDoubleAdd]
361
362def V_DIV_SCALE_F32 : VOP3_Pseudo <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> {
363  let SchedRW = [WriteFloatFMA, WriteSALU];
364  let AsmMatchConverter = "";
365}
366
367// Double precision division pre-scale.
368def V_DIV_SCALE_F64 : VOP3_Pseudo <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1> {
369  let SchedRW = [WriteDouble, WriteSALU];
370  let AsmMatchConverter = "";
371}
372
373def V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
374
375let Constraints = "@earlyclobber $vdst" in {
376def V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>;
377} // End Constraints = "@earlyclobber $vdst"
378
379def V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUtrig_preop> {
380  let SchedRW = [WriteDouble];
381}
382
383let SchedRW = [Write64Bit] in {
384// These instructions only exist on SI and CI
385let SubtargetPredicate = isSICI, Predicates = [isSICI] in {
386def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_PAT_GEN<VOP_I64_I64_I32>>, shl>;
387def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_PAT_GEN<VOP_I64_I64_I32>>, srl>;
388def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_PAT_GEN<VOP_I64_I64_I32>>, sra>;
389def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
390} // End SubtargetPredicate = isSICI, Predicates = [isSICI]
391
392let SubtargetPredicate = isVI in {
393def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
394def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
395def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>>;
396} // End SubtargetPredicate = isVI
397} // End SchedRW = [Write64Bit]
398
399let Predicates = [isVI] in {
400def : GCNPat <
401 (getDivergentFrag<shl>.ret i64:$x, i32:$y),
402 (V_LSHLREV_B64 $y, $x)
403>;
404def : AMDGPUPat <
405 (getDivergentFrag<srl>.ret i64:$x, i32:$y),
406 (V_LSHRREV_B64 $y, $x)
407>;
408def : AMDGPUPat <
409 (getDivergentFrag<sra>.ret i64:$x, i32:$y),
410 (V_ASHRREV_I64 $y, $x)
411>;
412}
413
414
415let SubtargetPredicate = isCIVI in {
416
417let Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] in {
418def V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>;
419def V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_V4I32, VOP3_CLAMP>>;
420} // End Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32]
421
422let isCommutable = 1 in {
423let SchedRW = [WriteQuarterRate32, WriteSALU] in {
424def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>;
425def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>;
426} // End SchedRW = [WriteDouble, WriteSALU]
427} // End isCommutable = 1
428
429} // End SubtargetPredicate = isCIVI
430
431
432def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup> {
433  let Predicates = [Has16BitInsts, isVIOnly];
434}
435def V_DIV_FIXUP_F16_gfx9 : VOP3Inst <"v_div_fixup_f16_gfx9",
436                                      VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUdiv_fixup> {
437  let renamedInGFX9 = 1;
438  let Predicates = [Has16BitInsts, isGFX9];
439}
440
441let SubtargetPredicate = Has16BitInsts, isCommutable = 1 in {
442
443let renamedInGFX9 = 1 in {
444def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
445def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
446def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
447def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>;
448def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>>;
449}
450
451let SubtargetPredicate = isGFX9 in {
452def V_MAD_F16_gfx9   : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>;
453def V_MAD_U16_gfx9   : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
454def V_MAD_I16_gfx9   : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
455def V_FMA_F16_gfx9   : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>;
456def V_INTERP_P2_F16_gfx9 : VOP3Interp <"v_interp_p2_f16_gfx9", VOP3_INTERP16<[f16, f32, i32, f32]>>;
457} // End SubtargetPredicate = isGFX9
458
459def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>>;
460def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>;
461
462} // End SubtargetPredicate = Has16BitInsts, isCommutable = 1
463
464let SubtargetPredicate = isVI in {
465def V_INTERP_P1_F32_e64  : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>;
466def V_INTERP_P2_F32_e64  : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>;
467def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>;
468
469def V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUperm>;
470} // End SubtargetPredicate = isVI
471
472let Predicates = [Has16BitInsts] in {
473
474multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2,
475                             Instruction inst, SDPatternOperator op3> {
476def : GCNPat <
477  (op2 (op1 i16:$src0, i16:$src1), i16:$src2),
478  (inst i16:$src0, i16:$src1, i16:$src2, (i1 0))
479>;
480
481}
482
483defm: Ternary_i16_Pats<mul, add, V_MAD_U16, zext>;
484defm: Ternary_i16_Pats<mul, add, V_MAD_I16, sext>;
485
486} // End Predicates = [Has16BitInsts]
487
488let SubtargetPredicate = isGFX9 in {
489def V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
490def V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
491def V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
492def V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
493def V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
494def V_AND_OR_B32 : VOP3Inst <"v_and_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
495def V_OR3_B32 : VOP3Inst <"v_or3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
496
497def V_XAD_U32 : VOP3Inst <"v_xad_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
498
499def V_MED3_F16 : VOP3Inst <"v_med3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmed3>;
500def V_MED3_I16 : VOP3Inst <"v_med3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmed3>;
501def V_MED3_U16 : VOP3Inst <"v_med3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumed3>;
502
503def V_MIN3_F16 : VOP3Inst <"v_min3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmin3>;
504def V_MIN3_I16 : VOP3Inst <"v_min3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmin3>;
505def V_MIN3_U16 : VOP3Inst <"v_min3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumin3>;
506
507def V_MAX3_F16 : VOP3Inst <"v_max3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmax3>;
508def V_MAX3_I16 : VOP3Inst <"v_max3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmax3>;
509def V_MAX3_U16 : VOP3Inst <"v_max3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumax3>;
510
511def V_ADD_I16 : VOP3Inst <"v_add_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>;
512def V_SUB_I16 : VOP3Inst <"v_sub_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>;
513
514def V_MAD_U32_U16 : VOP3Inst <"v_mad_u32_u16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>;
515def V_MAD_I32_I16 : VOP3Inst <"v_mad_i32_i16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>;
516
517def V_CVT_PKNORM_I16_F16 : VOP3Inst <"v_cvt_pknorm_i16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
518def V_CVT_PKNORM_U16_F16 : VOP3Inst <"v_cvt_pknorm_u16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
519
520def V_ADD_I32_gfx9 : VOP3Inst <"v_add_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>;
521def V_SUB_I32_gfx9 : VOP3Inst <"v_sub_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>;
522} // End SubtargetPredicate = isGFX9
523
524//===----------------------------------------------------------------------===//
525// Integer Clamp Patterns
526//===----------------------------------------------------------------------===//
527
528class getClampPat<VOPProfile P, SDPatternOperator node> {
529  dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2));
530  dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1));
531  dag ret1 = (P.DstVT (node P.Src0VT:$src0));
532  dag ret = !if(!eq(P.NumSrcArgs, 3), ret3,
533            !if(!eq(P.NumSrcArgs, 2), ret2,
534            ret1));
535}
536
537class getClampRes<VOPProfile P, Instruction inst> {
538  dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0));
539  dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0));
540  dag ret1 = (inst P.Src0VT:$src0, (i1 0));
541  dag ret = !if(!eq(P.NumSrcArgs, 3), ret3,
542            !if(!eq(P.NumSrcArgs, 2), ret2,
543            ret1));
544}
545
546class IntClampPat<VOP3Inst inst, SDPatternOperator node> : GCNPat<
547  getClampPat<inst.Pfl, node>.ret,
548  getClampRes<inst.Pfl, inst>.ret
549>;
550
551def : IntClampPat<V_MAD_I32_I24, AMDGPUmad_i24>;
552def : IntClampPat<V_MAD_U32_U24, AMDGPUmad_u24>;
553
554def : IntClampPat<V_SAD_U8, int_amdgcn_sad_u8>;
555def : IntClampPat<V_SAD_HI_U8, int_amdgcn_sad_hi_u8>;
556def : IntClampPat<V_SAD_U16, int_amdgcn_sad_u16>;
557
558def : IntClampPat<V_MSAD_U8, int_amdgcn_msad_u8>;
559def : IntClampPat<V_MQSAD_PK_U16_U8, int_amdgcn_mqsad_pk_u16_u8>;
560
561def : IntClampPat<V_QSAD_PK_U16_U8, int_amdgcn_qsad_pk_u16_u8>;
562def : IntClampPat<V_MQSAD_U32_U8, int_amdgcn_mqsad_u32_u8>;
563
564//===----------------------------------------------------------------------===//
565// Target
566//===----------------------------------------------------------------------===//
567
568//===----------------------------------------------------------------------===//
569// SI
570//===----------------------------------------------------------------------===//
571
572let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in {
573
574multiclass VOP3_Real_si<bits<9> op> {
575  def _si : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
576            VOP3e_si <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
577}
578
579multiclass VOP3be_Real_si<bits<9> op> {
580  def _si : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
581            VOP3be_si <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
582}
583
584} // End AssemblerPredicates = [isSICI], DecoderNamespace = "SICI"
585
586defm V_MAD_LEGACY_F32   : VOP3_Real_si <0x140>;
587defm V_MAD_F32          : VOP3_Real_si <0x141>;
588defm V_MAD_I32_I24      : VOP3_Real_si <0x142>;
589defm V_MAD_U32_U24      : VOP3_Real_si <0x143>;
590defm V_CUBEID_F32       : VOP3_Real_si <0x144>;
591defm V_CUBESC_F32       : VOP3_Real_si <0x145>;
592defm V_CUBETC_F32       : VOP3_Real_si <0x146>;
593defm V_CUBEMA_F32       : VOP3_Real_si <0x147>;
594defm V_BFE_U32          : VOP3_Real_si <0x148>;
595defm V_BFE_I32          : VOP3_Real_si <0x149>;
596defm V_BFI_B32          : VOP3_Real_si <0x14a>;
597defm V_FMA_F32          : VOP3_Real_si <0x14b>;
598defm V_FMA_F64          : VOP3_Real_si <0x14c>;
599defm V_LERP_U8          : VOP3_Real_si <0x14d>;
600defm V_ALIGNBIT_B32     : VOP3_Real_si <0x14e>;
601defm V_ALIGNBYTE_B32    : VOP3_Real_si <0x14f>;
602defm V_MULLIT_F32       : VOP3_Real_si <0x150>;
603defm V_MIN3_F32         : VOP3_Real_si <0x151>;
604defm V_MIN3_I32         : VOP3_Real_si <0x152>;
605defm V_MIN3_U32         : VOP3_Real_si <0x153>;
606defm V_MAX3_F32         : VOP3_Real_si <0x154>;
607defm V_MAX3_I32         : VOP3_Real_si <0x155>;
608defm V_MAX3_U32         : VOP3_Real_si <0x156>;
609defm V_MED3_F32         : VOP3_Real_si <0x157>;
610defm V_MED3_I32         : VOP3_Real_si <0x158>;
611defm V_MED3_U32         : VOP3_Real_si <0x159>;
612defm V_SAD_U8           : VOP3_Real_si <0x15a>;
613defm V_SAD_HI_U8        : VOP3_Real_si <0x15b>;
614defm V_SAD_U16          : VOP3_Real_si <0x15c>;
615defm V_SAD_U32          : VOP3_Real_si <0x15d>;
616defm V_CVT_PK_U8_F32    : VOP3_Real_si <0x15e>;
617defm V_DIV_FIXUP_F32    : VOP3_Real_si <0x15f>;
618defm V_DIV_FIXUP_F64    : VOP3_Real_si <0x160>;
619defm V_LSHL_B64         : VOP3_Real_si <0x161>;
620defm V_LSHR_B64         : VOP3_Real_si <0x162>;
621defm V_ASHR_I64         : VOP3_Real_si <0x163>;
622defm V_ADD_F64          : VOP3_Real_si <0x164>;
623defm V_MUL_F64          : VOP3_Real_si <0x165>;
624defm V_MIN_F64          : VOP3_Real_si <0x166>;
625defm V_MAX_F64          : VOP3_Real_si <0x167>;
626defm V_LDEXP_F64        : VOP3_Real_si <0x168>;
627defm V_MUL_LO_U32       : VOP3_Real_si <0x169>;
628defm V_MUL_HI_U32       : VOP3_Real_si <0x16a>;
629defm V_MUL_LO_I32       : VOP3_Real_si <0x16b>;
630defm V_MUL_HI_I32       : VOP3_Real_si <0x16c>;
631defm V_DIV_SCALE_F32    : VOP3be_Real_si <0x16d>;
632defm V_DIV_SCALE_F64    : VOP3be_Real_si <0x16e>;
633defm V_DIV_FMAS_F32     : VOP3_Real_si <0x16f>;
634defm V_DIV_FMAS_F64     : VOP3_Real_si <0x170>;
635defm V_MSAD_U8          : VOP3_Real_si <0x171>;
636defm V_MQSAD_PK_U16_U8  : VOP3_Real_si <0x173>;
637defm V_TRIG_PREOP_F64   : VOP3_Real_si <0x174>;
638
639//===----------------------------------------------------------------------===//
640// CI
641//===----------------------------------------------------------------------===//
642
643multiclass VOP3_Real_ci<bits<9> op> {
644  def _ci : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
645            VOP3e_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
646    let AssemblerPredicates = [isCIOnly];
647    let DecoderNamespace = "CI";
648  }
649}
650
651multiclass VOP3be_Real_ci<bits<9> op> {
652  def _ci : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
653            VOP3be_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
654    let AssemblerPredicates = [isCIOnly];
655    let DecoderNamespace = "CI";
656  }
657}
658
659defm V_QSAD_PK_U16_U8   : VOP3_Real_ci <0x172>;
660defm V_MQSAD_U32_U8     : VOP3_Real_ci <0x175>;
661defm V_MAD_U64_U32      : VOP3be_Real_ci <0x176>;
662defm V_MAD_I64_I32      : VOP3be_Real_ci <0x177>;
663
664//===----------------------------------------------------------------------===//
665// VI
666//===----------------------------------------------------------------------===//
667
668let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
669
670multiclass VOP3_Real_vi<bits<10> op> {
671  def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>,
672            VOP3e_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>;
673}
674
675multiclass VOP3be_Real_vi<bits<10> op> {
676  def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>,
677            VOP3be_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>;
678}
679
680multiclass VOP3OpSel_Real_gfx9<bits<10> op> {
681  def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>,
682            VOP3OpSel_gfx9 <op, !cast<VOP_Pseudo>(NAME).Pfl>;
683}
684
685multiclass VOP3Interp_Real_vi<bits<10> op> {
686  def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>,
687            VOP3Interp_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>;
688}
689
690} // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
691
692let AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI" in {
693
694multiclass VOP3_F16_Real_vi<bits<10> op> {
695  def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
696            VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
697}
698
699multiclass VOP3Interp_F16_Real_vi<bits<10> op> {
700  def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
701            VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
702}
703
704} // End AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI"
705
706let AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9" in {
707
708multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
709  def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
710            VOP3e_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> {
711              VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName);
712              let AsmString = AsmName # ps.AsmOperands;
713            }
714}
715
716multiclass VOP3OpSel_F16_Real_gfx9<bits<10> op, string AsmName> {
717  def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX9>,
718            VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
719              VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME);
720              let AsmString = AsmName # ps.AsmOperands;
721            }
722}
723
724multiclass VOP3Interp_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
725  def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
726            VOP3Interp_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> {
727              VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName);
728              let AsmString = AsmName # ps.AsmOperands;
729            }
730}
731
732multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> {
733  def _gfx9 : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX9>,
734              VOP3e_vi <op, !cast<VOP_Pseudo>(NAME).Pfl> {
735              VOP_Pseudo ps = !cast<VOP_Pseudo>(NAME);
736              let AsmString = AsmName # ps.AsmOperands;
737            }
738}
739
740} // End AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9"
741
742defm V_MAD_U64_U32      : VOP3be_Real_vi <0x1E8>;
743defm V_MAD_I64_I32      : VOP3be_Real_vi <0x1E9>;
744
745defm V_MAD_LEGACY_F32   : VOP3_Real_vi <0x1c0>;
746defm V_MAD_F32          : VOP3_Real_vi <0x1c1>;
747defm V_MAD_I32_I24      : VOP3_Real_vi <0x1c2>;
748defm V_MAD_U32_U24      : VOP3_Real_vi <0x1c3>;
749defm V_CUBEID_F32       : VOP3_Real_vi <0x1c4>;
750defm V_CUBESC_F32       : VOP3_Real_vi <0x1c5>;
751defm V_CUBETC_F32       : VOP3_Real_vi <0x1c6>;
752defm V_CUBEMA_F32       : VOP3_Real_vi <0x1c7>;
753defm V_BFE_U32          : VOP3_Real_vi <0x1c8>;
754defm V_BFE_I32          : VOP3_Real_vi <0x1c9>;
755defm V_BFI_B32          : VOP3_Real_vi <0x1ca>;
756defm V_FMA_F32          : VOP3_Real_vi <0x1cb>;
757defm V_FMA_F64          : VOP3_Real_vi <0x1cc>;
758defm V_LERP_U8          : VOP3_Real_vi <0x1cd>;
759defm V_ALIGNBIT_B32     : VOP3_Real_vi <0x1ce>;
760defm V_ALIGNBYTE_B32    : VOP3_Real_vi <0x1cf>;
761defm V_MIN3_F32         : VOP3_Real_vi <0x1d0>;
762defm V_MIN3_I32         : VOP3_Real_vi <0x1d1>;
763defm V_MIN3_U32         : VOP3_Real_vi <0x1d2>;
764defm V_MAX3_F32         : VOP3_Real_vi <0x1d3>;
765defm V_MAX3_I32         : VOP3_Real_vi <0x1d4>;
766defm V_MAX3_U32         : VOP3_Real_vi <0x1d5>;
767defm V_MED3_F32         : VOP3_Real_vi <0x1d6>;
768defm V_MED3_I32         : VOP3_Real_vi <0x1d7>;
769defm V_MED3_U32         : VOP3_Real_vi <0x1d8>;
770defm V_SAD_U8           : VOP3_Real_vi <0x1d9>;
771defm V_SAD_HI_U8        : VOP3_Real_vi <0x1da>;
772defm V_SAD_U16          : VOP3_Real_vi <0x1db>;
773defm V_SAD_U32          : VOP3_Real_vi <0x1dc>;
774defm V_CVT_PK_U8_F32    : VOP3_Real_vi <0x1dd>;
775defm V_DIV_FIXUP_F32    : VOP3_Real_vi <0x1de>;
776defm V_DIV_FIXUP_F64    : VOP3_Real_vi <0x1df>;
777defm V_DIV_SCALE_F32    : VOP3be_Real_vi <0x1e0>;
778defm V_DIV_SCALE_F64    : VOP3be_Real_vi <0x1e1>;
779defm V_DIV_FMAS_F32     : VOP3_Real_vi <0x1e2>;
780defm V_DIV_FMAS_F64     : VOP3_Real_vi <0x1e3>;
781defm V_MSAD_U8          : VOP3_Real_vi <0x1e4>;
782defm V_QSAD_PK_U16_U8   : VOP3_Real_vi <0x1e5>;
783defm V_MQSAD_PK_U16_U8  : VOP3_Real_vi <0x1e6>;
784defm V_MQSAD_U32_U8     : VOP3_Real_vi <0x1e7>;
785
786defm V_PERM_B32         : VOP3_Real_vi <0x1ed>;
787
788defm V_MAD_F16          : VOP3_F16_Real_vi <0x1ea>;
789defm V_MAD_U16          : VOP3_F16_Real_vi <0x1eb>;
790defm V_MAD_I16          : VOP3_F16_Real_vi <0x1ec>;
791defm V_FMA_F16          : VOP3_F16_Real_vi <0x1ee>;
792defm V_DIV_FIXUP_F16    : VOP3_F16_Real_vi <0x1ef>;
793defm V_INTERP_P2_F16    : VOP3Interp_F16_Real_vi <0x276>;
794
795defm V_MAD_LEGACY_F16       : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16",       "v_mad_legacy_f16">;
796defm V_MAD_LEGACY_U16       : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16",       "v_mad_legacy_u16">;
797defm V_MAD_LEGACY_I16       : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16",       "v_mad_legacy_i16">;
798defm V_FMA_LEGACY_F16       : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16",       "v_fma_legacy_f16">;
799defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16">;
800defm V_INTERP_P2_LEGACY_F16 : VOP3Interp_F16_Real_gfx9 <0x276, "V_INTERP_P2_F16", "v_interp_p2_legacy_f16">;
801
802defm V_MAD_F16_gfx9         : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">;
803defm V_MAD_U16_gfx9         : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">;
804defm V_MAD_I16_gfx9         : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">;
805defm V_FMA_F16_gfx9         : VOP3OpSel_F16_Real_gfx9 <0x206, "v_fma_f16">;
806defm V_DIV_FIXUP_F16_gfx9   : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">;
807defm V_INTERP_P2_F16_gfx9   : VOP3Interp_F16_Real_gfx9 <0x277, "V_INTERP_P2_F16_gfx9", "v_interp_p2_f16">;
808
809defm V_ADD_I32_gfx9         : VOP3_Real_gfx9 <0x29c, "v_add_i32">;
810defm V_SUB_I32_gfx9         : VOP3_Real_gfx9 <0x29d, "v_sub_i32">;
811
812defm V_INTERP_P1_F32_e64  : VOP3Interp_Real_vi <0x270>;
813defm V_INTERP_P2_F32_e64  : VOP3Interp_Real_vi <0x271>;
814defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>;
815
816defm V_INTERP_P1LL_F16  : VOP3Interp_Real_vi <0x274>;
817defm V_INTERP_P1LV_F16  : VOP3Interp_Real_vi <0x275>;
818defm V_ADD_F64          : VOP3_Real_vi <0x280>;
819defm V_MUL_F64          : VOP3_Real_vi <0x281>;
820defm V_MIN_F64          : VOP3_Real_vi <0x282>;
821defm V_MAX_F64          : VOP3_Real_vi <0x283>;
822defm V_LDEXP_F64        : VOP3_Real_vi <0x284>;
823defm V_MUL_LO_U32       : VOP3_Real_vi <0x285>;
824
825// removed from VI as identical to V_MUL_LO_U32
826let isAsmParserOnly = 1 in {
827defm V_MUL_LO_I32       : VOP3_Real_vi <0x285>;
828}
829
830defm V_MUL_HI_U32       : VOP3_Real_vi <0x286>;
831defm V_MUL_HI_I32       : VOP3_Real_vi <0x287>;
832
833defm V_READLANE_B32     : VOP3_Real_vi <0x289>;
834defm V_WRITELANE_B32    : VOP3_Real_vi <0x28a>;
835
836defm V_LSHLREV_B64      : VOP3_Real_vi <0x28f>;
837defm V_LSHRREV_B64      : VOP3_Real_vi <0x290>;
838defm V_ASHRREV_I64      : VOP3_Real_vi <0x291>;
839defm V_TRIG_PREOP_F64   : VOP3_Real_vi <0x292>;
840
841defm V_LSHL_ADD_U32 : VOP3_Real_vi <0x1fd>;
842defm V_ADD_LSHL_U32 : VOP3_Real_vi <0x1fe>;
843defm V_ADD3_U32 : VOP3_Real_vi <0x1ff>;
844defm V_LSHL_OR_B32 : VOP3_Real_vi <0x200>;
845defm V_AND_OR_B32 : VOP3_Real_vi <0x201>;
846defm V_OR3_B32 : VOP3_Real_vi <0x202>;
847defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx9 <0x2a0>;
848
849defm V_XAD_U32 : VOP3_Real_vi <0x1f3>;
850
851defm V_MIN3_F16 : VOP3OpSel_Real_gfx9 <0x1f4>;
852defm V_MIN3_I16 : VOP3OpSel_Real_gfx9 <0x1f5>;
853defm V_MIN3_U16 : VOP3OpSel_Real_gfx9 <0x1f6>;
854
855defm V_MAX3_F16 : VOP3OpSel_Real_gfx9 <0x1f7>;
856defm V_MAX3_I16 : VOP3OpSel_Real_gfx9 <0x1f8>;
857defm V_MAX3_U16 : VOP3OpSel_Real_gfx9 <0x1f9>;
858
859defm V_MED3_F16 : VOP3OpSel_Real_gfx9 <0x1fa>;
860defm V_MED3_I16 : VOP3OpSel_Real_gfx9 <0x1fb>;
861defm V_MED3_U16 : VOP3OpSel_Real_gfx9 <0x1fc>;
862
863defm V_ADD_I16  : VOP3OpSel_Real_gfx9 <0x29e>;
864defm V_SUB_I16  : VOP3OpSel_Real_gfx9 <0x29f>;
865
866defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx9 <0x1f1>;
867defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx9 <0x1f2>;
868
869defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx9 <0x299>;
870defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx9 <0x29a>;
871