1//===-- VOP3Instructions.td - Vector Instruction Defintions ---------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// VOP3 Classes 11//===----------------------------------------------------------------------===// 12 13class getVOP3ModPat<VOPProfile P, SDPatternOperator node> { 14 dag src0 = !if(P.HasOMod, 15 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 16 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)); 17 18 list<dag> ret3 = [(set P.DstVT:$vdst, 19 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 20 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), 21 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))]; 22 23 list<dag> ret2 = [(set P.DstVT:$vdst, 24 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 25 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))]; 26 27 list<dag> ret1 = [(set P.DstVT:$vdst, 28 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))]; 29 30 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 31 !if(!eq(P.NumSrcArgs, 2), ret2, 32 ret1)); 33} 34 35class getVOP3PModPat<VOPProfile P, SDPatternOperator node> { 36 list<dag> ret3 = [(set P.DstVT:$vdst, 37 (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp), 38 (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers))), 39 (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers)), 40 (P.Src2VT (VOP3PMods P.Src2VT:$src2, i32:$src2_modifiers))))]; 41 42 list<dag> ret2 = [(set P.DstVT:$vdst, 43 (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)), 44 (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers))), 45 (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers))))]; 46 47 list<dag> ret1 = [(set P.DstVT:$vdst, 48 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))]; 49 50 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 51 !if(!eq(P.NumSrcArgs, 2), ret2, 52 ret1)); 53} 54 55class getVOP3OpSelPat<VOPProfile P, SDPatternOperator node> { 56 list<dag> ret3 = [(set P.DstVT:$vdst, 57 (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp), 58 (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))), 59 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)), 60 (P.Src2VT (VOP3OpSel P.Src2VT:$src2, i32:$src2_modifiers))))]; 61 62 list<dag> ret2 = [(set P.DstVT:$vdst, 63 (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)), 64 (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))), 65 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))]; 66 67 list<dag> ret1 = [(set P.DstVT:$vdst, 68 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))]; 69 70 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 71 !if(!eq(P.NumSrcArgs, 2), ret2, 72 ret1)); 73} 74 75class getVOP3OpSelModPat<VOPProfile P, SDPatternOperator node> { 76 list<dag> ret3 = [(set P.DstVT:$vdst, 77 (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp), 78 (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 79 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)), 80 (P.Src2VT (VOP3OpSelMods P.Src2VT:$src2, i32:$src2_modifiers))))]; 81 82 list<dag> ret2 = [(set P.DstVT:$vdst, 83 (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)), 84 (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 85 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))]; 86 87 list<dag> ret1 = [(set P.DstVT:$vdst, 88 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))]; 89 90 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 91 !if(!eq(P.NumSrcArgs, 2), ret2, 92 ret1)); 93} 94 95class getVOP3Pat<VOPProfile P, SDPatternOperator node> { 96 list<dag> ret3 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))]; 97 list<dag> ret2 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$src1))]; 98 list<dag> ret1 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0))]; 99 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 100 !if(!eq(P.NumSrcArgs, 2), ret2, 101 ret1)); 102} 103 104class getVOP3ClampPat<VOPProfile P, SDPatternOperator node> { 105 list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i1:$clamp))]; 106 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))]; 107 list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, i1:$clamp))]; 108 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 109 !if(!eq(P.NumSrcArgs, 2), ret2, 110 ret1)); 111} 112 113class getVOP3MAIPat<VOPProfile P, SDPatternOperator node> { 114 list<dag> ret = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, 115 timm:$cbsz, timm:$abid, timm:$blgp))]; 116} 117 118class VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit VOP3Only = 0> : 119 VOP3_Pseudo<OpName, P, 120 !if(P.HasOpSel, 121 !if(P.HasModifiers, 122 getVOP3OpSelModPat<P, node>.ret, 123 getVOP3OpSelPat<P, node>.ret), 124 !if(P.HasModifiers, 125 getVOP3ModPat<P, node>.ret, 126 !if(P.HasIntClamp, 127 getVOP3ClampPat<P, node>.ret, 128 !if (P.IsMAI, 129 getVOP3MAIPat<P, node>.ret, 130 getVOP3Pat<P, node>.ret)))), 131 VOP3Only, 0, P.HasOpSel> { 132 133 let IntClamp = P.HasIntClamp; 134 let AsmMatchConverter = 135 !if(P.HasOpSel, 136 "cvtVOP3OpSel", 137 !if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)), 138 "cvtVOP3", 139 "")); 140} 141 142// Special case for v_div_fmas_{f32|f64}, since it seems to be the 143// only VOP instruction that implicitly reads VCC. 144let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in { 145def VOP_F32_F32_F32_F32_VCC : VOPProfile<[f32, f32, f32, f32]> { 146 let Outs64 = (outs DstRC.RegClass:$vdst); 147} 148def VOP_F64_F64_F64_F64_VCC : VOPProfile<[f64, f64, f64, f64]> { 149 let Outs64 = (outs DstRC.RegClass:$vdst); 150} 151} 152 153class VOP3Features<bit Clamp, bit OpSel, bit Packed, bit MAI> { 154 bit HasClamp = Clamp; 155 bit HasOpSel = OpSel; 156 bit IsPacked = Packed; 157 bit IsMAI = MAI; 158} 159 160def VOP3_REGULAR : VOP3Features<0, 0, 0, 0>; 161def VOP3_CLAMP : VOP3Features<1, 0, 0, 0>; 162def VOP3_OPSEL : VOP3Features<1, 1, 0, 0>; 163def VOP3_PACKED : VOP3Features<1, 1, 1, 0>; 164def VOP3_MAI : VOP3Features<0, 0, 0, 1>; 165 166class VOP3_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOPProfile<P.ArgVT> { 167 168 let HasClamp = !if(Features.HasClamp, 1, P.HasClamp); 169 let HasOpSel = !if(Features.HasOpSel, 1, P.HasOpSel); 170 let IsMAI = !if(Features.IsMAI, 1, P.IsMAI); 171 let IsPacked = !if(Features.IsPacked, 1, P.IsPacked); 172 173 let HasModifiers = !if(Features.IsPacked, !if(Features.IsMAI, 0, 1), P.HasModifiers); 174 175 // FIXME: Hack to stop printing _e64 176 let Outs64 = (outs DstRC.RegClass:$vdst); 177 let Asm64 = 178 " " # !if(Features.HasOpSel, 179 getAsmVOP3OpSel<NumSrcArgs, 180 HasIntClamp, 181 HasSrc0FloatMods, 182 HasSrc1FloatMods, 183 HasSrc2FloatMods>.ret, 184 !if(Features.HasClamp, 185 getAsm64<HasDst, NumSrcArgs, HasIntClamp, 186 HasModifiers, HasOMod, DstVT>.ret, 187 P.Asm64)); 188 let NeedPatGen = P.NeedPatGen; 189} 190 191class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> { 192 // v_div_scale_{f32|f64} do not support input modifiers. 193 let HasModifiers = 0; 194 let HasClamp = 0; 195 let HasOMod = 0; 196 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 197 let Asm64 = " $vdst, $sdst, $src0, $src1, $src2"; 198} 199 200def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32> { 201 // FIXME: Hack to stop printing _e64 202 let DstRC = RegisterOperand<VGPR_32>; 203} 204 205def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> { 206 // FIXME: Hack to stop printing _e64 207 let DstRC = RegisterOperand<VReg_64>; 208} 209 210def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> { 211 let HasClamp = 1; 212 213 // FIXME: Hack to stop printing _e64 214 let DstRC = RegisterOperand<VReg_64>; 215 216 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 217 let Asm64 = " $vdst, $sdst, $src0, $src1, $src2$clamp"; 218} 219 220//===----------------------------------------------------------------------===// 221// VOP3 INTERP 222//===----------------------------------------------------------------------===// 223 224class VOP3Interp<string OpName, VOPProfile P, list<dag> pattern = []> : 225 VOP3_Pseudo<OpName, P, pattern> { 226 let AsmMatchConverter = "cvtVOP3Interp"; 227} 228 229def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> { 230 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 231 Attr:$attr, AttrChan:$attrchan, 232 clampmod0:$clamp, omod0:$omod); 233 234 let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod"; 235} 236 237def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> { 238 let Ins64 = (ins InterpSlot:$src0, 239 Attr:$attr, AttrChan:$attrchan, 240 clampmod0:$clamp, omod0:$omod); 241 242 let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod"; 243 244 let HasClamp = 1; 245} 246 247class getInterp16Asm <bit HasSrc2, bit HasOMod> { 248 string src2 = !if(HasSrc2, ", $src2_modifiers", ""); 249 string omod = !if(HasOMod, "$omod", ""); 250 string ret = 251 " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod; 252} 253 254class getInterp16Ins <bit HasSrc2, bit HasOMod, 255 Operand Src0Mod, Operand Src2Mod> { 256 dag ret = !if(HasSrc2, 257 !if(HasOMod, 258 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 259 Attr:$attr, AttrChan:$attrchan, 260 Src2Mod:$src2_modifiers, VRegSrc_32:$src2, 261 highmod:$high, clampmod0:$clamp, omod0:$omod), 262 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 263 Attr:$attr, AttrChan:$attrchan, 264 Src2Mod:$src2_modifiers, VRegSrc_32:$src2, 265 highmod:$high, clampmod0:$clamp) 266 ), 267 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 268 Attr:$attr, AttrChan:$attrchan, 269 highmod:$high, clampmod0:$clamp, omod0:$omod) 270 ); 271} 272 273class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> { 274 275 let HasOMod = !if(!eq(DstVT.Value, f16.Value), 0, 1); 276 let HasHigh = 1; 277 278 let Outs64 = (outs VGPR_32:$vdst); 279 let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret; 280 let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret; 281} 282 283//===----------------------------------------------------------------------===// 284// VOP3 Instructions 285//===----------------------------------------------------------------------===// 286 287let isCommutable = 1 in { 288 289def V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 290def V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fmad>; 291def V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 292def V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 293def V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fma>; 294def V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>; 295 296let SchedRW = [WriteDoubleAdd] in { 297let FPDPRounding = 1 in { 298def V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, fma>; 299def V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, fadd, 1>; 300def V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, fmul, 1>; 301} // End FPDPRounding = 1 302def V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum_like, 1>; 303def V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum_like, 1>; 304} // End SchedRW = [WriteDoubleAdd] 305 306let SchedRW = [WriteQuarterRate32] in { 307def V_MUL_LO_U32 : VOP3Inst <"v_mul_lo_u32", VOP3_Profile<VOP_I32_I32_I32>, mul>; 308def V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", VOP3_Profile<VOP_I32_I32_I32>, mulhu>; 309def V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", VOP3_Profile<VOP_I32_I32_I32>>; 310def V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", VOP3_Profile<VOP_I32_I32_I32>, mulhs>; 311} // End SchedRW = [WriteQuarterRate32] 312 313let Uses = [VCC, EXEC] in { 314// v_div_fmas_f32: 315// result = src0 * src1 + src2 316// if (vcc) 317// result *= 2^32 318// 319def V_DIV_FMAS_F32 : VOP3_Pseudo <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC, []> { 320 let SchedRW = [WriteFloatFMA]; 321} 322// v_div_fmas_f64: 323// result = src0 * src1 + src2 324// if (vcc) 325// result *= 2^64 326// 327def V_DIV_FMAS_F64 : VOP3_Pseudo <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC, []> { 328 let SchedRW = [WriteDouble]; 329 let FPDPRounding = 1; 330} 331} // End Uses = [VCC, EXEC] 332 333} // End isCommutable = 1 334 335def V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubeid>; 336def V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubesc>; 337def V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubetc>; 338def V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubema>; 339def V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>; 340def V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>; 341def V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>; 342def V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbit>; 343def V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>; 344def V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmin3>; 345def V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>; 346def V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>; 347def V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>; 348def V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>; 349def V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>; 350def V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>; 351def V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>; 352def V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>; 353def V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 354def V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 355def V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 356def V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 357def V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>; 358def V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUdiv_fixup>; 359 360let SchedRW = [WriteDoubleAdd], FPDPRounding = 1 in { 361def V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>; 362def V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp, 1>; 363} // End SchedRW = [WriteDoubleAdd], FPDPRounding = 1 364 365def V_DIV_SCALE_F32 : VOP3_Pseudo <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> { 366 let SchedRW = [WriteFloatFMA, WriteSALU]; 367 let AsmMatchConverter = ""; 368} 369 370// Double precision division pre-scale. 371def V_DIV_SCALE_F64 : VOP3_Pseudo <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1> { 372 let SchedRW = [WriteDouble, WriteSALU]; 373 let AsmMatchConverter = ""; 374 let FPDPRounding = 1; 375} 376 377def V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 378 379let Constraints = "@earlyclobber $vdst" in { 380def V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>; 381} // End Constraints = "@earlyclobber $vdst" 382 383def V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUtrig_preop> { 384 let SchedRW = [WriteDouble]; 385} 386 387let SchedRW = [Write64Bit] in { 388let SubtargetPredicate = isGFX6GFX7 in { 389def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>, shl>; 390def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>, srl>; 391def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>, sra>; 392} // End SubtargetPredicate = isGFX6GFX7 393let SubtargetPredicate = isGFX6GFX7GFX10 in { 394def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 395} // End SubtargetPredicate = isGFX6GFX7GFX10 396 397let SubtargetPredicate = isGFX8Plus in { 398def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshl_rev>; 399def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshr_rev>; 400def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, ashr_rev>; 401} // End SubtargetPredicate = isGFX8Plus 402} // End SchedRW = [Write64Bit] 403 404 405let SchedRW = [Write32Bit] in { 406let SubtargetPredicate = isGFX8Plus in { 407def V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUperm>; 408} // End SubtargetPredicate = isGFX8Plus 409} // End SchedRW = [Write32Bit] 410 411let SubtargetPredicate = isGFX7Plus in { 412 413let Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] in { 414def V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>; 415def V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_V4I32, VOP3_CLAMP>>; 416} // End Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] 417 418let isCommutable = 1 in { 419let SchedRW = [WriteQuarterRate32, WriteSALU] in { 420def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>; 421def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>; 422} // End SchedRW = [WriteDouble, WriteSALU] 423} // End isCommutable = 1 424 425} // End SubtargetPredicate = isGFX7Plus 426 427 428def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup> { 429 let Predicates = [Has16BitInsts, isGFX8Only]; 430 let FPDPRounding = 1; 431} 432def V_DIV_FIXUP_F16_gfx9 : VOP3Inst <"v_div_fixup_f16_gfx9", 433 VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUdiv_fixup> { 434 let renamedInGFX9 = 1; 435 let Predicates = [Has16BitInsts, isGFX9Plus]; 436 let FPDPRounding = 1; 437} 438 439def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma> { 440 let Predicates = [Has16BitInsts, isGFX8Only]; 441 let FPDPRounding = 1; 442} 443def V_FMA_F16_gfx9 : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, fma> { 444 let renamedInGFX9 = 1; 445 let Predicates = [Has16BitInsts, isGFX9Plus]; 446 let FPDPRounding = 1; 447} 448 449let SubtargetPredicate = Has16BitInsts, isCommutable = 1 in { 450 451let renamedInGFX9 = 1 in { 452def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>; 453def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>; 454let FPDPRounding = 1 in { 455def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>; 456let Uses = [M0, EXEC] in { 457// For some reason the intrinsic operands are in a different order 458// from the instruction operands. 459def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>, 460 [(set f16:$vdst, 461 (int_amdgcn_interp_p2_f16 (VOP3Mods f32:$src2, i32:$src2_modifiers), 462 (VOP3Mods f32:$src0, i32:$src0_modifiers), 463 (i32 timm:$attrchan), 464 (i32 timm:$attr), 465 (i1 timm:$high), 466 M0))]>; 467} // End Uses = [M0, EXEC] 468} // End FPDPRounding = 1 469} // End renamedInGFX9 = 1 470 471let SubtargetPredicate = isGFX9Only in { 472def V_MAD_F16_gfx9 : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>> { 473 let FPDPRounding = 1; 474} 475} // End SubtargetPredicate = isGFX9Only 476 477let SubtargetPredicate = isGFX9Plus in { 478def V_MAD_U16_gfx9 : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>; 479def V_MAD_I16_gfx9 : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>; 480def V_INTERP_P2_F16_gfx9 : VOP3Interp <"v_interp_p2_f16_gfx9", VOP3_INTERP16<[f16, f32, i32, f32]>>; 481} // End SubtargetPredicate = isGFX9Plus 482 483let Uses = [M0, EXEC], FPDPRounding = 1 in { 484def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>, 485 [(set f32:$vdst, (int_amdgcn_interp_p1_f16 (VOP3Mods f32:$src0, i32:$src0_modifiers), 486 (i32 timm:$attrchan), 487 (i32 timm:$attr), 488 (i1 timm:$high), M0))]> { 489 // This predicate should only apply to the selection pattern. The 490 // instruction still exists and should decode on subtargets with 491 // other bank counts. 492 let OtherPredicates = [has32BankLDS]; 493} 494 495 496def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>; 497} // End Uses = [M0, EXEC], FPDPRounding = 1 498 499} // End SubtargetPredicate = Has16BitInsts, isCommutable = 1 500 501let SubtargetPredicate = isGFX8Plus, Uses = [M0, EXEC] in { 502def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>; 503def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>; 504def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>; 505} // End SubtargetPredicate = isGFX8Plus, Uses = [M0, EXEC] 506 507let Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] in { 508 509multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2, 510 Instruction inst, SDPatternOperator op3> { 511def : GCNPat < 512 (op2 (op1 i16:$src0, i16:$src1), i16:$src2), 513 (inst i16:$src0, i16:$src1, i16:$src2, (i1 0)) 514>; 515 516} 517 518defm: Ternary_i16_Pats<mul, add, V_MAD_U16, zext>; 519defm: Ternary_i16_Pats<mul, add, V_MAD_I16, sext>; 520 521} // End Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] 522 523let Predicates = [Has16BitInsts, isGFX10Plus] in { 524 525multiclass Ternary_i16_Pats_gfx9<SDPatternOperator op1, SDPatternOperator op2, 526 Instruction inst, SDPatternOperator op3> { 527def : GCNPat < 528 (op2 (op1 i16:$src0, i16:$src1), i16:$src2), 529 (inst SRCMODS.NONE, $src0, SRCMODS.NONE, $src1, SRCMODS.NONE, $src2, DSTCLAMP.NONE) 530>; 531 532} 533 534defm: Ternary_i16_Pats_gfx9<mul, add, V_MAD_U16_gfx9, zext>; 535defm: Ternary_i16_Pats_gfx9<mul, add, V_MAD_I16_gfx9, sext>; 536 537} // End Predicates = [Has16BitInsts, isGFX10Plus] 538 539class ThreeOpFrag<SDPatternOperator op1, SDPatternOperator op2> : PatFrag< 540 (ops node:$x, node:$y, node:$z), 541 // When the inner operation is used multiple times, selecting 3-op 542 // instructions may still be beneficial -- if the other users can be 543 // combined similarly. Let's be conservative for now. 544 (op2 (HasOneUseBinOp<op1> node:$x, node:$y), node:$z), 545 [{ 546 // Only use VALU ops when the result is divergent. 547 if (!N->isDivergent()) 548 return false; 549 550 // Check constant bus limitations. 551 // 552 // Note: Use !isDivergent as a conservative proxy for whether the value 553 // is in an SGPR (uniform values can end up in VGPRs as well). 554 unsigned ConstantBusUses = 0; 555 for (unsigned i = 0; i < 3; ++i) { 556 if (!Operands[i]->isDivergent() && 557 !isInlineImmediate(Operands[i].getNode())) { 558 ConstantBusUses++; 559 // This uses AMDGPU::V_ADD3_U32, but all three operand instructions 560 // have the same constant bus limit. 561 if (ConstantBusUses > Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32)) 562 return false; 563 } 564 } 565 566 return true; 567 }]> { 568 let PredicateCodeUsesOperands = 1; 569 570 // The divergence predicate is irrelevant in GlobalISel, as we have 571 // proper register bank checks. We also force all VOP instruction 572 // operands to VGPR, so we should not need to check the constant bus 573 // restriction. 574 // 575 // FIXME: With unlucky SGPR operands, we could penalize code by 576 // blocking folding SGPR->VGPR copies later. 577 // FIXME: There's no register bank verifier 578 // FIXME: Should add a way for the emitter to recognize this is a 579 // trivially true predicate to eliminate the check. 580 let GISelPredicateCode = [{return true;}]; 581} 582 583let SubtargetPredicate = isGFX9Plus in { 584def V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 585def V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 586def V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 587def V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 588def V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 589def V_AND_OR_B32 : VOP3Inst <"v_and_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 590def V_OR3_B32 : VOP3Inst <"v_or3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 591 592def V_XAD_U32 : VOP3Inst <"v_xad_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 593 594def V_MED3_F16 : VOP3Inst <"v_med3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmed3>; 595def V_MED3_I16 : VOP3Inst <"v_med3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmed3>; 596def V_MED3_U16 : VOP3Inst <"v_med3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumed3>; 597 598def V_MIN3_F16 : VOP3Inst <"v_min3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmin3>; 599def V_MIN3_I16 : VOP3Inst <"v_min3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmin3>; 600def V_MIN3_U16 : VOP3Inst <"v_min3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumin3>; 601 602def V_MAX3_F16 : VOP3Inst <"v_max3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmax3>; 603def V_MAX3_I16 : VOP3Inst <"v_max3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmax3>; 604def V_MAX3_U16 : VOP3Inst <"v_max3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumax3>; 605 606def V_ADD_I16 : VOP3Inst <"v_add_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>; 607def V_SUB_I16 : VOP3Inst <"v_sub_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>; 608 609def V_MAD_U32_U16 : VOP3Inst <"v_mad_u32_u16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>; 610def V_MAD_I32_I16 : VOP3Inst <"v_mad_i32_i16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>; 611 612def V_CVT_PKNORM_I16_F16 : VOP3Inst <"v_cvt_pknorm_i16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 613def V_CVT_PKNORM_U16_F16 : VOP3Inst <"v_cvt_pknorm_u16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 614 615def V_ADD_I32_gfx9 : VOP3Inst <"v_add_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>; 616def V_SUB_I32_gfx9 : VOP3Inst <"v_sub_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>; 617 618 619class ThreeOp_i32_Pats <SDPatternOperator op1, SDPatternOperator op2, Instruction inst> : GCNPat < 620 // This matches (op2 (op1 i32:$src0, i32:$src1), i32:$src2) with conditions. 621 (ThreeOpFrag<op1, op2> i32:$src0, i32:$src1, i32:$src2), 622 (inst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2) 623>; 624 625def : ThreeOp_i32_Pats<shl, add, V_LSHL_ADD_U32>; 626def : ThreeOp_i32_Pats<add, shl, V_ADD_LSHL_U32>; 627def : ThreeOp_i32_Pats<add, add, V_ADD3_U32>; 628def : ThreeOp_i32_Pats<shl, or, V_LSHL_OR_B32>; 629def : ThreeOp_i32_Pats<and, or, V_AND_OR_B32>; 630def : ThreeOp_i32_Pats<or, or, V_OR3_B32>; 631def : ThreeOp_i32_Pats<xor, add, V_XAD_U32>; 632 633} // End SubtargetPredicate = isGFX9Plus 634 635def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3_OPSEL> { 636 let Src0RC64 = VRegSrc_32; 637 let Src1RC64 = SCSrc_b32; 638 let Src2RC64 = SCSrc_b32; 639 let InsVOP3OpSel = (ins IntOpSelMods:$src0_modifiers, VRegSrc_32:$src0, 640 IntOpSelMods:$src1_modifiers, SCSrc_b32:$src1, 641 IntOpSelMods:$src2_modifiers, SCSrc_b32:$src2, 642 VGPR_32:$vdst_in, op_sel:$op_sel); 643 let HasClamp = 0; 644 let HasOMod = 0; 645} 646 647class PermlanePat<SDPatternOperator permlane, 648 Instruction inst> : GCNPat< 649 (permlane i32:$vdst_in, i32:$src0, i32:$src1, i32:$src2, 650 timm:$fi, timm:$bc), 651 (inst (as_i1timm $fi), VGPR_32:$src0, (as_i1timm $bc), 652 SCSrc_b32:$src1, 0, SCSrc_b32:$src2, VGPR_32:$vdst_in) 653>; 654 655// Permlane intrinsic that has either fetch invalid or bound control 656// fields enabled. 657class BoundControlOrFetchInvalidPermlane<SDPatternOperator permlane> : 658 PatFrag<(ops node:$vdst_in, node:$src0, node:$src1, node:$src2, 659 node:$fi, node:$bc), 660 (permlane node:$vdst_in, node:$src0, node: 661 $src1, node:$src2, node:$fi, node:$bc)> { 662 let PredicateCode = [{ return N->getConstantOperandVal(5) != 0 || 663 N->getConstantOperandVal(6) != 0; }]; 664 let GISelPredicateCode = [{ 665 return MI.getOperand(6).getImm() != 0 || 666 MI.getOperand(7).getImm() != 0; 667 }]; 668} 669 670// Drop the input value if it won't be read. 671class PermlaneDiscardVDstIn<SDPatternOperator permlane, 672 Instruction inst> : GCNPat< 673 (permlane srcvalue, i32:$src0, i32:$src1, i32:$src2, 674 timm:$fi, timm:$bc), 675 (inst (as_i1timm $fi), VGPR_32:$src0, (as_i1timm $bc), 676 SCSrc_b32:$src1, 0, SCSrc_b32:$src2, 677 (IMPLICIT_DEF)) 678>; 679 680 681let SubtargetPredicate = isGFX10Plus in { 682 def V_XOR3_B32 : VOP3Inst <"v_xor3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 683 def : ThreeOp_i32_Pats<xor, xor, V_XOR3_B32>; 684 685 let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in { 686 def V_PERMLANE16_B32 : VOP3Inst <"v_permlane16_b32", VOP3_PERMLANE_Profile>; 687 def V_PERMLANEX16_B32 : VOP3Inst <"v_permlanex16_b32", VOP3_PERMLANE_Profile>; 688 } // End $vdst = $vdst_in, DisableEncoding $vdst_in 689 690 def : PermlanePat<int_amdgcn_permlane16, V_PERMLANE16_B32>; 691 def : PermlanePat<int_amdgcn_permlanex16, V_PERMLANEX16_B32>; 692 693 def : PermlaneDiscardVDstIn< 694 BoundControlOrFetchInvalidPermlane<int_amdgcn_permlane16>, 695 V_PERMLANE16_B32>; 696 def : PermlaneDiscardVDstIn< 697 BoundControlOrFetchInvalidPermlane<int_amdgcn_permlanex16>, 698 V_PERMLANEX16_B32>; 699} // End SubtargetPredicate = isGFX10Plus 700 701//===----------------------------------------------------------------------===// 702// Integer Clamp Patterns 703//===----------------------------------------------------------------------===// 704 705class getClampPat<VOPProfile P, SDPatternOperator node> { 706 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2)); 707 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1)); 708 dag ret1 = (P.DstVT (node P.Src0VT:$src0)); 709 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3, 710 !if(!eq(P.NumSrcArgs, 2), ret2, 711 ret1)); 712} 713 714class getClampRes<VOPProfile P, Instruction inst> { 715 dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0)); 716 dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0)); 717 dag ret1 = (inst P.Src0VT:$src0, (i1 0)); 718 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3, 719 !if(!eq(P.NumSrcArgs, 2), ret2, 720 ret1)); 721} 722 723class IntClampPat<VOP3Inst inst, SDPatternOperator node> : GCNPat< 724 getClampPat<inst.Pfl, node>.ret, 725 getClampRes<inst.Pfl, inst>.ret 726>; 727 728def : IntClampPat<V_MAD_I32_I24, AMDGPUmad_i24>; 729def : IntClampPat<V_MAD_U32_U24, AMDGPUmad_u24>; 730 731def : IntClampPat<V_SAD_U8, int_amdgcn_sad_u8>; 732def : IntClampPat<V_SAD_HI_U8, int_amdgcn_sad_hi_u8>; 733def : IntClampPat<V_SAD_U16, int_amdgcn_sad_u16>; 734 735def : IntClampPat<V_MSAD_U8, int_amdgcn_msad_u8>; 736def : IntClampPat<V_MQSAD_PK_U16_U8, int_amdgcn_mqsad_pk_u16_u8>; 737 738def : IntClampPat<V_QSAD_PK_U16_U8, int_amdgcn_qsad_pk_u16_u8>; 739def : IntClampPat<V_MQSAD_U32_U8, int_amdgcn_mqsad_u32_u8>; 740 741 742//===----------------------------------------------------------------------===// 743// Target-specific instruction encodings. 744//===----------------------------------------------------------------------===// 745 746//===----------------------------------------------------------------------===// 747// GFX10. 748//===----------------------------------------------------------------------===// 749 750let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in { 751 multiclass VOP3_Real_gfx10<bits<10> op> { 752 def _gfx10 : 753 VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX10>, 754 VOP3e_gfx10<op, !cast<VOP_Pseudo>(NAME).Pfl>; 755 } 756 multiclass VOP3_Real_gfx10_with_name<bits<10> op, string opName, 757 string asmName> { 758 def _gfx10 : 759 VOP3_Real<!cast<VOP3_Pseudo>(opName), SIEncodingFamily.GFX10>, 760 VOP3e_gfx10<op, !cast<VOP3_Pseudo>(opName).Pfl> { 761 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName); 762 let AsmString = asmName # ps.AsmOperands; 763 } 764 } 765 multiclass VOP3be_Real_gfx10<bits<10> op> { 766 def _gfx10 : 767 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>, 768 VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME).Pfl>; 769 } 770 multiclass VOP3Interp_Real_gfx10<bits<10> op> { 771 def _gfx10 : 772 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>, 773 VOP3Interp_gfx10<op, !cast<VOP3_Pseudo>(NAME).Pfl>; 774 } 775 multiclass VOP3OpSel_Real_gfx10<bits<10> op> { 776 def _gfx10 : 777 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>, 778 VOP3OpSel_gfx10<op, !cast<VOP3_Pseudo>(NAME).Pfl>; 779 } 780 multiclass VOP3OpSel_Real_gfx10_with_name<bits<10> op, string opName, 781 string asmName> { 782 def _gfx10 : 783 VOP3_Real<!cast<VOP3_Pseudo>(opName), SIEncodingFamily.GFX10>, 784 VOP3OpSel_gfx10<op, !cast<VOP3_Pseudo>(opName).Pfl> { 785 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName); 786 let AsmString = asmName # ps.AsmOperands; 787 } 788 } 789} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" 790 791defm V_READLANE_B32 : VOP3_Real_gfx10<0x360>; 792 793let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in) in { 794 defm V_WRITELANE_B32 : VOP3_Real_gfx10<0x361>; 795} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in) 796 797defm V_XOR3_B32 : VOP3_Real_gfx10<0x178>; 798defm V_LSHLREV_B64 : VOP3_Real_gfx10<0x2ff>; 799defm V_LSHRREV_B64 : VOP3_Real_gfx10<0x300>; 800defm V_ASHRREV_I64 : VOP3_Real_gfx10<0x301>; 801defm V_PERM_B32 : VOP3_Real_gfx10<0x344>; 802defm V_XAD_U32 : VOP3_Real_gfx10<0x345>; 803defm V_LSHL_ADD_U32 : VOP3_Real_gfx10<0x346>; 804defm V_ADD_LSHL_U32 : VOP3_Real_gfx10<0x347>; 805defm V_ADD3_U32 : VOP3_Real_gfx10<0x36d>; 806defm V_LSHL_OR_B32 : VOP3_Real_gfx10<0x36f>; 807defm V_AND_OR_B32 : VOP3_Real_gfx10<0x371>; 808defm V_OR3_B32 : VOP3_Real_gfx10<0x372>; 809 810// TODO-GFX10: add MC tests for v_add/sub_nc_i16 811defm V_ADD_NC_I16 : 812 VOP3OpSel_Real_gfx10_with_name<0x30d, "V_ADD_I16", "v_add_nc_i16">; 813defm V_SUB_NC_I16 : 814 VOP3OpSel_Real_gfx10_with_name<0x30e, "V_SUB_I16", "v_sub_nc_i16">; 815defm V_SUB_NC_I32 : 816 VOP3_Real_gfx10_with_name<0x376, "V_SUB_I32_gfx9", "v_sub_nc_i32">; 817defm V_ADD_NC_I32 : 818 VOP3_Real_gfx10_with_name<0x37f, "V_ADD_I32_gfx9", "v_add_nc_i32">; 819 820defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_gfx10<0x200>; 821defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_gfx10<0x201>; 822defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_gfx10<0x202>; 823 824defm V_INTERP_P1LL_F16 : VOP3Interp_Real_gfx10<0x342>; 825defm V_INTERP_P1LV_F16 : VOP3Interp_Real_gfx10<0x343>; 826defm V_INTERP_P2_F16 : VOP3Interp_Real_gfx10<0x35a>; 827 828defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx10<0x311>; 829defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx10<0x312>; 830defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx10<0x313>; 831 832defm V_MIN3_F16 : VOP3OpSel_Real_gfx10<0x351>; 833defm V_MIN3_I16 : VOP3OpSel_Real_gfx10<0x352>; 834defm V_MIN3_U16 : VOP3OpSel_Real_gfx10<0x353>; 835defm V_MAX3_F16 : VOP3OpSel_Real_gfx10<0x354>; 836defm V_MAX3_I16 : VOP3OpSel_Real_gfx10<0x355>; 837defm V_MAX3_U16 : VOP3OpSel_Real_gfx10<0x356>; 838defm V_MED3_F16 : VOP3OpSel_Real_gfx10<0x357>; 839defm V_MED3_I16 : VOP3OpSel_Real_gfx10<0x358>; 840defm V_MED3_U16 : VOP3OpSel_Real_gfx10<0x359>; 841defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx10<0x373>; 842defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx10<0x375>; 843 844defm V_MAD_U16 : 845 VOP3OpSel_Real_gfx10_with_name<0x340, "V_MAD_U16_gfx9", "v_mad_u16">; 846defm V_FMA_F16 : 847 VOP3OpSel_Real_gfx10_with_name<0x34b, "V_FMA_F16_gfx9", "v_fma_f16">; 848defm V_MAD_I16 : 849 VOP3OpSel_Real_gfx10_with_name<0x35e, "V_MAD_I16_gfx9", "v_mad_i16">; 850defm V_DIV_FIXUP_F16 : 851 VOP3OpSel_Real_gfx10_with_name<0x35f, "V_DIV_FIXUP_F16_gfx9", "v_div_fixup_f16">; 852 853// FIXME-GFX10-OPSEL: Need to add "selective" opsel support to some of these 854// (they do not support SDWA or DPP). 855defm V_ADD_NC_U16 : VOP3_Real_gfx10_with_name<0x303, "V_ADD_U16_e64", "v_add_nc_u16">; 856defm V_SUB_NC_U16 : VOP3_Real_gfx10_with_name<0x304, "V_SUB_U16_e64", "v_sub_nc_u16">; 857defm V_MUL_LO_U16 : VOP3_Real_gfx10_with_name<0x305, "V_MUL_LO_U16_e64", "v_mul_lo_u16">; 858defm V_LSHRREV_B16 : VOP3_Real_gfx10_with_name<0x307, "V_LSHRREV_B16_e64", "v_lshrrev_b16">; 859defm V_ASHRREV_I16 : VOP3_Real_gfx10_with_name<0x308, "V_ASHRREV_I16_e64", "v_ashrrev_i16">; 860defm V_MAX_U16 : VOP3_Real_gfx10_with_name<0x309, "V_MAX_U16_e64", "v_max_u16">; 861defm V_MAX_I16 : VOP3_Real_gfx10_with_name<0x30a, "V_MAX_I16_e64", "v_max_i16">; 862defm V_MIN_U16 : VOP3_Real_gfx10_with_name<0x30b, "V_MIN_U16_e64", "v_min_u16">; 863defm V_MIN_I16 : VOP3_Real_gfx10_with_name<0x30c, "V_MIN_I16_e64", "v_min_i16">; 864defm V_LSHLREV_B16 : VOP3_Real_gfx10_with_name<0x314, "V_LSHLREV_B16_e64", "v_lshlrev_b16">; 865defm V_PERMLANE16_B32 : VOP3OpSel_Real_gfx10<0x377>; 866defm V_PERMLANEX16_B32 : VOP3OpSel_Real_gfx10<0x378>; 867 868//===----------------------------------------------------------------------===// 869// GFX7, GFX10. 870//===----------------------------------------------------------------------===// 871 872let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in { 873 multiclass VOP3_Real_gfx7<bits<10> op> { 874 def _gfx7 : 875 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>, 876 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME).Pfl>; 877 } 878 multiclass VOP3be_Real_gfx7<bits<10> op> { 879 def _gfx7 : 880 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>, 881 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME).Pfl>; 882 } 883} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" 884 885multiclass VOP3_Real_gfx7_gfx10<bits<10> op> : 886 VOP3_Real_gfx7<op>, VOP3_Real_gfx10<op>; 887 888multiclass VOP3be_Real_gfx7_gfx10<bits<10> op> : 889 VOP3be_Real_gfx7<op>, VOP3be_Real_gfx10<op>; 890 891defm V_QSAD_PK_U16_U8 : VOP3_Real_gfx7_gfx10<0x172>; 892defm V_MQSAD_U32_U8 : VOP3_Real_gfx7_gfx10<0x175>; 893defm V_MAD_U64_U32 : VOP3be_Real_gfx7_gfx10<0x176>; 894defm V_MAD_I64_I32 : VOP3be_Real_gfx7_gfx10<0x177>; 895 896//===----------------------------------------------------------------------===// 897// GFX6, GFX7, GFX10. 898//===----------------------------------------------------------------------===// 899 900let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in { 901 multiclass VOP3_Real_gfx6_gfx7<bits<10> op> { 902 def _gfx6_gfx7 : 903 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>, 904 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME).Pfl>; 905 } 906 multiclass VOP3be_Real_gfx6_gfx7<bits<10> op> { 907 def _gfx6_gfx7 : 908 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>, 909 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME).Pfl>; 910 } 911} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" 912 913multiclass VOP3_Real_gfx6_gfx7_gfx10<bits<10> op> : 914 VOP3_Real_gfx6_gfx7<op>, VOP3_Real_gfx10<op>; 915 916multiclass VOP3be_Real_gfx6_gfx7_gfx10<bits<10> op> : 917 VOP3be_Real_gfx6_gfx7<op>, VOP3be_Real_gfx10<op>; 918 919defm V_LSHL_B64 : VOP3_Real_gfx6_gfx7<0x161>; 920defm V_LSHR_B64 : VOP3_Real_gfx6_gfx7<0x162>; 921defm V_ASHR_I64 : VOP3_Real_gfx6_gfx7<0x163>; 922 923defm V_MAD_LEGACY_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x140>; 924defm V_MAD_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x141>; 925defm V_MAD_I32_I24 : VOP3_Real_gfx6_gfx7_gfx10<0x142>; 926defm V_MAD_U32_U24 : VOP3_Real_gfx6_gfx7_gfx10<0x143>; 927defm V_CUBEID_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x144>; 928defm V_CUBESC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x145>; 929defm V_CUBETC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x146>; 930defm V_CUBEMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x147>; 931defm V_BFE_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x148>; 932defm V_BFE_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x149>; 933defm V_BFI_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14a>; 934defm V_FMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x14b>; 935defm V_FMA_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x14c>; 936defm V_LERP_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x14d>; 937defm V_ALIGNBIT_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14e>; 938defm V_ALIGNBYTE_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14f>; 939defm V_MULLIT_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x150>; 940defm V_MIN3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x151>; 941defm V_MIN3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x152>; 942defm V_MIN3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x153>; 943defm V_MAX3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x154>; 944defm V_MAX3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x155>; 945defm V_MAX3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x156>; 946defm V_MED3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x157>; 947defm V_MED3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x158>; 948defm V_MED3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x159>; 949defm V_SAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15a>; 950defm V_SAD_HI_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15b>; 951defm V_SAD_U16 : VOP3_Real_gfx6_gfx7_gfx10<0x15c>; 952defm V_SAD_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x15d>; 953defm V_CVT_PK_U8_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15e>; 954defm V_DIV_FIXUP_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15f>; 955defm V_DIV_FIXUP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x160>; 956defm V_ADD_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x164>; 957defm V_MUL_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x165>; 958defm V_MIN_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x166>; 959defm V_MAX_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x167>; 960defm V_LDEXP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x168>; 961defm V_MUL_LO_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x169>; 962defm V_MUL_HI_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x16a>; 963defm V_MUL_LO_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x16b>; 964defm V_MUL_HI_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x16c>; 965defm V_DIV_FMAS_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x16f>; 966defm V_DIV_FMAS_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x170>; 967defm V_MSAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x171>; 968defm V_MQSAD_PK_U16_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x173>; 969defm V_TRIG_PREOP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x174>; 970defm V_DIV_SCALE_F32 : VOP3be_Real_gfx6_gfx7_gfx10<0x16d>; 971defm V_DIV_SCALE_F64 : VOP3be_Real_gfx6_gfx7_gfx10<0x16e>; 972 973//===----------------------------------------------------------------------===// 974// GFX8, GFX9 (VI). 975//===----------------------------------------------------------------------===// 976 977let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in { 978 979multiclass VOP3_Real_vi<bits<10> op> { 980 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 981 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>; 982} 983 984multiclass VOP3be_Real_vi<bits<10> op> { 985 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 986 VOP3be_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>; 987} 988 989multiclass VOP3OpSel_Real_gfx9<bits<10> op> { 990 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 991 VOP3OpSel_gfx9 <op, !cast<VOP_Pseudo>(NAME).Pfl>; 992} 993 994multiclass VOP3Interp_Real_vi<bits<10> op> { 995 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 996 VOP3Interp_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>; 997} 998 999} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" 1000 1001let AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" in { 1002 1003multiclass VOP3_F16_Real_vi<bits<10> op> { 1004 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>, 1005 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>; 1006} 1007 1008multiclass VOP3Interp_F16_Real_vi<bits<10> op> { 1009 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>, 1010 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>; 1011} 1012 1013} // End AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" 1014 1015let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in { 1016 1017multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> { 1018 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>, 1019 VOP3e_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> { 1020 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName); 1021 let AsmString = AsmName # ps.AsmOperands; 1022 } 1023} 1024 1025multiclass VOP3OpSel_F16_Real_gfx9<bits<10> op, string AsmName> { 1026 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX9>, 1027 VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME).Pfl> { 1028 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME); 1029 let AsmString = AsmName # ps.AsmOperands; 1030 } 1031} 1032 1033multiclass VOP3Interp_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> { 1034 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>, 1035 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> { 1036 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName); 1037 let AsmString = AsmName # ps.AsmOperands; 1038 } 1039} 1040 1041multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> { 1042 def _gfx9 : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX9>, 1043 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME).Pfl> { 1044 VOP_Pseudo ps = !cast<VOP_Pseudo>(NAME); 1045 let AsmString = AsmName # ps.AsmOperands; 1046 } 1047} 1048 1049} // End AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" 1050 1051defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>; 1052defm V_MAD_I64_I32 : VOP3be_Real_vi <0x1E9>; 1053 1054defm V_MAD_LEGACY_F32 : VOP3_Real_vi <0x1c0>; 1055defm V_MAD_F32 : VOP3_Real_vi <0x1c1>; 1056defm V_MAD_I32_I24 : VOP3_Real_vi <0x1c2>; 1057defm V_MAD_U32_U24 : VOP3_Real_vi <0x1c3>; 1058defm V_CUBEID_F32 : VOP3_Real_vi <0x1c4>; 1059defm V_CUBESC_F32 : VOP3_Real_vi <0x1c5>; 1060defm V_CUBETC_F32 : VOP3_Real_vi <0x1c6>; 1061defm V_CUBEMA_F32 : VOP3_Real_vi <0x1c7>; 1062defm V_BFE_U32 : VOP3_Real_vi <0x1c8>; 1063defm V_BFE_I32 : VOP3_Real_vi <0x1c9>; 1064defm V_BFI_B32 : VOP3_Real_vi <0x1ca>; 1065defm V_FMA_F32 : VOP3_Real_vi <0x1cb>; 1066defm V_FMA_F64 : VOP3_Real_vi <0x1cc>; 1067defm V_LERP_U8 : VOP3_Real_vi <0x1cd>; 1068defm V_ALIGNBIT_B32 : VOP3_Real_vi <0x1ce>; 1069defm V_ALIGNBYTE_B32 : VOP3_Real_vi <0x1cf>; 1070defm V_MIN3_F32 : VOP3_Real_vi <0x1d0>; 1071defm V_MIN3_I32 : VOP3_Real_vi <0x1d1>; 1072defm V_MIN3_U32 : VOP3_Real_vi <0x1d2>; 1073defm V_MAX3_F32 : VOP3_Real_vi <0x1d3>; 1074defm V_MAX3_I32 : VOP3_Real_vi <0x1d4>; 1075defm V_MAX3_U32 : VOP3_Real_vi <0x1d5>; 1076defm V_MED3_F32 : VOP3_Real_vi <0x1d6>; 1077defm V_MED3_I32 : VOP3_Real_vi <0x1d7>; 1078defm V_MED3_U32 : VOP3_Real_vi <0x1d8>; 1079defm V_SAD_U8 : VOP3_Real_vi <0x1d9>; 1080defm V_SAD_HI_U8 : VOP3_Real_vi <0x1da>; 1081defm V_SAD_U16 : VOP3_Real_vi <0x1db>; 1082defm V_SAD_U32 : VOP3_Real_vi <0x1dc>; 1083defm V_CVT_PK_U8_F32 : VOP3_Real_vi <0x1dd>; 1084defm V_DIV_FIXUP_F32 : VOP3_Real_vi <0x1de>; 1085defm V_DIV_FIXUP_F64 : VOP3_Real_vi <0x1df>; 1086defm V_DIV_SCALE_F32 : VOP3be_Real_vi <0x1e0>; 1087defm V_DIV_SCALE_F64 : VOP3be_Real_vi <0x1e1>; 1088defm V_DIV_FMAS_F32 : VOP3_Real_vi <0x1e2>; 1089defm V_DIV_FMAS_F64 : VOP3_Real_vi <0x1e3>; 1090defm V_MSAD_U8 : VOP3_Real_vi <0x1e4>; 1091defm V_QSAD_PK_U16_U8 : VOP3_Real_vi <0x1e5>; 1092defm V_MQSAD_PK_U16_U8 : VOP3_Real_vi <0x1e6>; 1093defm V_MQSAD_U32_U8 : VOP3_Real_vi <0x1e7>; 1094 1095defm V_PERM_B32 : VOP3_Real_vi <0x1ed>; 1096 1097defm V_MAD_F16 : VOP3_F16_Real_vi <0x1ea>; 1098defm V_MAD_U16 : VOP3_F16_Real_vi <0x1eb>; 1099defm V_MAD_I16 : VOP3_F16_Real_vi <0x1ec>; 1100defm V_FMA_F16 : VOP3_F16_Real_vi <0x1ee>; 1101defm V_DIV_FIXUP_F16 : VOP3_F16_Real_vi <0x1ef>; 1102defm V_INTERP_P2_F16 : VOP3Interp_F16_Real_vi <0x276>; 1103 1104let FPDPRounding = 1 in { 1105defm V_MAD_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16", "v_mad_legacy_f16">; 1106defm V_FMA_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16", "v_fma_legacy_f16">; 1107defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16">; 1108defm V_INTERP_P2_LEGACY_F16 : VOP3Interp_F16_Real_gfx9 <0x276, "V_INTERP_P2_F16", "v_interp_p2_legacy_f16">; 1109} // End FPDPRounding = 1 1110 1111defm V_MAD_LEGACY_U16 : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16", "v_mad_legacy_u16">; 1112defm V_MAD_LEGACY_I16 : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16", "v_mad_legacy_i16">; 1113 1114defm V_MAD_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">; 1115defm V_MAD_U16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">; 1116defm V_MAD_I16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">; 1117defm V_FMA_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x206, "v_fma_f16">; 1118defm V_DIV_FIXUP_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">; 1119defm V_INTERP_P2_F16_gfx9 : VOP3Interp_F16_Real_gfx9 <0x277, "V_INTERP_P2_F16_gfx9", "v_interp_p2_f16">; 1120 1121defm V_ADD_I32_gfx9 : VOP3_Real_gfx9 <0x29c, "v_add_i32">; 1122defm V_SUB_I32_gfx9 : VOP3_Real_gfx9 <0x29d, "v_sub_i32">; 1123 1124defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_vi <0x270>; 1125defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_vi <0x271>; 1126defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>; 1127 1128defm V_INTERP_P1LL_F16 : VOP3Interp_Real_vi <0x274>; 1129defm V_INTERP_P1LV_F16 : VOP3Interp_Real_vi <0x275>; 1130defm V_ADD_F64 : VOP3_Real_vi <0x280>; 1131defm V_MUL_F64 : VOP3_Real_vi <0x281>; 1132defm V_MIN_F64 : VOP3_Real_vi <0x282>; 1133defm V_MAX_F64 : VOP3_Real_vi <0x283>; 1134defm V_LDEXP_F64 : VOP3_Real_vi <0x284>; 1135defm V_MUL_LO_U32 : VOP3_Real_vi <0x285>; 1136 1137// removed from VI as identical to V_MUL_LO_U32 1138let isAsmParserOnly = 1 in { 1139defm V_MUL_LO_I32 : VOP3_Real_vi <0x285>; 1140} 1141 1142defm V_MUL_HI_U32 : VOP3_Real_vi <0x286>; 1143defm V_MUL_HI_I32 : VOP3_Real_vi <0x287>; 1144 1145defm V_READLANE_B32 : VOP3_Real_vi <0x289>; 1146defm V_WRITELANE_B32 : VOP3_Real_vi <0x28a>; 1147 1148defm V_LSHLREV_B64 : VOP3_Real_vi <0x28f>; 1149defm V_LSHRREV_B64 : VOP3_Real_vi <0x290>; 1150defm V_ASHRREV_I64 : VOP3_Real_vi <0x291>; 1151defm V_TRIG_PREOP_F64 : VOP3_Real_vi <0x292>; 1152 1153defm V_LSHL_ADD_U32 : VOP3_Real_vi <0x1fd>; 1154defm V_ADD_LSHL_U32 : VOP3_Real_vi <0x1fe>; 1155defm V_ADD3_U32 : VOP3_Real_vi <0x1ff>; 1156defm V_LSHL_OR_B32 : VOP3_Real_vi <0x200>; 1157defm V_AND_OR_B32 : VOP3_Real_vi <0x201>; 1158defm V_OR3_B32 : VOP3_Real_vi <0x202>; 1159defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx9 <0x2a0>; 1160 1161defm V_XAD_U32 : VOP3_Real_vi <0x1f3>; 1162 1163defm V_MIN3_F16 : VOP3OpSel_Real_gfx9 <0x1f4>; 1164defm V_MIN3_I16 : VOP3OpSel_Real_gfx9 <0x1f5>; 1165defm V_MIN3_U16 : VOP3OpSel_Real_gfx9 <0x1f6>; 1166 1167defm V_MAX3_F16 : VOP3OpSel_Real_gfx9 <0x1f7>; 1168defm V_MAX3_I16 : VOP3OpSel_Real_gfx9 <0x1f8>; 1169defm V_MAX3_U16 : VOP3OpSel_Real_gfx9 <0x1f9>; 1170 1171defm V_MED3_F16 : VOP3OpSel_Real_gfx9 <0x1fa>; 1172defm V_MED3_I16 : VOP3OpSel_Real_gfx9 <0x1fb>; 1173defm V_MED3_U16 : VOP3OpSel_Real_gfx9 <0x1fc>; 1174 1175defm V_ADD_I16 : VOP3OpSel_Real_gfx9 <0x29e>; 1176defm V_SUB_I16 : VOP3OpSel_Real_gfx9 <0x29f>; 1177 1178defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx9 <0x1f1>; 1179defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx9 <0x1f2>; 1180 1181defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx9 <0x299>; 1182defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx9 <0x29a>; 1183