1//===-- VOP3Instructions.td - Vector Instruction Defintions ---------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// VOP3 Classes 11//===----------------------------------------------------------------------===// 12 13class getVOP3ModPat<VOPProfile P, SDPatternOperator node> { 14 dag src0 = !if(P.HasOMod, 15 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 16 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)); 17 18 list<dag> ret3 = [(set P.DstVT:$vdst, 19 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 20 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), 21 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))]; 22 23 list<dag> ret2 = [(set P.DstVT:$vdst, 24 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 25 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))]; 26 27 list<dag> ret1 = [(set P.DstVT:$vdst, 28 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))]; 29 30 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 31 !if(!eq(P.NumSrcArgs, 2), ret2, 32 ret1)); 33} 34 35class getVOP3PModPat<VOPProfile P, SDPatternOperator node, bit HasExplicitClamp> { 36 dag src0_dag = (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers)); 37 dag src1_dag = (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers)); 38 dag src2_dag = (P.Src2VT (VOP3PMods P.Src2VT:$src2, i32:$src2_modifiers)); 39 dag clamp_dag = (i1 timm:$clamp); 40 41 list<dag> ret3 = [(set P.DstVT:$vdst, 42 !if(HasExplicitClamp, 43 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, src2_dag, clamp_dag), 44 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, src2_dag)))]; 45 46 list<dag> ret2 = [(set P.DstVT:$vdst, 47 !if(HasExplicitClamp, 48 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, clamp_dag), 49 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag)))]; 50 51 list<dag> ret1 = [(set P.DstVT:$vdst, 52 !if(HasExplicitClamp, 53 (DivergentFragOrOp<node, P>.ret src0_dag, clamp_dag), 54 (DivergentFragOrOp<node, P>.ret src0_dag)))]; 55 56 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 57 !if(!eq(P.NumSrcArgs, 2), ret2, 58 ret1)); 59} 60 61class getVOP3OpSelPat<VOPProfile P, SDPatternOperator node> { 62 list<dag> ret3 = [(set P.DstVT:$vdst, 63 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)), 64 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)), 65 (P.Src2VT (VOP3OpSel P.Src2VT:$src2, i32:$src2_modifiers))))]; 66 67 list<dag> ret2 = [(set P.DstVT:$vdst, 68 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)), 69 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))]; 70 71 list<dag> ret1 = [(set P.DstVT:$vdst, 72 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))))]; 73 74 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 75 !if(!eq(P.NumSrcArgs, 2), ret2, 76 ret1)); 77} 78 79class getVOP3OpSelModPat<VOPProfile P, SDPatternOperator node> { 80 list<dag> ret3 = [(set P.DstVT:$vdst, 81 (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers), 82 (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 83 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)), 84 (P.Src2VT (VOP3OpSelMods P.Src2VT:$src2, i32:$src2_modifiers))))]; 85 86 list<dag> ret2 = [(set P.DstVT:$vdst, 87 (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers)), 88 (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 89 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))]; 90 91 list<dag> ret1 = [(set P.DstVT:$vdst, 92 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))))]; 93 94 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 95 !if(!eq(P.NumSrcArgs, 2), ret2, 96 ret1)); 97} 98 99class getVOP3Pat<VOPProfile P, SDPatternOperator node> { 100 list<dag> ret3 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))]; 101 list<dag> ret2 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$src1))]; 102 list<dag> ret1 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0))]; 103 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 104 !if(!eq(P.NumSrcArgs, 2), ret2, 105 ret1)); 106} 107 108class getVOP3ClampPat<VOPProfile P, SDPatternOperator node> { 109 list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i1:$clamp))]; 110 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))]; 111 list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, i1:$clamp))]; 112 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 113 !if(!eq(P.NumSrcArgs, 2), ret2, 114 ret1)); 115} 116 117class getVOP3MAIPat<VOPProfile P, SDPatternOperator node> { 118 list<dag> ret = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, 119 timm:$cbsz, timm:$abid, timm:$blgp))]; 120} 121 122class VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit VOP3Only = 0> : 123 VOP3_Pseudo<OpName, P, 124 !if(P.HasOpSel, 125 !if(P.HasModifiers, 126 getVOP3OpSelModPat<P, node>.ret, 127 getVOP3OpSelPat<P, node>.ret), 128 !if(P.HasModifiers, 129 getVOP3ModPat<P, node>.ret, 130 !if(P.HasIntClamp, 131 getVOP3ClampPat<P, node>.ret, 132 !if (P.IsMAI, 133 getVOP3MAIPat<P, node>.ret, 134 getVOP3Pat<P, node>.ret)))), 135 VOP3Only, 0, P.HasOpSel> { 136 137 let IntClamp = P.HasIntClamp; 138 let AsmMatchConverter = 139 !if(P.HasOpSel, 140 "cvtVOP3OpSel", 141 !if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)), 142 "cvtVOP3", 143 "")); 144} 145 146// Special case for v_div_fmas_{f32|f64}, since it seems to be the 147// only VOP instruction that implicitly reads VCC. 148let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in { 149def VOP_F32_F32_F32_F32_VCC : VOPProfile<[f32, f32, f32, f32]> { 150 let Outs64 = (outs DstRC.RegClass:$vdst); 151} 152def VOP_F64_F64_F64_F64_VCC : VOPProfile<[f64, f64, f64, f64]> { 153 let Outs64 = (outs DstRC.RegClass:$vdst); 154} 155} 156 157class VOP3Features<bit Clamp, bit OpSel, bit Packed, bit MAI> { 158 bit HasClamp = Clamp; 159 bit HasOpSel = OpSel; 160 bit IsPacked = Packed; 161 bit IsMAI = MAI; 162} 163 164def VOP3_REGULAR : VOP3Features<0, 0, 0, 0>; 165def VOP3_CLAMP : VOP3Features<1, 0, 0, 0>; 166def VOP3_OPSEL : VOP3Features<1, 1, 0, 0>; 167def VOP3_PACKED : VOP3Features<1, 1, 1, 0>; 168def VOP3_MAI : VOP3Features<0, 0, 0, 1>; 169 170class VOP3_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOPProfile<P.ArgVT> { 171 172 let HasClamp = !if(Features.HasClamp, 1, P.HasClamp); 173 let HasOpSel = !if(Features.HasOpSel, 1, P.HasOpSel); 174 let IsMAI = !if(Features.IsMAI, 1, P.IsMAI); 175 let IsPacked = !if(Features.IsPacked, 1, P.IsPacked); 176 177 let HasModifiers = !if(Features.IsPacked, !if(Features.IsMAI, 0, 1), P.HasModifiers); 178 179 // FIXME: Hack to stop printing _e64 180 let Outs64 = (outs DstRC.RegClass:$vdst); 181 let Asm64 = 182 " " # !if(Features.HasOpSel, 183 getAsmVOP3OpSel<NumSrcArgs, 184 HasIntClamp, 185 HasSrc0FloatMods, 186 HasSrc1FloatMods, 187 HasSrc2FloatMods>.ret, 188 !if(Features.HasClamp, 189 getAsm64<HasDst, NumSrcArgs, HasIntClamp, 190 HasModifiers, HasOMod, DstVT>.ret, 191 P.Asm64)); 192 let NeedPatGen = P.NeedPatGen; 193} 194 195class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> { 196 // v_div_scale_{f32|f64} do not support input modifiers. 197 let HasModifiers = 0; 198 let HasClamp = 0; 199 let HasOMod = 0; 200 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 201 let Asm64 = " $vdst, $sdst, $src0, $src1, $src2"; 202} 203 204def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32> { 205 // FIXME: Hack to stop printing _e64 206 let DstRC = RegisterOperand<VGPR_32>; 207} 208 209def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> { 210 // FIXME: Hack to stop printing _e64 211 let DstRC = RegisterOperand<VReg_64>; 212} 213 214def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> { 215 let HasClamp = 1; 216 217 // FIXME: Hack to stop printing _e64 218 let DstRC = RegisterOperand<VReg_64>; 219 220 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 221 let Asm64 = " $vdst, $sdst, $src0, $src1, $src2$clamp"; 222} 223 224//===----------------------------------------------------------------------===// 225// VOP3 INTERP 226//===----------------------------------------------------------------------===// 227 228class VOP3Interp<string OpName, VOPProfile P, list<dag> pattern = []> : 229 VOP3_Pseudo<OpName, P, pattern> { 230 let AsmMatchConverter = "cvtVOP3Interp"; 231} 232 233def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> { 234 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 235 Attr:$attr, AttrChan:$attrchan, 236 clampmod0:$clamp, omod0:$omod); 237 238 let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod"; 239} 240 241def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> { 242 let Ins64 = (ins InterpSlot:$src0, 243 Attr:$attr, AttrChan:$attrchan, 244 clampmod0:$clamp, omod0:$omod); 245 246 let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod"; 247 248 let HasClamp = 1; 249} 250 251class getInterp16Asm <bit HasSrc2, bit HasOMod> { 252 string src2 = !if(HasSrc2, ", $src2_modifiers", ""); 253 string omod = !if(HasOMod, "$omod", ""); 254 string ret = 255 " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod; 256} 257 258class getInterp16Ins <bit HasSrc2, bit HasOMod, 259 Operand Src0Mod, Operand Src2Mod> { 260 dag ret = !if(HasSrc2, 261 !if(HasOMod, 262 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 263 Attr:$attr, AttrChan:$attrchan, 264 Src2Mod:$src2_modifiers, VRegSrc_32:$src2, 265 highmod:$high, clampmod0:$clamp, omod0:$omod), 266 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 267 Attr:$attr, AttrChan:$attrchan, 268 Src2Mod:$src2_modifiers, VRegSrc_32:$src2, 269 highmod:$high, clampmod0:$clamp) 270 ), 271 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 272 Attr:$attr, AttrChan:$attrchan, 273 highmod:$high, clampmod0:$clamp, omod0:$omod) 274 ); 275} 276 277class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> { 278 279 let HasOMod = !if(!eq(DstVT.Value, f16.Value), 0, 1); 280 let HasHigh = 1; 281 282 let Outs64 = (outs VGPR_32:$vdst); 283 let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret; 284 let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret; 285} 286 287//===----------------------------------------------------------------------===// 288// VOP3 Instructions 289//===----------------------------------------------------------------------===// 290 291let isCommutable = 1 in { 292 293def V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 294def V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fmad>; 295def V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 296def V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 297def V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fma>; 298def V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>; 299 300let SchedRW = [WriteDoubleAdd] in { 301let FPDPRounding = 1 in { 302def V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, fma>; 303def V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, fadd, 1>; 304def V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, fmul, 1>; 305} // End FPDPRounding = 1 306def V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum_like, 1>; 307def V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum_like, 1>; 308} // End SchedRW = [WriteDoubleAdd] 309 310let SchedRW = [WriteQuarterRate32] in { 311def V_MUL_LO_U32 : VOP3Inst <"v_mul_lo_u32", VOP3_Profile<VOP_I32_I32_I32>, mul>; 312def V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", VOP3_Profile<VOP_I32_I32_I32>, mulhu>; 313def V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", VOP3_Profile<VOP_I32_I32_I32>>; 314def V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", VOP3_Profile<VOP_I32_I32_I32>, mulhs>; 315} // End SchedRW = [WriteQuarterRate32] 316 317let Uses = [VCC, EXEC] in { 318// v_div_fmas_f32: 319// result = src0 * src1 + src2 320// if (vcc) 321// result *= 2^32 322// 323def V_DIV_FMAS_F32 : VOP3_Pseudo <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC, []> { 324 let SchedRW = [WriteFloatFMA]; 325} 326// v_div_fmas_f64: 327// result = src0 * src1 + src2 328// if (vcc) 329// result *= 2^64 330// 331def V_DIV_FMAS_F64 : VOP3_Pseudo <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC, []> { 332 let SchedRW = [WriteDouble]; 333 let FPDPRounding = 1; 334} 335} // End Uses = [VCC, EXEC] 336 337} // End isCommutable = 1 338 339def V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubeid>; 340def V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubesc>; 341def V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubetc>; 342def V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubema>; 343def V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>; 344def V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>; 345def V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>; 346def V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, fshr>; 347def V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>; 348def V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmin3>; 349def V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>; 350def V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>; 351def V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>; 352def V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>; 353def V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>; 354def V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>; 355def V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>; 356def V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>; 357def V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 358def V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 359def V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 360def V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 361def V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>; 362def V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUdiv_fixup>; 363 364let SchedRW = [WriteDoubleAdd], FPDPRounding = 1 in { 365def V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>; 366def V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp, 1>; 367} // End SchedRW = [WriteDoubleAdd], FPDPRounding = 1 368 369def V_DIV_SCALE_F32 : VOP3_Pseudo <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> { 370 let SchedRW = [WriteFloatFMA, WriteSALU]; 371 let AsmMatchConverter = ""; 372} 373 374// Double precision division pre-scale. 375def V_DIV_SCALE_F64 : VOP3_Pseudo <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1> { 376 let SchedRW = [WriteDouble, WriteSALU]; 377 let AsmMatchConverter = ""; 378 let FPDPRounding = 1; 379} 380 381def V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 382 383let Constraints = "@earlyclobber $vdst" in { 384def V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>; 385} // End Constraints = "@earlyclobber $vdst" 386 387def V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUtrig_preop> { 388 let SchedRW = [WriteDouble]; 389} 390 391let SchedRW = [Write64Bit] in { 392let SubtargetPredicate = isGFX6GFX7 in { 393def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>, shl>; 394def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>, srl>; 395def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>, sra>; 396} // End SubtargetPredicate = isGFX6GFX7 397 398let SubtargetPredicate = isGFX8Plus in { 399def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshl_rev>; 400def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshr_rev>; 401def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, ashr_rev>; 402} // End SubtargetPredicate = isGFX8Plus 403} // End SchedRW = [Write64Bit] 404 405def : GCNPat< 406 (i64 (getDivergentFrag<sext>.ret i16:$src)), 407 (REG_SEQUENCE VReg_64, 408 (i32 (V_BFE_I32 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))), sub0, 409 (i32 (COPY_TO_REGCLASS 410 (V_ASHRREV_I32_e32 (S_MOV_B32 (i32 0x1f)), (i32 (V_BFE_I32 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))) 411 ), VGPR_32)), sub1) 412>; 413 414def : GCNPat< 415 (i32 (getDivergentFrag<sext>.ret i16:$src)), 416 (i32 (V_BFE_I32 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))) 417>; 418 419let SubtargetPredicate = isGFX6GFX7GFX10 in { 420def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 421} // End SubtargetPredicate = isGFX6GFX7GFX10 422 423let SchedRW = [Write32Bit] in { 424let SubtargetPredicate = isGFX8Plus in { 425def V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUperm>; 426} // End SubtargetPredicate = isGFX8Plus 427} // End SchedRW = [Write32Bit] 428 429let SubtargetPredicate = isGFX7Plus in { 430 431let Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] in { 432def V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>; 433def V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_V4I32, VOP3_CLAMP>>; 434} // End Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] 435 436let isCommutable = 1 in { 437let SchedRW = [WriteQuarterRate32, WriteSALU] in { 438def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>; 439def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>; 440} // End SchedRW = [WriteQuarterRate32, WriteSALU] 441} // End isCommutable = 1 442 443} // End SubtargetPredicate = isGFX7Plus 444 445 446def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup> { 447 let Predicates = [Has16BitInsts, isGFX8Only]; 448 let FPDPRounding = 1; 449} 450def V_DIV_FIXUP_F16_gfx9 : VOP3Inst <"v_div_fixup_f16_gfx9", 451 VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUdiv_fixup> { 452 let renamedInGFX9 = 1; 453 let Predicates = [Has16BitInsts, isGFX9Plus]; 454 let FPDPRounding = 1; 455} 456 457def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma> { 458 let Predicates = [Has16BitInsts, isGFX8Only]; 459 let FPDPRounding = 1; 460} 461def V_FMA_F16_gfx9 : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, fma> { 462 let renamedInGFX9 = 1; 463 let Predicates = [Has16BitInsts, isGFX9Plus]; 464 let FPDPRounding = 1; 465} 466 467let SubtargetPredicate = Has16BitInsts, isCommutable = 1 in { 468 469let renamedInGFX9 = 1 in { 470def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>; 471def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>; 472let FPDPRounding = 1 in { 473def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>; 474let Uses = [M0, EXEC] in { 475// For some reason the intrinsic operands are in a different order 476// from the instruction operands. 477def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>, 478 [(set f16:$vdst, 479 (int_amdgcn_interp_p2_f16 (VOP3Mods f32:$src2, i32:$src2_modifiers), 480 (VOP3Mods f32:$src0, i32:$src0_modifiers), 481 (i32 timm:$attrchan), 482 (i32 timm:$attr), 483 (i1 timm:$high), 484 M0))]>; 485} // End Uses = [M0, EXEC] 486} // End FPDPRounding = 1 487} // End renamedInGFX9 = 1 488 489let SubtargetPredicate = isGFX9Only in { 490def V_MAD_F16_gfx9 : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>> { 491 let FPDPRounding = 1; 492} 493} // End SubtargetPredicate = isGFX9Only 494 495let SubtargetPredicate = isGFX9Plus in { 496def V_MAD_U16_gfx9 : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>; 497def V_MAD_I16_gfx9 : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>; 498def V_INTERP_P2_F16_gfx9 : VOP3Interp <"v_interp_p2_f16_gfx9", VOP3_INTERP16<[f16, f32, i32, f32]>>; 499} // End SubtargetPredicate = isGFX9Plus 500 501let Uses = [M0, EXEC], FPDPRounding = 1 in { 502def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>, 503 [(set f32:$vdst, (int_amdgcn_interp_p1_f16 (VOP3Mods f32:$src0, i32:$src0_modifiers), 504 (i32 timm:$attrchan), 505 (i32 timm:$attr), 506 (i1 timm:$high), M0))]> { 507 // This predicate should only apply to the selection pattern. The 508 // instruction still exists and should decode on subtargets with 509 // other bank counts. 510 let OtherPredicates = [has32BankLDS]; 511} 512 513 514def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>; 515} // End Uses = [M0, EXEC], FPDPRounding = 1 516 517} // End SubtargetPredicate = Has16BitInsts, isCommutable = 1 518 519let SubtargetPredicate = isGFX8Plus, Uses = [M0, EXEC] in { 520def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>; 521def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>; 522def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>; 523} // End SubtargetPredicate = isGFX8Plus, Uses = [M0, EXEC] 524 525let Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] in { 526 527multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2, 528 Instruction inst, SDPatternOperator op3> { 529def : GCNPat < 530 (op2 (op1 i16:$src0, i16:$src1), i16:$src2), 531 (inst i16:$src0, i16:$src1, i16:$src2, (i1 0)) 532>; 533 534} 535 536defm: Ternary_i16_Pats<mul, add, V_MAD_U16, zext>; 537defm: Ternary_i16_Pats<mul, add, V_MAD_I16, sext>; 538 539} // End Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] 540 541let Predicates = [Has16BitInsts, isGFX10Plus] in { 542 543multiclass Ternary_i16_Pats_gfx9<SDPatternOperator op1, SDPatternOperator op2, 544 Instruction inst, SDPatternOperator op3> { 545def : GCNPat < 546 (op2 (op1 i16:$src0, i16:$src1), i16:$src2), 547 (inst SRCMODS.NONE, $src0, SRCMODS.NONE, $src1, SRCMODS.NONE, $src2, DSTCLAMP.NONE) 548>; 549 550} 551 552defm: Ternary_i16_Pats_gfx9<mul, add, V_MAD_U16_gfx9, zext>; 553defm: Ternary_i16_Pats_gfx9<mul, add, V_MAD_I16_gfx9, sext>; 554 555} // End Predicates = [Has16BitInsts, isGFX10Plus] 556 557class ThreeOpFrag<SDPatternOperator op1, SDPatternOperator op2> : PatFrag< 558 (ops node:$x, node:$y, node:$z), 559 // When the inner operation is used multiple times, selecting 3-op 560 // instructions may still be beneficial -- if the other users can be 561 // combined similarly. Let's be conservative for now. 562 (op2 (HasOneUseBinOp<op1> node:$x, node:$y), node:$z), 563 [{ 564 // Only use VALU ops when the result is divergent. 565 if (!N->isDivergent()) 566 return false; 567 568 // Check constant bus limitations. 569 // 570 // Note: Use !isDivergent as a conservative proxy for whether the value 571 // is in an SGPR (uniform values can end up in VGPRs as well). 572 unsigned ConstantBusUses = 0; 573 for (unsigned i = 0; i < 3; ++i) { 574 if (!Operands[i]->isDivergent() && 575 !isInlineImmediate(Operands[i].getNode())) { 576 ConstantBusUses++; 577 // This uses AMDGPU::V_ADD3_U32, but all three operand instructions 578 // have the same constant bus limit. 579 if (ConstantBusUses > Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32)) 580 return false; 581 } 582 } 583 584 return true; 585 }]> { 586 let PredicateCodeUsesOperands = 1; 587 588 // The divergence predicate is irrelevant in GlobalISel, as we have 589 // proper register bank checks. We also force all VOP instruction 590 // operands to VGPR, so we should not need to check the constant bus 591 // restriction. 592 // 593 // FIXME: With unlucky SGPR operands, we could penalize code by 594 // blocking folding SGPR->VGPR copies later. 595 // FIXME: There's no register bank verifier 596 // FIXME: Should add a way for the emitter to recognize this is a 597 // trivially true predicate to eliminate the check. 598 let GISelPredicateCode = [{return true;}]; 599} 600 601let SubtargetPredicate = isGFX9Plus in { 602def V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 603def V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 604def V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 605def V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 606def V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 607def V_AND_OR_B32 : VOP3Inst <"v_and_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 608def V_OR3_B32 : VOP3Inst <"v_or3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 609 610def V_XAD_U32 : VOP3Inst <"v_xad_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 611 612def V_MED3_F16 : VOP3Inst <"v_med3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmed3>; 613def V_MED3_I16 : VOP3Inst <"v_med3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmed3>; 614def V_MED3_U16 : VOP3Inst <"v_med3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumed3>; 615 616def V_MIN3_F16 : VOP3Inst <"v_min3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmin3>; 617def V_MIN3_I16 : VOP3Inst <"v_min3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmin3>; 618def V_MIN3_U16 : VOP3Inst <"v_min3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumin3>; 619 620def V_MAX3_F16 : VOP3Inst <"v_max3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmax3>; 621def V_MAX3_I16 : VOP3Inst <"v_max3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmax3>; 622def V_MAX3_U16 : VOP3Inst <"v_max3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumax3>; 623 624def V_ADD_I16 : VOP3Inst <"v_add_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>; 625def V_SUB_I16 : VOP3Inst <"v_sub_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>; 626 627def V_MAD_U32_U16 : VOP3Inst <"v_mad_u32_u16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>; 628def V_MAD_I32_I16 : VOP3Inst <"v_mad_i32_i16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>; 629 630def V_CVT_PKNORM_I16_F16 : VOP3Inst <"v_cvt_pknorm_i16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 631def V_CVT_PKNORM_U16_F16 : VOP3Inst <"v_cvt_pknorm_u16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 632 633def V_ADD_I32_gfx9 : VOP3Inst <"v_add_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>; 634def V_SUB_I32_gfx9 : VOP3Inst <"v_sub_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>; 635 636 637class ThreeOp_i32_Pats <SDPatternOperator op1, SDPatternOperator op2, Instruction inst> : GCNPat < 638 // This matches (op2 (op1 i32:$src0, i32:$src1), i32:$src2) with conditions. 639 (ThreeOpFrag<op1, op2> i32:$src0, i32:$src1, i32:$src2), 640 (inst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2) 641>; 642 643def : ThreeOp_i32_Pats<shl, add, V_LSHL_ADD_U32>; 644def : ThreeOp_i32_Pats<add, shl, V_ADD_LSHL_U32>; 645def : ThreeOp_i32_Pats<add, add, V_ADD3_U32>; 646def : ThreeOp_i32_Pats<shl, or, V_LSHL_OR_B32>; 647def : ThreeOp_i32_Pats<and, or, V_AND_OR_B32>; 648def : ThreeOp_i32_Pats<or, or, V_OR3_B32>; 649def : ThreeOp_i32_Pats<xor, add, V_XAD_U32>; 650 651} // End SubtargetPredicate = isGFX9Plus 652 653def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3_OPSEL> { 654 let Src0RC64 = VRegSrc_32; 655 let Src1RC64 = SCSrc_b32; 656 let Src2RC64 = SCSrc_b32; 657 let InsVOP3OpSel = (ins IntOpSelMods:$src0_modifiers, VRegSrc_32:$src0, 658 IntOpSelMods:$src1_modifiers, SCSrc_b32:$src1, 659 IntOpSelMods:$src2_modifiers, SCSrc_b32:$src2, 660 VGPR_32:$vdst_in, op_sel:$op_sel); 661 let HasClamp = 0; 662 let HasOMod = 0; 663} 664 665class PermlanePat<SDPatternOperator permlane, 666 Instruction inst> : GCNPat< 667 (permlane i32:$vdst_in, i32:$src0, i32:$src1, i32:$src2, 668 timm:$fi, timm:$bc), 669 (inst (as_i1timm $fi), VGPR_32:$src0, (as_i1timm $bc), 670 SCSrc_b32:$src1, 0, SCSrc_b32:$src2, VGPR_32:$vdst_in) 671>; 672 673// Permlane intrinsic that has either fetch invalid or bound control 674// fields enabled. 675class BoundControlOrFetchInvalidPermlane<SDPatternOperator permlane> : 676 PatFrag<(ops node:$vdst_in, node:$src0, node:$src1, node:$src2, 677 node:$fi, node:$bc), 678 (permlane node:$vdst_in, node:$src0, node: 679 $src1, node:$src2, node:$fi, node:$bc)> { 680 let PredicateCode = [{ return N->getConstantOperandVal(5) != 0 || 681 N->getConstantOperandVal(6) != 0; }]; 682 let GISelPredicateCode = [{ 683 return MI.getOperand(6).getImm() != 0 || 684 MI.getOperand(7).getImm() != 0; 685 }]; 686} 687 688// Drop the input value if it won't be read. 689class PermlaneDiscardVDstIn<SDPatternOperator permlane, 690 Instruction inst> : GCNPat< 691 (permlane srcvalue, i32:$src0, i32:$src1, i32:$src2, 692 timm:$fi, timm:$bc), 693 (inst (as_i1timm $fi), VGPR_32:$src0, (as_i1timm $bc), 694 SCSrc_b32:$src1, 0, SCSrc_b32:$src2, 695 (IMPLICIT_DEF)) 696>; 697 698 699let SubtargetPredicate = isGFX10Plus in { 700 def V_XOR3_B32 : VOP3Inst <"v_xor3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 701 def : ThreeOp_i32_Pats<xor, xor, V_XOR3_B32>; 702 703 let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in { 704 def V_PERMLANE16_B32 : VOP3Inst <"v_permlane16_b32", VOP3_PERMLANE_Profile>; 705 def V_PERMLANEX16_B32 : VOP3Inst <"v_permlanex16_b32", VOP3_PERMLANE_Profile>; 706 } // End $vdst = $vdst_in, DisableEncoding $vdst_in 707 708 def : PermlanePat<int_amdgcn_permlane16, V_PERMLANE16_B32>; 709 def : PermlanePat<int_amdgcn_permlanex16, V_PERMLANEX16_B32>; 710 711 def : PermlaneDiscardVDstIn< 712 BoundControlOrFetchInvalidPermlane<int_amdgcn_permlane16>, 713 V_PERMLANE16_B32>; 714 def : PermlaneDiscardVDstIn< 715 BoundControlOrFetchInvalidPermlane<int_amdgcn_permlanex16>, 716 V_PERMLANEX16_B32>; 717} // End SubtargetPredicate = isGFX10Plus 718 719class DivFmasPat<ValueType vt, Instruction inst, Register CondReg> : GCNPat< 720 (AMDGPUdiv_fmas (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)), 721 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), 722 (vt (VOP3Mods vt:$src2, i32:$src2_modifiers)), 723 (i1 CondReg)), 724 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, $src2_modifiers, $src2) 725>; 726 727let WaveSizePredicate = isWave64 in { 728def : DivFmasPat<f32, V_DIV_FMAS_F32, VCC>; 729def : DivFmasPat<f64, V_DIV_FMAS_F64, VCC>; 730} 731 732let WaveSizePredicate = isWave32 in { 733def : DivFmasPat<f32, V_DIV_FMAS_F32, VCC_LO>; 734def : DivFmasPat<f64, V_DIV_FMAS_F64, VCC_LO>; 735} 736 737//===----------------------------------------------------------------------===// 738// Integer Clamp Patterns 739//===----------------------------------------------------------------------===// 740 741class getClampPat<VOPProfile P, SDPatternOperator node> { 742 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2)); 743 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1)); 744 dag ret1 = (P.DstVT (node P.Src0VT:$src0)); 745 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3, 746 !if(!eq(P.NumSrcArgs, 2), ret2, 747 ret1)); 748} 749 750class getClampRes<VOPProfile P, Instruction inst> { 751 dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0)); 752 dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0)); 753 dag ret1 = (inst P.Src0VT:$src0, (i1 0)); 754 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3, 755 !if(!eq(P.NumSrcArgs, 2), ret2, 756 ret1)); 757} 758 759class IntClampPat<VOP3Inst inst, SDPatternOperator node> : GCNPat< 760 getClampPat<inst.Pfl, node>.ret, 761 getClampRes<inst.Pfl, inst>.ret 762>; 763 764def : IntClampPat<V_MAD_I32_I24, AMDGPUmad_i24>; 765def : IntClampPat<V_MAD_U32_U24, AMDGPUmad_u24>; 766 767def : IntClampPat<V_SAD_U8, int_amdgcn_sad_u8>; 768def : IntClampPat<V_SAD_HI_U8, int_amdgcn_sad_hi_u8>; 769def : IntClampPat<V_SAD_U16, int_amdgcn_sad_u16>; 770 771def : IntClampPat<V_MSAD_U8, int_amdgcn_msad_u8>; 772def : IntClampPat<V_MQSAD_PK_U16_U8, int_amdgcn_mqsad_pk_u16_u8>; 773 774def : IntClampPat<V_QSAD_PK_U16_U8, int_amdgcn_qsad_pk_u16_u8>; 775def : IntClampPat<V_MQSAD_U32_U8, int_amdgcn_mqsad_u32_u8>; 776 777 778//===----------------------------------------------------------------------===// 779// Target-specific instruction encodings. 780//===----------------------------------------------------------------------===// 781 782//===----------------------------------------------------------------------===// 783// GFX10. 784//===----------------------------------------------------------------------===// 785 786let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in { 787 multiclass VOP3_Real_gfx10<bits<10> op> { 788 def _gfx10 : 789 VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX10>, 790 VOP3e_gfx10<op, !cast<VOP_Pseudo>(NAME).Pfl>; 791 } 792 multiclass VOP3_Real_gfx10_with_name<bits<10> op, string opName, 793 string asmName> { 794 def _gfx10 : 795 VOP3_Real<!cast<VOP3_Pseudo>(opName), SIEncodingFamily.GFX10>, 796 VOP3e_gfx10<op, !cast<VOP3_Pseudo>(opName).Pfl> { 797 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName); 798 let AsmString = asmName # ps.AsmOperands; 799 } 800 } 801 multiclass VOP3be_Real_gfx10<bits<10> op> { 802 def _gfx10 : 803 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>, 804 VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME).Pfl>; 805 } 806 multiclass VOP3Interp_Real_gfx10<bits<10> op> { 807 def _gfx10 : 808 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>, 809 VOP3Interp_gfx10<op, !cast<VOP3_Pseudo>(NAME).Pfl>; 810 } 811 multiclass VOP3OpSel_Real_gfx10<bits<10> op> { 812 def _gfx10 : 813 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>, 814 VOP3OpSel_gfx10<op, !cast<VOP3_Pseudo>(NAME).Pfl>; 815 } 816 multiclass VOP3OpSel_Real_gfx10_with_name<bits<10> op, string opName, 817 string asmName> { 818 def _gfx10 : 819 VOP3_Real<!cast<VOP3_Pseudo>(opName), SIEncodingFamily.GFX10>, 820 VOP3OpSel_gfx10<op, !cast<VOP3_Pseudo>(opName).Pfl> { 821 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName); 822 let AsmString = asmName # ps.AsmOperands; 823 } 824 } 825} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" 826 827defm V_READLANE_B32 : VOP3_Real_gfx10<0x360>; 828 829let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in) in { 830 defm V_WRITELANE_B32 : VOP3_Real_gfx10<0x361>; 831} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in) 832 833defm V_XOR3_B32 : VOP3_Real_gfx10<0x178>; 834defm V_LSHLREV_B64 : VOP3_Real_gfx10<0x2ff>; 835defm V_LSHRREV_B64 : VOP3_Real_gfx10<0x300>; 836defm V_ASHRREV_I64 : VOP3_Real_gfx10<0x301>; 837defm V_PERM_B32 : VOP3_Real_gfx10<0x344>; 838defm V_XAD_U32 : VOP3_Real_gfx10<0x345>; 839defm V_LSHL_ADD_U32 : VOP3_Real_gfx10<0x346>; 840defm V_ADD_LSHL_U32 : VOP3_Real_gfx10<0x347>; 841defm V_ADD3_U32 : VOP3_Real_gfx10<0x36d>; 842defm V_LSHL_OR_B32 : VOP3_Real_gfx10<0x36f>; 843defm V_AND_OR_B32 : VOP3_Real_gfx10<0x371>; 844defm V_OR3_B32 : VOP3_Real_gfx10<0x372>; 845 846// TODO-GFX10: add MC tests for v_add/sub_nc_i16 847defm V_ADD_NC_I16 : 848 VOP3OpSel_Real_gfx10_with_name<0x30d, "V_ADD_I16", "v_add_nc_i16">; 849defm V_SUB_NC_I16 : 850 VOP3OpSel_Real_gfx10_with_name<0x30e, "V_SUB_I16", "v_sub_nc_i16">; 851defm V_SUB_NC_I32 : 852 VOP3_Real_gfx10_with_name<0x376, "V_SUB_I32_gfx9", "v_sub_nc_i32">; 853defm V_ADD_NC_I32 : 854 VOP3_Real_gfx10_with_name<0x37f, "V_ADD_I32_gfx9", "v_add_nc_i32">; 855 856defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_gfx10<0x200>; 857defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_gfx10<0x201>; 858defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_gfx10<0x202>; 859 860defm V_INTERP_P1LL_F16 : VOP3Interp_Real_gfx10<0x342>; 861defm V_INTERP_P1LV_F16 : VOP3Interp_Real_gfx10<0x343>; 862defm V_INTERP_P2_F16 : VOP3Interp_Real_gfx10<0x35a>; 863 864defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx10<0x311>; 865defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx10<0x312>; 866defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx10<0x313>; 867 868defm V_MIN3_F16 : VOP3OpSel_Real_gfx10<0x351>; 869defm V_MIN3_I16 : VOP3OpSel_Real_gfx10<0x352>; 870defm V_MIN3_U16 : VOP3OpSel_Real_gfx10<0x353>; 871defm V_MAX3_F16 : VOP3OpSel_Real_gfx10<0x354>; 872defm V_MAX3_I16 : VOP3OpSel_Real_gfx10<0x355>; 873defm V_MAX3_U16 : VOP3OpSel_Real_gfx10<0x356>; 874defm V_MED3_F16 : VOP3OpSel_Real_gfx10<0x357>; 875defm V_MED3_I16 : VOP3OpSel_Real_gfx10<0x358>; 876defm V_MED3_U16 : VOP3OpSel_Real_gfx10<0x359>; 877defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx10<0x373>; 878defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx10<0x375>; 879 880defm V_MAD_U16 : 881 VOP3OpSel_Real_gfx10_with_name<0x340, "V_MAD_U16_gfx9", "v_mad_u16">; 882defm V_FMA_F16 : 883 VOP3OpSel_Real_gfx10_with_name<0x34b, "V_FMA_F16_gfx9", "v_fma_f16">; 884defm V_MAD_I16 : 885 VOP3OpSel_Real_gfx10_with_name<0x35e, "V_MAD_I16_gfx9", "v_mad_i16">; 886defm V_DIV_FIXUP_F16 : 887 VOP3OpSel_Real_gfx10_with_name<0x35f, "V_DIV_FIXUP_F16_gfx9", "v_div_fixup_f16">; 888 889// FIXME-GFX10-OPSEL: Need to add "selective" opsel support to some of these 890// (they do not support SDWA or DPP). 891defm V_ADD_NC_U16 : VOP3_Real_gfx10_with_name<0x303, "V_ADD_U16_e64", "v_add_nc_u16">; 892defm V_SUB_NC_U16 : VOP3_Real_gfx10_with_name<0x304, "V_SUB_U16_e64", "v_sub_nc_u16">; 893defm V_MUL_LO_U16 : VOP3_Real_gfx10_with_name<0x305, "V_MUL_LO_U16_e64", "v_mul_lo_u16">; 894defm V_LSHRREV_B16 : VOP3_Real_gfx10_with_name<0x307, "V_LSHRREV_B16_e64", "v_lshrrev_b16">; 895defm V_ASHRREV_I16 : VOP3_Real_gfx10_with_name<0x308, "V_ASHRREV_I16_e64", "v_ashrrev_i16">; 896defm V_MAX_U16 : VOP3_Real_gfx10_with_name<0x309, "V_MAX_U16_e64", "v_max_u16">; 897defm V_MAX_I16 : VOP3_Real_gfx10_with_name<0x30a, "V_MAX_I16_e64", "v_max_i16">; 898defm V_MIN_U16 : VOP3_Real_gfx10_with_name<0x30b, "V_MIN_U16_e64", "v_min_u16">; 899defm V_MIN_I16 : VOP3_Real_gfx10_with_name<0x30c, "V_MIN_I16_e64", "v_min_i16">; 900defm V_LSHLREV_B16 : VOP3_Real_gfx10_with_name<0x314, "V_LSHLREV_B16_e64", "v_lshlrev_b16">; 901defm V_PERMLANE16_B32 : VOP3OpSel_Real_gfx10<0x377>; 902defm V_PERMLANEX16_B32 : VOP3OpSel_Real_gfx10<0x378>; 903 904//===----------------------------------------------------------------------===// 905// GFX7, GFX10. 906//===----------------------------------------------------------------------===// 907 908let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in { 909 multiclass VOP3_Real_gfx7<bits<10> op> { 910 def _gfx7 : 911 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>, 912 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME).Pfl>; 913 } 914 multiclass VOP3be_Real_gfx7<bits<10> op> { 915 def _gfx7 : 916 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>, 917 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME).Pfl>; 918 } 919} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" 920 921multiclass VOP3_Real_gfx7_gfx10<bits<10> op> : 922 VOP3_Real_gfx7<op>, VOP3_Real_gfx10<op>; 923 924multiclass VOP3be_Real_gfx7_gfx10<bits<10> op> : 925 VOP3be_Real_gfx7<op>, VOP3be_Real_gfx10<op>; 926 927defm V_QSAD_PK_U16_U8 : VOP3_Real_gfx7_gfx10<0x172>; 928defm V_MQSAD_U32_U8 : VOP3_Real_gfx7_gfx10<0x175>; 929defm V_MAD_U64_U32 : VOP3be_Real_gfx7_gfx10<0x176>; 930defm V_MAD_I64_I32 : VOP3be_Real_gfx7_gfx10<0x177>; 931 932//===----------------------------------------------------------------------===// 933// GFX6, GFX7, GFX10. 934//===----------------------------------------------------------------------===// 935 936let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in { 937 multiclass VOP3_Real_gfx6_gfx7<bits<10> op> { 938 def _gfx6_gfx7 : 939 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>, 940 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME).Pfl>; 941 } 942 multiclass VOP3be_Real_gfx6_gfx7<bits<10> op> { 943 def _gfx6_gfx7 : 944 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>, 945 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME).Pfl>; 946 } 947} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" 948 949multiclass VOP3_Real_gfx6_gfx7_gfx10<bits<10> op> : 950 VOP3_Real_gfx6_gfx7<op>, VOP3_Real_gfx10<op>; 951 952multiclass VOP3be_Real_gfx6_gfx7_gfx10<bits<10> op> : 953 VOP3be_Real_gfx6_gfx7<op>, VOP3be_Real_gfx10<op>; 954 955defm V_LSHL_B64 : VOP3_Real_gfx6_gfx7<0x161>; 956defm V_LSHR_B64 : VOP3_Real_gfx6_gfx7<0x162>; 957defm V_ASHR_I64 : VOP3_Real_gfx6_gfx7<0x163>; 958 959defm V_MAD_LEGACY_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x140>; 960defm V_MAD_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x141>; 961defm V_MAD_I32_I24 : VOP3_Real_gfx6_gfx7_gfx10<0x142>; 962defm V_MAD_U32_U24 : VOP3_Real_gfx6_gfx7_gfx10<0x143>; 963defm V_CUBEID_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x144>; 964defm V_CUBESC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x145>; 965defm V_CUBETC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x146>; 966defm V_CUBEMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x147>; 967defm V_BFE_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x148>; 968defm V_BFE_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x149>; 969defm V_BFI_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14a>; 970defm V_FMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x14b>; 971defm V_FMA_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x14c>; 972defm V_LERP_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x14d>; 973defm V_ALIGNBIT_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14e>; 974defm V_ALIGNBYTE_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14f>; 975defm V_MULLIT_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x150>; 976defm V_MIN3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x151>; 977defm V_MIN3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x152>; 978defm V_MIN3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x153>; 979defm V_MAX3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x154>; 980defm V_MAX3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x155>; 981defm V_MAX3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x156>; 982defm V_MED3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x157>; 983defm V_MED3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x158>; 984defm V_MED3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x159>; 985defm V_SAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15a>; 986defm V_SAD_HI_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15b>; 987defm V_SAD_U16 : VOP3_Real_gfx6_gfx7_gfx10<0x15c>; 988defm V_SAD_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x15d>; 989defm V_CVT_PK_U8_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15e>; 990defm V_DIV_FIXUP_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15f>; 991defm V_DIV_FIXUP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x160>; 992defm V_ADD_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x164>; 993defm V_MUL_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x165>; 994defm V_MIN_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x166>; 995defm V_MAX_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x167>; 996defm V_LDEXP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x168>; 997defm V_MUL_LO_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x169>; 998defm V_MUL_HI_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x16a>; 999defm V_MUL_LO_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x16b>; 1000defm V_MUL_HI_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x16c>; 1001defm V_DIV_FMAS_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x16f>; 1002defm V_DIV_FMAS_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x170>; 1003defm V_MSAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x171>; 1004defm V_MQSAD_PK_U16_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x173>; 1005defm V_TRIG_PREOP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x174>; 1006defm V_DIV_SCALE_F32 : VOP3be_Real_gfx6_gfx7_gfx10<0x16d>; 1007defm V_DIV_SCALE_F64 : VOP3be_Real_gfx6_gfx7_gfx10<0x16e>; 1008 1009//===----------------------------------------------------------------------===// 1010// GFX8, GFX9 (VI). 1011//===----------------------------------------------------------------------===// 1012 1013let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in { 1014 1015multiclass VOP3_Real_vi<bits<10> op> { 1016 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 1017 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>; 1018} 1019 1020multiclass VOP3be_Real_vi<bits<10> op> { 1021 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 1022 VOP3be_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>; 1023} 1024 1025multiclass VOP3OpSel_Real_gfx9<bits<10> op> { 1026 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 1027 VOP3OpSel_gfx9 <op, !cast<VOP_Pseudo>(NAME).Pfl>; 1028} 1029 1030multiclass VOP3Interp_Real_vi<bits<10> op> { 1031 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 1032 VOP3Interp_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>; 1033} 1034 1035} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" 1036 1037let AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" in { 1038 1039multiclass VOP3_F16_Real_vi<bits<10> op> { 1040 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>, 1041 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>; 1042} 1043 1044multiclass VOP3Interp_F16_Real_vi<bits<10> op> { 1045 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>, 1046 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>; 1047} 1048 1049} // End AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" 1050 1051let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in { 1052 1053multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> { 1054 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>, 1055 VOP3e_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> { 1056 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName); 1057 let AsmString = AsmName # ps.AsmOperands; 1058 } 1059} 1060 1061multiclass VOP3OpSel_F16_Real_gfx9<bits<10> op, string AsmName> { 1062 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX9>, 1063 VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME).Pfl> { 1064 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME); 1065 let AsmString = AsmName # ps.AsmOperands; 1066 } 1067} 1068 1069multiclass VOP3Interp_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> { 1070 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>, 1071 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> { 1072 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName); 1073 let AsmString = AsmName # ps.AsmOperands; 1074 } 1075} 1076 1077multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> { 1078 def _gfx9 : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX9>, 1079 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME).Pfl> { 1080 VOP_Pseudo ps = !cast<VOP_Pseudo>(NAME); 1081 let AsmString = AsmName # ps.AsmOperands; 1082 } 1083} 1084 1085} // End AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" 1086 1087defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>; 1088defm V_MAD_I64_I32 : VOP3be_Real_vi <0x1E9>; 1089 1090defm V_MAD_LEGACY_F32 : VOP3_Real_vi <0x1c0>; 1091defm V_MAD_F32 : VOP3_Real_vi <0x1c1>; 1092defm V_MAD_I32_I24 : VOP3_Real_vi <0x1c2>; 1093defm V_MAD_U32_U24 : VOP3_Real_vi <0x1c3>; 1094defm V_CUBEID_F32 : VOP3_Real_vi <0x1c4>; 1095defm V_CUBESC_F32 : VOP3_Real_vi <0x1c5>; 1096defm V_CUBETC_F32 : VOP3_Real_vi <0x1c6>; 1097defm V_CUBEMA_F32 : VOP3_Real_vi <0x1c7>; 1098defm V_BFE_U32 : VOP3_Real_vi <0x1c8>; 1099defm V_BFE_I32 : VOP3_Real_vi <0x1c9>; 1100defm V_BFI_B32 : VOP3_Real_vi <0x1ca>; 1101defm V_FMA_F32 : VOP3_Real_vi <0x1cb>; 1102defm V_FMA_F64 : VOP3_Real_vi <0x1cc>; 1103defm V_LERP_U8 : VOP3_Real_vi <0x1cd>; 1104defm V_ALIGNBIT_B32 : VOP3_Real_vi <0x1ce>; 1105defm V_ALIGNBYTE_B32 : VOP3_Real_vi <0x1cf>; 1106defm V_MIN3_F32 : VOP3_Real_vi <0x1d0>; 1107defm V_MIN3_I32 : VOP3_Real_vi <0x1d1>; 1108defm V_MIN3_U32 : VOP3_Real_vi <0x1d2>; 1109defm V_MAX3_F32 : VOP3_Real_vi <0x1d3>; 1110defm V_MAX3_I32 : VOP3_Real_vi <0x1d4>; 1111defm V_MAX3_U32 : VOP3_Real_vi <0x1d5>; 1112defm V_MED3_F32 : VOP3_Real_vi <0x1d6>; 1113defm V_MED3_I32 : VOP3_Real_vi <0x1d7>; 1114defm V_MED3_U32 : VOP3_Real_vi <0x1d8>; 1115defm V_SAD_U8 : VOP3_Real_vi <0x1d9>; 1116defm V_SAD_HI_U8 : VOP3_Real_vi <0x1da>; 1117defm V_SAD_U16 : VOP3_Real_vi <0x1db>; 1118defm V_SAD_U32 : VOP3_Real_vi <0x1dc>; 1119defm V_CVT_PK_U8_F32 : VOP3_Real_vi <0x1dd>; 1120defm V_DIV_FIXUP_F32 : VOP3_Real_vi <0x1de>; 1121defm V_DIV_FIXUP_F64 : VOP3_Real_vi <0x1df>; 1122defm V_DIV_SCALE_F32 : VOP3be_Real_vi <0x1e0>; 1123defm V_DIV_SCALE_F64 : VOP3be_Real_vi <0x1e1>; 1124defm V_DIV_FMAS_F32 : VOP3_Real_vi <0x1e2>; 1125defm V_DIV_FMAS_F64 : VOP3_Real_vi <0x1e3>; 1126defm V_MSAD_U8 : VOP3_Real_vi <0x1e4>; 1127defm V_QSAD_PK_U16_U8 : VOP3_Real_vi <0x1e5>; 1128defm V_MQSAD_PK_U16_U8 : VOP3_Real_vi <0x1e6>; 1129defm V_MQSAD_U32_U8 : VOP3_Real_vi <0x1e7>; 1130 1131defm V_PERM_B32 : VOP3_Real_vi <0x1ed>; 1132 1133defm V_MAD_F16 : VOP3_F16_Real_vi <0x1ea>; 1134defm V_MAD_U16 : VOP3_F16_Real_vi <0x1eb>; 1135defm V_MAD_I16 : VOP3_F16_Real_vi <0x1ec>; 1136defm V_FMA_F16 : VOP3_F16_Real_vi <0x1ee>; 1137defm V_DIV_FIXUP_F16 : VOP3_F16_Real_vi <0x1ef>; 1138defm V_INTERP_P2_F16 : VOP3Interp_F16_Real_vi <0x276>; 1139 1140let FPDPRounding = 1 in { 1141defm V_MAD_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16", "v_mad_legacy_f16">; 1142defm V_FMA_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16", "v_fma_legacy_f16">; 1143defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16">; 1144defm V_INTERP_P2_LEGACY_F16 : VOP3Interp_F16_Real_gfx9 <0x276, "V_INTERP_P2_F16", "v_interp_p2_legacy_f16">; 1145} // End FPDPRounding = 1 1146 1147defm V_MAD_LEGACY_U16 : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16", "v_mad_legacy_u16">; 1148defm V_MAD_LEGACY_I16 : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16", "v_mad_legacy_i16">; 1149 1150defm V_MAD_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">; 1151defm V_MAD_U16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">; 1152defm V_MAD_I16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">; 1153defm V_FMA_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x206, "v_fma_f16">; 1154defm V_DIV_FIXUP_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">; 1155defm V_INTERP_P2_F16_gfx9 : VOP3Interp_F16_Real_gfx9 <0x277, "V_INTERP_P2_F16_gfx9", "v_interp_p2_f16">; 1156 1157defm V_ADD_I32_gfx9 : VOP3_Real_gfx9 <0x29c, "v_add_i32">; 1158defm V_SUB_I32_gfx9 : VOP3_Real_gfx9 <0x29d, "v_sub_i32">; 1159 1160defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_vi <0x270>; 1161defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_vi <0x271>; 1162defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>; 1163 1164defm V_INTERP_P1LL_F16 : VOP3Interp_Real_vi <0x274>; 1165defm V_INTERP_P1LV_F16 : VOP3Interp_Real_vi <0x275>; 1166defm V_ADD_F64 : VOP3_Real_vi <0x280>; 1167defm V_MUL_F64 : VOP3_Real_vi <0x281>; 1168defm V_MIN_F64 : VOP3_Real_vi <0x282>; 1169defm V_MAX_F64 : VOP3_Real_vi <0x283>; 1170defm V_LDEXP_F64 : VOP3_Real_vi <0x284>; 1171defm V_MUL_LO_U32 : VOP3_Real_vi <0x285>; 1172 1173// removed from VI as identical to V_MUL_LO_U32 1174let isAsmParserOnly = 1 in { 1175defm V_MUL_LO_I32 : VOP3_Real_vi <0x285>; 1176} 1177 1178defm V_MUL_HI_U32 : VOP3_Real_vi <0x286>; 1179defm V_MUL_HI_I32 : VOP3_Real_vi <0x287>; 1180 1181defm V_READLANE_B32 : VOP3_Real_vi <0x289>; 1182defm V_WRITELANE_B32 : VOP3_Real_vi <0x28a>; 1183 1184defm V_LSHLREV_B64 : VOP3_Real_vi <0x28f>; 1185defm V_LSHRREV_B64 : VOP3_Real_vi <0x290>; 1186defm V_ASHRREV_I64 : VOP3_Real_vi <0x291>; 1187defm V_TRIG_PREOP_F64 : VOP3_Real_vi <0x292>; 1188 1189defm V_LSHL_ADD_U32 : VOP3_Real_vi <0x1fd>; 1190defm V_ADD_LSHL_U32 : VOP3_Real_vi <0x1fe>; 1191defm V_ADD3_U32 : VOP3_Real_vi <0x1ff>; 1192defm V_LSHL_OR_B32 : VOP3_Real_vi <0x200>; 1193defm V_AND_OR_B32 : VOP3_Real_vi <0x201>; 1194defm V_OR3_B32 : VOP3_Real_vi <0x202>; 1195defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx9 <0x2a0>; 1196 1197defm V_XAD_U32 : VOP3_Real_vi <0x1f3>; 1198 1199defm V_MIN3_F16 : VOP3OpSel_Real_gfx9 <0x1f4>; 1200defm V_MIN3_I16 : VOP3OpSel_Real_gfx9 <0x1f5>; 1201defm V_MIN3_U16 : VOP3OpSel_Real_gfx9 <0x1f6>; 1202 1203defm V_MAX3_F16 : VOP3OpSel_Real_gfx9 <0x1f7>; 1204defm V_MAX3_I16 : VOP3OpSel_Real_gfx9 <0x1f8>; 1205defm V_MAX3_U16 : VOP3OpSel_Real_gfx9 <0x1f9>; 1206 1207defm V_MED3_F16 : VOP3OpSel_Real_gfx9 <0x1fa>; 1208defm V_MED3_I16 : VOP3OpSel_Real_gfx9 <0x1fb>; 1209defm V_MED3_U16 : VOP3OpSel_Real_gfx9 <0x1fc>; 1210 1211defm V_ADD_I16 : VOP3OpSel_Real_gfx9 <0x29e>; 1212defm V_SUB_I16 : VOP3OpSel_Real_gfx9 <0x29f>; 1213 1214defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx9 <0x1f1>; 1215defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx9 <0x1f2>; 1216 1217defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx9 <0x299>; 1218defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx9 <0x29a>; 1219