1//===-- VOP3Instructions.td - Vector Instruction Defintions ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// VOP3 Classes 12//===----------------------------------------------------------------------===// 13 14class getVOP3ModPat<VOPProfile P, SDPatternOperator node> { 15 list<dag> ret3 = [(set P.DstVT:$vdst, 16 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), 17 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), 18 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))]; 19 20 list<dag> ret2 = [(set P.DstVT:$vdst, 21 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), 22 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))]; 23 24 list<dag> ret1 = [(set P.DstVT:$vdst, 25 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod))))]; 26 27 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 28 !if(!eq(P.NumSrcArgs, 2), ret2, 29 ret1)); 30} 31 32class getVOP3PModPat<VOPProfile P, SDPatternOperator node> { 33 list<dag> ret3 = [(set P.DstVT:$vdst, 34 (node (P.Src0VT !if(P.HasClamp, (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp), 35 (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers))), 36 (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers)), 37 (P.Src2VT (VOP3PMods P.Src2VT:$src2, i32:$src2_modifiers))))]; 38 39 list<dag> ret2 = [(set P.DstVT:$vdst, 40 (node !if(P.HasClamp, (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)), 41 (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers))), 42 (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers))))]; 43 44 list<dag> ret1 = [(set P.DstVT:$vdst, 45 (node (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))]; 46 47 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 48 !if(!eq(P.NumSrcArgs, 2), ret2, 49 ret1)); 50} 51 52class getVOP3Pat<VOPProfile P, SDPatternOperator node> { 53 list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))]; 54 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]; 55 list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]; 56 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 57 !if(!eq(P.NumSrcArgs, 2), ret2, 58 ret1)); 59} 60 61class VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit VOP3Only = 0> : 62 VOP3_Pseudo<OpName, P, 63 !if(P.HasModifiers, getVOP3ModPat<P, node>.ret, getVOP3Pat<P, node>.ret), 64 VOP3Only>; 65 66// Special case for v_div_fmas_{f32|f64}, since it seems to be the 67// only VOP instruction that implicitly reads VCC. 68let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in { 69def VOP_F32_F32_F32_F32_VCC : VOPProfile<[f32, f32, f32, f32]> { 70 let Outs64 = (outs DstRC.RegClass:$vdst); 71} 72def VOP_F64_F64_F64_F64_VCC : VOPProfile<[f64, f64, f64, f64]> { 73 let Outs64 = (outs DstRC.RegClass:$vdst); 74} 75} 76 77class getVOP3VCC<VOPProfile P, SDPatternOperator node> { 78 list<dag> ret = 79 [(set P.DstVT:$vdst, 80 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), 81 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), 82 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)), 83 (i1 VCC)))]; 84} 85 86class VOP3_Profile<VOPProfile P> : VOPProfile<P.ArgVT> { 87 // FIXME: Hack to stop printing _e64 88 let Outs64 = (outs DstRC.RegClass:$vdst); 89 let Asm64 = " " # P.Asm64; 90} 91 92class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> { 93 // v_div_scale_{f32|f64} do not support input modifiers. 94 let HasModifiers = 0; 95 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst); 96 let Asm64 = " $vdst, $sdst, $src0, $src1, $src2"; 97} 98 99def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32> { 100 // FIXME: Hack to stop printing _e64 101 let DstRC = RegisterOperand<VGPR_32>; 102} 103 104def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> { 105 // FIXME: Hack to stop printing _e64 106 let DstRC = RegisterOperand<VReg_64>; 107} 108 109//===----------------------------------------------------------------------===// 110// VOP3 Instructions 111//===----------------------------------------------------------------------===// 112 113let isCommutable = 1 in { 114 115def V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 116def V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fmad>; 117def V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUmad_i24>; 118def V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUmad_u24>; 119def V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fma>; 120def V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, fma>; 121def V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>; 122 123let SchedRW = [WriteDoubleAdd] in { 124def V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, fadd, 1>; 125def V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, fmul, 1>; 126def V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum, 1>; 127def V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum, 1>; 128} // End SchedRW = [WriteDoubleAdd] 129 130let SchedRW = [WriteQuarterRate32] in { 131def V_MUL_LO_U32 : VOP3Inst <"v_mul_lo_u32", VOP3_Profile<VOP_I32_I32_I32>>; 132def V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", VOP3_Profile<VOP_I32_I32_I32>, mulhu>; 133def V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", VOP3_Profile<VOP_I32_I32_I32>>; 134def V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", VOP3_Profile<VOP_I32_I32_I32>, mulhs>; 135} // End SchedRW = [WriteQuarterRate32] 136 137let Uses = [VCC, EXEC] in { 138// v_div_fmas_f32: 139// result = src0 * src1 + src2 140// if (vcc) 141// result *= 2^32 142// 143def V_DIV_FMAS_F32 : VOP3_Pseudo <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC, 144 getVOP3VCC<VOP_F32_F32_F32_F32_VCC, AMDGPUdiv_fmas>.ret> { 145 let SchedRW = [WriteFloatFMA]; 146} 147// v_div_fmas_f64: 148// result = src0 * src1 + src2 149// if (vcc) 150// result *= 2^64 151// 152def V_DIV_FMAS_F64 : VOP3_Pseudo <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC, 153 getVOP3VCC<VOP_F64_F64_F64_F64_VCC, AMDGPUdiv_fmas>.ret> { 154 let SchedRW = [WriteDouble]; 155} 156} // End Uses = [VCC, EXEC] 157 158} // End isCommutable = 1 159 160def V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubeid>; 161def V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubesc>; 162def V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubetc>; 163def V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubema>; 164def V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>; 165def V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>; 166def V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>; 167def V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 168def V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 169def V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmin3>; 170def V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>; 171def V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>; 172def V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>; 173def V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>; 174def V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>; 175def V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>; 176def V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>; 177def V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>; 178def V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_sad_u8>; 179def V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_sad_hi_u8>; 180def V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_sad_u16>; 181def V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 182def V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>; 183def V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUdiv_fixup>; 184 185let SchedRW = [WriteDoubleAdd] in { 186def V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>; 187def V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp, 1>; 188} // End SchedRW = [WriteDoubleAdd] 189 190def V_DIV_SCALE_F32 : VOP3_Pseudo <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> { 191 let SchedRW = [WriteFloatFMA, WriteSALU]; 192 let hasExtraSrcRegAllocReq = 1; 193 let AsmMatchConverter = ""; 194} 195 196// Double precision division pre-scale. 197def V_DIV_SCALE_F64 : VOP3_Pseudo <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1> { 198 let SchedRW = [WriteDouble, WriteSALU]; 199 let hasExtraSrcRegAllocReq = 1; 200 let AsmMatchConverter = ""; 201} 202 203def V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_msad_u8>; 204def V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64>, int_amdgcn_mqsad_pk_u16_u8>; 205 206def V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUtrig_preop> { 207 let SchedRW = [WriteDouble]; 208} 209 210// These instructions only exist on SI and CI 211let SubtargetPredicate = isSICI in { 212def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>>; 213def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>>; 214def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>>; 215def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 216} // End SubtargetPredicate = isSICI 217 218let SubtargetPredicate = isVI in { 219def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>>; 220def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>>; 221def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>>; 222} // End SubtargetPredicate = isVI 223 224 225let SubtargetPredicate = isCIVI in { 226 227def V_MQSAD_U16_U8 : VOP3Inst <"v_mqsad_u16_u8", VOP3_Profile<VOP_I32_I32_I32>>; 228def V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64>, int_amdgcn_qsad_pk_u16_u8>; 229def V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_V4I32>, int_amdgcn_mqsad_u32_u8>; 230 231let isCommutable = 1 in { 232def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3_Profile<VOP_I64_I32_I32_I64>>; 233 234// XXX - Does this set VCC? 235def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3_Profile<VOP_I64_I32_I32_I64>>; 236} // End isCommutable = 1 237 238} // End SubtargetPredicate = isCIVI 239 240 241let SubtargetPredicate = isVI in { 242 243let isCommutable = 1 in { 244 245def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>; 246def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>; 247def V_INTERP_P1LL_F16 : VOP3Inst <"v_interp_p1ll_f16", VOP3_Profile<VOP_F32_F32_F16>>; 248def V_INTERP_P1LV_F16 : VOP3Inst <"v_interp_p1lv_f16", VOP3_Profile<VOP_F32_F32_F16_F16>>; 249def V_INTERP_P2_F16 : VOP3Inst <"v_interp_p2_f16", VOP3_Profile<VOP_F16_F32_F16_F32>>; 250def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>; 251 252def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16>>; 253def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>; 254 255} // End isCommutable = 1 256 257} // End SubtargetPredicate = isVI 258 259let Predicates = [isVI] in { 260 261multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2, 262 Instruction inst, SDPatternOperator op3> { 263def : Pat< 264 (op2 (op1 i16:$src0, i16:$src1), i16:$src2), 265 (inst i16:$src0, i16:$src1, i16:$src2) 266>; 267 268def : Pat< 269 (i32 (op3 (op2 (op1 i16:$src0, i16:$src1), i16:$src2))), 270 (inst i16:$src0, i16:$src1, i16:$src2) 271>; 272 273def : Pat< 274 (i64 (op3 (op2 (op1 i16:$src0, i16:$src1), i16:$src2))), 275 (REG_SEQUENCE VReg_64, 276 (inst i16:$src0, i16:$src1, i16:$src2), sub0, 277 (V_MOV_B32_e32 (i32 0)), sub1) 278>; 279} 280 281defm: Ternary_i16_Pats<mul, add, V_MAD_U16, zext>; 282defm: Ternary_i16_Pats<mul, add, V_MAD_I16, sext>; 283 284} // End Predicates = [isVI] 285 286let SubtargetPredicate = isGFX9 in { 287def V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile<VOP_B32_F16_F16>>; 288def V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 289def V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 290def V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 291def V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 292def V_AND_OR_B32 : VOP3Inst <"v_and_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 293def V_OR3_B32 : VOP3Inst <"v_or3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 294 295def V_MED3_F16 : VOP3Inst <"v_med3_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUfmed3>; 296def V_MED3_I16 : VOP3Inst <"v_med3_i16", VOP3_Profile<VOP_I16_I16_I16_I16>, AMDGPUsmed3>; 297def V_MED3_U16 : VOP3Inst <"v_med3_u16", VOP3_Profile<VOP_I16_I16_I16_I16>, AMDGPUumed3>; 298} 299 300 301//===----------------------------------------------------------------------===// 302// Target 303//===----------------------------------------------------------------------===// 304 305//===----------------------------------------------------------------------===// 306// SI 307//===----------------------------------------------------------------------===// 308 309let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in { 310 311multiclass VOP3_Real_si<bits<9> op> { 312 def _si : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>, 313 VOP3e_si <op, !cast<VOP3_Pseudo>(NAME).Pfl>; 314} 315 316multiclass VOP3be_Real_si<bits<9> op> { 317 def _si : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>, 318 VOP3be_si <op, !cast<VOP3_Pseudo>(NAME).Pfl>; 319} 320 321} // End AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" 322 323defm V_MAD_LEGACY_F32 : VOP3_Real_si <0x140>; 324defm V_MAD_F32 : VOP3_Real_si <0x141>; 325defm V_MAD_I32_I24 : VOP3_Real_si <0x142>; 326defm V_MAD_U32_U24 : VOP3_Real_si <0x143>; 327defm V_CUBEID_F32 : VOP3_Real_si <0x144>; 328defm V_CUBESC_F32 : VOP3_Real_si <0x145>; 329defm V_CUBETC_F32 : VOP3_Real_si <0x146>; 330defm V_CUBEMA_F32 : VOP3_Real_si <0x147>; 331defm V_BFE_U32 : VOP3_Real_si <0x148>; 332defm V_BFE_I32 : VOP3_Real_si <0x149>; 333defm V_BFI_B32 : VOP3_Real_si <0x14a>; 334defm V_FMA_F32 : VOP3_Real_si <0x14b>; 335defm V_FMA_F64 : VOP3_Real_si <0x14c>; 336defm V_LERP_U8 : VOP3_Real_si <0x14d>; 337defm V_ALIGNBIT_B32 : VOP3_Real_si <0x14e>; 338defm V_ALIGNBYTE_B32 : VOP3_Real_si <0x14f>; 339defm V_MULLIT_F32 : VOP3_Real_si <0x150>; 340defm V_MIN3_F32 : VOP3_Real_si <0x151>; 341defm V_MIN3_I32 : VOP3_Real_si <0x152>; 342defm V_MIN3_U32 : VOP3_Real_si <0x153>; 343defm V_MAX3_F32 : VOP3_Real_si <0x154>; 344defm V_MAX3_I32 : VOP3_Real_si <0x155>; 345defm V_MAX3_U32 : VOP3_Real_si <0x156>; 346defm V_MED3_F32 : VOP3_Real_si <0x157>; 347defm V_MED3_I32 : VOP3_Real_si <0x158>; 348defm V_MED3_U32 : VOP3_Real_si <0x159>; 349defm V_SAD_U8 : VOP3_Real_si <0x15a>; 350defm V_SAD_HI_U8 : VOP3_Real_si <0x15b>; 351defm V_SAD_U16 : VOP3_Real_si <0x15c>; 352defm V_SAD_U32 : VOP3_Real_si <0x15d>; 353defm V_CVT_PK_U8_F32 : VOP3_Real_si <0x15e>; 354defm V_DIV_FIXUP_F32 : VOP3_Real_si <0x15f>; 355defm V_DIV_FIXUP_F64 : VOP3_Real_si <0x160>; 356defm V_LSHL_B64 : VOP3_Real_si <0x161>; 357defm V_LSHR_B64 : VOP3_Real_si <0x162>; 358defm V_ASHR_I64 : VOP3_Real_si <0x163>; 359defm V_ADD_F64 : VOP3_Real_si <0x164>; 360defm V_MUL_F64 : VOP3_Real_si <0x165>; 361defm V_MIN_F64 : VOP3_Real_si <0x166>; 362defm V_MAX_F64 : VOP3_Real_si <0x167>; 363defm V_LDEXP_F64 : VOP3_Real_si <0x168>; 364defm V_MUL_LO_U32 : VOP3_Real_si <0x169>; 365defm V_MUL_HI_U32 : VOP3_Real_si <0x16a>; 366defm V_MUL_LO_I32 : VOP3_Real_si <0x16b>; 367defm V_MUL_HI_I32 : VOP3_Real_si <0x16c>; 368defm V_DIV_SCALE_F32 : VOP3be_Real_si <0x16d>; 369defm V_DIV_SCALE_F64 : VOP3be_Real_si <0x16e>; 370defm V_DIV_FMAS_F32 : VOP3_Real_si <0x16f>; 371defm V_DIV_FMAS_F64 : VOP3_Real_si <0x170>; 372defm V_MSAD_U8 : VOP3_Real_si <0x171>; 373defm V_MQSAD_PK_U16_U8 : VOP3_Real_si <0x173>; 374defm V_TRIG_PREOP_F64 : VOP3_Real_si <0x174>; 375 376//===----------------------------------------------------------------------===// 377// CI 378//===----------------------------------------------------------------------===// 379 380multiclass VOP3_Real_ci<bits<9> op> { 381 def _ci : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>, 382 VOP3e_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> { 383 let AssemblerPredicates = [isCIOnly]; 384 let DecoderNamespace = "CI"; 385 } 386} 387 388defm V_MQSAD_U16_U8 : VOP3_Real_ci <0x172>; 389defm V_QSAD_PK_U16_U8 : VOP3_Real_ci <0x172>; 390defm V_MQSAD_U32_U8 : VOP3_Real_ci <0x174>; 391defm V_MAD_U64_U32 : VOP3_Real_ci <0x176>; 392defm V_MAD_I64_I32 : VOP3_Real_ci <0x177>; 393 394//===----------------------------------------------------------------------===// 395// VI 396//===----------------------------------------------------------------------===// 397 398let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in { 399 400multiclass VOP3_Real_vi<bits<10> op> { 401 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>, 402 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>; 403} 404 405multiclass VOP3be_Real_vi<bits<10> op> { 406 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>, 407 VOP3be_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>; 408} 409 410} // End AssemblerPredicates = [isVI], DecoderNamespace = "VI" 411 412defm V_MQSAD_U16_U8 : VOP3_Real_vi <0x172>; 413defm V_MAD_U64_U32 : VOP3_Real_vi <0x176>; 414defm V_MAD_I64_I32 : VOP3_Real_vi <0x177>; 415 416defm V_MAD_LEGACY_F32 : VOP3_Real_vi <0x1c0>; 417defm V_MAD_F32 : VOP3_Real_vi <0x1c1>; 418defm V_MAD_I32_I24 : VOP3_Real_vi <0x1c2>; 419defm V_MAD_U32_U24 : VOP3_Real_vi <0x1c3>; 420defm V_CUBEID_F32 : VOP3_Real_vi <0x1c4>; 421defm V_CUBESC_F32 : VOP3_Real_vi <0x1c5>; 422defm V_CUBETC_F32 : VOP3_Real_vi <0x1c6>; 423defm V_CUBEMA_F32 : VOP3_Real_vi <0x1c7>; 424defm V_BFE_U32 : VOP3_Real_vi <0x1c8>; 425defm V_BFE_I32 : VOP3_Real_vi <0x1c9>; 426defm V_BFI_B32 : VOP3_Real_vi <0x1ca>; 427defm V_FMA_F32 : VOP3_Real_vi <0x1cb>; 428defm V_FMA_F64 : VOP3_Real_vi <0x1cc>; 429defm V_LERP_U8 : VOP3_Real_vi <0x1cd>; 430defm V_ALIGNBIT_B32 : VOP3_Real_vi <0x1ce>; 431defm V_ALIGNBYTE_B32 : VOP3_Real_vi <0x1cf>; 432defm V_MIN3_F32 : VOP3_Real_vi <0x1d0>; 433defm V_MIN3_I32 : VOP3_Real_vi <0x1d1>; 434defm V_MIN3_U32 : VOP3_Real_vi <0x1d2>; 435defm V_MAX3_F32 : VOP3_Real_vi <0x1d3>; 436defm V_MAX3_I32 : VOP3_Real_vi <0x1d4>; 437defm V_MAX3_U32 : VOP3_Real_vi <0x1d5>; 438defm V_MED3_F32 : VOP3_Real_vi <0x1d6>; 439defm V_MED3_I32 : VOP3_Real_vi <0x1d7>; 440defm V_MED3_U32 : VOP3_Real_vi <0x1d8>; 441defm V_SAD_U8 : VOP3_Real_vi <0x1d9>; 442defm V_SAD_HI_U8 : VOP3_Real_vi <0x1da>; 443defm V_SAD_U16 : VOP3_Real_vi <0x1db>; 444defm V_SAD_U32 : VOP3_Real_vi <0x1dc>; 445defm V_CVT_PK_U8_F32 : VOP3_Real_vi <0x1dd>; 446defm V_DIV_FIXUP_F32 : VOP3_Real_vi <0x1de>; 447defm V_DIV_FIXUP_F64 : VOP3_Real_vi <0x1df>; 448defm V_DIV_SCALE_F32 : VOP3be_Real_vi <0x1e0>; 449defm V_DIV_SCALE_F64 : VOP3be_Real_vi <0x1e1>; 450defm V_DIV_FMAS_F32 : VOP3_Real_vi <0x1e2>; 451defm V_DIV_FMAS_F64 : VOP3_Real_vi <0x1e3>; 452defm V_MSAD_U8 : VOP3_Real_vi <0x1e4>; 453defm V_QSAD_PK_U16_U8 : VOP3_Real_vi <0x1e5>; 454defm V_MQSAD_PK_U16_U8 : VOP3_Real_vi <0x1e6>; 455defm V_MQSAD_U32_U8 : VOP3_Real_vi <0x1e7>; 456 457defm V_MAD_F16 : VOP3_Real_vi <0x1ea>; 458defm V_MAD_U16 : VOP3_Real_vi <0x1eb>; 459defm V_MAD_I16 : VOP3_Real_vi <0x1ec>; 460 461defm V_FMA_F16 : VOP3_Real_vi <0x1ee>; 462defm V_DIV_FIXUP_F16 : VOP3_Real_vi <0x1ef>; 463 464defm V_INTERP_P1LL_F16 : VOP3_Real_vi <0x274>; 465defm V_INTERP_P1LV_F16 : VOP3_Real_vi <0x275>; 466defm V_INTERP_P2_F16 : VOP3_Real_vi <0x276>; 467defm V_ADD_F64 : VOP3_Real_vi <0x280>; 468defm V_MUL_F64 : VOP3_Real_vi <0x281>; 469defm V_MIN_F64 : VOP3_Real_vi <0x282>; 470defm V_MAX_F64 : VOP3_Real_vi <0x283>; 471defm V_LDEXP_F64 : VOP3_Real_vi <0x284>; 472defm V_MUL_LO_U32 : VOP3_Real_vi <0x285>; 473 474// removed from VI as identical to V_MUL_LO_U32 475let isAsmParserOnly = 1 in { 476defm V_MUL_LO_I32 : VOP3_Real_vi <0x285>; 477} 478 479defm V_MUL_HI_U32 : VOP3_Real_vi <0x286>; 480defm V_MUL_HI_I32 : VOP3_Real_vi <0x287>; 481 482defm V_LSHLREV_B64 : VOP3_Real_vi <0x28f>; 483defm V_LSHRREV_B64 : VOP3_Real_vi <0x290>; 484defm V_ASHRREV_I64 : VOP3_Real_vi <0x291>; 485defm V_TRIG_PREOP_F64 : VOP3_Real_vi <0x292>; 486 487defm V_LSHL_ADD_U32 : VOP3_Real_vi <0x1fd>; 488defm V_ADD_LSHL_U32 : VOP3_Real_vi <0x1fe>; 489defm V_ADD3_U32 : VOP3_Real_vi <0x1ff>; 490defm V_LSHL_OR_B32 : VOP3_Real_vi <0x200>; 491defm V_AND_OR_B32 : VOP3_Real_vi <0x201>; 492defm V_OR3_B32 : VOP3_Real_vi <0x202>; 493defm V_PACK_B32_F16 : VOP3_Real_vi <0x2a0>; 494 495defm V_MED3_F16 : VOP3_Real_vi <0x1fa>; 496defm V_MED3_I16 : VOP3_Real_vi <0x1fb>; 497defm V_MED3_U16 : VOP3_Real_vi <0x1fc>; 498