1//===-- VOP3Instructions.td - Vector Instruction Definitions --------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// VOP3 Classes 11//===----------------------------------------------------------------------===// 12 13class getVOP3ModPat<VOPProfile P, SDPatternOperator node> { 14 dag src0 = !if(P.HasOMod, 15 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 16 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)); 17 18 list<dag> ret3 = [(set P.DstVT:$vdst, 19 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 20 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), 21 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))]; 22 23 list<dag> ret2 = [(set P.DstVT:$vdst, 24 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 25 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))]; 26 27 list<dag> ret1 = [(set P.DstVT:$vdst, 28 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))]; 29 30 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 31 !if(!eq(P.NumSrcArgs, 2), ret2, 32 ret1)); 33} 34 35class getVOP3PModPat<VOPProfile P, SDPatternOperator node, bit HasExplicitClamp> { 36 dag src0_dag = (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers)); 37 dag src1_dag = (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers)); 38 dag src2_dag = (P.Src2VT (VOP3PMods P.Src2VT:$src2, i32:$src2_modifiers)); 39 dag clamp_dag = (i1 timm:$clamp); 40 41 list<dag> ret3 = [(set P.DstVT:$vdst, 42 !if(HasExplicitClamp, 43 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, src2_dag, clamp_dag), 44 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, src2_dag)))]; 45 46 list<dag> ret2 = [(set P.DstVT:$vdst, 47 !if(HasExplicitClamp, 48 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, clamp_dag), 49 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag)))]; 50 51 list<dag> ret1 = [(set P.DstVT:$vdst, 52 !if(HasExplicitClamp, 53 (DivergentFragOrOp<node, P>.ret src0_dag, clamp_dag), 54 (DivergentFragOrOp<node, P>.ret src0_dag)))]; 55 56 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 57 !if(!eq(P.NumSrcArgs, 2), ret2, 58 ret1)); 59} 60 61class getVOP3OpSelPat<VOPProfile P, SDPatternOperator node> { 62 list<dag> ret3 = [(set P.DstVT:$vdst, 63 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)), 64 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)), 65 (P.Src2VT (VOP3OpSel P.Src2VT:$src2, i32:$src2_modifiers))))]; 66 67 list<dag> ret2 = [(set P.DstVT:$vdst, 68 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)), 69 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))]; 70 71 list<dag> ret1 = [(set P.DstVT:$vdst, 72 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))))]; 73 74 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 75 !if(!eq(P.NumSrcArgs, 2), ret2, 76 ret1)); 77} 78 79class getVOP3OpSelModPat<VOPProfile P, SDPatternOperator node> { 80 list<dag> ret3 = [(set P.DstVT:$vdst, 81 (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers), 82 (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 83 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)), 84 (P.Src2VT (VOP3OpSelMods P.Src2VT:$src2, i32:$src2_modifiers))))]; 85 86 list<dag> ret2 = [(set P.DstVT:$vdst, 87 (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers)), 88 (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 89 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))]; 90 91 list<dag> ret1 = [(set P.DstVT:$vdst, 92 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))))]; 93 94 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 95 !if(!eq(P.NumSrcArgs, 2), ret2, 96 ret1)); 97} 98 99class getVOP3Pat<VOPProfile P, SDPatternOperator node> { 100 list<dag> ret3 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))]; 101 list<dag> ret2 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$src1))]; 102 list<dag> ret1 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0))]; 103 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 104 !if(!eq(P.NumSrcArgs, 2), ret2, 105 ret1)); 106} 107 108class getVOP3ClampPat<VOPProfile P, SDPatternOperator node> { 109 list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i1:$clamp))]; 110 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))]; 111 list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, i1:$clamp))]; 112 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 113 !if(!eq(P.NumSrcArgs, 2), ret2, 114 ret1)); 115} 116 117class getVOP3MAIPat<VOPProfile P, SDPatternOperator node> { 118 list<dag> ret = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, 119 timm:$cbsz, timm:$abid, timm:$blgp))]; 120} 121 122// Consistently gives instructions a _e64 suffix. 123multiclass VOP3Inst_Pseudo_Wrapper<string opName, VOPProfile P, list<dag> pattern = [], bit VOP3Only = 0> { 124 def _e64 : VOP3_Pseudo<opName, P, pattern, VOP3Only>; 125} 126 127class VOP3InstBase<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit VOP3Only = 0> : 128 VOP3_Pseudo<OpName, P, 129 !if(P.HasOpSel, 130 !if(P.HasModifiers, 131 getVOP3OpSelModPat<P, node>.ret, 132 getVOP3OpSelPat<P, node>.ret), 133 !if(P.HasModifiers, 134 getVOP3ModPat<P, node>.ret, 135 !if(P.HasIntClamp, 136 getVOP3ClampPat<P, node>.ret, 137 !if (P.IsMAI, 138 getVOP3MAIPat<P, node>.ret, 139 getVOP3Pat<P, node>.ret)))), 140 VOP3Only, 0, P.HasOpSel> { 141 142 let IntClamp = P.HasIntClamp; 143 let AsmMatchConverter = 144 !if(P.HasOpSel, 145 "cvtVOP3OpSel", 146 !if(!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), 147 "cvtVOP3", 148 "")); 149} 150 151multiclass VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit VOP3Only = 0> { 152 def _e64 : VOP3InstBase<OpName, P, node, VOP3Only>; 153} 154 155// Special case for v_div_fmas_{f32|f64}, since it seems to be the 156// only VOP instruction that implicitly reads VCC. 157let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in { 158def VOP_F32_F32_F32_F32_VCC : VOPProfile<[f32, f32, f32, f32]> { 159 let Outs64 = (outs DstRC.RegClass:$vdst); 160} 161def VOP_F64_F64_F64_F64_VCC : VOPProfile<[f64, f64, f64, f64]> { 162 let Outs64 = (outs DstRC.RegClass:$vdst); 163} 164} 165 166class VOP3Features<bit Clamp, bit OpSel, bit Packed, bit MAI> { 167 bit HasClamp = Clamp; 168 bit HasOpSel = OpSel; 169 bit IsPacked = Packed; 170 bit IsMAI = MAI; 171} 172 173def VOP3_REGULAR : VOP3Features<0, 0, 0, 0>; 174def VOP3_CLAMP : VOP3Features<1, 0, 0, 0>; 175def VOP3_OPSEL : VOP3Features<1, 1, 0, 0>; 176def VOP3_PACKED : VOP3Features<1, 1, 1, 0>; 177def VOP3_MAI : VOP3Features<0, 0, 0, 1>; 178 179class VOP3_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOPProfile<P.ArgVT> { 180 181 let HasClamp = !if(Features.HasClamp, 1, P.HasClamp); 182 let HasOpSel = !if(Features.HasOpSel, 1, P.HasOpSel); 183 let IsMAI = !if(Features.IsMAI, 1, P.IsMAI); 184 let IsPacked = !if(Features.IsPacked, 1, P.IsPacked); 185 186 let HasModifiers = !if(Features.IsMAI, 0, !or(Features.IsPacked, P.HasModifiers)); 187 let IsSingle = 1; 188} 189 190class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> { 191 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 192 let Asm64 = "$vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod"; 193 let IsSingle = 1; 194} 195 196def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32>; 197def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64>; 198 199def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> { 200 let HasClamp = 1; 201 let IsSingle = 1; 202 203 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 204 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp"; 205} 206 207//===----------------------------------------------------------------------===// 208// VOP3 INTERP 209//===----------------------------------------------------------------------===// 210 211class VOP3Interp<string OpName, VOPProfile P, list<dag> pattern = []> : 212 VOP3_Pseudo<OpName, P, pattern> { 213 let AsmMatchConverter = "cvtVOP3Interp"; 214 let mayRaiseFPException = 0; 215} 216 217def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> { 218 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 219 Attr:$attr, AttrChan:$attrchan, 220 clampmod0:$clamp, omod0:$omod); 221 222 let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod"; 223} 224 225def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> { 226 let Ins64 = (ins InterpSlot:$src0, 227 Attr:$attr, AttrChan:$attrchan, 228 clampmod0:$clamp, omod0:$omod); 229 230 let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod"; 231 232 let HasClamp = 1; 233 let HasSrc0Mods = 0; 234} 235 236class getInterp16Asm <bit HasSrc2, bit HasOMod> { 237 string src2 = !if(HasSrc2, ", $src2_modifiers", ""); 238 string omod = !if(HasOMod, "$omod", ""); 239 string ret = 240 " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod; 241} 242 243class getInterp16Ins <bit HasSrc2, bit HasOMod, 244 Operand Src0Mod, Operand Src2Mod> { 245 dag ret = !if(HasSrc2, 246 !if(HasOMod, 247 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 248 Attr:$attr, AttrChan:$attrchan, 249 Src2Mod:$src2_modifiers, VRegSrc_32:$src2, 250 highmod:$high, clampmod0:$clamp, omod0:$omod), 251 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 252 Attr:$attr, AttrChan:$attrchan, 253 Src2Mod:$src2_modifiers, VRegSrc_32:$src2, 254 highmod:$high, clampmod0:$clamp) 255 ), 256 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 257 Attr:$attr, AttrChan:$attrchan, 258 highmod:$high, clampmod0:$clamp, omod0:$omod) 259 ); 260} 261 262class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> { 263 264 let HasOMod = !ne(DstVT.Value, f16.Value); 265 let HasHigh = 1; 266 267 let Outs64 = (outs VGPR_32:$vdst); 268 let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret; 269 let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret; 270} 271 272//===----------------------------------------------------------------------===// 273// VOP3 Instructions 274//===----------------------------------------------------------------------===// 275 276let isCommutable = 1 in { 277 278let mayRaiseFPException = 0 in { 279let SubtargetPredicate = HasMadMacF32Insts in { 280defm V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 281defm V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fmad>; 282} // End SubtargetPredicate = HasMadMacInsts 283 284let SubtargetPredicate = HasFmaLegacy32 in 285defm V_FMA_LEGACY_F32 : VOP3Inst <"v_fma_legacy_f32", 286 VOP3_Profile<VOP_F32_F32_F32_F32>, 287 int_amdgcn_fma_legacy>; 288} 289 290defm V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 291defm V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 292defm V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, any_fma>; 293defm V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>; 294 295let SchedRW = [WriteDoubleAdd] in { 296let FPDPRounding = 1 in { 297defm V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, any_fma>; 298defm V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, any_fadd, 1>; 299defm V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, fmul, 1>; 300} // End FPDPRounding = 1 301defm V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum_like, 1>; 302defm V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum_like, 1>; 303} // End SchedRW = [WriteDoubleAdd] 304 305let SchedRW = [WriteIntMul] in { 306defm V_MUL_LO_U32 : VOP3Inst <"v_mul_lo_u32", VOP3_Profile<VOP_I32_I32_I32>, mul>; 307defm V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", VOP3_Profile<VOP_I32_I32_I32>, mulhu>; 308defm V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", VOP3_Profile<VOP_I32_I32_I32>>; 309defm V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", VOP3_Profile<VOP_I32_I32_I32>, mulhs>; 310} // End SchedRW = [WriteIntMul] 311 312let Uses = [MODE, VCC, EXEC] in { 313// v_div_fmas_f32: 314// result = src0 * src1 + src2 315// if (vcc) 316// result *= 2^32 317// 318let SchedRW = [WriteFloatFMA] in 319defm V_DIV_FMAS_F32 : VOP3Inst_Pseudo_Wrapper <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC, []>; 320// v_div_fmas_f64: 321// result = src0 * src1 + src2 322// if (vcc) 323// result *= 2^64 324// 325let SchedRW = [WriteDouble], FPDPRounding = 1 in 326defm V_DIV_FMAS_F64 : VOP3Inst_Pseudo_Wrapper <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC, []>; 327} // End Uses = [MODE, VCC, EXEC] 328 329} // End isCommutable = 1 330 331let mayRaiseFPException = 0 in { 332defm V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubeid>; 333defm V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubesc>; 334defm V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubetc>; 335defm V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubema>; 336} // End mayRaiseFPException 337 338defm V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>; 339defm V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>; 340defm V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>; 341defm V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, fshr>; 342defm V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>; 343 344// XXX - No FPException seems suspect but manual doesn't say it does 345let mayRaiseFPException = 0 in { 346 let isCommutable = 1 in { 347 defm V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>; 348 defm V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>; 349 defm V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>; 350 defm V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>; 351 defm V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>; 352 defm V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>; 353 } // End isCommutable = 1 354 defm V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmin3>; 355 defm V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>; 356 defm V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>; 357} // End mayRaiseFPException = 0 358 359let isCommutable = 1 in { 360 defm V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 361 defm V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 362 defm V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 363 defm V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 364} // End isCommutable = 1 365defm V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>; 366 367defm V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUdiv_fixup>; 368 369let SchedRW = [WriteDoubleAdd], FPDPRounding = 1 in { 370 defm V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>; 371 defm V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp, 1>; 372} // End SchedRW = [WriteDoubleAdd], FPDPRounding = 1 373 374 375let mayRaiseFPException = 0 in { // Seems suspicious but manual doesn't say it does. 376 let SchedRW = [WriteFloatFMA, WriteSALU] in 377 defm V_DIV_SCALE_F32 : VOP3Inst_Pseudo_Wrapper <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> ; 378 379 // Double precision division pre-scale. 380 let SchedRW = [WriteDouble, WriteSALU], FPDPRounding = 1 in 381 defm V_DIV_SCALE_F64 : VOP3Inst_Pseudo_Wrapper <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1>; 382} // End mayRaiseFPException = 0 383 384defm V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 385 386let Constraints = "@earlyclobber $vdst" in { 387defm V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>; 388} // End Constraints = "@earlyclobber $vdst" 389 390 391let SchedRW = [WriteDouble] in { 392defm V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, int_amdgcn_trig_preop>; 393} // End SchedRW = [WriteDouble] 394 395let SchedRW = [Write64Bit] in { 396 let SubtargetPredicate = isGFX6GFX7 in { 397 defm V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>, shl>; 398 defm V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>, srl>; 399 defm V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>, sra>; 400 } // End SubtargetPredicate = isGFX6GFX7 401 402 let SubtargetPredicate = isGFX8Plus in { 403 defm V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshl_rev>; 404 defm V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshr_rev>; 405 defm V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, ashr_rev>; 406 } // End SubtargetPredicate = isGFX8Plus 407} // End SchedRW = [Write64Bit] 408 409def : GCNPat< 410 (i32 (getDivergentFrag<sext>.ret i16:$src)), 411 (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))) 412>; 413 414let SubtargetPredicate = isGFX6GFX7GFX10 in { 415defm V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 416} // End SubtargetPredicate = isGFX6GFX7GFX10 417 418let SchedRW = [Write32Bit] in { 419let SubtargetPredicate = isGFX8Plus in { 420defm V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUperm>; 421} // End SubtargetPredicate = isGFX8Plus 422} // End SchedRW = [Write32Bit] 423 424let SubtargetPredicate = isGFX7Plus in { 425 426let Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] in { 427defm V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>; 428defm V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_V4I32, VOP3_CLAMP>>; 429} // End Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] 430 431let isCommutable = 1 in { 432let SchedRW = [WriteIntMul, WriteSALU] in { 433defm V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>; 434defm V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>; 435} // End SchedRW = [WriteIntMul, WriteSALU] 436} // End isCommutable = 1 437 438} // End SubtargetPredicate = isGFX7Plus 439 440let FPDPRounding = 1 in { 441 let Predicates = [Has16BitInsts, isGFX8Only] in { 442 defm V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>; 443 defm V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, any_fma>; 444 } // End Predicates = [Has16BitInsts, isGFX8Only] 445 446 let renamedInGFX9 = 1, Predicates = [Has16BitInsts, isGFX9Plus] in { 447 defm V_DIV_FIXUP_F16_gfx9 : VOP3Inst <"v_div_fixup_f16_gfx9", 448 VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUdiv_fixup>; 449 defm V_FMA_F16_gfx9 : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, any_fma>; 450 } // End renamedInGFX9 = 1, Predicates = [Has16BitInsts, isGFX9Plus] 451} // End FPDPRounding = 1 452 453let SubtargetPredicate = Has16BitInsts, isCommutable = 1 in { 454 455let renamedInGFX9 = 1 in { 456 defm V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>; 457 defm V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>; 458 let FPDPRounding = 1 in { 459 defm V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>; 460 let Uses = [MODE, M0, EXEC] in { 461 let OtherPredicates = [isNotGFX90APlus] in 462 // For some reason the intrinsic operands are in a different order 463 // from the instruction operands. 464 def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>, 465 [(set f16:$vdst, 466 (int_amdgcn_interp_p2_f16 (VOP3Mods f32:$src2, i32:$src2_modifiers), 467 (VOP3Mods f32:$src0, i32:$src0_modifiers), 468 (i32 timm:$attrchan), 469 (i32 timm:$attr), 470 (i1 timm:$high), 471 M0))]>; 472 } // End Uses = [M0, MODE, EXEC] 473 } // End FPDPRounding = 1 474} // End renamedInGFX9 = 1 475 476let SubtargetPredicate = isGFX9Only, FPDPRounding = 1 in { 477 defm V_MAD_F16_gfx9 : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>> ; 478} // End SubtargetPredicate = isGFX9Only, FPDPRounding = 1 479 480let SubtargetPredicate = isGFX9Plus in { 481defm V_MAD_U16_gfx9 : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>; 482defm V_MAD_I16_gfx9 : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>; 483let OtherPredicates = [isNotGFX90APlus] in 484def V_INTERP_P2_F16_gfx9 : VOP3Interp <"v_interp_p2_f16_gfx9", VOP3_INTERP16<[f16, f32, i32, f32]>>; 485} // End SubtargetPredicate = isGFX9Plus 486 487// This predicate should only apply to the selection pattern. The 488// instruction still exists and should decode on subtargets with 489// other bank counts. 490let OtherPredicates = [isNotGFX90APlus, has32BankLDS], Uses = [MODE, M0, EXEC], FPDPRounding = 1 in { 491def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>, 492 [(set f32:$vdst, (int_amdgcn_interp_p1_f16 (VOP3Mods f32:$src0, i32:$src0_modifiers), 493 (i32 timm:$attrchan), 494 (i32 timm:$attr), 495 (i1 timm:$high), M0))]>; 496} // End OtherPredicates = [isNotGFX90APlus, has32BankLDS], Uses = [MODE, M0, EXEC], FPDPRounding = 1 497 498let OtherPredicates = [isNotGFX90APlus], Uses = [MODE, M0, EXEC], FPDPRounding = 1 in { 499def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>; 500} // End OtherPredicates = [isNotGFX90APlus], Uses = [MODE, M0, EXEC], FPDPRounding = 1 501 502} // End SubtargetPredicate = Has16BitInsts, isCommutable = 1 503 504def : GCNPat< 505 (i64 (getDivergentFrag<sext>.ret i16:$src)), 506 (REG_SEQUENCE VReg_64, 507 (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))), sub0, 508 (i32 (COPY_TO_REGCLASS 509 (V_ASHRREV_I32_e32 (S_MOV_B32 (i32 0x1f)), (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))) 510 ), VGPR_32)), sub1) 511>; 512 513let SubtargetPredicate = isGFX8Plus, Uses = [MODE, M0, EXEC], OtherPredicates = [isNotGFX90APlus] in { 514def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>; 515def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>; 516def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>; 517} // End SubtargetPredicate = isGFX8Plus, Uses = [MODE, M0, EXEC], OtherPredicates = [isNotGFX90APlus] 518 519let Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] in { 520 521multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2, 522 Instruction inst, SDPatternOperator op3> { 523def : GCNPat < 524 (op2 (op1 i16:$src0, i16:$src1), i16:$src2), 525 (inst i16:$src0, i16:$src1, i16:$src2, (i1 0)) 526>; 527 528} 529 530defm: Ternary_i16_Pats<mul, add, V_MAD_U16_e64, zext>; 531defm: Ternary_i16_Pats<mul, add, V_MAD_I16_e64, sext>; 532 533} // End Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] 534 535let Predicates = [Has16BitInsts, isGFX10Plus] in { 536 537multiclass Ternary_i16_Pats_gfx9<SDPatternOperator op1, SDPatternOperator op2, 538 Instruction inst, SDPatternOperator op3> { 539def : GCNPat < 540 (op2 (op1 i16:$src0, i16:$src1), i16:$src2), 541 (inst SRCMODS.NONE, $src0, SRCMODS.NONE, $src1, SRCMODS.NONE, $src2, DSTCLAMP.NONE) 542>; 543 544} 545 546defm: Ternary_i16_Pats_gfx9<mul, add, V_MAD_U16_gfx9_e64, zext>; 547defm: Ternary_i16_Pats_gfx9<mul, add, V_MAD_I16_gfx9_e64, sext>; 548 549} // End Predicates = [Has16BitInsts, isGFX10Plus] 550 551class ThreeOpFrag<SDPatternOperator op1, SDPatternOperator op2> : PatFrag< 552 (ops node:$x, node:$y, node:$z), 553 // When the inner operation is used multiple times, selecting 3-op 554 // instructions may still be beneficial -- if the other users can be 555 // combined similarly. Let's be conservative for now. 556 (op2 (HasOneUseBinOp<op1> node:$x, node:$y), node:$z), 557 [{ 558 // Only use VALU ops when the result is divergent. 559 if (!N->isDivergent()) 560 return false; 561 562 // Check constant bus limitations. 563 // 564 // Note: Use !isDivergent as a conservative proxy for whether the value 565 // is in an SGPR (uniform values can end up in VGPRs as well). 566 unsigned ConstantBusUses = 0; 567 for (unsigned i = 0; i < 3; ++i) { 568 if (!Operands[i]->isDivergent() && 569 !isInlineImmediate(Operands[i].getNode())) { 570 ConstantBusUses++; 571 // This uses AMDGPU::V_ADD3_U32_e64, but all three operand instructions 572 // have the same constant bus limit. 573 if (ConstantBusUses > Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64)) 574 return false; 575 } 576 } 577 578 return true; 579 }]> { 580 let PredicateCodeUsesOperands = 1; 581 582 // The divergence predicate is irrelevant in GlobalISel, as we have 583 // proper register bank checks. We just need to verify the constant 584 // bus restriction when all the sources are considered. 585 // 586 // FIXME: With unlucky SGPR operands, we could penalize code by 587 // blocking folding SGPR->VGPR copies later. 588 // FIXME: There's no register bank verifier 589 let GISelPredicateCode = [{ 590 const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64); 591 int ConstantBusUses = 0; 592 for (unsigned i = 0; i < 3; ++i) { 593 const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI); 594 if (RegBank->getID() == AMDGPU::SGPRRegBankID) { 595 if (++ConstantBusUses > ConstantBusLimit) 596 return false; 597 } 598 } 599 return true; 600 }]; 601} 602 603let SubtargetPredicate = isGFX9Plus in { 604let isCommutable = 1 in { 605 defm V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 606 defm V_AND_OR_B32 : VOP3Inst <"v_and_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 607 defm V_OR3_B32 : VOP3Inst <"v_or3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 608 defm V_XAD_U32 : VOP3Inst <"v_xad_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 609 defm V_ADD_I32 : VOP3Inst <"v_add_i32", VOP3_Profile<VOP_I32_I32_I32_ARITH>>; 610 defm V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 611} // End isCommutable = 1 612// TODO src0 contains the opsel bit for dst, so if we commute, need to mask and swap this 613// to the new src0. 614defm V_MED3_F16 : VOP3Inst <"v_med3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmed3>; 615defm V_MED3_I16 : VOP3Inst <"v_med3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmed3>; 616defm V_MED3_U16 : VOP3Inst <"v_med3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumed3>; 617 618defm V_MIN3_F16 : VOP3Inst <"v_min3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmin3>; 619defm V_MIN3_I16 : VOP3Inst <"v_min3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmin3>; 620defm V_MIN3_U16 : VOP3Inst <"v_min3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumin3>; 621 622defm V_MAX3_F16 : VOP3Inst <"v_max3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmax3>; 623defm V_MAX3_I16 : VOP3Inst <"v_max3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmax3>; 624defm V_MAX3_U16 : VOP3Inst <"v_max3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumax3>; 625 626defm V_ADD_I16 : VOP3Inst <"v_add_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>; 627defm V_SUB_I16 : VOP3Inst <"v_sub_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>; 628 629defm V_MAD_U32_U16 : VOP3Inst <"v_mad_u32_u16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>; 630defm V_MAD_I32_I16 : VOP3Inst <"v_mad_i32_i16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>; 631 632defm V_CVT_PKNORM_I16_F16 : VOP3Inst <"v_cvt_pknorm_i16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 633defm V_CVT_PKNORM_U16_F16 : VOP3Inst <"v_cvt_pknorm_u16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 634 635defm V_SUB_I32 : VOP3Inst <"v_sub_i32", VOP3_Profile<VOP_I32_I32_I32_ARITH>>; 636defm V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 637defm V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 638defm V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 639 640 641 642class ThreeOp_i32_Pats <SDPatternOperator op1, SDPatternOperator op2, Instruction inst> : GCNPat < 643 // This matches (op2 (op1 i32:$src0, i32:$src1), i32:$src2) with conditions. 644 (ThreeOpFrag<op1, op2> i32:$src0, i32:$src1, i32:$src2), 645 (inst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2) 646>; 647 648def : ThreeOp_i32_Pats<shl, add, V_LSHL_ADD_U32_e64>; 649def : ThreeOp_i32_Pats<add, shl, V_ADD_LSHL_U32_e64>; 650def : ThreeOp_i32_Pats<add, add, V_ADD3_U32_e64>; 651def : ThreeOp_i32_Pats<shl, or, V_LSHL_OR_B32_e64>; 652def : ThreeOp_i32_Pats<and, or, V_AND_OR_B32_e64>; 653def : ThreeOp_i32_Pats<or, or, V_OR3_B32_e64>; 654def : ThreeOp_i32_Pats<xor, add, V_XAD_U32_e64>; 655 656def : VOPBinOpClampPat<saddsat, V_ADD_I32_e64, i32>; 657def : VOPBinOpClampPat<ssubsat, V_SUB_I32_e64, i32>; 658 659 660// FIXME: Probably should hardcode clamp bit in pseudo and avoid this. 661class OpSelBinOpClampPat<SDPatternOperator node, 662 Instruction inst> : GCNPat< 663 (node (i16 (VOP3OpSel i16:$src0, i32:$src0_modifiers)), 664 (i16 (VOP3OpSel i16:$src1, i32:$src1_modifiers))), 665 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, DSTCLAMP.ENABLE, 0) 666>; 667 668def : OpSelBinOpClampPat<saddsat, V_ADD_I16_e64>; 669def : OpSelBinOpClampPat<ssubsat, V_SUB_I16_e64>; 670} // End SubtargetPredicate = isGFX9Plus 671 672def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3_OPSEL> { 673 let Src0RC64 = VRegSrc_32; 674 let Src1RC64 = SCSrc_b32; 675 let Src2RC64 = SCSrc_b32; 676 let InsVOP3OpSel = (ins IntOpSelMods:$src0_modifiers, VRegSrc_32:$src0, 677 IntOpSelMods:$src1_modifiers, SCSrc_b32:$src1, 678 IntOpSelMods:$src2_modifiers, SCSrc_b32:$src2, 679 VGPR_32:$vdst_in, op_sel0:$op_sel); 680 let HasClamp = 0; 681} 682 683class PermlanePat<SDPatternOperator permlane, 684 Instruction inst> : GCNPat< 685 (permlane i32:$vdst_in, i32:$src0, i32:$src1, i32:$src2, 686 timm:$fi, timm:$bc), 687 (inst (as_i1timm $fi), VGPR_32:$src0, (as_i1timm $bc), 688 SCSrc_b32:$src1, 0, SCSrc_b32:$src2, VGPR_32:$vdst_in) 689>; 690 691// Permlane intrinsic that has either fetch invalid or bound control 692// fields enabled. 693class BoundControlOrFetchInvalidPermlane<SDPatternOperator permlane> : 694 PatFrag<(ops node:$vdst_in, node:$src0, node:$src1, node:$src2, 695 node:$fi, node:$bc), 696 (permlane node:$vdst_in, node:$src0, node: 697 $src1, node:$src2, node:$fi, node:$bc)> { 698 let PredicateCode = [{ return N->getConstantOperandVal(5) != 0 || 699 N->getConstantOperandVal(6) != 0; }]; 700 let GISelPredicateCode = [{ 701 return MI.getOperand(6).getImm() != 0 || 702 MI.getOperand(7).getImm() != 0; 703 }]; 704} 705 706// Drop the input value if it won't be read. 707class PermlaneDiscardVDstIn<SDPatternOperator permlane, 708 Instruction inst> : GCNPat< 709 (permlane srcvalue, i32:$src0, i32:$src1, i32:$src2, 710 timm:$fi, timm:$bc), 711 (inst (as_i1timm $fi), VGPR_32:$src0, (as_i1timm $bc), 712 SCSrc_b32:$src1, 0, SCSrc_b32:$src2, 713 (IMPLICIT_DEF)) 714>; 715 716 717let SubtargetPredicate = isGFX10Plus in { 718 let isCommutable = 1 in { 719 defm V_XOR3_B32 : VOP3Inst <"v_xor3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 720 } // End isCommutable = 1 721 def : ThreeOp_i32_Pats<xor, xor, V_XOR3_B32_e64>; 722 723 let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in { 724 defm V_PERMLANE16_B32 : VOP3Inst<"v_permlane16_b32", VOP3_PERMLANE_Profile>; 725 defm V_PERMLANEX16_B32 : VOP3Inst<"v_permlanex16_b32", VOP3_PERMLANE_Profile>; 726 } // End $vdst = $vdst_in, DisableEncoding $vdst_in 727 728 def : PermlanePat<int_amdgcn_permlane16, V_PERMLANE16_B32_e64>; 729 def : PermlanePat<int_amdgcn_permlanex16, V_PERMLANEX16_B32_e64>; 730 731 def : PermlaneDiscardVDstIn< 732 BoundControlOrFetchInvalidPermlane<int_amdgcn_permlane16>, 733 V_PERMLANE16_B32_e64>; 734 def : PermlaneDiscardVDstIn< 735 BoundControlOrFetchInvalidPermlane<int_amdgcn_permlanex16>, 736 V_PERMLANEX16_B32_e64>; 737} // End SubtargetPredicate = isGFX10Plus 738 739class DivFmasPat<ValueType vt, Instruction inst, Register CondReg> : GCNPat< 740 (AMDGPUdiv_fmas (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)), 741 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), 742 (vt (VOP3Mods vt:$src2, i32:$src2_modifiers)), 743 (i1 CondReg)), 744 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, $src2_modifiers, $src2) 745>; 746 747let WaveSizePredicate = isWave64 in { 748def : DivFmasPat<f32, V_DIV_FMAS_F32_e64, VCC>; 749def : DivFmasPat<f64, V_DIV_FMAS_F64_e64, VCC>; 750} 751 752let WaveSizePredicate = isWave32 in { 753def : DivFmasPat<f32, V_DIV_FMAS_F32_e64, VCC_LO>; 754def : DivFmasPat<f64, V_DIV_FMAS_F64_e64, VCC_LO>; 755} 756 757//===----------------------------------------------------------------------===// 758// Integer Clamp Patterns 759//===----------------------------------------------------------------------===// 760 761class getClampPat<VOPProfile P, SDPatternOperator node> { 762 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2)); 763 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1)); 764 dag ret1 = (P.DstVT (node P.Src0VT:$src0)); 765 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3, 766 !if(!eq(P.NumSrcArgs, 2), ret2, 767 ret1)); 768} 769 770class getClampRes<VOPProfile P, Instruction inst> { 771 dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0)); 772 dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0)); 773 dag ret1 = (inst P.Src0VT:$src0, (i1 0)); 774 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3, 775 !if(!eq(P.NumSrcArgs, 2), ret2, 776 ret1)); 777} 778 779class IntClampPat<VOP3InstBase inst, SDPatternOperator node> : GCNPat< 780 getClampPat<inst.Pfl, node>.ret, 781 getClampRes<inst.Pfl, inst>.ret 782>; 783 784def : IntClampPat<V_MAD_I32_I24_e64, AMDGPUmad_i24>; 785def : IntClampPat<V_MAD_U32_U24_e64, AMDGPUmad_u24>; 786 787def : IntClampPat<V_SAD_U8_e64, int_amdgcn_sad_u8>; 788def : IntClampPat<V_SAD_HI_U8_e64, int_amdgcn_sad_hi_u8>; 789def : IntClampPat<V_SAD_U16_e64, int_amdgcn_sad_u16>; 790 791def : IntClampPat<V_MSAD_U8_e64, int_amdgcn_msad_u8>; 792def : IntClampPat<V_MQSAD_PK_U16_U8_e64, int_amdgcn_mqsad_pk_u16_u8>; 793 794def : IntClampPat<V_QSAD_PK_U16_U8_e64, int_amdgcn_qsad_pk_u16_u8>; 795def : IntClampPat<V_MQSAD_U32_U8_e64, int_amdgcn_mqsad_u32_u8>; 796 797 798//===----------------------------------------------------------------------===// 799// Target-specific instruction encodings. 800//===----------------------------------------------------------------------===// 801 802//===----------------------------------------------------------------------===// 803// GFX10. 804//===----------------------------------------------------------------------===// 805 806let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in { 807 multiclass VOP3_Real_gfx10<bits<10> op> { 808 def _gfx10 : 809 VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 810 VOP3e_gfx10<op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 811 } 812 multiclass VOP3_Real_No_Suffix_gfx10<bits<10> op> { 813 def _gfx10 : 814 VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX10>, 815 VOP3e_gfx10<op, !cast<VOP_Pseudo>(NAME).Pfl>; 816 } 817 multiclass VOP3_Real_gfx10_with_name<bits<10> op, string opName, 818 string asmName> { 819 def _gfx10 : 820 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>, 821 VOP3e_gfx10<op, !cast<VOP3_Pseudo>(opName#"_e64").Pfl> { 822 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64"); 823 let AsmString = asmName # ps.AsmOperands; 824 let IsSingle = 1; 825 } 826 } 827 multiclass VOP3be_Real_gfx10<bits<10> op> { 828 def _gfx10 : 829 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 830 VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 831 } 832 multiclass VOP3Interp_Real_gfx10<bits<10> op> { 833 def _gfx10 : 834 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>, 835 VOP3Interp_gfx10<op, !cast<VOP3_Pseudo>(NAME).Pfl>; 836 } 837 multiclass VOP3OpSel_Real_gfx10<bits<10> op> { 838 def _gfx10 : 839 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 840 VOP3OpSel_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 841 } 842 multiclass VOP3OpSel_Real_gfx10_with_name<bits<10> op, string opName, 843 string asmName> { 844 def _gfx10 : 845 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>, 846 VOP3OpSel_gfx10<op, !cast<VOP3_Pseudo>(opName#"_e64").Pfl> { 847 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64"); 848 let AsmString = asmName # ps.AsmOperands; 849 } 850 } 851} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" 852 853defm V_READLANE_B32 : VOP3_Real_No_Suffix_gfx10<0x360>; 854 855let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in { 856 defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_gfx10<0x361>; 857} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) 858 859let SubtargetPredicate = isGFX10Before1030 in { 860 defm V_MUL_LO_I32 : VOP3_Real_gfx10<0x16b>; 861} 862 863defm V_XOR3_B32 : VOP3_Real_gfx10<0x178>; 864defm V_LSHLREV_B64 : VOP3_Real_gfx10<0x2ff>; 865defm V_LSHRREV_B64 : VOP3_Real_gfx10<0x300>; 866defm V_ASHRREV_I64 : VOP3_Real_gfx10<0x301>; 867defm V_PERM_B32 : VOP3_Real_gfx10<0x344>; 868defm V_XAD_U32 : VOP3_Real_gfx10<0x345>; 869defm V_LSHL_ADD_U32 : VOP3_Real_gfx10<0x346>; 870defm V_ADD_LSHL_U32 : VOP3_Real_gfx10<0x347>; 871defm V_ADD3_U32 : VOP3_Real_gfx10<0x36d>; 872defm V_LSHL_OR_B32 : VOP3_Real_gfx10<0x36f>; 873defm V_AND_OR_B32 : VOP3_Real_gfx10<0x371>; 874defm V_OR3_B32 : VOP3_Real_gfx10<0x372>; 875 876// TODO-GFX10: add MC tests for v_add/sub_nc_i16 877defm V_ADD_NC_I16 : 878 VOP3OpSel_Real_gfx10_with_name<0x30d, "V_ADD_I16", "v_add_nc_i16">; 879defm V_SUB_NC_I16 : 880 VOP3OpSel_Real_gfx10_with_name<0x30e, "V_SUB_I16", "v_sub_nc_i16">; 881defm V_SUB_NC_I32 : 882 VOP3_Real_gfx10_with_name<0x376, "V_SUB_I32", "v_sub_nc_i32">; 883defm V_ADD_NC_I32 : 884 VOP3_Real_gfx10_with_name<0x37f, "V_ADD_I32", "v_add_nc_i32">; 885 886defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_gfx10<0x200>; 887defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_gfx10<0x201>; 888defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_gfx10<0x202>; 889 890defm V_INTERP_P1LL_F16 : VOP3Interp_Real_gfx10<0x342>; 891defm V_INTERP_P1LV_F16 : VOP3Interp_Real_gfx10<0x343>; 892defm V_INTERP_P2_F16 : VOP3Interp_Real_gfx10<0x35a>; 893 894defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx10<0x311>; 895defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx10<0x312>; 896defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx10<0x313>; 897 898defm V_MIN3_F16 : VOP3OpSel_Real_gfx10<0x351>; 899defm V_MIN3_I16 : VOP3OpSel_Real_gfx10<0x352>; 900defm V_MIN3_U16 : VOP3OpSel_Real_gfx10<0x353>; 901defm V_MAX3_F16 : VOP3OpSel_Real_gfx10<0x354>; 902defm V_MAX3_I16 : VOP3OpSel_Real_gfx10<0x355>; 903defm V_MAX3_U16 : VOP3OpSel_Real_gfx10<0x356>; 904defm V_MED3_F16 : VOP3OpSel_Real_gfx10<0x357>; 905defm V_MED3_I16 : VOP3OpSel_Real_gfx10<0x358>; 906defm V_MED3_U16 : VOP3OpSel_Real_gfx10<0x359>; 907defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx10<0x373>; 908defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx10<0x375>; 909 910defm V_MAD_U16 : 911 VOP3OpSel_Real_gfx10_with_name<0x340, "V_MAD_U16_gfx9", "v_mad_u16">; 912defm V_FMA_F16 : 913 VOP3OpSel_Real_gfx10_with_name<0x34b, "V_FMA_F16_gfx9", "v_fma_f16">; 914defm V_MAD_I16 : 915 VOP3OpSel_Real_gfx10_with_name<0x35e, "V_MAD_I16_gfx9", "v_mad_i16">; 916defm V_DIV_FIXUP_F16 : 917 VOP3OpSel_Real_gfx10_with_name<0x35f, "V_DIV_FIXUP_F16_gfx9", "v_div_fixup_f16">; 918 919// FIXME-GFX10-OPSEL: Need to add "selective" opsel support to some of these 920// (they do not support SDWA or DPP). 921defm V_ADD_NC_U16 : VOP3_Real_gfx10_with_name<0x303, "V_ADD_U16", "v_add_nc_u16">; 922defm V_SUB_NC_U16 : VOP3_Real_gfx10_with_name<0x304, "V_SUB_U16", "v_sub_nc_u16">; 923defm V_MUL_LO_U16 : VOP3_Real_gfx10_with_name<0x305, "V_MUL_LO_U16", "v_mul_lo_u16">; 924defm V_LSHRREV_B16 : VOP3_Real_gfx10_with_name<0x307, "V_LSHRREV_B16", "v_lshrrev_b16">; 925defm V_ASHRREV_I16 : VOP3_Real_gfx10_with_name<0x308, "V_ASHRREV_I16", "v_ashrrev_i16">; 926defm V_MAX_U16 : VOP3_Real_gfx10_with_name<0x309, "V_MAX_U16", "v_max_u16">; 927defm V_MAX_I16 : VOP3_Real_gfx10_with_name<0x30a, "V_MAX_I16", "v_max_i16">; 928defm V_MIN_U16 : VOP3_Real_gfx10_with_name<0x30b, "V_MIN_U16", "v_min_u16">; 929defm V_MIN_I16 : VOP3_Real_gfx10_with_name<0x30c, "V_MIN_I16", "v_min_i16">; 930defm V_LSHLREV_B16 : VOP3_Real_gfx10_with_name<0x314, "V_LSHLREV_B16", "v_lshlrev_b16">; 931defm V_PERMLANE16_B32 : VOP3OpSel_Real_gfx10<0x377>; 932defm V_PERMLANEX16_B32 : VOP3OpSel_Real_gfx10<0x378>; 933 934//===----------------------------------------------------------------------===// 935// GFX7, GFX10. 936//===----------------------------------------------------------------------===// 937 938let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in { 939 multiclass VOP3_Real_gfx7<bits<10> op> { 940 def _gfx7 : 941 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 942 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 943 } 944 multiclass VOP3be_Real_gfx7<bits<10> op> { 945 def _gfx7 : 946 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 947 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 948 } 949} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" 950 951multiclass VOP3_Real_gfx7_gfx10<bits<10> op> : 952 VOP3_Real_gfx7<op>, VOP3_Real_gfx10<op>; 953 954multiclass VOP3be_Real_gfx7_gfx10<bits<10> op> : 955 VOP3be_Real_gfx7<op>, VOP3be_Real_gfx10<op>; 956 957defm V_QSAD_PK_U16_U8 : VOP3_Real_gfx7_gfx10<0x172>; 958defm V_MQSAD_U32_U8 : VOP3_Real_gfx7_gfx10<0x175>; 959defm V_MAD_U64_U32 : VOP3be_Real_gfx7_gfx10<0x176>; 960defm V_MAD_I64_I32 : VOP3be_Real_gfx7_gfx10<0x177>; 961 962//===----------------------------------------------------------------------===// 963// GFX6, GFX7, GFX10. 964//===----------------------------------------------------------------------===// 965 966let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in { 967 multiclass VOP3_Real_gfx6_gfx7<bits<10> op> { 968 def _gfx6_gfx7 : 969 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 970 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 971 } 972 multiclass VOP3be_Real_gfx6_gfx7<bits<10> op> { 973 def _gfx6_gfx7 : 974 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 975 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 976 } 977} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" 978 979multiclass VOP3_Real_gfx6_gfx7_gfx10<bits<10> op> : 980 VOP3_Real_gfx6_gfx7<op>, VOP3_Real_gfx10<op>; 981 982multiclass VOP3be_Real_gfx6_gfx7_gfx10<bits<10> op> : 983 VOP3be_Real_gfx6_gfx7<op>, VOP3be_Real_gfx10<op>; 984 985defm V_LSHL_B64 : VOP3_Real_gfx6_gfx7<0x161>; 986defm V_LSHR_B64 : VOP3_Real_gfx6_gfx7<0x162>; 987defm V_ASHR_I64 : VOP3_Real_gfx6_gfx7<0x163>; 988defm V_MUL_LO_I32 : VOP3_Real_gfx6_gfx7<0x16b>; 989 990defm V_MAD_LEGACY_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x140>; 991defm V_MAD_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x141>; 992defm V_MAD_I32_I24 : VOP3_Real_gfx6_gfx7_gfx10<0x142>; 993defm V_MAD_U32_U24 : VOP3_Real_gfx6_gfx7_gfx10<0x143>; 994defm V_CUBEID_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x144>; 995defm V_CUBESC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x145>; 996defm V_CUBETC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x146>; 997defm V_CUBEMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x147>; 998defm V_BFE_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x148>; 999defm V_BFE_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x149>; 1000defm V_BFI_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14a>; 1001defm V_FMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x14b>; 1002defm V_FMA_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x14c>; 1003defm V_LERP_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x14d>; 1004defm V_ALIGNBIT_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14e>; 1005defm V_ALIGNBYTE_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14f>; 1006defm V_MULLIT_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x150>; 1007defm V_MIN3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x151>; 1008defm V_MIN3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x152>; 1009defm V_MIN3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x153>; 1010defm V_MAX3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x154>; 1011defm V_MAX3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x155>; 1012defm V_MAX3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x156>; 1013defm V_MED3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x157>; 1014defm V_MED3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x158>; 1015defm V_MED3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x159>; 1016defm V_SAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15a>; 1017defm V_SAD_HI_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15b>; 1018defm V_SAD_U16 : VOP3_Real_gfx6_gfx7_gfx10<0x15c>; 1019defm V_SAD_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x15d>; 1020defm V_CVT_PK_U8_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15e>; 1021defm V_DIV_FIXUP_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15f>; 1022defm V_DIV_FIXUP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x160>; 1023defm V_ADD_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x164>; 1024defm V_MUL_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x165>; 1025defm V_MIN_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x166>; 1026defm V_MAX_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x167>; 1027defm V_LDEXP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x168>; 1028defm V_MUL_LO_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x169>; 1029defm V_MUL_HI_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x16a>; 1030defm V_MUL_HI_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x16c>; 1031defm V_DIV_FMAS_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x16f>; 1032defm V_DIV_FMAS_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x170>; 1033defm V_MSAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x171>; 1034defm V_MQSAD_PK_U16_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x173>; 1035defm V_TRIG_PREOP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x174>; 1036defm V_DIV_SCALE_F32 : VOP3be_Real_gfx6_gfx7_gfx10<0x16d>; 1037defm V_DIV_SCALE_F64 : VOP3be_Real_gfx6_gfx7_gfx10<0x16e>; 1038 1039// NB: Same opcode as v_mad_legacy_f32 1040let DecoderNamespace = "GFX10_B" in 1041defm V_FMA_LEGACY_F32 : VOP3_Real_gfx10<0x140>; 1042 1043//===----------------------------------------------------------------------===// 1044// GFX8, GFX9 (VI). 1045//===----------------------------------------------------------------------===// 1046 1047let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in { 1048 1049multiclass VOP3_Real_vi<bits<10> op> { 1050 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1051 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 1052} 1053multiclass VOP3_Real_No_Suffix_vi<bits<10> op> { 1054 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 1055 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>; 1056} 1057 1058multiclass VOP3be_Real_vi<bits<10> op> { 1059 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1060 VOP3be_vi <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 1061} 1062 1063multiclass VOP3OpSel_Real_gfx9<bits<10> op> { 1064 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1065 VOP3OpSel_gfx9 <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 1066} 1067 1068multiclass VOP3Interp_Real_vi<bits<10> op> { 1069 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 1070 VOP3Interp_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>; 1071} 1072 1073} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" 1074 1075let AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" in { 1076 1077multiclass VOP3_F16_Real_vi<bits<10> op> { 1078 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1079 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1080} 1081 1082multiclass VOP3Interp_F16_Real_vi<bits<10> op> { 1083 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>, 1084 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>; 1085} 1086 1087} // End AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" 1088 1089let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in { 1090 1091multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> { 1092 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>, 1093 VOP3e_vi <op, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> { 1094 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64"); 1095 let AsmString = AsmName # ps.AsmOperands; 1096 } 1097} 1098 1099multiclass VOP3OpSel_F16_Real_gfx9<bits<10> op, string AsmName> { 1100 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>, 1101 VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1102 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME#"_e64"); 1103 let AsmString = AsmName # ps.AsmOperands; 1104 } 1105} 1106 1107multiclass VOP3Interp_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> { 1108 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>, 1109 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> { 1110 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName); 1111 let AsmString = AsmName # ps.AsmOperands; 1112 } 1113} 1114 1115multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> { 1116 def _gfx9 : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>, 1117 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl> { 1118 VOP_Pseudo ps = !cast<VOP_Pseudo>(NAME#"_e64"); 1119 let AsmString = AsmName # ps.AsmOperands; 1120 } 1121} 1122 1123} // End AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" 1124 1125defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>; 1126defm V_MAD_I64_I32 : VOP3be_Real_vi <0x1E9>; 1127 1128defm V_MAD_LEGACY_F32 : VOP3_Real_vi <0x1c0>; 1129defm V_MAD_F32 : VOP3_Real_vi <0x1c1>; 1130defm V_MAD_I32_I24 : VOP3_Real_vi <0x1c2>; 1131defm V_MAD_U32_U24 : VOP3_Real_vi <0x1c3>; 1132defm V_CUBEID_F32 : VOP3_Real_vi <0x1c4>; 1133defm V_CUBESC_F32 : VOP3_Real_vi <0x1c5>; 1134defm V_CUBETC_F32 : VOP3_Real_vi <0x1c6>; 1135defm V_CUBEMA_F32 : VOP3_Real_vi <0x1c7>; 1136defm V_BFE_U32 : VOP3_Real_vi <0x1c8>; 1137defm V_BFE_I32 : VOP3_Real_vi <0x1c9>; 1138defm V_BFI_B32 : VOP3_Real_vi <0x1ca>; 1139defm V_FMA_F32 : VOP3_Real_vi <0x1cb>; 1140defm V_FMA_F64 : VOP3_Real_vi <0x1cc>; 1141defm V_LERP_U8 : VOP3_Real_vi <0x1cd>; 1142defm V_ALIGNBIT_B32 : VOP3_Real_vi <0x1ce>; 1143defm V_ALIGNBYTE_B32 : VOP3_Real_vi <0x1cf>; 1144defm V_MIN3_F32 : VOP3_Real_vi <0x1d0>; 1145defm V_MIN3_I32 : VOP3_Real_vi <0x1d1>; 1146defm V_MIN3_U32 : VOP3_Real_vi <0x1d2>; 1147defm V_MAX3_F32 : VOP3_Real_vi <0x1d3>; 1148defm V_MAX3_I32 : VOP3_Real_vi <0x1d4>; 1149defm V_MAX3_U32 : VOP3_Real_vi <0x1d5>; 1150defm V_MED3_F32 : VOP3_Real_vi <0x1d6>; 1151defm V_MED3_I32 : VOP3_Real_vi <0x1d7>; 1152defm V_MED3_U32 : VOP3_Real_vi <0x1d8>; 1153defm V_SAD_U8 : VOP3_Real_vi <0x1d9>; 1154defm V_SAD_HI_U8 : VOP3_Real_vi <0x1da>; 1155defm V_SAD_U16 : VOP3_Real_vi <0x1db>; 1156defm V_SAD_U32 : VOP3_Real_vi <0x1dc>; 1157defm V_CVT_PK_U8_F32 : VOP3_Real_vi <0x1dd>; 1158defm V_DIV_FIXUP_F32 : VOP3_Real_vi <0x1de>; 1159defm V_DIV_FIXUP_F64 : VOP3_Real_vi <0x1df>; 1160defm V_DIV_SCALE_F32 : VOP3be_Real_vi <0x1e0>; 1161defm V_DIV_SCALE_F64 : VOP3be_Real_vi <0x1e1>; 1162defm V_DIV_FMAS_F32 : VOP3_Real_vi <0x1e2>; 1163defm V_DIV_FMAS_F64 : VOP3_Real_vi <0x1e3>; 1164defm V_MSAD_U8 : VOP3_Real_vi <0x1e4>; 1165defm V_QSAD_PK_U16_U8 : VOP3_Real_vi <0x1e5>; 1166defm V_MQSAD_PK_U16_U8 : VOP3_Real_vi <0x1e6>; 1167defm V_MQSAD_U32_U8 : VOP3_Real_vi <0x1e7>; 1168 1169defm V_PERM_B32 : VOP3_Real_vi <0x1ed>; 1170 1171defm V_MAD_F16 : VOP3_F16_Real_vi <0x1ea>; 1172defm V_MAD_U16 : VOP3_F16_Real_vi <0x1eb>; 1173defm V_MAD_I16 : VOP3_F16_Real_vi <0x1ec>; 1174defm V_FMA_F16 : VOP3_F16_Real_vi <0x1ee>; 1175defm V_DIV_FIXUP_F16 : VOP3_F16_Real_vi <0x1ef>; 1176defm V_INTERP_P2_F16 : VOP3Interp_F16_Real_vi <0x276>; 1177 1178let FPDPRounding = 1 in { 1179defm V_MAD_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16", "v_mad_legacy_f16">; 1180defm V_FMA_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16", "v_fma_legacy_f16">; 1181defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16">; 1182defm V_INTERP_P2_LEGACY_F16 : VOP3Interp_F16_Real_gfx9 <0x276, "V_INTERP_P2_F16", "v_interp_p2_legacy_f16">; 1183} // End FPDPRounding = 1 1184 1185defm V_MAD_LEGACY_U16 : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16", "v_mad_legacy_u16">; 1186defm V_MAD_LEGACY_I16 : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16", "v_mad_legacy_i16">; 1187 1188defm V_MAD_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">; 1189defm V_MAD_U16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">; 1190defm V_MAD_I16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">; 1191defm V_FMA_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x206, "v_fma_f16">; 1192defm V_DIV_FIXUP_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">; 1193defm V_INTERP_P2_F16_gfx9 : VOP3Interp_F16_Real_gfx9 <0x277, "V_INTERP_P2_F16_gfx9", "v_interp_p2_f16">; 1194 1195defm V_ADD_I32 : VOP3_Real_vi <0x29c>; 1196defm V_SUB_I32 : VOP3_Real_vi <0x29d>; 1197 1198defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_vi <0x270>; 1199defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_vi <0x271>; 1200defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>; 1201 1202defm V_INTERP_P1LL_F16 : VOP3Interp_Real_vi <0x274>; 1203defm V_INTERP_P1LV_F16 : VOP3Interp_Real_vi <0x275>; 1204defm V_ADD_F64 : VOP3_Real_vi <0x280>; 1205defm V_MUL_F64 : VOP3_Real_vi <0x281>; 1206defm V_MIN_F64 : VOP3_Real_vi <0x282>; 1207defm V_MAX_F64 : VOP3_Real_vi <0x283>; 1208defm V_LDEXP_F64 : VOP3_Real_vi <0x284>; 1209defm V_MUL_LO_U32 : VOP3_Real_vi <0x285>; 1210 1211// removed from VI as identical to V_MUL_LO_U32 1212let isAsmParserOnly = 1 in { 1213defm V_MUL_LO_I32 : VOP3_Real_vi <0x285>; 1214} 1215 1216defm V_MUL_HI_U32 : VOP3_Real_vi <0x286>; 1217defm V_MUL_HI_I32 : VOP3_Real_vi <0x287>; 1218 1219defm V_READLANE_B32 : VOP3_Real_No_Suffix_vi <0x289>; 1220defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_vi <0x28a>; 1221 1222defm V_LSHLREV_B64 : VOP3_Real_vi <0x28f>; 1223defm V_LSHRREV_B64 : VOP3_Real_vi <0x290>; 1224defm V_ASHRREV_I64 : VOP3_Real_vi <0x291>; 1225defm V_TRIG_PREOP_F64 : VOP3_Real_vi <0x292>; 1226 1227defm V_LSHL_ADD_U32 : VOP3_Real_vi <0x1fd>; 1228defm V_ADD_LSHL_U32 : VOP3_Real_vi <0x1fe>; 1229defm V_ADD3_U32 : VOP3_Real_vi <0x1ff>; 1230defm V_LSHL_OR_B32 : VOP3_Real_vi <0x200>; 1231defm V_AND_OR_B32 : VOP3_Real_vi <0x201>; 1232defm V_OR3_B32 : VOP3_Real_vi <0x202>; 1233defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx9 <0x2a0>; 1234 1235defm V_XAD_U32 : VOP3_Real_vi <0x1f3>; 1236 1237defm V_MIN3_F16 : VOP3OpSel_Real_gfx9 <0x1f4>; 1238defm V_MIN3_I16 : VOP3OpSel_Real_gfx9 <0x1f5>; 1239defm V_MIN3_U16 : VOP3OpSel_Real_gfx9 <0x1f6>; 1240 1241defm V_MAX3_F16 : VOP3OpSel_Real_gfx9 <0x1f7>; 1242defm V_MAX3_I16 : VOP3OpSel_Real_gfx9 <0x1f8>; 1243defm V_MAX3_U16 : VOP3OpSel_Real_gfx9 <0x1f9>; 1244 1245defm V_MED3_F16 : VOP3OpSel_Real_gfx9 <0x1fa>; 1246defm V_MED3_I16 : VOP3OpSel_Real_gfx9 <0x1fb>; 1247defm V_MED3_U16 : VOP3OpSel_Real_gfx9 <0x1fc>; 1248 1249defm V_ADD_I16 : VOP3OpSel_Real_gfx9 <0x29e>; 1250defm V_SUB_I16 : VOP3OpSel_Real_gfx9 <0x29f>; 1251 1252defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx9 <0x1f1>; 1253defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx9 <0x1f2>; 1254 1255defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx9 <0x299>; 1256defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx9 <0x29a>; 1257