1//===-- VOP3Instructions.td - Vector Instruction Definitions --------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// VOP3 Classes 11//===----------------------------------------------------------------------===// 12 13class getVOP3ModPat<VOPProfile P, SDPatternOperator node> { 14 dag src0 = !if(P.HasOMod, 15 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 16 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)); 17 18 list<dag> ret3 = [(set P.DstVT:$vdst, 19 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 20 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), 21 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))]; 22 23 list<dag> ret2 = [(set P.DstVT:$vdst, 24 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 25 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))]; 26 27 list<dag> ret1 = [(set P.DstVT:$vdst, 28 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))]; 29 30 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 31 !if(!eq(P.NumSrcArgs, 2), ret2, 32 ret1)); 33} 34 35class getVOP3PModPat<VOPProfile P, SDPatternOperator node, bit HasExplicitClamp, 36 bit IsDOT = 0, 37 ComplexPattern SrcPat = !if(IsDOT, VOP3PModsDOT, VOP3PMods)> { 38 dag src0_dag = (P.Src0VT (SrcPat P.Src0VT:$src0, i32:$src0_modifiers)); 39 dag src1_dag = (P.Src1VT (SrcPat P.Src1VT:$src1, i32:$src1_modifiers)); 40 dag src2_dag = (P.Src2VT (SrcPat P.Src2VT:$src2, i32:$src2_modifiers)); 41 dag clamp_dag = (i1 timm:$clamp); 42 43 list<dag> ret3 = [(set P.DstVT:$vdst, 44 !if(HasExplicitClamp, 45 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, src2_dag, clamp_dag), 46 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, src2_dag)))]; 47 48 list<dag> ret2 = [(set P.DstVT:$vdst, 49 !if(HasExplicitClamp, 50 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, clamp_dag), 51 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag)))]; 52 53 list<dag> ret1 = [(set P.DstVT:$vdst, 54 !if(HasExplicitClamp, 55 (DivergentFragOrOp<node, P>.ret src0_dag, clamp_dag), 56 (DivergentFragOrOp<node, P>.ret src0_dag)))]; 57 58 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 59 !if(!eq(P.NumSrcArgs, 2), ret2, 60 ret1)); 61} 62 63class getVOP3OpSelPat<VOPProfile P, SDPatternOperator node> { 64 list<dag> ret3 = [(set P.DstVT:$vdst, 65 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)), 66 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)), 67 (P.Src2VT (VOP3OpSel P.Src2VT:$src2, i32:$src2_modifiers))))]; 68 69 list<dag> ret2 = [(set P.DstVT:$vdst, 70 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)), 71 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))]; 72 73 list<dag> ret1 = [(set P.DstVT:$vdst, 74 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))))]; 75 76 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 77 !if(!eq(P.NumSrcArgs, 2), ret2, 78 ret1)); 79} 80 81class getVOP3OpSelModPat<VOPProfile P, SDPatternOperator node> { 82 list<dag> ret3 = [(set P.DstVT:$vdst, 83 (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers), 84 (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 85 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)), 86 (P.Src2VT (VOP3OpSelMods P.Src2VT:$src2, i32:$src2_modifiers))))]; 87 88 list<dag> ret2 = [(set P.DstVT:$vdst, 89 (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers)), 90 (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 91 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))]; 92 93 list<dag> ret1 = [(set P.DstVT:$vdst, 94 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))))]; 95 96 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 97 !if(!eq(P.NumSrcArgs, 2), ret2, 98 ret1)); 99} 100 101class getVOP3Pat<VOPProfile P, SDPatternOperator node> { 102 list<dag> ret3 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))]; 103 list<dag> ret2 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$src1))]; 104 list<dag> ret1 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0))]; 105 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 106 !if(!eq(P.NumSrcArgs, 2), ret2, 107 ret1)); 108} 109 110class getVOP3ClampPat<VOPProfile P, SDPatternOperator node> { 111 list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i1:$clamp))]; 112 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))]; 113 list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, i1:$clamp))]; 114 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 115 !if(!eq(P.NumSrcArgs, 2), ret2, 116 ret1)); 117} 118 119class getVOP3MAIPat<VOPProfile P, SDPatternOperator node> { 120 list<dag> ret = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, 121 timm:$cbsz, timm:$abid, timm:$blgp))]; 122} 123 124// Consistently gives instructions a _e64 suffix. 125multiclass VOP3Inst_Pseudo_Wrapper<string opName, VOPProfile P, list<dag> pattern = []> { 126 def _e64 : VOP3_Pseudo<opName, P, pattern>; 127} 128 129class VOP3InstBase<string OpName, VOPProfile P, SDPatternOperator node = null_frag> : 130 VOP3_Pseudo<OpName, P, 131 !if(P.HasOpSel, 132 !if(P.HasModifiers, 133 getVOP3OpSelModPat<P, node>.ret, 134 getVOP3OpSelPat<P, node>.ret), 135 !if(P.HasModifiers, 136 getVOP3ModPat<P, node>.ret, 137 !if(P.HasIntClamp, 138 getVOP3ClampPat<P, node>.ret, 139 !if (P.IsMAI, 140 getVOP3MAIPat<P, node>.ret, 141 getVOP3Pat<P, node>.ret)))), 142 0, P.HasOpSel> { 143 144 let IntClamp = P.HasIntClamp; 145 let AsmMatchConverter = 146 !if(P.HasOpSel, 147 "cvtVOP3OpSel", 148 !if(!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), 149 "cvtVOP3", 150 "")); 151} 152 153multiclass VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> { 154 def _e64 : VOP3InstBase<OpName, P, node>; 155} 156 157// Special case for v_div_fmas_{f32|f64}, since it seems to be the 158// only VOP instruction that implicitly reads VCC. 159let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in { 160def VOP_F32_F32_F32_F32_VCC : VOPProfile<[f32, f32, f32, f32]> { 161 let Outs64 = (outs DstRC.RegClass:$vdst); 162} 163def VOP_F64_F64_F64_F64_VCC : VOPProfile<[f64, f64, f64, f64]> { 164 let Outs64 = (outs DstRC.RegClass:$vdst); 165} 166} 167 168class VOP3Features<bit Clamp, bit OpSel, bit Packed, bit MAI> { 169 bit HasClamp = Clamp; 170 bit HasOpSel = OpSel; 171 bit IsPacked = Packed; 172 bit IsMAI = MAI; 173} 174 175def VOP3_REGULAR : VOP3Features<0, 0, 0, 0>; 176def VOP3_CLAMP : VOP3Features<1, 0, 0, 0>; 177def VOP3_OPSEL : VOP3Features<1, 1, 0, 0>; 178def VOP3_PACKED : VOP3Features<1, 1, 1, 0>; 179def VOP3_MAI : VOP3Features<0, 0, 0, 1>; 180 181class VOP3_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOPProfile<P.ArgVT> { 182 183 let HasClamp = !if(Features.HasClamp, 1, P.HasClamp); 184 let HasOpSel = !if(Features.HasOpSel, 1, P.HasOpSel); 185 let IsMAI = !if(Features.IsMAI, 1, P.IsMAI); 186 let IsPacked = !if(Features.IsPacked, 1, P.IsPacked); 187 188 let HasModifiers = !if(Features.IsMAI, 0, !or(Features.IsPacked, P.HasModifiers)); 189 let IsSingle = 1; 190} 191 192class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> { 193 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 194 let Asm64 = "$vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod"; 195 let IsSingle = 1; 196} 197 198def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32>; 199def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64>; 200 201def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> { 202 let HasClamp = 1; 203 let IsSingle = 1; 204 205 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 206 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp"; 207} 208 209//===----------------------------------------------------------------------===// 210// VOP3 INTERP 211//===----------------------------------------------------------------------===// 212 213class VOP3Interp<string OpName, VOPProfile P, list<dag> pattern = []> : 214 VOP3_Pseudo<OpName, P, pattern> { 215 let AsmMatchConverter = "cvtVOP3Interp"; 216 let mayRaiseFPException = 0; 217} 218 219def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> { 220 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 221 Attr:$attr, AttrChan:$attrchan, 222 clampmod0:$clamp, omod0:$omod); 223 224 let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod"; 225} 226 227def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> { 228 let Ins64 = (ins InterpSlot:$src0, 229 Attr:$attr, AttrChan:$attrchan, 230 clampmod0:$clamp, omod0:$omod); 231 232 let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod"; 233 234 let HasClamp = 1; 235 let HasSrc0Mods = 0; 236} 237 238class getInterp16Asm <bit HasSrc2, bit HasOMod> { 239 string src2 = !if(HasSrc2, ", $src2_modifiers", ""); 240 string omod = !if(HasOMod, "$omod", ""); 241 string ret = 242 " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod; 243} 244 245class getInterp16Ins <bit HasSrc2, bit HasOMod, 246 Operand Src0Mod, Operand Src2Mod> { 247 dag ret = !if(HasSrc2, 248 !if(HasOMod, 249 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 250 Attr:$attr, AttrChan:$attrchan, 251 Src2Mod:$src2_modifiers, VRegSrc_32:$src2, 252 highmod:$high, clampmod0:$clamp, omod0:$omod), 253 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 254 Attr:$attr, AttrChan:$attrchan, 255 Src2Mod:$src2_modifiers, VRegSrc_32:$src2, 256 highmod:$high, clampmod0:$clamp) 257 ), 258 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 259 Attr:$attr, AttrChan:$attrchan, 260 highmod:$high, clampmod0:$clamp, omod0:$omod) 261 ); 262} 263 264class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> { 265 266 let HasOMod = !ne(DstVT.Value, f16.Value); 267 let HasHigh = 1; 268 269 let Outs64 = (outs DstRC.RegClass:$vdst); 270 let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret; 271 let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret; 272} 273 274//===----------------------------------------------------------------------===// 275// VOP3 Instructions 276//===----------------------------------------------------------------------===// 277 278let isCommutable = 1 in { 279 280let isReMaterializable = 1 in { 281let mayRaiseFPException = 0 in { 282let SubtargetPredicate = HasMadMacF32Insts in { 283defm V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 284defm V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fmad>; 285} // End SubtargetPredicate = HasMadMacInsts 286 287let SubtargetPredicate = HasFmaLegacy32 in 288defm V_FMA_LEGACY_F32 : VOP3Inst <"v_fma_legacy_f32", 289 VOP3_Profile<VOP_F32_F32_F32_F32>, 290 int_amdgcn_fma_legacy>; 291} 292 293defm V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 294defm V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 295defm V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, any_fma>; 296defm V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>; 297 298let SchedRW = [WriteDoubleAdd] in { 299let FPDPRounding = 1 in { 300defm V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, any_fma>; 301defm V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, any_fadd>; 302defm V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, fmul>; 303} // End FPDPRounding = 1 304defm V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum_like>; 305defm V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum_like>; 306} // End SchedRW = [WriteDoubleAdd] 307 308let SchedRW = [WriteIntMul] in { 309defm V_MUL_LO_U32 : VOP3Inst <"v_mul_lo_u32", VOP3_Profile<VOP_I32_I32_I32>, DivergentBinFrag<mul>>; 310defm V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", VOP3_Profile<VOP_I32_I32_I32>, mulhu>; 311defm V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", VOP3_Profile<VOP_I32_I32_I32>>; 312defm V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", VOP3_Profile<VOP_I32_I32_I32>, mulhs>; 313} // End SchedRW = [WriteIntMul] 314} // End isReMaterializable = 1 315 316let Uses = [MODE, VCC, EXEC] in { 317// v_div_fmas_f32: 318// result = src0 * src1 + src2 319// if (vcc) 320// result *= 2^32 321// 322let SchedRW = [WriteFloatFMA] in 323defm V_DIV_FMAS_F32 : VOP3Inst_Pseudo_Wrapper <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC, []>; 324// v_div_fmas_f64: 325// result = src0 * src1 + src2 326// if (vcc) 327// result *= 2^64 328// 329let SchedRW = [WriteDouble], FPDPRounding = 1 in 330defm V_DIV_FMAS_F64 : VOP3Inst_Pseudo_Wrapper <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC, []>; 331} // End Uses = [MODE, VCC, EXEC] 332 333} // End isCommutable = 1 334 335let isReMaterializable = 1 in { 336let mayRaiseFPException = 0 in { 337defm V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubeid>; 338defm V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubesc>; 339defm V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubetc>; 340defm V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubema>; 341} // End mayRaiseFPException 342 343defm V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>; 344defm V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>; 345defm V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>; 346defm V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, fshr>; 347defm V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>; 348 349// XXX - No FPException seems suspect but manual doesn't say it does 350let mayRaiseFPException = 0 in { 351 let isCommutable = 1 in { 352 defm V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>; 353 defm V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>; 354 defm V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>; 355 defm V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>; 356 defm V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>; 357 defm V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>; 358 } // End isCommutable = 1 359 defm V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmin3>; 360 defm V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>; 361 defm V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>; 362} // End mayRaiseFPException = 0 363 364let isCommutable = 1 in { 365 defm V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 366 defm V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 367 defm V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 368 defm V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 369} // End isCommutable = 1 370defm V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>; 371 372defm V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUdiv_fixup>; 373 374let SchedRW = [WriteDoubleAdd], FPDPRounding = 1 in { 375 defm V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>; 376 defm V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp>; 377} // End SchedRW = [WriteDoubleAdd], FPDPRounding = 1 378} // End isReMaterializable = 1 379 380 381let mayRaiseFPException = 0 in { // Seems suspicious but manual doesn't say it does. 382 let SchedRW = [WriteFloatFMA, WriteSALU] in 383 defm V_DIV_SCALE_F32 : VOP3Inst_Pseudo_Wrapper <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32> ; 384 385 // Double precision division pre-scale. 386 let SchedRW = [WriteDouble, WriteSALU], FPDPRounding = 1 in 387 defm V_DIV_SCALE_F64 : VOP3Inst_Pseudo_Wrapper <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64>; 388} // End mayRaiseFPException = 0 389 390let isReMaterializable = 1 in 391defm V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 392 393let Constraints = "@earlyclobber $vdst" in { 394defm V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>; 395} // End Constraints = "@earlyclobber $vdst" 396 397 398let isReMaterializable = 1 in { 399let SchedRW = [WriteDouble] in { 400defm V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, int_amdgcn_trig_preop>; 401} // End SchedRW = [WriteDouble] 402 403let SchedRW = [Write64Bit] in { 404 let SubtargetPredicate = isGFX6GFX7 in { 405 defm V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>, cshl_64>; 406 defm V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>, csrl_64>; 407 defm V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>, csra_64>; 408 } // End SubtargetPredicate = isGFX6GFX7 409 410 let SubtargetPredicate = isGFX8Plus in { 411 defm V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>, clshl_rev_64>; 412 defm V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>, clshr_rev_64>; 413 defm V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, cashr_rev_64>; 414 } // End SubtargetPredicate = isGFX8Plus 415} // End SchedRW = [Write64Bit] 416} // End isReMaterializable = 1 417 418def : GCNPat< 419 (i32 (getDivergentFrag<sext>.ret i16:$src)), 420 (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))) 421>; 422 423let isReMaterializable = 1 in { 424let SubtargetPredicate = isGFX6GFX7GFX10 in { 425defm V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 426} // End SubtargetPredicate = isGFX6GFX7GFX10 427 428let SchedRW = [Write32Bit] in { 429let SubtargetPredicate = isGFX8Plus in { 430defm V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUperm>; 431} // End SubtargetPredicate = isGFX8Plus 432} // End SchedRW = [Write32Bit] 433} // End isReMaterializable = 1 434 435let SubtargetPredicate = isGFX7Plus in { 436 437let Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] in { 438defm V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>; 439defm V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_V4I32, VOP3_CLAMP>>; 440} // End Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] 441 442let isCommutable = 1 in { 443let SchedRW = [WriteIntMul, WriteSALU] in { 444defm V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>; 445defm V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>; 446} // End SchedRW = [WriteIntMul, WriteSALU] 447} // End isCommutable = 1 448 449} // End SubtargetPredicate = isGFX7Plus 450 451let FPDPRounding = 1 in { 452 let Predicates = [Has16BitInsts, isGFX8Only] in { 453 defm V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>; 454 defm V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, any_fma>; 455 } // End Predicates = [Has16BitInsts, isGFX8Only] 456 457 let renamedInGFX9 = 1, Predicates = [Has16BitInsts, isGFX9Plus] in { 458 defm V_DIV_FIXUP_F16_gfx9 : VOP3Inst <"v_div_fixup_f16_gfx9", 459 VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUdiv_fixup>; 460 defm V_FMA_F16_gfx9 : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, any_fma>; 461 } // End renamedInGFX9 = 1, Predicates = [Has16BitInsts, isGFX9Plus] 462} // End FPDPRounding = 1 463 464let SubtargetPredicate = Has16BitInsts, isCommutable = 1 in { 465 466let renamedInGFX9 = 1 in { 467 defm V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>; 468 defm V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>; 469 let FPDPRounding = 1 in { 470 defm V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>; 471 let Uses = [MODE, M0, EXEC] in { 472 let OtherPredicates = [isNotGFX90APlus] in 473 // For some reason the intrinsic operands are in a different order 474 // from the instruction operands. 475 def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>, 476 [(set f16:$vdst, 477 (int_amdgcn_interp_p2_f16 (VOP3Mods f32:$src2, i32:$src2_modifiers), 478 (VOP3Mods f32:$src0, i32:$src0_modifiers), 479 (i32 timm:$attrchan), 480 (i32 timm:$attr), 481 (i1 timm:$high), 482 M0))]>; 483 } // End Uses = [M0, MODE, EXEC] 484 } // End FPDPRounding = 1 485} // End renamedInGFX9 = 1 486 487let SubtargetPredicate = isGFX9Only, FPDPRounding = 1 in { 488 defm V_MAD_F16_gfx9 : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>> ; 489} // End SubtargetPredicate = isGFX9Only, FPDPRounding = 1 490 491let SubtargetPredicate = isGFX9Plus in { 492defm V_MAD_U16_gfx9 : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>; 493defm V_MAD_I16_gfx9 : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>; 494let OtherPredicates = [isNotGFX90APlus] in 495def V_INTERP_P2_F16_gfx9 : VOP3Interp <"v_interp_p2_f16_gfx9", VOP3_INTERP16<[f16, f32, i32, f32]>>; 496} // End SubtargetPredicate = isGFX9Plus 497 498// This predicate should only apply to the selection pattern. The 499// instruction still exists and should decode on subtargets with 500// other bank counts. 501let OtherPredicates = [isNotGFX90APlus, has32BankLDS], Uses = [MODE, M0, EXEC], FPDPRounding = 1 in { 502def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>, 503 [(set f32:$vdst, (int_amdgcn_interp_p1_f16 (VOP3Mods f32:$src0, i32:$src0_modifiers), 504 (i32 timm:$attrchan), 505 (i32 timm:$attr), 506 (i1 timm:$high), M0))]>; 507} // End OtherPredicates = [isNotGFX90APlus, has32BankLDS], Uses = [MODE, M0, EXEC], FPDPRounding = 1 508 509let OtherPredicates = [isNotGFX90APlus], Uses = [MODE, M0, EXEC], FPDPRounding = 1 in { 510def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>; 511} // End OtherPredicates = [isNotGFX90APlus], Uses = [MODE, M0, EXEC], FPDPRounding = 1 512 513} // End SubtargetPredicate = Has16BitInsts, isCommutable = 1 514 515def : GCNPat< 516 (i64 (getDivergentFrag<sext>.ret i16:$src)), 517 (REG_SEQUENCE VReg_64, 518 (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))), sub0, 519 (i32 (COPY_TO_REGCLASS 520 (V_ASHRREV_I32_e32 (S_MOV_B32 (i32 0x1f)), (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))) 521 ), VGPR_32)), sub1) 522>; 523 524let SubtargetPredicate = isGFX8Plus, Uses = [MODE, M0, EXEC], OtherPredicates = [isNotGFX90APlus] in { 525def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>; 526def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>; 527def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>; 528} // End SubtargetPredicate = isGFX8Plus, Uses = [MODE, M0, EXEC], OtherPredicates = [isNotGFX90APlus] 529 530let Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] in { 531 532multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2, 533 Instruction inst> { 534def : GCNPat < 535 (op2 (op1 i16:$src0, i16:$src1), i16:$src2), 536 (inst i16:$src0, i16:$src1, i16:$src2, (i1 0)) 537>; 538 539} 540 541defm: Ternary_i16_Pats<mul, add, V_MAD_U16_e64>; 542defm: Ternary_i16_Pats<mul, add, V_MAD_I16_e64>; 543 544} // End Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] 545 546let Predicates = [Has16BitInsts, isGFX10Plus] in { 547 548multiclass Ternary_i16_Pats_gfx9<SDPatternOperator op1, SDPatternOperator op2, 549 Instruction inst> { 550def : GCNPat < 551 (op2 (op1 i16:$src0, i16:$src1), i16:$src2), 552 (inst SRCMODS.NONE, $src0, SRCMODS.NONE, $src1, SRCMODS.NONE, $src2, DSTCLAMP.NONE) 553>; 554 555} 556 557defm: Ternary_i16_Pats_gfx9<mul, add, V_MAD_U16_gfx9_e64>; 558defm: Ternary_i16_Pats_gfx9<mul, add, V_MAD_I16_gfx9_e64>; 559 560} // End Predicates = [Has16BitInsts, isGFX10Plus] 561 562class ThreeOpFrag<SDPatternOperator op1, SDPatternOperator op2> : PatFrag< 563 (ops node:$x, node:$y, node:$z), 564 // When the inner operation is used multiple times, selecting 3-op 565 // instructions may still be beneficial -- if the other users can be 566 // combined similarly. Let's be conservative for now. 567 (op2 (HasOneUseBinOp<op1> node:$x, node:$y), node:$z), 568 [{ 569 // Only use VALU ops when the result is divergent. 570 if (!N->isDivergent()) 571 return false; 572 573 // Check constant bus limitations. 574 // 575 // Note: Use !isDivergent as a conservative proxy for whether the value 576 // is in an SGPR (uniform values can end up in VGPRs as well). 577 unsigned ConstantBusUses = 0; 578 for (unsigned i = 0; i < 3; ++i) { 579 if (!Operands[i]->isDivergent() && 580 !isInlineImmediate(Operands[i].getNode())) { 581 ConstantBusUses++; 582 // This uses AMDGPU::V_ADD3_U32_e64, but all three operand instructions 583 // have the same constant bus limit. 584 if (ConstantBusUses > Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64)) 585 return false; 586 } 587 } 588 589 return true; 590 }]> { 591 let PredicateCodeUsesOperands = 1; 592 593 // The divergence predicate is irrelevant in GlobalISel, as we have 594 // proper register bank checks. We just need to verify the constant 595 // bus restriction when all the sources are considered. 596 // 597 // FIXME: With unlucky SGPR operands, we could penalize code by 598 // blocking folding SGPR->VGPR copies later. 599 // FIXME: There's no register bank verifier 600 let GISelPredicateCode = [{ 601 const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64); 602 int ConstantBusUses = 0; 603 for (unsigned i = 0; i < 3; ++i) { 604 const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI); 605 if (RegBank->getID() == AMDGPU::SGPRRegBankID) { 606 if (++ConstantBusUses > ConstantBusLimit) 607 return false; 608 } 609 } 610 return true; 611 }]; 612} 613 614def shl_0_to_4 : PatFrag< 615 (ops node:$src0, node:$src1), (shl node:$src0, node:$src1), 616 [{ 617 if (auto *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 618 return C->getZExtValue() <= 4; 619 } 620 return false; 621 }]> { 622 let GISelPredicateCode = [{ 623 int64_t Imm = 0; 624 if (!mi_match(MI.getOperand(2).getReg(), MRI, m_ICst(Imm)) && 625 !mi_match(MI.getOperand(2).getReg(), MRI, m_Copy(m_ICst(Imm)))) 626 return false; 627 return (uint64_t)Imm <= 4; 628 }]; 629} 630 631let SubtargetPredicate = isGFX9Plus in { 632let isCommutable = 1, isReMaterializable = 1 in { 633 defm V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 634 defm V_AND_OR_B32 : VOP3Inst <"v_and_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 635 defm V_OR3_B32 : VOP3Inst <"v_or3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 636 defm V_XAD_U32 : VOP3Inst <"v_xad_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 637 defm V_ADD_I32 : VOP3Inst <"v_add_i32", VOP3_Profile<VOP_I32_I32_I32_ARITH>>; 638 defm V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 639} // End isCommutable = 1, isReMaterializable = 1 640// TODO src0 contains the opsel bit for dst, so if we commute, need to mask and swap this 641// to the new src0. 642defm V_MED3_F16 : VOP3Inst <"v_med3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmed3>; 643defm V_MED3_I16 : VOP3Inst <"v_med3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmed3>; 644defm V_MED3_U16 : VOP3Inst <"v_med3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumed3>; 645 646defm V_MIN3_F16 : VOP3Inst <"v_min3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmin3>; 647defm V_MIN3_I16 : VOP3Inst <"v_min3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmin3>; 648defm V_MIN3_U16 : VOP3Inst <"v_min3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumin3>; 649 650defm V_MAX3_F16 : VOP3Inst <"v_max3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmax3>; 651defm V_MAX3_I16 : VOP3Inst <"v_max3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmax3>; 652defm V_MAX3_U16 : VOP3Inst <"v_max3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumax3>; 653 654defm V_ADD_I16 : VOP3Inst <"v_add_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>; 655defm V_SUB_I16 : VOP3Inst <"v_sub_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>; 656 657defm V_MAD_U32_U16 : VOP3Inst <"v_mad_u32_u16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>; 658defm V_MAD_I32_I16 : VOP3Inst <"v_mad_i32_i16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>; 659 660defm V_CVT_PKNORM_I16_F16 : VOP3Inst <"v_cvt_pknorm_i16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 661defm V_CVT_PKNORM_U16_F16 : VOP3Inst <"v_cvt_pknorm_u16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 662 663defm V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 664 665let isReMaterializable = 1 in { 666defm V_SUB_I32 : VOP3Inst <"v_sub_i32", VOP3_Profile<VOP_I32_I32_I32_ARITH>>; 667defm V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 668defm V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 669} // End isReMaterializable = 1 670 671// V_LSHL_ADD_U64: D0.u64 = (S0.u64 << S1.u[2:0]) + S2.u64 672// src0 is shifted left by 0-4 (use “0” to get ADD_U64). 673let SubtargetPredicate = isGFX940Plus in 674defm V_LSHL_ADD_U64 : VOP3Inst <"v_lshl_add_u64", VOP3_Profile<VOP_I64_I64_I32_I64>>; 675 676class ThreeOp_i32_Pats <SDPatternOperator op1, SDPatternOperator op2, Instruction inst> : GCNPat < 677 // This matches (op2 (op1 i32:$src0, i32:$src1), i32:$src2) with conditions. 678 (ThreeOpFrag<op1, op2> i32:$src0, i32:$src1, i32:$src2), 679 (inst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2) 680>; 681 682def : ThreeOp_i32_Pats<cshl_32, add, V_LSHL_ADD_U32_e64>; 683def : ThreeOp_i32_Pats<add, cshl_32, V_ADD_LSHL_U32_e64>; 684def : ThreeOp_i32_Pats<add, add, V_ADD3_U32_e64>; 685def : ThreeOp_i32_Pats<cshl_32, or, V_LSHL_OR_B32_e64>; 686def : ThreeOp_i32_Pats<and, or, V_AND_OR_B32_e64>; 687def : ThreeOp_i32_Pats<or, or, V_OR3_B32_e64>; 688def : ThreeOp_i32_Pats<xor, add, V_XAD_U32_e64>; 689 690let SubtargetPredicate = isGFX940Plus in 691def : GCNPat< 692 (ThreeOpFrag<shl_0_to_4, add> i64:$src0, i32:$src1, i64:$src2), 693 (V_LSHL_ADD_U64_e64 VSrc_b64:$src0, VSrc_b32:$src1, VSrc_b64:$src2) 694>; 695 696def : VOPBinOpClampPat<saddsat, V_ADD_I32_e64, i32>; 697def : VOPBinOpClampPat<ssubsat, V_SUB_I32_e64, i32>; 698 699def : GCNPat<(getDivergentFrag<or>.ret (or_oneuse i64:$src0, i64:$src1), i64:$src2), 700 (REG_SEQUENCE VReg_64, 701 (V_OR3_B32_e64 (i32 (EXTRACT_SUBREG $src0, sub0)), 702 (i32 (EXTRACT_SUBREG $src1, sub0)), 703 (i32 (EXTRACT_SUBREG $src2, sub0))), sub0, 704 (V_OR3_B32_e64 (i32 (EXTRACT_SUBREG $src0, sub1)), 705 (i32 (EXTRACT_SUBREG $src1, sub1)), 706 (i32 (EXTRACT_SUBREG $src2, sub1))), sub1)>; 707 708// FIXME: Probably should hardcode clamp bit in pseudo and avoid this. 709class OpSelBinOpClampPat<SDPatternOperator node, 710 Instruction inst> : GCNPat< 711 (node (i16 (VOP3OpSel i16:$src0, i32:$src0_modifiers)), 712 (i16 (VOP3OpSel i16:$src1, i32:$src1_modifiers))), 713 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, DSTCLAMP.ENABLE, 0) 714>; 715 716def : OpSelBinOpClampPat<saddsat, V_ADD_I16_e64>; 717def : OpSelBinOpClampPat<ssubsat, V_SUB_I16_e64>; 718} // End SubtargetPredicate = isGFX9Plus 719 720def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3_OPSEL> { 721 let Src0RC64 = VRegSrc_32; 722 let Src1RC64 = SCSrc_b32; 723 let Src2RC64 = SCSrc_b32; 724 let InsVOP3OpSel = (ins IntOpSelMods:$src0_modifiers, VRegSrc_32:$src0, 725 IntOpSelMods:$src1_modifiers, SCSrc_b32:$src1, 726 IntOpSelMods:$src2_modifiers, SCSrc_b32:$src2, 727 VGPR_32:$vdst_in, op_sel0:$op_sel); 728 let HasClamp = 0; 729} 730 731class PermlanePat<SDPatternOperator permlane, 732 Instruction inst> : GCNPat< 733 (permlane i32:$vdst_in, i32:$src0, i32:$src1, i32:$src2, 734 timm:$fi, timm:$bc), 735 (inst (as_i1timm $fi), VGPR_32:$src0, (as_i1timm $bc), 736 SCSrc_b32:$src1, 0, SCSrc_b32:$src2, VGPR_32:$vdst_in) 737>; 738 739// Permlane intrinsic that has either fetch invalid or bound control 740// fields enabled. 741class BoundControlOrFetchInvalidPermlane<SDPatternOperator permlane> : 742 PatFrag<(ops node:$vdst_in, node:$src0, node:$src1, node:$src2, 743 node:$fi, node:$bc), 744 (permlane node:$vdst_in, node:$src0, node: 745 $src1, node:$src2, node:$fi, node:$bc)> { 746 let PredicateCode = [{ return N->getConstantOperandVal(5) != 0 || 747 N->getConstantOperandVal(6) != 0; }]; 748 let GISelPredicateCode = [{ 749 return MI.getOperand(6).getImm() != 0 || 750 MI.getOperand(7).getImm() != 0; 751 }]; 752} 753 754// Drop the input value if it won't be read. 755class PermlaneDiscardVDstIn<SDPatternOperator permlane, 756 Instruction inst> : GCNPat< 757 (permlane srcvalue, i32:$src0, i32:$src1, i32:$src2, 758 timm:$fi, timm:$bc), 759 (inst (as_i1timm $fi), VGPR_32:$src0, (as_i1timm $bc), 760 SCSrc_b32:$src1, 0, SCSrc_b32:$src2, 761 (IMPLICIT_DEF)) 762>; 763 764 765let SubtargetPredicate = isGFX10Plus in { 766 let isCommutable = 1, isReMaterializable = 1 in { 767 defm V_XOR3_B32 : VOP3Inst <"v_xor3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 768 } // End isCommutable = 1, isReMaterializable = 1 769 def : ThreeOp_i32_Pats<xor, xor, V_XOR3_B32_e64>; 770 771 let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in { 772 defm V_PERMLANE16_B32 : VOP3Inst<"v_permlane16_b32", VOP3_PERMLANE_Profile>; 773 defm V_PERMLANEX16_B32 : VOP3Inst<"v_permlanex16_b32", VOP3_PERMLANE_Profile>; 774 } // End $vdst = $vdst_in, DisableEncoding $vdst_in 775 776 def : PermlanePat<int_amdgcn_permlane16, V_PERMLANE16_B32_e64>; 777 def : PermlanePat<int_amdgcn_permlanex16, V_PERMLANEX16_B32_e64>; 778 779 def : PermlaneDiscardVDstIn< 780 BoundControlOrFetchInvalidPermlane<int_amdgcn_permlane16>, 781 V_PERMLANE16_B32_e64>; 782 def : PermlaneDiscardVDstIn< 783 BoundControlOrFetchInvalidPermlane<int_amdgcn_permlanex16>, 784 V_PERMLANEX16_B32_e64>; 785} // End SubtargetPredicate = isGFX10Plus 786 787class DivFmasPat<ValueType vt, Instruction inst, Register CondReg> : GCNPat< 788 (AMDGPUdiv_fmas (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)), 789 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), 790 (vt (VOP3Mods vt:$src2, i32:$src2_modifiers)), 791 (i1 CondReg)), 792 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, $src2_modifiers, $src2) 793>; 794 795let WaveSizePredicate = isWave64 in { 796def : DivFmasPat<f32, V_DIV_FMAS_F32_e64, VCC>; 797def : DivFmasPat<f64, V_DIV_FMAS_F64_e64, VCC>; 798} 799 800let WaveSizePredicate = isWave32 in { 801def : DivFmasPat<f32, V_DIV_FMAS_F32_e64, VCC_LO>; 802def : DivFmasPat<f64, V_DIV_FMAS_F64_e64, VCC_LO>; 803} 804 805//===----------------------------------------------------------------------===// 806// Integer Clamp Patterns 807//===----------------------------------------------------------------------===// 808 809class getClampPat<VOPProfile P, SDPatternOperator node> { 810 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2)); 811 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1)); 812 dag ret1 = (P.DstVT (node P.Src0VT:$src0)); 813 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3, 814 !if(!eq(P.NumSrcArgs, 2), ret2, 815 ret1)); 816} 817 818class getClampRes<VOPProfile P, Instruction inst> { 819 dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0)); 820 dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0)); 821 dag ret1 = (inst P.Src0VT:$src0, (i1 0)); 822 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3, 823 !if(!eq(P.NumSrcArgs, 2), ret2, 824 ret1)); 825} 826 827class IntClampPat<VOP3InstBase inst, SDPatternOperator node> : GCNPat< 828 getClampPat<inst.Pfl, node>.ret, 829 getClampRes<inst.Pfl, inst>.ret 830>; 831 832def : IntClampPat<V_MAD_I32_I24_e64, AMDGPUmad_i24>; 833def : IntClampPat<V_MAD_U32_U24_e64, AMDGPUmad_u24>; 834 835def : IntClampPat<V_SAD_U8_e64, int_amdgcn_sad_u8>; 836def : IntClampPat<V_SAD_HI_U8_e64, int_amdgcn_sad_hi_u8>; 837def : IntClampPat<V_SAD_U16_e64, int_amdgcn_sad_u16>; 838 839def : IntClampPat<V_MSAD_U8_e64, int_amdgcn_msad_u8>; 840def : IntClampPat<V_MQSAD_PK_U16_U8_e64, int_amdgcn_mqsad_pk_u16_u8>; 841 842def : IntClampPat<V_QSAD_PK_U16_U8_e64, int_amdgcn_qsad_pk_u16_u8>; 843def : IntClampPat<V_MQSAD_U32_U8_e64, int_amdgcn_mqsad_u32_u8>; 844 845 846//===----------------------------------------------------------------------===// 847// Target-specific instruction encodings. 848//===----------------------------------------------------------------------===// 849 850//===----------------------------------------------------------------------===// 851// GFX10. 852//===----------------------------------------------------------------------===// 853 854let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in { 855 multiclass VOP3_Real_gfx10<bits<10> op> { 856 def _gfx10 : 857 VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 858 VOP3e_gfx10<op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 859 } 860 multiclass VOP3_Real_No_Suffix_gfx10<bits<10> op> { 861 def _gfx10 : 862 VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX10>, 863 VOP3e_gfx10<op, !cast<VOP_Pseudo>(NAME).Pfl>; 864 } 865 multiclass VOP3_Real_gfx10_with_name<bits<10> op, string opName, 866 string asmName> { 867 def _gfx10 : 868 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>, 869 VOP3e_gfx10<op, !cast<VOP3_Pseudo>(opName#"_e64").Pfl> { 870 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64"); 871 let AsmString = asmName # ps.AsmOperands; 872 let IsSingle = 1; 873 } 874 } 875 multiclass VOP3be_Real_gfx10<bits<10> op> { 876 def _gfx10 : 877 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 878 VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 879 } 880 multiclass VOP3Interp_Real_gfx10<bits<10> op> { 881 def _gfx10 : 882 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>, 883 VOP3Interp_gfx10<op, !cast<VOP3_Pseudo>(NAME).Pfl>; 884 } 885 multiclass VOP3OpSel_Real_gfx10<bits<10> op> { 886 def _gfx10 : 887 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 888 VOP3OpSel_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 889 } 890 multiclass VOP3OpSel_Real_gfx10_with_name<bits<10> op, string opName, 891 string asmName> { 892 def _gfx10 : 893 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>, 894 VOP3OpSel_gfx10<op, !cast<VOP3_Pseudo>(opName#"_e64").Pfl> { 895 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64"); 896 let AsmString = asmName # ps.AsmOperands; 897 } 898 } 899} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" 900 901defm V_READLANE_B32 : VOP3_Real_No_Suffix_gfx10<0x360>; 902 903let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in { 904 defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_gfx10<0x361>; 905} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) 906 907let SubtargetPredicate = isGFX10Before1030 in { 908 defm V_MUL_LO_I32 : VOP3_Real_gfx10<0x16b>; 909} 910 911defm V_XOR3_B32 : VOP3_Real_gfx10<0x178>; 912defm V_LSHLREV_B64 : VOP3_Real_gfx10<0x2ff>; 913defm V_LSHRREV_B64 : VOP3_Real_gfx10<0x300>; 914defm V_ASHRREV_I64 : VOP3_Real_gfx10<0x301>; 915defm V_PERM_B32 : VOP3_Real_gfx10<0x344>; 916defm V_XAD_U32 : VOP3_Real_gfx10<0x345>; 917defm V_LSHL_ADD_U32 : VOP3_Real_gfx10<0x346>; 918defm V_ADD_LSHL_U32 : VOP3_Real_gfx10<0x347>; 919defm V_ADD3_U32 : VOP3_Real_gfx10<0x36d>; 920defm V_LSHL_OR_B32 : VOP3_Real_gfx10<0x36f>; 921defm V_AND_OR_B32 : VOP3_Real_gfx10<0x371>; 922defm V_OR3_B32 : VOP3_Real_gfx10<0x372>; 923 924// TODO-GFX10: add MC tests for v_add/sub_nc_i16 925defm V_ADD_NC_I16 : 926 VOP3OpSel_Real_gfx10_with_name<0x30d, "V_ADD_I16", "v_add_nc_i16">; 927defm V_SUB_NC_I16 : 928 VOP3OpSel_Real_gfx10_with_name<0x30e, "V_SUB_I16", "v_sub_nc_i16">; 929defm V_SUB_NC_I32 : 930 VOP3_Real_gfx10_with_name<0x376, "V_SUB_I32", "v_sub_nc_i32">; 931defm V_ADD_NC_I32 : 932 VOP3_Real_gfx10_with_name<0x37f, "V_ADD_I32", "v_add_nc_i32">; 933 934defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_gfx10<0x200>; 935defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_gfx10<0x201>; 936defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_gfx10<0x202>; 937 938defm V_INTERP_P1LL_F16 : VOP3Interp_Real_gfx10<0x342>; 939defm V_INTERP_P1LV_F16 : VOP3Interp_Real_gfx10<0x343>; 940defm V_INTERP_P2_F16 : VOP3Interp_Real_gfx10<0x35a>; 941 942defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx10<0x311>; 943defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx10<0x312>; 944defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx10<0x313>; 945 946defm V_MIN3_F16 : VOP3OpSel_Real_gfx10<0x351>; 947defm V_MIN3_I16 : VOP3OpSel_Real_gfx10<0x352>; 948defm V_MIN3_U16 : VOP3OpSel_Real_gfx10<0x353>; 949defm V_MAX3_F16 : VOP3OpSel_Real_gfx10<0x354>; 950defm V_MAX3_I16 : VOP3OpSel_Real_gfx10<0x355>; 951defm V_MAX3_U16 : VOP3OpSel_Real_gfx10<0x356>; 952defm V_MED3_F16 : VOP3OpSel_Real_gfx10<0x357>; 953defm V_MED3_I16 : VOP3OpSel_Real_gfx10<0x358>; 954defm V_MED3_U16 : VOP3OpSel_Real_gfx10<0x359>; 955defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx10<0x373>; 956defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx10<0x375>; 957 958defm V_MAD_U16 : 959 VOP3OpSel_Real_gfx10_with_name<0x340, "V_MAD_U16_gfx9", "v_mad_u16">; 960defm V_FMA_F16 : 961 VOP3OpSel_Real_gfx10_with_name<0x34b, "V_FMA_F16_gfx9", "v_fma_f16">; 962defm V_MAD_I16 : 963 VOP3OpSel_Real_gfx10_with_name<0x35e, "V_MAD_I16_gfx9", "v_mad_i16">; 964defm V_DIV_FIXUP_F16 : 965 VOP3OpSel_Real_gfx10_with_name<0x35f, "V_DIV_FIXUP_F16_gfx9", "v_div_fixup_f16">; 966 967// FIXME-GFX10-OPSEL: Need to add "selective" opsel support to some of these 968// (they do not support SDWA or DPP). 969defm V_ADD_NC_U16 : VOP3_Real_gfx10_with_name<0x303, "V_ADD_U16", "v_add_nc_u16">; 970defm V_SUB_NC_U16 : VOP3_Real_gfx10_with_name<0x304, "V_SUB_U16", "v_sub_nc_u16">; 971defm V_MUL_LO_U16 : VOP3_Real_gfx10_with_name<0x305, "V_MUL_LO_U16", "v_mul_lo_u16">; 972defm V_LSHRREV_B16 : VOP3_Real_gfx10_with_name<0x307, "V_LSHRREV_B16", "v_lshrrev_b16">; 973defm V_ASHRREV_I16 : VOP3_Real_gfx10_with_name<0x308, "V_ASHRREV_I16", "v_ashrrev_i16">; 974defm V_MAX_U16 : VOP3_Real_gfx10_with_name<0x309, "V_MAX_U16", "v_max_u16">; 975defm V_MAX_I16 : VOP3_Real_gfx10_with_name<0x30a, "V_MAX_I16", "v_max_i16">; 976defm V_MIN_U16 : VOP3_Real_gfx10_with_name<0x30b, "V_MIN_U16", "v_min_u16">; 977defm V_MIN_I16 : VOP3_Real_gfx10_with_name<0x30c, "V_MIN_I16", "v_min_i16">; 978defm V_LSHLREV_B16 : VOP3_Real_gfx10_with_name<0x314, "V_LSHLREV_B16", "v_lshlrev_b16">; 979defm V_PERMLANE16_B32 : VOP3OpSel_Real_gfx10<0x377>; 980defm V_PERMLANEX16_B32 : VOP3OpSel_Real_gfx10<0x378>; 981 982//===----------------------------------------------------------------------===// 983// GFX7, GFX10. 984//===----------------------------------------------------------------------===// 985 986let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in { 987 multiclass VOP3_Real_gfx7<bits<10> op> { 988 def _gfx7 : 989 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 990 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 991 } 992 multiclass VOP3be_Real_gfx7<bits<10> op> { 993 def _gfx7 : 994 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 995 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 996 } 997} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" 998 999multiclass VOP3_Real_gfx7_gfx10<bits<10> op> : 1000 VOP3_Real_gfx7<op>, VOP3_Real_gfx10<op>; 1001 1002multiclass VOP3be_Real_gfx7_gfx10<bits<10> op> : 1003 VOP3be_Real_gfx7<op>, VOP3be_Real_gfx10<op>; 1004 1005defm V_QSAD_PK_U16_U8 : VOP3_Real_gfx7_gfx10<0x172>; 1006defm V_MQSAD_U32_U8 : VOP3_Real_gfx7_gfx10<0x175>; 1007defm V_MAD_U64_U32 : VOP3be_Real_gfx7_gfx10<0x176>; 1008defm V_MAD_I64_I32 : VOP3be_Real_gfx7_gfx10<0x177>; 1009 1010//===----------------------------------------------------------------------===// 1011// GFX6, GFX7, GFX10. 1012//===----------------------------------------------------------------------===// 1013 1014let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in { 1015 multiclass VOP3_Real_gfx6_gfx7<bits<10> op> { 1016 def _gfx6_gfx7 : 1017 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 1018 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1019 } 1020 multiclass VOP3be_Real_gfx6_gfx7<bits<10> op> { 1021 def _gfx6_gfx7 : 1022 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 1023 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1024 } 1025} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" 1026 1027multiclass VOP3_Real_gfx6_gfx7_gfx10<bits<10> op> : 1028 VOP3_Real_gfx6_gfx7<op>, VOP3_Real_gfx10<op>; 1029 1030multiclass VOP3be_Real_gfx6_gfx7_gfx10<bits<10> op> : 1031 VOP3be_Real_gfx6_gfx7<op>, VOP3be_Real_gfx10<op>; 1032 1033defm V_LSHL_B64 : VOP3_Real_gfx6_gfx7<0x161>; 1034defm V_LSHR_B64 : VOP3_Real_gfx6_gfx7<0x162>; 1035defm V_ASHR_I64 : VOP3_Real_gfx6_gfx7<0x163>; 1036defm V_MUL_LO_I32 : VOP3_Real_gfx6_gfx7<0x16b>; 1037 1038defm V_MAD_LEGACY_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x140>; 1039defm V_MAD_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x141>; 1040defm V_MAD_I32_I24 : VOP3_Real_gfx6_gfx7_gfx10<0x142>; 1041defm V_MAD_U32_U24 : VOP3_Real_gfx6_gfx7_gfx10<0x143>; 1042defm V_CUBEID_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x144>; 1043defm V_CUBESC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x145>; 1044defm V_CUBETC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x146>; 1045defm V_CUBEMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x147>; 1046defm V_BFE_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x148>; 1047defm V_BFE_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x149>; 1048defm V_BFI_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14a>; 1049defm V_FMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x14b>; 1050defm V_FMA_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x14c>; 1051defm V_LERP_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x14d>; 1052defm V_ALIGNBIT_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14e>; 1053defm V_ALIGNBYTE_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14f>; 1054defm V_MULLIT_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x150>; 1055defm V_MIN3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x151>; 1056defm V_MIN3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x152>; 1057defm V_MIN3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x153>; 1058defm V_MAX3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x154>; 1059defm V_MAX3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x155>; 1060defm V_MAX3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x156>; 1061defm V_MED3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x157>; 1062defm V_MED3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x158>; 1063defm V_MED3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x159>; 1064defm V_SAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15a>; 1065defm V_SAD_HI_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15b>; 1066defm V_SAD_U16 : VOP3_Real_gfx6_gfx7_gfx10<0x15c>; 1067defm V_SAD_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x15d>; 1068defm V_CVT_PK_U8_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15e>; 1069defm V_DIV_FIXUP_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15f>; 1070defm V_DIV_FIXUP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x160>; 1071defm V_ADD_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x164>; 1072defm V_MUL_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x165>; 1073defm V_MIN_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x166>; 1074defm V_MAX_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x167>; 1075defm V_LDEXP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x168>; 1076defm V_MUL_LO_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x169>; 1077defm V_MUL_HI_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x16a>; 1078defm V_MUL_HI_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x16c>; 1079defm V_DIV_FMAS_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x16f>; 1080defm V_DIV_FMAS_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x170>; 1081defm V_MSAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x171>; 1082defm V_MQSAD_PK_U16_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x173>; 1083defm V_TRIG_PREOP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x174>; 1084defm V_DIV_SCALE_F32 : VOP3be_Real_gfx6_gfx7_gfx10<0x16d>; 1085defm V_DIV_SCALE_F64 : VOP3be_Real_gfx6_gfx7_gfx10<0x16e>; 1086 1087// NB: Same opcode as v_mad_legacy_f32 1088let DecoderNamespace = "GFX10_B" in 1089defm V_FMA_LEGACY_F32 : VOP3_Real_gfx10<0x140>; 1090 1091//===----------------------------------------------------------------------===// 1092// GFX8, GFX9 (VI). 1093//===----------------------------------------------------------------------===// 1094 1095let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in { 1096 1097multiclass VOP3_Real_vi<bits<10> op> { 1098 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1099 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 1100} 1101multiclass VOP3_Real_No_Suffix_vi<bits<10> op> { 1102 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 1103 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>; 1104} 1105 1106multiclass VOP3be_Real_vi<bits<10> op> { 1107 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1108 VOP3be_vi <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 1109} 1110 1111multiclass VOP3OpSel_Real_gfx9<bits<10> op> { 1112 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1113 VOP3OpSel_gfx9 <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 1114} 1115 1116multiclass VOP3Interp_Real_vi<bits<10> op> { 1117 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 1118 VOP3Interp_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>; 1119} 1120 1121} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" 1122 1123let AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" in { 1124 1125multiclass VOP3_F16_Real_vi<bits<10> op> { 1126 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1127 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1128} 1129 1130multiclass VOP3Interp_F16_Real_vi<bits<10> op> { 1131 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>, 1132 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>; 1133} 1134 1135} // End AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" 1136 1137let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in { 1138 1139multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> { 1140 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>, 1141 VOP3e_vi <op, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> { 1142 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64"); 1143 let AsmString = AsmName # ps.AsmOperands; 1144 } 1145} 1146 1147multiclass VOP3OpSel_F16_Real_gfx9<bits<10> op, string AsmName> { 1148 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>, 1149 VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1150 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME#"_e64"); 1151 let AsmString = AsmName # ps.AsmOperands; 1152 } 1153} 1154 1155multiclass VOP3Interp_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> { 1156 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>, 1157 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> { 1158 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName); 1159 let AsmString = AsmName # ps.AsmOperands; 1160 } 1161} 1162 1163multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> { 1164 def _gfx9 : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>, 1165 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl> { 1166 VOP_Pseudo ps = !cast<VOP_Pseudo>(NAME#"_e64"); 1167 let AsmString = AsmName # ps.AsmOperands; 1168 } 1169} 1170 1171} // End AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" 1172 1173defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>; 1174defm V_MAD_I64_I32 : VOP3be_Real_vi <0x1E9>; 1175 1176defm V_MAD_LEGACY_F32 : VOP3_Real_vi <0x1c0>; 1177defm V_MAD_F32 : VOP3_Real_vi <0x1c1>; 1178defm V_MAD_I32_I24 : VOP3_Real_vi <0x1c2>; 1179defm V_MAD_U32_U24 : VOP3_Real_vi <0x1c3>; 1180defm V_CUBEID_F32 : VOP3_Real_vi <0x1c4>; 1181defm V_CUBESC_F32 : VOP3_Real_vi <0x1c5>; 1182defm V_CUBETC_F32 : VOP3_Real_vi <0x1c6>; 1183defm V_CUBEMA_F32 : VOP3_Real_vi <0x1c7>; 1184defm V_BFE_U32 : VOP3_Real_vi <0x1c8>; 1185defm V_BFE_I32 : VOP3_Real_vi <0x1c9>; 1186defm V_BFI_B32 : VOP3_Real_vi <0x1ca>; 1187defm V_FMA_F32 : VOP3_Real_vi <0x1cb>; 1188defm V_FMA_F64 : VOP3_Real_vi <0x1cc>; 1189defm V_LERP_U8 : VOP3_Real_vi <0x1cd>; 1190defm V_ALIGNBIT_B32 : VOP3_Real_vi <0x1ce>; 1191defm V_ALIGNBYTE_B32 : VOP3_Real_vi <0x1cf>; 1192defm V_MIN3_F32 : VOP3_Real_vi <0x1d0>; 1193defm V_MIN3_I32 : VOP3_Real_vi <0x1d1>; 1194defm V_MIN3_U32 : VOP3_Real_vi <0x1d2>; 1195defm V_MAX3_F32 : VOP3_Real_vi <0x1d3>; 1196defm V_MAX3_I32 : VOP3_Real_vi <0x1d4>; 1197defm V_MAX3_U32 : VOP3_Real_vi <0x1d5>; 1198defm V_MED3_F32 : VOP3_Real_vi <0x1d6>; 1199defm V_MED3_I32 : VOP3_Real_vi <0x1d7>; 1200defm V_MED3_U32 : VOP3_Real_vi <0x1d8>; 1201defm V_SAD_U8 : VOP3_Real_vi <0x1d9>; 1202defm V_SAD_HI_U8 : VOP3_Real_vi <0x1da>; 1203defm V_SAD_U16 : VOP3_Real_vi <0x1db>; 1204defm V_SAD_U32 : VOP3_Real_vi <0x1dc>; 1205defm V_CVT_PK_U8_F32 : VOP3_Real_vi <0x1dd>; 1206defm V_DIV_FIXUP_F32 : VOP3_Real_vi <0x1de>; 1207defm V_DIV_FIXUP_F64 : VOP3_Real_vi <0x1df>; 1208defm V_DIV_SCALE_F32 : VOP3be_Real_vi <0x1e0>; 1209defm V_DIV_SCALE_F64 : VOP3be_Real_vi <0x1e1>; 1210defm V_DIV_FMAS_F32 : VOP3_Real_vi <0x1e2>; 1211defm V_DIV_FMAS_F64 : VOP3_Real_vi <0x1e3>; 1212defm V_MSAD_U8 : VOP3_Real_vi <0x1e4>; 1213defm V_QSAD_PK_U16_U8 : VOP3_Real_vi <0x1e5>; 1214defm V_MQSAD_PK_U16_U8 : VOP3_Real_vi <0x1e6>; 1215defm V_MQSAD_U32_U8 : VOP3_Real_vi <0x1e7>; 1216 1217defm V_PERM_B32 : VOP3_Real_vi <0x1ed>; 1218 1219defm V_MAD_F16 : VOP3_F16_Real_vi <0x1ea>; 1220defm V_MAD_U16 : VOP3_F16_Real_vi <0x1eb>; 1221defm V_MAD_I16 : VOP3_F16_Real_vi <0x1ec>; 1222defm V_FMA_F16 : VOP3_F16_Real_vi <0x1ee>; 1223defm V_DIV_FIXUP_F16 : VOP3_F16_Real_vi <0x1ef>; 1224defm V_INTERP_P2_F16 : VOP3Interp_F16_Real_vi <0x276>; 1225 1226let FPDPRounding = 1 in { 1227defm V_MAD_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16", "v_mad_legacy_f16">; 1228defm V_FMA_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16", "v_fma_legacy_f16">; 1229defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16">; 1230defm V_INTERP_P2_LEGACY_F16 : VOP3Interp_F16_Real_gfx9 <0x276, "V_INTERP_P2_F16", "v_interp_p2_legacy_f16">; 1231} // End FPDPRounding = 1 1232 1233defm V_MAD_LEGACY_U16 : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16", "v_mad_legacy_u16">; 1234defm V_MAD_LEGACY_I16 : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16", "v_mad_legacy_i16">; 1235 1236defm V_MAD_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">; 1237defm V_MAD_U16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">; 1238defm V_MAD_I16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">; 1239defm V_FMA_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x206, "v_fma_f16">; 1240defm V_DIV_FIXUP_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">; 1241defm V_INTERP_P2_F16_gfx9 : VOP3Interp_F16_Real_gfx9 <0x277, "V_INTERP_P2_F16_gfx9", "v_interp_p2_f16">; 1242 1243defm V_ADD_I32 : VOP3_Real_vi <0x29c>; 1244defm V_SUB_I32 : VOP3_Real_vi <0x29d>; 1245 1246defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_vi <0x270>; 1247defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_vi <0x271>; 1248defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>; 1249 1250defm V_INTERP_P1LL_F16 : VOP3Interp_Real_vi <0x274>; 1251defm V_INTERP_P1LV_F16 : VOP3Interp_Real_vi <0x275>; 1252defm V_ADD_F64 : VOP3_Real_vi <0x280>; 1253defm V_MUL_F64 : VOP3_Real_vi <0x281>; 1254defm V_MIN_F64 : VOP3_Real_vi <0x282>; 1255defm V_MAX_F64 : VOP3_Real_vi <0x283>; 1256defm V_LDEXP_F64 : VOP3_Real_vi <0x284>; 1257defm V_MUL_LO_U32 : VOP3_Real_vi <0x285>; 1258 1259// removed from VI as identical to V_MUL_LO_U32 1260let isAsmParserOnly = 1 in { 1261defm V_MUL_LO_I32 : VOP3_Real_vi <0x285>; 1262} 1263 1264defm V_MUL_HI_U32 : VOP3_Real_vi <0x286>; 1265defm V_MUL_HI_I32 : VOP3_Real_vi <0x287>; 1266 1267defm V_READLANE_B32 : VOP3_Real_No_Suffix_vi <0x289>; 1268defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_vi <0x28a>; 1269 1270defm V_LSHLREV_B64 : VOP3_Real_vi <0x28f>; 1271defm V_LSHRREV_B64 : VOP3_Real_vi <0x290>; 1272defm V_ASHRREV_I64 : VOP3_Real_vi <0x291>; 1273defm V_TRIG_PREOP_F64 : VOP3_Real_vi <0x292>; 1274 1275defm V_LSHL_ADD_U32 : VOP3_Real_vi <0x1fd>; 1276defm V_ADD_LSHL_U32 : VOP3_Real_vi <0x1fe>; 1277defm V_ADD3_U32 : VOP3_Real_vi <0x1ff>; 1278defm V_LSHL_OR_B32 : VOP3_Real_vi <0x200>; 1279defm V_AND_OR_B32 : VOP3_Real_vi <0x201>; 1280defm V_OR3_B32 : VOP3_Real_vi <0x202>; 1281defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx9 <0x2a0>; 1282 1283defm V_XAD_U32 : VOP3_Real_vi <0x1f3>; 1284 1285defm V_MIN3_F16 : VOP3OpSel_Real_gfx9 <0x1f4>; 1286defm V_MIN3_I16 : VOP3OpSel_Real_gfx9 <0x1f5>; 1287defm V_MIN3_U16 : VOP3OpSel_Real_gfx9 <0x1f6>; 1288 1289defm V_MAX3_F16 : VOP3OpSel_Real_gfx9 <0x1f7>; 1290defm V_MAX3_I16 : VOP3OpSel_Real_gfx9 <0x1f8>; 1291defm V_MAX3_U16 : VOP3OpSel_Real_gfx9 <0x1f9>; 1292 1293defm V_MED3_F16 : VOP3OpSel_Real_gfx9 <0x1fa>; 1294defm V_MED3_I16 : VOP3OpSel_Real_gfx9 <0x1fb>; 1295defm V_MED3_U16 : VOP3OpSel_Real_gfx9 <0x1fc>; 1296 1297defm V_ADD_I16 : VOP3OpSel_Real_gfx9 <0x29e>; 1298defm V_SUB_I16 : VOP3OpSel_Real_gfx9 <0x29f>; 1299 1300defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx9 <0x1f1>; 1301defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx9 <0x1f2>; 1302 1303defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx9 <0x299>; 1304defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx9 <0x29a>; 1305 1306defm V_LSHL_ADD_U64 : VOP3_Real_vi <0x208>; 1307