1//===-- VOP2Instructions.td - Vector Instruction Definitions --------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// VOP2 Classes 11//===----------------------------------------------------------------------===// 12 13class VOP2e <bits<6> op, VOPProfile P> : Enc32 { 14 bits<8> vdst; 15 bits<9> src0; 16 bits<8> src1; 17 18 let Inst{8-0} = !if(P.HasSrc0, src0, 0); 19 let Inst{16-9} = !if(P.HasSrc1, src1, 0); 20 let Inst{24-17} = !if(P.EmitDst, vdst, 0); 21 let Inst{30-25} = op; 22 let Inst{31} = 0x0; //encoding 23} 24 25class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 { 26 bits<8> vdst; 27 bits<9> src0; 28 bits<8> src1; 29 bits<32> imm; 30 31 let Inst{8-0} = !if(P.HasSrc0, src0, 0); 32 let Inst{16-9} = !if(P.HasSrc1, src1, 0); 33 let Inst{24-17} = !if(P.EmitDst, vdst, 0); 34 let Inst{30-25} = op; 35 let Inst{31} = 0x0; // encoding 36 let Inst{63-32} = imm; 37} 38 39class VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> { 40 bits<8> vdst; 41 bits<8> src1; 42 43 let Inst{8-0} = 0xf9; // sdwa 44 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 45 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 46 let Inst{30-25} = op; 47 let Inst{31} = 0x0; // encoding 48} 49 50class VOP2_SDWA9Ae <bits<6> op, VOPProfile P> : VOP_SDWA9Ae <P> { 51 bits<8> vdst; 52 bits<9> src1; 53 54 let Inst{8-0} = 0xf9; // sdwa 55 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 56 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 57 let Inst{30-25} = op; 58 let Inst{31} = 0x0; // encoding 59 let Inst{63} = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr 60} 61 62class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> : 63 VOP_Pseudo <opName, suffix, P, P.Outs32, P.Ins32, "", pattern> { 64 65 let AsmOperands = P.Asm32; 66 67 let Size = 4; 68 let mayLoad = 0; 69 let mayStore = 0; 70 let hasSideEffects = 0; 71 72 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 73 74 let mayRaiseFPException = ReadsModeReg; 75 76 let VOP2 = 1; 77 let VALU = 1; 78 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 79 80 let AsmVariantName = AMDGPUAsmVariants.Default; 81} 82 83class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> : 84 VOP_Real <ps>, 85 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 86 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 87 88 let VALU = 1; 89 let VOP2 = 1; 90 let isPseudo = 0; 91 let isCodeGenOnly = 0; 92 93 let Constraints = ps.Constraints; 94 let DisableEncoding = ps.DisableEncoding; 95 96 // copy relevant pseudo op flags 97 let SubtargetPredicate = ps.SubtargetPredicate; 98 let OtherPredicates = ps.OtherPredicates; 99 let AsmMatchConverter = ps.AsmMatchConverter; 100 let AsmVariantName = ps.AsmVariantName; 101 let Constraints = ps.Constraints; 102 let DisableEncoding = ps.DisableEncoding; 103 let TSFlags = ps.TSFlags; 104 let UseNamedOperandTable = ps.UseNamedOperandTable; 105 let Uses = ps.Uses; 106 let Defs = ps.Defs; 107 let SchedRW = ps.SchedRW; 108 let mayLoad = ps.mayLoad; 109 let mayStore = ps.mayStore; 110} 111 112class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : 113 VOP_SDWA_Pseudo <OpName, P, pattern> { 114 let AsmMatchConverter = "cvtSdwaVOP2"; 115} 116 117class VOP2_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : 118 VOP_DPP_Pseudo <OpName, P, pattern> { 119} 120 121 122class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies { 123 list<dag> ret = !if(P.HasModifiers, 124 [(set P.DstVT:$vdst, 125 (node (P.Src0VT 126 !if(P.HasOMod, 127 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 128 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))), 129 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], 130 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]); 131} 132 133multiclass VOP2Inst_e32<string opName, 134 VOPProfile P, 135 SDPatternOperator node = null_frag, 136 string revOp = opName, 137 bit GFX9Renamed = 0> { 138 let renamedInGFX9 = GFX9Renamed in { 139 def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>, 140 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>; 141 } // End renamedInGFX9 = GFX9Renamed 142} 143 144multiclass VOP2Inst_e64<string opName, 145 VOPProfile P, 146 SDPatternOperator node = null_frag, 147 string revOp = opName, 148 bit GFX9Renamed = 0> { 149 let renamedInGFX9 = GFX9Renamed in { 150 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>, 151 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>; 152 } // End renamedInGFX9 = GFX9Renamed 153} 154 155multiclass VOP2Inst_sdwa<string opName, 156 VOPProfile P, 157 SDPatternOperator node = null_frag, 158 string revOp = opName, 159 bit GFX9Renamed = 0> { 160 let renamedInGFX9 = GFX9Renamed in { 161 foreach _ = BoolToList<P.HasExtSDWA>.ret in 162 def _sdwa : VOP2_SDWA_Pseudo <opName, P>; 163 } // End renamedInGFX9 = GFX9Renamed 164} 165 166multiclass VOP2Inst<string opName, 167 VOPProfile P, 168 SDPatternOperator node = null_frag, 169 string revOp = opName, 170 bit GFX9Renamed = 0> : 171 VOP2Inst_e32<opName, P, node, revOp, GFX9Renamed>, 172 VOP2Inst_e64<opName, P, node, revOp, GFX9Renamed>, 173 VOP2Inst_sdwa<opName, P, node, revOp, GFX9Renamed> { 174 let renamedInGFX9 = GFX9Renamed in { 175 foreach _ = BoolToList<P.HasExtDPP>.ret in 176 def _dpp : VOP2_DPP_Pseudo <opName, P>; 177 } 178} 179 180multiclass VOP2bInst <string opName, 181 VOPProfile P, 182 SDPatternOperator node = null_frag, 183 string revOp = opName, 184 bit GFX9Renamed = 0, 185 bit useSGPRInput = !eq(P.NumSrcArgs, 3)> { 186 let renamedInGFX9 = GFX9Renamed in { 187 let SchedRW = [Write32Bit, WriteSALU] in { 188 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in { 189 def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>, 190 Commutable_REV<revOp#"_e32", !eq(revOp, opName)> { 191 let usesCustomInserter = !eq(P.NumSrcArgs, 2); 192 } 193 194 foreach _ = BoolToList<P.HasExtSDWA>.ret in 195 def _sdwa : VOP2_SDWA_Pseudo <opName, P> { 196 let AsmMatchConverter = "cvtSdwaVOP2b"; 197 } 198 foreach _ = BoolToList<P.HasExtDPP>.ret in 199 def _dpp : VOP2_DPP_Pseudo <opName, P>; 200 } 201 202 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>, 203 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>; 204 } 205 } 206} 207 208class VOP2bInstAlias <VOP2_Pseudo ps, Instruction inst, 209 string OpName, string opnd> : 210 InstAlias <OpName#" "#!subst("vcc", opnd, ps.Pfl.Asm32), 211 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0, 212 ps.Pfl.Src1RC32:$src1)>, 213 PredicateControl { 214} 215 216multiclass VOP2bInstAliases<VOP2_Pseudo ps, VOP2_Real inst, string OpName> { 217 let WaveSizePredicate = isWave32 in { 218 def : VOP2bInstAlias<ps, inst, OpName, "vcc_lo">; 219 } 220 let WaveSizePredicate = isWave64 in { 221 def : VOP2bInstAlias<ps, inst, OpName, "vcc">; 222 } 223} 224 225multiclass VOP2eInst <string opName, 226 VOPProfile P, 227 SDPatternOperator node = null_frag, 228 string revOp = opName, 229 bit useSGPRInput = !eq(P.NumSrcArgs, 3)> { 230 231 let SchedRW = [Write32Bit] in { 232 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in { 233 def _e32 : VOP2_Pseudo <opName, P>, 234 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>; 235 236 foreach _ = BoolToList<P.HasExtSDWA>.ret in 237 def _sdwa : VOP2_SDWA_Pseudo <opName, P> { 238 let AsmMatchConverter = "cvtSdwaVOP2e"; 239 } 240 241 foreach _ = BoolToList<P.HasExtDPP>.ret in 242 def _dpp : VOP2_DPP_Pseudo <opName, P>; 243 } 244 245 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>, 246 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>; 247 } 248} 249 250class VOP2eInstAlias <VOP2_Pseudo ps, Instruction inst, string opnd = ""> : 251 InstAlias <ps.OpName#" "#ps.Pfl.Asm32#", "#opnd, 252 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0, 253 ps.Pfl.Src1RC32:$src1)>, PredicateControl; 254 255class VOP2e64InstAlias <VOP3_Pseudo ps, Instruction inst> : 256 InstAlias <ps.OpName#" "#ps.Pfl.Asm64, 257 (inst ps.Pfl.DstRC:$vdst, VOPDstS64orS32:$sdst, 258 ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, clampmod:$clamp)>, 259 PredicateControl; 260 261multiclass VOP2eInstAliases<VOP2_Pseudo ps, VOP2_Real inst> { 262 let WaveSizePredicate = isWave32 in { 263 def : VOP2eInstAlias<ps, inst, "vcc_lo">; 264 } 265 let WaveSizePredicate = isWave64 in { 266 def : VOP2eInstAlias<ps, inst, "vcc">; 267 } 268} 269 270class VOP_MADAK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> { 271 field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm); 272 field dag Ins32 = !if(!eq(vt.Size, 32), 273 (ins VCSrc_f32:$src0, VGPR_32:$src1, ImmOpType:$imm), 274 (ins VCSrc_f16:$src0, VGPR_32:$src1, ImmOpType:$imm)); 275 field bit HasExt = 0; 276 let IsSingle = 1; 277 278 field string Asm32 = "$vdst, $src0, $src1, $imm"; 279} 280 281def VOP_MADAK_F16 : VOP_MADAK <f16>; 282def VOP_MADAK_F32 : VOP_MADAK <f32>; 283 284class VOP_MADMK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> { 285 field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm); 286 field dag Ins32 = (ins VCSrc_f32:$src0, ImmOpType:$imm, VGPR_32:$src1); 287 field bit HasExt = 0; 288 let IsSingle = 1; 289 290 field string Asm32 = "$vdst, $src0, $imm, $src1"; 291} 292 293def VOP_MADMK_F16 : VOP_MADMK <f16>; 294def VOP_MADMK_F32 : VOP_MADMK <f32>; 295 296class getRegisterOperandForVT<ValueType VT> { 297 RegisterOperand ret = RegisterOperand<getVregSrcForVT<VT>.ret>; 298} 299 300// FIXME: Remove src2_modifiers. It isn't used, so is wasting memory 301// and processing time but it makes it easier to convert to mad. 302class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, vt0]> { 303 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, getVregSrcForVT<Src2VT>.ret:$src2); 304 let Ins64 = getIns64<Src0RC64, Src1RC64, getRegisterOperandForVT<Src2VT>.ret, 3, 305 0, HasModifiers, HasModifiers, HasOMod, 306 Src0Mod, Src1Mod, Src2Mod>.ret; 307 let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, 308 Src1ModDPP:$src1_modifiers, Src1DPP:$src1, 309 getVregSrcForVT<Src2VT>.ret:$src2, // stub argument 310 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 311 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 312 let InsDPP16 = !con(InsDPP, (ins FI:$fi)); 313 let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, 314 Src1ModDPP:$src1_modifiers, Src1DPP:$src1, 315 getVregSrcForVT<Src2VT>.ret:$src2, // stub argument 316 dpp8:$dpp8, FI:$fi); 317 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 318 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 319 getVregSrcForVT<Src2VT>.ret:$src2, // stub argument 320 clampmod:$clamp, omod:$omod, 321 dst_sel:$dst_sel, dst_unused:$dst_unused, 322 src0_sel:$src0_sel, src1_sel:$src1_sel); 323 let Asm32 = getAsm32<1, 2, vt0>.ret; 324 let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, vt0>.ret; 325 let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt0>.ret; 326 let AsmDPP16 = getAsmDPP16<1, 2, HasModifiers, vt0>.ret; 327 let AsmDPP8 = getAsmDPP8<1, 2, 0, vt0>.ret; 328 let AsmSDWA = getAsmSDWA<1, 2, vt0>.ret; 329 let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt0>.ret; 330 let HasSrc2 = 0; 331 let HasSrc2Mods = 0; 332 333 let HasExt = 1; 334 let HasExtDPP = 1; 335 let HasExtSDWA = 1; 336 let HasExtSDWA9 = 0; 337 let TieRegDPP = "$src2"; 338} 339 340def VOP_MAC_F16 : VOP_MAC <f16>; 341def VOP_MAC_F32 : VOP_MAC <f32>; 342let HasExtDPP = 0 in 343def VOP_MAC_LEGACY_F32 : VOP_MAC <f32>; 344let HasExtSDWA = 0, HasExt64BitDPP = 1 in 345def VOP_MAC_F64 : VOP_MAC <f64>; 346 347class VOP_DOT_ACC<ValueType vt0, ValueType vt1> : VOP_MAC<vt0, vt1> { 348 let HasClamp = 0; 349 let HasExtSDWA = 0; 350 let HasOpSel = 0; 351 let IsPacked = 0; 352} 353 354def VOP_DOT_ACC_F32_V2F16 : VOP_DOT_ACC<f32, v2f16> { 355 let Src0ModDPP = FPVRegInputMods; 356 let Src1ModDPP = FPVRegInputMods; 357} 358 359def VOP_DOT_ACC_I32_I32 : VOP_DOT_ACC<i32, i32> { 360 let HasSrc0Mods = 1; 361 let HasSrc1Mods = 1; 362} 363 364// Write out to vcc or arbitrary SGPR. 365def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], 0, /*EnableClamp=*/1> { 366 let Asm32 = "$vdst, vcc, $src0, $src1"; 367 let Asm64 = "$vdst, $sdst, $src0, $src1$clamp"; 368 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 369 let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 370 let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 371 let AsmDPP8 = "$vdst, vcc, $src0, $src1 $dpp8$fi"; 372 let AsmDPP16 = AsmDPP#"$fi"; 373 let Outs32 = (outs DstRC:$vdst); 374 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 375} 376 377// Write out to vcc or arbitrary SGPR and read in from vcc or 378// arbitrary SGPR. 379def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], 0, /*EnableClamp=*/1> { 380 let Asm32 = "$vdst, vcc, $src0, $src1, vcc"; 381 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp"; 382 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 383 let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 384 let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 385 let AsmDPP8 = "$vdst, vcc, $src0, $src1, vcc $dpp8$fi"; 386 let AsmDPP16 = AsmDPP#"$fi"; 387 let Outs32 = (outs DstRC:$vdst); 388 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 389 390 // Suppress src2 implied by type since the 32-bit encoding uses an 391 // implicit VCC use. 392 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1); 393 394 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 395 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 396 clampmod:$clamp, 397 dst_sel:$dst_sel, dst_unused:$dst_unused, 398 src0_sel:$src0_sel, src1_sel:$src1_sel); 399 400 let InsDPP = (ins DstRCDPP:$old, 401 Src0DPP:$src0, 402 Src1DPP:$src1, 403 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 404 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 405 let InsDPP16 = !con(InsDPP, (ins FI:$fi)); 406 407 let HasExt = 1; 408 let HasExtDPP = 1; 409 let HasExtSDWA = 1; 410 let HasExtSDWA9 = 1; 411} 412 413// Read in from vcc or arbitrary SGPR. 414def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], /*EnableF32SrcMods=*/1> { 415 let Asm32 = "$vdst, $src0, $src1"; 416 let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2"; 417 let AsmSDWA = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 418 let AsmSDWA9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 419 let AsmDPP = "$vdst, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 420 let AsmDPP8 = "$vdst, $src0, $src1, vcc $dpp8$fi"; 421 let AsmDPP16 = AsmDPP#"$fi"; 422 423 let Outs32 = (outs DstRC:$vdst); 424 let Outs64 = (outs DstRC:$vdst); 425 426 // Suppress src2 implied by type since the 32-bit encoding uses an 427 // implicit VCC use. 428 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1); 429 430 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 431 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 432 clampmod:$clamp, 433 dst_sel:$dst_sel, dst_unused:$dst_unused, 434 src0_sel:$src0_sel, src1_sel:$src1_sel); 435 436 let InsDPP = (ins DstRCDPP:$old, 437 Src0ModDPP:$src0_modifiers, Src0DPP:$src0, 438 Src1ModDPP:$src1_modifiers, Src1DPP:$src1, 439 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 440 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 441 let InsDPP16 = !con(InsDPP, (ins FI:$fi)); 442 443 let HasExt = 1; 444 let HasExtDPP = 1; 445 let HasExtSDWA = 1; 446 let HasExtSDWA9 = 1; 447} 448 449def VOP_READLANE : VOPProfile<[i32, i32, i32]> { 450 let Outs32 = (outs SReg_32:$vdst); 451 let Outs64 = Outs32; 452 let Ins32 = (ins VRegOrLds_32:$src0, SCSrc_b32:$src1); 453 let Ins64 = Ins32; 454 let Asm32 = " $vdst, $src0, $src1"; 455 let Asm64 = Asm32; 456 457 let HasExt = 0; 458 let HasExtDPP = 0; 459 let HasExt64BitDPP = 0; 460 let HasExtSDWA = 0; 461 let HasExtSDWA9 = 0; 462} 463 464def VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> { 465 let Outs32 = (outs VGPR_32:$vdst); 466 let Outs64 = Outs32; 467 let Ins32 = (ins SCSrc_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in); 468 let Ins64 = Ins32; 469 let Asm32 = " $vdst, $src0, $src1"; 470 let Asm64 = Asm32; 471 let HasSrc2 = 0; 472 let HasSrc2Mods = 0; 473 474 let HasExt = 0; 475 let HasExtDPP = 0; 476 let HasExt64BitDPP = 0; 477 let HasExtSDWA = 0; 478 let HasExtSDWA9 = 0; 479} 480 481//===----------------------------------------------------------------------===// 482// VOP2 Instructions 483//===----------------------------------------------------------------------===// 484 485defm V_CNDMASK_B32 : VOP2eInst <"v_cndmask_b32", VOP2e_I32_I32_I32_I1>; 486let SubtargetPredicate = HasMadMacF32Insts in 487def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, []>; 488 489let isCommutable = 1 in { 490defm V_ADD_F32 : VOP2Inst <"v_add_f32", VOP_F32_F32_F32, any_fadd>; 491defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, any_fsub>; 492defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">; 493defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>; 494defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, any_fmul>; 495defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32_ARITH, AMDGPUmul_i24>; 496defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_i24>; 497defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32_ARITH, AMDGPUmul_u24>; 498defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_u24>; 499defm V_MIN_F32 : VOP2Inst <"v_min_f32", VOP_F32_F32_F32, fminnum_like>; 500defm V_MAX_F32 : VOP2Inst <"v_max_f32", VOP_F32_F32_F32, fmaxnum_like>; 501defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smin>; 502defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smax>; 503defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umin>; 504defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umax>; 505defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, lshr_rev, "v_lshr_b32">; 506defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, ashr_rev, "v_ashr_i32">; 507defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, lshl_rev, "v_lshl_b32">; 508defm V_AND_B32 : VOP2Inst <"v_and_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, and>; 509defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, or>; 510defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, xor>; 511 512let mayRaiseFPException = 0 in { 513let OtherPredicates = [HasMadMacF32Insts] in { 514let Constraints = "$vdst = $src2", DisableEncoding="$src2", 515 isConvertibleToThreeAddress = 1 in { 516defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>; 517 518let SubtargetPredicate = isGFX6GFX7GFX10 in 519defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_MAC_LEGACY_F32>; 520} // End Constraints = "$vdst = $src2", DisableEncoding="$src2", 521 // isConvertibleToThreeAddress = 1 522 523def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32, []>; 524} // End OtherPredicates = [HasMadMacF32Insts] 525} // End mayRaiseFPException = 0 526 527// No patterns so that the scalar instructions are always selected. 528// The scalar versions will be replaced with vector when needed later. 529defm V_ADD_CO_U32 : VOP2bInst <"v_add_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_add_co_u32", 1>; 530defm V_SUB_CO_U32 : VOP2bInst <"v_sub_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>; 531defm V_SUBREV_CO_U32 : VOP2bInst <"v_subrev_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>; 532defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_addc_u32", 1>; 533defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>; 534defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>; 535 536 537let SubtargetPredicate = HasAddNoCarryInsts in { 538defm V_ADD_U32 : VOP2Inst <"v_add_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_add_u32", 1>; 539defm V_SUB_U32 : VOP2Inst <"v_sub_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>; 540defm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>; 541} 542 543} // End isCommutable = 1 544 545// These are special and do not read the exec mask. 546let isConvergent = 1, Uses = []<Register> in { 547def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE, 548 [(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))]>; 549 550let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in { 551def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE, 552 [(set i32:$vdst, (int_amdgcn_writelane i32:$src0, i32:$src1, i32:$vdst_in))]>; 553} // End $vdst = $vdst_in, DisableEncoding $vdst_in 554} // End isConvergent = 1 555 556defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_NO_EXT<VOP_I32_I32_I32>>; 557defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, add_ctpop>; 558defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_lo>; 559defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_hi>; 560defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_NO_EXT<VOP_F32_F32_I32>, AMDGPUldexp>; 561defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_NO_EXT<VOP_I32_F32_I32>>; // TODO: set "Uses = dst" 562 563let ReadsModeReg = 0, mayRaiseFPException = 0 in { 564defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_i16_f32>; 565defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_u16_f32>; 566} 567 568defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_NO_EXT<VOP_V2F16_F32_F32>, AMDGPUpkrtz_f16_f32>; 569defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_u16_u32>; 570defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_i16_i32>; 571 572 573let SubtargetPredicate = isGFX6GFX7 in { 574defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>; 575defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>; 576} // End SubtargetPredicate = isGFX6GFX7 577 578let isCommutable = 1 in { 579let SubtargetPredicate = isGFX6GFX7 in { 580defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, srl>; 581defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, sra>; 582defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, shl>; 583} // End SubtargetPredicate = isGFX6GFX7 584} // End isCommutable = 1 585 586 587class DivergentBinOp<SDPatternOperator Op, VOP_Pseudo Inst> : 588 GCNPat< 589 (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1), 590 !if(!cast<Commutable_REV>(Inst).IsOrig, 591 (Inst $src0, $src1), 592 (Inst $src1, $src0) 593 ) 594 >; 595 596class DivergentClampingBinOp<SDPatternOperator Op, VOP_Pseudo Inst> : 597 GCNPat< 598 (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1), 599 !if(!cast<Commutable_REV>(Inst).IsOrig, 600 (Inst $src0, $src1, 0), 601 (Inst $src1, $src0, 0) 602 ) 603 >; 604 605def : DivergentBinOp<srl, V_LSHRREV_B32_e64>; 606def : DivergentBinOp<sra, V_ASHRREV_I32_e64>; 607def : DivergentBinOp<shl, V_LSHLREV_B32_e64>; 608 609let SubtargetPredicate = HasAddNoCarryInsts in { 610 def : DivergentClampingBinOp<add, V_ADD_U32_e64>; 611 def : DivergentClampingBinOp<sub, V_SUB_U32_e64>; 612} 613 614let SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] in { 615def : DivergentClampingBinOp<add, V_ADD_CO_U32_e64>; 616def : DivergentClampingBinOp<sub, V_SUB_CO_U32_e64>; 617} 618 619def : DivergentBinOp<adde, V_ADDC_U32_e32>; 620def : DivergentBinOp<sube, V_SUBB_U32_e32>; 621 622class divergent_i64_BinOp <SDPatternOperator Op, Instruction Inst> : 623 GCNPat< 624 (getDivergentFrag<Op>.ret i64:$src0, i64:$src1), 625 (REG_SEQUENCE VReg_64, 626 (Inst 627 (i32 (EXTRACT_SUBREG $src0, sub0)), 628 (i32 (EXTRACT_SUBREG $src1, sub0)) 629 ), sub0, 630 (Inst 631 (i32 (EXTRACT_SUBREG $src0, sub1)), 632 (i32 (EXTRACT_SUBREG $src1, sub1)) 633 ), sub1 634 ) 635 >; 636 637def : divergent_i64_BinOp <and, V_AND_B32_e32>; 638def : divergent_i64_BinOp <or, V_OR_B32_e32>; 639def : divergent_i64_BinOp <xor, V_XOR_B32_e32>; 640 641let SubtargetPredicate = Has16BitInsts in { 642 643let FPDPRounding = 1 in { 644def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16, [], "">; 645defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>; 646} // End FPDPRounding = 1 647 648defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16, lshl_rev>; 649defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16, lshr_rev>; 650defm V_ASHRREV_I16 : VOP2Inst <"v_ashrrev_i16", VOP_I16_I16_I16, ashr_rev>; 651 652let isCommutable = 1 in { 653let FPDPRounding = 1 in { 654defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, any_fadd>; 655defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, any_fsub>; 656defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">; 657defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, any_fmul>; 658 659let mayRaiseFPException = 0 in { 660def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">; 661} 662 663} // End FPDPRounding = 1 664defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16_ARITH, add>; 665defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16_ARITH, sub>; 666defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16_ARITH, null_frag, "v_sub_u16">; 667defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16, mul>; 668defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum_like>; 669defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum_like>; 670defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16, umax>; 671defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16, smax>; 672defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16, umin>; 673defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16, smin>; 674 675let Constraints = "$vdst = $src2", DisableEncoding="$src2", 676 isConvertibleToThreeAddress = 1 in { 677defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>; 678} 679} // End isCommutable = 1 680 681} // End SubtargetPredicate = Has16BitInsts 682 683let SubtargetPredicate = HasDLInsts in { 684 685defm V_XNOR_B32 : VOP2Inst <"v_xnor_b32", VOP_I32_I32_I32, xnor>; 686 687let Constraints = "$vdst = $src2", 688 DisableEncoding = "$src2", 689 isConvertibleToThreeAddress = 1, 690 isCommutable = 1 in 691defm V_FMAC_F32 : VOP2Inst <"v_fmac_f32", VOP_MAC_F32>; 692 693} // End SubtargetPredicate = HasDLInsts 694 695let SubtargetPredicate = HasFmaLegacy32 in { 696 697let Constraints = "$vdst = $src2", 698 DisableEncoding = "$src2", 699 isConvertibleToThreeAddress = 1, 700 isCommutable = 1 in 701defm V_FMAC_LEGACY_F32 : VOP2Inst <"v_fmac_legacy_f32", VOP_MAC_LEGACY_F32>; 702 703} // End SubtargetPredicate = HasFmaLegacy32 704 705let SubtargetPredicate = isGFX90APlus, 706 Constraints = "$vdst = $src2", 707 DisableEncoding="$src2", 708 isConvertibleToThreeAddress = 1, 709 isCommutable = 1, 710 SchedRW = [WriteDoubleAdd] in 711defm V_FMAC_F64 : VOP2Inst <"v_fmac_f64", VOP_MAC_F64>; 712 713let Constraints = "$vdst = $src2", 714 DisableEncoding="$src2", 715 isConvertibleToThreeAddress = 1, 716 isCommutable = 1, 717 IsDOT = 1 in { 718 let SubtargetPredicate = HasDot5Insts in 719 defm V_DOT2C_F32_F16 : VOP2Inst<"v_dot2c_f32_f16", VOP_DOT_ACC_F32_V2F16>; 720 let SubtargetPredicate = HasDot6Insts in 721 defm V_DOT4C_I32_I8 : VOP2Inst<"v_dot4c_i32_i8", VOP_DOT_ACC_I32_I32>; 722 723 let SubtargetPredicate = HasDot4Insts in 724 defm V_DOT2C_I32_I16 : VOP2Inst<"v_dot2c_i32_i16", VOP_DOT_ACC_I32_I32>; 725 let SubtargetPredicate = HasDot3Insts in 726 defm V_DOT8C_I32_I4 : VOP2Inst<"v_dot8c_i32_i4", VOP_DOT_ACC_I32_I32>; 727} 728 729let AddedComplexity = 30 in { 730 def : GCNPat< 731 (f32 (AMDGPUfdot2 v2f16:$src0, v2f16:$src1, f32:$src2, (i1 DSTCLAMP.NONE))), 732 (f32 (V_DOT2C_F32_F16_e32 $src0, $src1, $src2)) 733 > { 734 let SubtargetPredicate = HasDot5Insts; 735 } 736 def : GCNPat< 737 (i32 (int_amdgcn_sdot4 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))), 738 (i32 (V_DOT4C_I32_I8_e32 $src0, $src1, $src2)) 739 > { 740 let SubtargetPredicate = HasDot6Insts; 741 } 742 def : GCNPat< 743 (i32 (int_amdgcn_sdot2 v2i16:$src0, v2i16:$src1, i32:$src2, (i1 DSTCLAMP.NONE))), 744 (i32 (V_DOT2C_I32_I16_e32 $src0, $src1, $src2)) 745 > { 746 let SubtargetPredicate = HasDot4Insts; 747 } 748 def : GCNPat< 749 (i32 (int_amdgcn_sdot8 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))), 750 (i32 (V_DOT8C_I32_I4_e32 $src0, $src1, $src2)) 751 > { 752 let SubtargetPredicate = HasDot3Insts; 753 } 754} // End AddedComplexity = 30 755 756let SubtargetPredicate = HasFmaakFmamkF32Insts in { 757def V_FMAMK_F32 : VOP2_Pseudo<"v_fmamk_f32", VOP_MADMK_F32, [], "">; 758 759let isCommutable = 1 in 760def V_FMAAK_F32 : VOP2_Pseudo<"v_fmaak_f32", VOP_MADAK_F32, [], "">; 761} 762 763let SubtargetPredicate = isGFX10Plus in { 764 765let FPDPRounding = 1 in { 766def V_FMAMK_F16 : VOP2_Pseudo <"v_fmamk_f16", VOP_MADMK_F16, [], "">; 767 768let isCommutable = 1 in 769def V_FMAAK_F16 : VOP2_Pseudo <"v_fmaak_f16", VOP_MADAK_F16, [], "">; 770} // End FPDPRounding = 1 771 772let Constraints = "$vdst = $src2", 773 DisableEncoding="$src2", 774 isConvertibleToThreeAddress = 1, 775 isCommutable = 1 in { 776defm V_FMAC_F16 : VOP2Inst <"v_fmac_f16", VOP_MAC_F16>; 777} 778 779} // End SubtargetPredicate = isGFX10Plus 780 781let SubtargetPredicate = HasPkFmacF16Inst in { 782defm V_PK_FMAC_F16 : VOP2Inst<"v_pk_fmac_f16", VOP_V2F16_V2F16_V2F16>; 783} // End SubtargetPredicate = HasPkFmacF16Inst 784 785// Note: 16-bit instructions produce a 0 result in the high 16-bits 786// on GFX8 and GFX9 and preserve high 16 bits on GFX10+ 787multiclass Arithmetic_i16_0Hi_Pats <SDPatternOperator op, Instruction inst> { 788 789def : GCNPat< 790 (i32 (zext (op i16:$src0, i16:$src1))), 791 (inst VSrc_b16:$src0, VSrc_b16:$src1) 792>; 793 794def : GCNPat< 795 (i64 (zext (op i16:$src0, i16:$src1))), 796 (REG_SEQUENCE VReg_64, 797 (inst $src0, $src1), sub0, 798 (V_MOV_B32_e32 (i32 0)), sub1) 799>; 800} 801 802class ZExt_i16_i1_Pat <SDNode ext> : GCNPat < 803 (i16 (ext i1:$src)), 804 (V_CNDMASK_B32_e64 (i32 0/*src0mod*/), (i32 0/*src0*/), 805 (i32 0/*src1mod*/), (i32 1/*src1*/), 806 $src) 807>; 808 809foreach vt = [i16, v2i16] in { 810def : GCNPat < 811 (and vt:$src0, vt:$src1), 812 (V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1) 813>; 814 815def : GCNPat < 816 (or vt:$src0, vt:$src1), 817 (V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1) 818>; 819 820def : GCNPat < 821 (xor vt:$src0, vt:$src1), 822 (V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1) 823>; 824} 825 826let Predicates = [Has16BitInsts] in { 827 828// Undo sub x, c -> add x, -c canonicalization since c is more likely 829// an inline immediate than -c. 830// TODO: Also do for 64-bit. 831def : GCNPat< 832 (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)), 833 (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1) 834>; 835 836 837let Predicates = [Has16BitInsts, isGFX7GFX8GFX9] in { 838 839def : GCNPat< 840 (i32 (zext (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)))), 841 (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1) 842>; 843 844defm : Arithmetic_i16_0Hi_Pats<add, V_ADD_U16_e64>; 845defm : Arithmetic_i16_0Hi_Pats<mul, V_MUL_LO_U16_e64>; 846defm : Arithmetic_i16_0Hi_Pats<sub, V_SUB_U16_e64>; 847defm : Arithmetic_i16_0Hi_Pats<smin, V_MIN_I16_e64>; 848defm : Arithmetic_i16_0Hi_Pats<smax, V_MAX_I16_e64>; 849defm : Arithmetic_i16_0Hi_Pats<umin, V_MIN_U16_e64>; 850defm : Arithmetic_i16_0Hi_Pats<umax, V_MAX_U16_e64>; 851defm : Arithmetic_i16_0Hi_Pats<lshl_rev, V_LSHLREV_B16_e64>; 852defm : Arithmetic_i16_0Hi_Pats<lshr_rev, V_LSHRREV_B16_e64>; 853defm : Arithmetic_i16_0Hi_Pats<ashr_rev, V_ASHRREV_I16_e64>; 854} // End Predicates = [Has16BitInsts, isGFX7GFX8GFX9] 855 856def : ZExt_i16_i1_Pat<zext>; 857def : ZExt_i16_i1_Pat<anyext>; 858 859def : GCNPat < 860 (i16 (sext i1:$src)), 861 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0), 862 /*src1mod*/(i32 0), /*src1*/(i32 -1), $src) 863>; 864 865} // End Predicates = [Has16BitInsts] 866 867 868let SubtargetPredicate = HasIntClamp in { 869// Set clamp bit for saturation. 870def : VOPBinOpClampPat<uaddsat, V_ADD_CO_U32_e64, i32>; 871def : VOPBinOpClampPat<usubsat, V_SUB_CO_U32_e64, i32>; 872} 873 874let SubtargetPredicate = HasAddNoCarryInsts, OtherPredicates = [HasIntClamp] in { 875let AddedComplexity = 1 in { // Prefer over form with carry-out. 876def : VOPBinOpClampPat<uaddsat, V_ADD_U32_e64, i32>; 877def : VOPBinOpClampPat<usubsat, V_SUB_U32_e64, i32>; 878} 879} 880 881let SubtargetPredicate = Has16BitInsts, OtherPredicates = [HasIntClamp] in { 882def : VOPBinOpClampPat<uaddsat, V_ADD_U16_e64, i16>; 883def : VOPBinOpClampPat<usubsat, V_SUB_U16_e64, i16>; 884} 885 886//===----------------------------------------------------------------------===// 887// Target-specific instruction encodings. 888//===----------------------------------------------------------------------===// 889 890class VOP2_DPP<bits<6> op, VOP2_DPP_Pseudo ps, 891 string opName = ps.OpName, VOPProfile p = ps.Pfl, 892 bit IsDPP16 = 0> : 893 VOP_DPP<opName, p, IsDPP16> { 894 let hasSideEffects = ps.hasSideEffects; 895 let Defs = ps.Defs; 896 let SchedRW = ps.SchedRW; 897 let Uses = ps.Uses; 898 899 bits<8> vdst; 900 bits<8> src1; 901 let Inst{8-0} = 0xfa; 902 let Inst{16-9} = !if(p.HasSrc1, src1{7-0}, 0); 903 let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0); 904 let Inst{30-25} = op; 905 let Inst{31} = 0x0; 906} 907 908class Base_VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps, 909 string opName = ps.OpName, VOPProfile p = ps.Pfl> : 910 VOP2_DPP<op, ps, opName, p, 1> { 911 let AssemblerPredicate = HasDPP16; 912 let SubtargetPredicate = HasDPP16; 913 let OtherPredicates = ps.OtherPredicates; 914} 915 916class VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps, 917 string opName = ps.OpName, VOPProfile p = ps.Pfl> : 918 Base_VOP2_DPP16<op, ps, opName, p>, 919 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX10>; 920 921class VOP2_DPP8<bits<6> op, VOP2_Pseudo ps, 922 string opName = ps.OpName, VOPProfile p = ps.Pfl> : 923 VOP_DPP8<ps.OpName, p> { 924 let hasSideEffects = ps.hasSideEffects; 925 let Defs = ps.Defs; 926 let SchedRW = ps.SchedRW; 927 let Uses = ps.Uses; 928 929 bits<8> vdst; 930 bits<8> src1; 931 932 let Inst{8-0} = fi; 933 let Inst{16-9} = !if(p.HasSrc1, src1{7-0}, 0); 934 let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0); 935 let Inst{30-25} = op; 936 let Inst{31} = 0x0; 937 938 let OtherPredicates = ps.OtherPredicates; 939} 940 941//===----------------------------------------------------------------------===// 942// GFX10. 943//===----------------------------------------------------------------------===// 944 945let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in { 946 //===------------------------------- VOP2 -------------------------------===// 947 multiclass VOP2Only_Real_MADK_gfx10<bits<6> op> { 948 def _gfx10 : 949 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX10>, 950 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 951 } 952 multiclass VOP2Only_Real_MADK_gfx10_with_name<bits<6> op, string opName, 953 string asmName> { 954 def _gfx10 : 955 VOP2_Real<!cast<VOP2_Pseudo>(opName), SIEncodingFamily.GFX10>, 956 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> { 957 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName); 958 let AsmString = asmName # ps.AsmOperands; 959 } 960 } 961 multiclass VOP2_Real_e32_gfx10<bits<6> op> { 962 def _e32_gfx10 : 963 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>, 964 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 965 } 966 multiclass VOP2_Real_e64_gfx10<bits<6> op> { 967 def _e64_gfx10 : 968 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 969 VOP3e_gfx10<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 970 } 971 multiclass VOP2_Real_sdwa_gfx10<bits<6> op> { 972 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in 973 def _sdwa_gfx10 : 974 VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 975 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> { 976 let DecoderNamespace = "SDWA10"; 977 } 978 } 979 multiclass VOP2_Real_dpp_gfx10<bits<6> op> { 980 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in 981 def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> { 982 let DecoderNamespace = "SDWA10"; 983 } 984 } 985 multiclass VOP2_Real_dpp8_gfx10<bits<6> op> { 986 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in 987 def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(NAME#"_e32")> { 988 let DecoderNamespace = "DPP8"; 989 } 990 } 991 992 //===------------------------- VOP2 (with name) -------------------------===// 993 multiclass VOP2_Real_e32_gfx10_with_name<bits<6> op, string opName, 994 string asmName> { 995 def _e32_gfx10 : 996 VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>, 997 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> { 998 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32"); 999 let AsmString = asmName # ps.AsmOperands; 1000 } 1001 } 1002 multiclass VOP2_Real_e64_gfx10_with_name<bits<6> op, string opName, 1003 string asmName> { 1004 def _e64_gfx10 : 1005 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>, 1006 VOP3e_gfx10<{0, 1, 0, 0, op{5-0}}, 1007 !cast<VOP3_Pseudo>(opName#"_e64").Pfl> { 1008 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1009 let AsmString = asmName # ps.AsmOperands; 1010 } 1011 } 1012 let DecoderNamespace = "SDWA10" in { 1013 multiclass VOP2_Real_sdwa_gfx10_with_name<bits<6> op, string opName, 1014 string asmName> { 1015 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in 1016 def _sdwa_gfx10 : 1017 VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>, 1018 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> { 1019 VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa"); 1020 let AsmString = asmName # ps.AsmOperands; 1021 } 1022 } 1023 multiclass VOP2_Real_dpp_gfx10_with_name<bits<6> op, string opName, 1024 string asmName> { 1025 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1026 def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp")> { 1027 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32"); 1028 let AsmString = asmName # ps.Pfl.AsmDPP16; 1029 } 1030 } 1031 multiclass VOP2_Real_dpp8_gfx10_with_name<bits<6> op, string opName, 1032 string asmName> { 1033 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1034 def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> { 1035 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32"); 1036 let AsmString = asmName # ps.Pfl.AsmDPP8; 1037 let DecoderNamespace = "DPP8"; 1038 } 1039 } 1040 } // End DecoderNamespace = "SDWA10" 1041 1042 //===------------------------------ VOP2be ------------------------------===// 1043 multiclass VOP2be_Real_e32_gfx10<bits<6> op, string opName, string asmName> { 1044 def _e32_gfx10 : 1045 VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>, 1046 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> { 1047 VOP2_Pseudo Ps = !cast<VOP2_Pseudo>(opName#"_e32"); 1048 let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands); 1049 } 1050 } 1051 multiclass VOP2be_Real_e64_gfx10<bits<6> op, string opName, string asmName> { 1052 def _e64_gfx10 : 1053 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>, 1054 VOP3be_gfx10<{0, 1, 0, 0, op{5-0}}, 1055 !cast<VOP3_Pseudo>(opName#"_e64").Pfl> { 1056 VOP3_Pseudo Ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1057 let AsmString = asmName # Ps.AsmOperands; 1058 } 1059 } 1060 multiclass VOP2be_Real_sdwa_gfx10<bits<6> op, string opName, string asmName> { 1061 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in 1062 def _sdwa_gfx10 : 1063 VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>, 1064 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> { 1065 VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa"); 1066 let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands); 1067 let DecoderNamespace = "SDWA10"; 1068 } 1069 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in 1070 def _sdwa_w32_gfx10 : 1071 Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>, 1072 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> { 1073 VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa"); 1074 let AsmString = asmName # !subst("vcc", "vcc_lo", Ps.AsmOperands); 1075 let isAsmParserOnly = 1; 1076 let DecoderNamespace = "SDWA10"; 1077 let WaveSizePredicate = isWave32; 1078 } 1079 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in 1080 def _sdwa_w64_gfx10 : 1081 Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>, 1082 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> { 1083 VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa"); 1084 let AsmString = asmName # Ps.AsmOperands; 1085 let isAsmParserOnly = 1; 1086 let DecoderNamespace = "SDWA10"; 1087 let WaveSizePredicate = isWave64; 1088 } 1089 } 1090 multiclass VOP2be_Real_dpp_gfx10<bits<6> op, string opName, string asmName> { 1091 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1092 def _dpp_gfx10 : 1093 VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> { 1094 string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16; 1095 let AsmString = asmName # !subst(", vcc", "", AsmDPP); 1096 let DecoderNamespace = "SDWA10"; 1097 } 1098 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1099 def _dpp_w32_gfx10 : 1100 Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> { 1101 string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16; 1102 let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP); 1103 let isAsmParserOnly = 1; 1104 let WaveSizePredicate = isWave32; 1105 } 1106 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1107 def _dpp_w64_gfx10 : 1108 Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> { 1109 string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16; 1110 let AsmString = asmName # AsmDPP; 1111 let isAsmParserOnly = 1; 1112 let WaveSizePredicate = isWave64; 1113 } 1114 } 1115 multiclass VOP2be_Real_dpp8_gfx10<bits<6> op, string opName, string asmName> { 1116 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1117 def _dpp8_gfx10 : 1118 VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> { 1119 string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8; 1120 let AsmString = asmName # !subst(", vcc", "", AsmDPP8); 1121 let DecoderNamespace = "DPP8"; 1122 } 1123 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1124 def _dpp8_w32_gfx10 : 1125 VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> { 1126 string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8; 1127 let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8); 1128 let isAsmParserOnly = 1; 1129 let WaveSizePredicate = isWave32; 1130 } 1131 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1132 def _dpp8_w64_gfx10 : 1133 VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> { 1134 string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8; 1135 let AsmString = asmName # AsmDPP8; 1136 let isAsmParserOnly = 1; 1137 let WaveSizePredicate = isWave64; 1138 } 1139 } 1140 1141 //===----------------------------- VOP3Only -----------------------------===// 1142 multiclass VOP3Only_Real_gfx10<bits<10> op> { 1143 def _e64_gfx10 : 1144 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 1145 VOP3e_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1146 let IsSingle = 1; 1147 } 1148 } 1149 1150 //===---------------------------- VOP3beOnly ----------------------------===// 1151 multiclass VOP3beOnly_Real_gfx10<bits<10> op> { 1152 def _e64_gfx10 : 1153 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 1154 VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1155 let IsSingle = 1; 1156 } 1157 } 1158} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" 1159 1160multiclass VOP2be_Real_gfx10<bits<6> op, string opName, string asmName> : 1161 VOP2be_Real_e32_gfx10<op, opName, asmName>, 1162 VOP2be_Real_e64_gfx10<op, opName, asmName>, 1163 VOP2be_Real_sdwa_gfx10<op, opName, asmName>, 1164 VOP2be_Real_dpp_gfx10<op, opName, asmName>, 1165 VOP2be_Real_dpp8_gfx10<op, opName, asmName>; 1166 1167multiclass VOP2e_Real_gfx10<bits<6> op, string opName, string asmName> : 1168 VOP2_Real_e32_gfx10<op>, 1169 VOP2_Real_e64_gfx10<op>, 1170 VOP2be_Real_sdwa_gfx10<op, opName, asmName>, 1171 VOP2be_Real_dpp_gfx10<op, opName, asmName>, 1172 VOP2be_Real_dpp8_gfx10<op, opName, asmName>; 1173 1174multiclass VOP2_Real_gfx10<bits<6> op> : 1175 VOP2_Real_e32_gfx10<op>, VOP2_Real_e64_gfx10<op>, 1176 VOP2_Real_sdwa_gfx10<op>, VOP2_Real_dpp_gfx10<op>, VOP2_Real_dpp8_gfx10<op>; 1177 1178multiclass VOP2_Real_gfx10_with_name<bits<6> op, string opName, 1179 string asmName> : 1180 VOP2_Real_e32_gfx10_with_name<op, opName, asmName>, 1181 VOP2_Real_e64_gfx10_with_name<op, opName, asmName>, 1182 VOP2_Real_sdwa_gfx10_with_name<op, opName, asmName>, 1183 VOP2_Real_dpp_gfx10_with_name<op, opName, asmName>, 1184 VOP2_Real_dpp8_gfx10_with_name<op, opName, asmName>; 1185 1186// NB: Same opcode as v_mac_legacy_f32 1187let DecoderNamespace = "GFX10_B" in 1188defm V_FMAC_LEGACY_F32 : VOP2_Real_gfx10<0x006>; 1189 1190defm V_XNOR_B32 : VOP2_Real_gfx10<0x01e>; 1191defm V_FMAC_F32 : VOP2_Real_gfx10<0x02b>; 1192defm V_FMAMK_F32 : VOP2Only_Real_MADK_gfx10<0x02c>; 1193defm V_FMAAK_F32 : VOP2Only_Real_MADK_gfx10<0x02d>; 1194defm V_ADD_F16 : VOP2_Real_gfx10<0x032>; 1195defm V_SUB_F16 : VOP2_Real_gfx10<0x033>; 1196defm V_SUBREV_F16 : VOP2_Real_gfx10<0x034>; 1197defm V_MUL_F16 : VOP2_Real_gfx10<0x035>; 1198defm V_FMAC_F16 : VOP2_Real_gfx10<0x036>; 1199defm V_FMAMK_F16 : VOP2Only_Real_MADK_gfx10<0x037>; 1200defm V_FMAAK_F16 : VOP2Only_Real_MADK_gfx10<0x038>; 1201defm V_MAX_F16 : VOP2_Real_gfx10<0x039>; 1202defm V_MIN_F16 : VOP2_Real_gfx10<0x03a>; 1203defm V_LDEXP_F16 : VOP2_Real_gfx10<0x03b>; 1204 1205let IsSingle = 1 in { 1206defm V_PK_FMAC_F16 : VOP2_Real_e32_gfx10<0x03c>; 1207} 1208 1209// VOP2 no carry-in, carry-out. 1210defm V_ADD_NC_U32 : 1211 VOP2_Real_gfx10_with_name<0x025, "V_ADD_U32", "v_add_nc_u32">; 1212defm V_SUB_NC_U32 : 1213 VOP2_Real_gfx10_with_name<0x026, "V_SUB_U32", "v_sub_nc_u32">; 1214defm V_SUBREV_NC_U32 : 1215 VOP2_Real_gfx10_with_name<0x027, "V_SUBREV_U32", "v_subrev_nc_u32">; 1216 1217// VOP2 carry-in, carry-out. 1218defm V_ADD_CO_CI_U32 : 1219 VOP2be_Real_gfx10<0x028, "V_ADDC_U32", "v_add_co_ci_u32">; 1220defm V_SUB_CO_CI_U32 : 1221 VOP2be_Real_gfx10<0x029, "V_SUBB_U32", "v_sub_co_ci_u32">; 1222defm V_SUBREV_CO_CI_U32 : 1223 VOP2be_Real_gfx10<0x02a, "V_SUBBREV_U32", "v_subrev_co_ci_u32">; 1224 1225defm V_CNDMASK_B32 : 1226 VOP2e_Real_gfx10<0x001, "V_CNDMASK_B32", "v_cndmask_b32">; 1227 1228// VOP3 only. 1229defm V_BFM_B32 : VOP3Only_Real_gfx10<0x363>; 1230defm V_BCNT_U32_B32 : VOP3Only_Real_gfx10<0x364>; 1231defm V_MBCNT_LO_U32_B32 : VOP3Only_Real_gfx10<0x365>; 1232defm V_MBCNT_HI_U32_B32 : VOP3Only_Real_gfx10<0x366>; 1233defm V_LDEXP_F32 : VOP3Only_Real_gfx10<0x362>; 1234defm V_CVT_PKNORM_I16_F32 : VOP3Only_Real_gfx10<0x368>; 1235defm V_CVT_PKNORM_U16_F32 : VOP3Only_Real_gfx10<0x369>; 1236defm V_CVT_PK_U16_U32 : VOP3Only_Real_gfx10<0x36a>; 1237defm V_CVT_PK_I16_I32 : VOP3Only_Real_gfx10<0x36b>; 1238 1239// VOP3 carry-out. 1240defm V_ADD_CO_U32 : VOP3beOnly_Real_gfx10<0x30f>; 1241defm V_SUB_CO_U32 : VOP3beOnly_Real_gfx10<0x310>; 1242defm V_SUBREV_CO_U32 : VOP3beOnly_Real_gfx10<0x319>; 1243 1244let SubtargetPredicate = isGFX10Plus in { 1245 defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx10>; 1246 1247 defm : VOP2bInstAliases< 1248 V_ADDC_U32_e32, V_ADD_CO_CI_U32_e32_gfx10, "v_add_co_ci_u32">; 1249 defm : VOP2bInstAliases< 1250 V_SUBB_U32_e32, V_SUB_CO_CI_U32_e32_gfx10, "v_sub_co_ci_u32">; 1251 defm : VOP2bInstAliases< 1252 V_SUBBREV_U32_e32, V_SUBREV_CO_CI_U32_e32_gfx10, "v_subrev_co_ci_u32">; 1253} // End SubtargetPredicate = isGFX10Plus 1254 1255//===----------------------------------------------------------------------===// 1256// GFX6, GFX7, GFX10. 1257//===----------------------------------------------------------------------===// 1258 1259class VOP2_DPPe <bits<6> op, VOP2_DPP_Pseudo ps, VOPProfile P = ps.Pfl> : 1260 VOP_DPPe <P> { 1261 bits<8> vdst; 1262 bits<8> src1; 1263 let Inst{8-0} = 0xfa; //dpp 1264 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 1265 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 1266 let Inst{30-25} = op; 1267 let Inst{31} = 0x0; //encoding 1268} 1269 1270let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in { 1271 multiclass VOP2_Lane_Real_gfx6_gfx7<bits<6> op> { 1272 def _gfx6_gfx7 : 1273 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>, 1274 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 1275 } 1276 multiclass VOP2Only_Real_MADK_gfx6_gfx7<bits<6> op> { 1277 def _gfx6_gfx7 : 1278 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>, 1279 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 1280 } 1281 multiclass VOP2_Real_e32_gfx6_gfx7<bits<6> op, string PseudoName = NAME> { 1282 def _e32_gfx6_gfx7 : 1283 VOP2_Real<!cast<VOP2_Pseudo>(PseudoName#"_e32"), SIEncodingFamily.SI>, 1284 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(PseudoName#"_e32").Pfl>; 1285 } 1286 multiclass VOP2_Real_e64_gfx6_gfx7<bits<6> op, string PseudoName = NAME> { 1287 def _e64_gfx6_gfx7 : 1288 VOP3_Real<!cast<VOP3_Pseudo>(PseudoName#"_e64"), SIEncodingFamily.SI>, 1289 VOP3e_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(PseudoName#"_e64").Pfl>; 1290 } 1291 multiclass VOP2be_Real_e64_gfx6_gfx7<bits<6> op, string PseudoName = NAME> { 1292 def _e64_gfx6_gfx7 : 1293 VOP3_Real<!cast<VOP3_Pseudo>(PseudoName#"_e64"), SIEncodingFamily.SI>, 1294 VOP3be_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(PseudoName#"_e64").Pfl>; 1295 } 1296} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" 1297 1298multiclass VOP2Only_Real_MADK_gfx6_gfx7_gfx10<bits<6> op> : 1299 VOP2Only_Real_MADK_gfx6_gfx7<op>, VOP2Only_Real_MADK_gfx10<op>; 1300 1301multiclass VOP2_Real_gfx6_gfx7<bits<6> op> : 1302 VOP2_Real_e32_gfx6_gfx7<op>, VOP2_Real_e64_gfx6_gfx7<op>; 1303 1304multiclass VOP2_Real_gfx6_gfx7_gfx10<bits<6> op> : 1305 VOP2_Real_gfx6_gfx7<op>, VOP2_Real_gfx10<op>; 1306 1307multiclass VOP2be_Real_gfx6_gfx7<bits<6> op> : 1308 VOP2_Real_e32_gfx6_gfx7<op>, VOP2be_Real_e64_gfx6_gfx7<op>; 1309 1310multiclass VOP2be_Real_gfx6_gfx7_with_name<bits<6> op, 1311 string PseudoName, string asmName> { 1312 defvar ps32 = !cast<VOP2_Pseudo>(PseudoName#"_e32"); 1313 defvar ps64 = !cast<VOP3_Pseudo>(PseudoName#"_e64"); 1314 1315 let AsmString = asmName # ps32.AsmOperands in { 1316 defm "" : VOP2_Real_e32_gfx6_gfx7<op, PseudoName>; 1317 } 1318 1319 let AsmString = asmName # ps64.AsmOperands in { 1320 defm "" : VOP2be_Real_e64_gfx6_gfx7<op, PseudoName>; 1321 } 1322} 1323 1324defm V_CNDMASK_B32 : VOP2_Real_gfx6_gfx7<0x000>; 1325defm V_MIN_LEGACY_F32 : VOP2_Real_gfx6_gfx7<0x00d>; 1326defm V_MAX_LEGACY_F32 : VOP2_Real_gfx6_gfx7<0x00e>; 1327defm V_LSHR_B32 : VOP2_Real_gfx6_gfx7<0x015>; 1328defm V_ASHR_I32 : VOP2_Real_gfx6_gfx7<0x017>; 1329defm V_LSHL_B32 : VOP2_Real_gfx6_gfx7<0x019>; 1330defm V_BFM_B32 : VOP2_Real_gfx6_gfx7<0x01e>; 1331defm V_BCNT_U32_B32 : VOP2_Real_gfx6_gfx7<0x022>; 1332defm V_MBCNT_LO_U32_B32 : VOP2_Real_gfx6_gfx7<0x023>; 1333defm V_MBCNT_HI_U32_B32 : VOP2_Real_gfx6_gfx7<0x024>; 1334defm V_LDEXP_F32 : VOP2_Real_gfx6_gfx7<0x02b>; 1335defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_gfx6_gfx7<0x02c>; 1336defm V_CVT_PKNORM_I16_F32 : VOP2_Real_gfx6_gfx7<0x02d>; 1337defm V_CVT_PKNORM_U16_F32 : VOP2_Real_gfx6_gfx7<0x02e>; 1338defm V_CVT_PK_U16_U32 : VOP2_Real_gfx6_gfx7<0x030>; 1339defm V_CVT_PK_I16_I32 : VOP2_Real_gfx6_gfx7<0x031>; 1340 1341// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in 1342// VI, but the VI instructions behave the same as the SI versions. 1343defm V_ADD_I32 : VOP2be_Real_gfx6_gfx7_with_name<0x025, "V_ADD_CO_U32", "v_add_i32">; 1344defm V_SUB_I32 : VOP2be_Real_gfx6_gfx7_with_name<0x026, "V_SUB_CO_U32", "v_sub_i32">; 1345defm V_SUBREV_I32 : VOP2be_Real_gfx6_gfx7_with_name<0x027, "V_SUBREV_CO_U32", "v_subrev_i32">; 1346defm V_ADDC_U32 : VOP2be_Real_gfx6_gfx7<0x028>; 1347defm V_SUBB_U32 : VOP2be_Real_gfx6_gfx7<0x029>; 1348defm V_SUBBREV_U32 : VOP2be_Real_gfx6_gfx7<0x02a>; 1349 1350defm V_READLANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x001>; 1351 1352let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in { 1353 defm V_WRITELANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x002>; 1354} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) 1355 1356let SubtargetPredicate = isGFX6GFX7 in { 1357 defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx6_gfx7>; 1358 defm : VOP2eInstAliases<V_ADD_CO_U32_e32, V_ADD_I32_e32_gfx6_gfx7>; 1359 defm : VOP2eInstAliases<V_SUB_CO_U32_e32, V_SUB_I32_e32_gfx6_gfx7>; 1360 defm : VOP2eInstAliases<V_SUBREV_CO_U32_e32, V_SUBREV_I32_e32_gfx6_gfx7>; 1361 1362 def : VOP2e64InstAlias<V_ADD_CO_U32_e64, V_ADD_I32_e64_gfx6_gfx7>; 1363 def : VOP2e64InstAlias<V_SUB_CO_U32_e64, V_SUB_I32_e64_gfx6_gfx7>; 1364 def : VOP2e64InstAlias<V_SUBREV_CO_U32_e64, V_SUBREV_I32_e64_gfx6_gfx7>; 1365} // End SubtargetPredicate = isGFX6GFX7 1366 1367defm V_ADD_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x003>; 1368defm V_SUB_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x004>; 1369defm V_SUBREV_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x005>; 1370defm V_MAC_LEGACY_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x006>; 1371defm V_MUL_LEGACY_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x007>; 1372defm V_MUL_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x008>; 1373defm V_MUL_I32_I24 : VOP2_Real_gfx6_gfx7_gfx10<0x009>; 1374defm V_MUL_HI_I32_I24 : VOP2_Real_gfx6_gfx7_gfx10<0x00a>; 1375defm V_MUL_U32_U24 : VOP2_Real_gfx6_gfx7_gfx10<0x00b>; 1376defm V_MUL_HI_U32_U24 : VOP2_Real_gfx6_gfx7_gfx10<0x00c>; 1377defm V_MIN_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x00f>; 1378defm V_MAX_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x010>; 1379defm V_MIN_I32 : VOP2_Real_gfx6_gfx7_gfx10<0x011>; 1380defm V_MAX_I32 : VOP2_Real_gfx6_gfx7_gfx10<0x012>; 1381defm V_MIN_U32 : VOP2_Real_gfx6_gfx7_gfx10<0x013>; 1382defm V_MAX_U32 : VOP2_Real_gfx6_gfx7_gfx10<0x014>; 1383defm V_LSHRREV_B32 : VOP2_Real_gfx6_gfx7_gfx10<0x016>; 1384defm V_ASHRREV_I32 : VOP2_Real_gfx6_gfx7_gfx10<0x018>; 1385defm V_LSHLREV_B32 : VOP2_Real_gfx6_gfx7_gfx10<0x01a>; 1386defm V_AND_B32 : VOP2_Real_gfx6_gfx7_gfx10<0x01b>; 1387defm V_OR_B32 : VOP2_Real_gfx6_gfx7_gfx10<0x01c>; 1388defm V_XOR_B32 : VOP2_Real_gfx6_gfx7_gfx10<0x01d>; 1389defm V_MAC_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x01f>; 1390defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x02f>; 1391defm V_MADMK_F32 : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x020>; 1392defm V_MADAK_F32 : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x021>; 1393 1394//===----------------------------------------------------------------------===// 1395// GFX8, GFX9 (VI). 1396//===----------------------------------------------------------------------===// 1397 1398let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in { 1399 1400multiclass VOP2_Real_MADK_vi <bits<6> op> { 1401 def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>, 1402 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 1403} 1404 1405multiclass VOP2_Real_e32_vi <bits<6> op> { 1406 def _e32_vi : 1407 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>, 1408 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 1409} 1410 1411multiclass VOP2_Real_e64_vi <bits<10> op> { 1412 def _e64_vi : 1413 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1414 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1415} 1416 1417multiclass VOP2_Real_e64only_vi <bits<10> op> { 1418 def _e64_vi : 1419 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1420 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1421 let IsSingle = 1; 1422 } 1423} 1424 1425multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> : 1426 VOP2_Real_e32_vi<op>, 1427 VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>; 1428 1429} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" 1430 1431multiclass VOP2_SDWA_Real <bits<6> op> { 1432 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA>.ret in 1433 def _sdwa_vi : 1434 VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 1435 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 1436} 1437 1438multiclass VOP2_SDWA9_Real <bits<6> op> { 1439 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in 1440 def _sdwa_gfx9 : 1441 VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 1442 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 1443} 1444 1445let AssemblerPredicate = isGFX8Only in { 1446 1447multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName> { 1448 def _e32_vi : 1449 VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.VI>, 1450 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> { 1451 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32"); 1452 let AsmString = AsmName # ps.AsmOperands; 1453 let DecoderNamespace = "GFX8"; 1454 } 1455 def _e64_vi : 1456 VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.VI>, 1457 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> { 1458 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64"); 1459 let AsmString = AsmName # ps.AsmOperands; 1460 let DecoderNamespace = "GFX8"; 1461 } 1462 foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA>.ret in 1463 def _sdwa_vi : 1464 VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>, 1465 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> { 1466 VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa"); 1467 let AsmString = AsmName # ps.AsmOperands; 1468 } 1469 foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in 1470 def _dpp_vi : 1471 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.VI>, 1472 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> { 1473 VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp"); 1474 let AsmString = AsmName # ps.AsmOperands; 1475 } 1476} 1477} 1478 1479let AssemblerPredicate = isGFX9Only in { 1480 1481multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> { 1482 def _e32_gfx9 : 1483 VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.GFX9>, 1484 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> { 1485 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32"); 1486 let AsmString = AsmName # ps.AsmOperands; 1487 let DecoderNamespace = "GFX9"; 1488 } 1489 def _e64_gfx9 : 1490 VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>, 1491 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> { 1492 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64"); 1493 let AsmString = AsmName # ps.AsmOperands; 1494 let DecoderNamespace = "GFX9"; 1495 } 1496 foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA9>.ret in 1497 def _sdwa_gfx9 : 1498 VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>, 1499 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> { 1500 VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa"); 1501 let AsmString = AsmName # ps.AsmOperands; 1502 } 1503 foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in 1504 def _dpp_gfx9 : 1505 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.GFX9>, 1506 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> { 1507 VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp"); 1508 let AsmString = AsmName # ps.AsmOperands; 1509 let DecoderNamespace = "SDWA9"; 1510 } 1511} 1512 1513multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> { 1514 def _e32_gfx9 : 1515 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX9>, 1516 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>{ 1517 let DecoderNamespace = "GFX9"; 1518 } 1519 def _e64_gfx9 : 1520 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>, 1521 VOP3e_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1522 let DecoderNamespace = "GFX9"; 1523 } 1524 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in 1525 def _sdwa_gfx9 : 1526 VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 1527 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> { 1528 } 1529 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in 1530 def _dpp_gfx9 : 1531 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>, 1532 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> { 1533 let DecoderNamespace = "SDWA9"; 1534 } 1535} 1536 1537} // AssemblerPredicate = isGFX9Only 1538 1539multiclass VOP2_Real_e32e64_vi <bits<6> op> : 1540 Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> { 1541 1542 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in 1543 def _dpp_vi : 1544 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.VI>, 1545 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>; 1546} 1547 1548defm V_CNDMASK_B32 : VOP2_Real_e32e64_vi <0x0>; 1549defm V_ADD_F32 : VOP2_Real_e32e64_vi <0x1>; 1550defm V_SUB_F32 : VOP2_Real_e32e64_vi <0x2>; 1551defm V_SUBREV_F32 : VOP2_Real_e32e64_vi <0x3>; 1552let AssemblerPredicate = isGCN3ExcludingGFX90A in 1553defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_vi <0x4>; 1554defm V_MUL_F32 : VOP2_Real_e32e64_vi <0x5>; 1555defm V_MUL_I32_I24 : VOP2_Real_e32e64_vi <0x6>; 1556defm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_vi <0x7>; 1557defm V_MUL_U32_U24 : VOP2_Real_e32e64_vi <0x8>; 1558defm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_vi <0x9>; 1559defm V_MIN_F32 : VOP2_Real_e32e64_vi <0xa>; 1560defm V_MAX_F32 : VOP2_Real_e32e64_vi <0xb>; 1561defm V_MIN_I32 : VOP2_Real_e32e64_vi <0xc>; 1562defm V_MAX_I32 : VOP2_Real_e32e64_vi <0xd>; 1563defm V_MIN_U32 : VOP2_Real_e32e64_vi <0xe>; 1564defm V_MAX_U32 : VOP2_Real_e32e64_vi <0xf>; 1565defm V_LSHRREV_B32 : VOP2_Real_e32e64_vi <0x10>; 1566defm V_ASHRREV_I32 : VOP2_Real_e32e64_vi <0x11>; 1567defm V_LSHLREV_B32 : VOP2_Real_e32e64_vi <0x12>; 1568defm V_AND_B32 : VOP2_Real_e32e64_vi <0x13>; 1569defm V_OR_B32 : VOP2_Real_e32e64_vi <0x14>; 1570defm V_XOR_B32 : VOP2_Real_e32e64_vi <0x15>; 1571defm V_MAC_F32 : VOP2_Real_e32e64_vi <0x16>; 1572defm V_MADMK_F32 : VOP2_Real_MADK_vi <0x17>; 1573defm V_MADAK_F32 : VOP2_Real_MADK_vi <0x18>; 1574 1575defm V_ADD_U32 : VOP2be_Real_e32e64_vi_only <0x19, "V_ADD_CO_U32", "v_add_u32">; 1576defm V_SUB_U32 : VOP2be_Real_e32e64_vi_only <0x1a, "V_SUB_CO_U32", "v_sub_u32">; 1577defm V_SUBREV_U32 : VOP2be_Real_e32e64_vi_only <0x1b, "V_SUBREV_CO_U32", "v_subrev_u32">; 1578defm V_ADDC_U32 : VOP2be_Real_e32e64_vi_only <0x1c, "V_ADDC_U32", "v_addc_u32">; 1579defm V_SUBB_U32 : VOP2be_Real_e32e64_vi_only <0x1d, "V_SUBB_U32", "v_subb_u32">; 1580defm V_SUBBREV_U32 : VOP2be_Real_e32e64_vi_only <0x1e, "V_SUBBREV_U32", "v_subbrev_u32">; 1581 1582defm V_ADD_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x19, "V_ADD_CO_U32", "v_add_co_u32">; 1583defm V_SUB_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1a, "V_SUB_CO_U32", "v_sub_co_u32">; 1584defm V_SUBREV_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1b, "V_SUBREV_CO_U32", "v_subrev_co_u32">; 1585defm V_ADDC_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1c, "V_ADDC_U32", "v_addc_co_u32">; 1586defm V_SUBB_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1d, "V_SUBB_U32", "v_subb_co_u32">; 1587defm V_SUBBREV_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1e, "V_SUBBREV_U32", "v_subbrev_co_u32">; 1588 1589defm V_ADD_U32 : VOP2_Real_e32e64_gfx9 <0x34>; 1590defm V_SUB_U32 : VOP2_Real_e32e64_gfx9 <0x35>; 1591defm V_SUBREV_U32 : VOP2_Real_e32e64_gfx9 <0x36>; 1592 1593defm V_BFM_B32 : VOP2_Real_e64only_vi <0x293>; 1594defm V_BCNT_U32_B32 : VOP2_Real_e64only_vi <0x28b>; 1595defm V_MBCNT_LO_U32_B32 : VOP2_Real_e64only_vi <0x28c>; 1596defm V_MBCNT_HI_U32_B32 : VOP2_Real_e64only_vi <0x28d>; 1597defm V_LDEXP_F32 : VOP2_Real_e64only_vi <0x288>; 1598defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64only_vi <0x1f0>; 1599defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64only_vi <0x294>; 1600defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64only_vi <0x295>; 1601defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e64only_vi <0x296>; 1602defm V_CVT_PK_U16_U32 : VOP2_Real_e64only_vi <0x297>; 1603defm V_CVT_PK_I16_I32 : VOP2_Real_e64only_vi <0x298>; 1604 1605defm V_ADD_F16 : VOP2_Real_e32e64_vi <0x1f>; 1606defm V_SUB_F16 : VOP2_Real_e32e64_vi <0x20>; 1607defm V_SUBREV_F16 : VOP2_Real_e32e64_vi <0x21>; 1608defm V_MUL_F16 : VOP2_Real_e32e64_vi <0x22>; 1609defm V_MAC_F16 : VOP2_Real_e32e64_vi <0x23>; 1610defm V_MADMK_F16 : VOP2_Real_MADK_vi <0x24>; 1611defm V_MADAK_F16 : VOP2_Real_MADK_vi <0x25>; 1612defm V_ADD_U16 : VOP2_Real_e32e64_vi <0x26>; 1613defm V_SUB_U16 : VOP2_Real_e32e64_vi <0x27>; 1614defm V_SUBREV_U16 : VOP2_Real_e32e64_vi <0x28>; 1615defm V_MUL_LO_U16 : VOP2_Real_e32e64_vi <0x29>; 1616defm V_LSHLREV_B16 : VOP2_Real_e32e64_vi <0x2a>; 1617defm V_LSHRREV_B16 : VOP2_Real_e32e64_vi <0x2b>; 1618defm V_ASHRREV_I16 : VOP2_Real_e32e64_vi <0x2c>; 1619defm V_MAX_F16 : VOP2_Real_e32e64_vi <0x2d>; 1620defm V_MIN_F16 : VOP2_Real_e32e64_vi <0x2e>; 1621defm V_MAX_U16 : VOP2_Real_e32e64_vi <0x2f>; 1622defm V_MAX_I16 : VOP2_Real_e32e64_vi <0x30>; 1623defm V_MIN_U16 : VOP2_Real_e32e64_vi <0x31>; 1624defm V_MIN_I16 : VOP2_Real_e32e64_vi <0x32>; 1625defm V_LDEXP_F16 : VOP2_Real_e32e64_vi <0x33>; 1626 1627let SubtargetPredicate = isGFX8GFX9 in { 1628 1629// Aliases to simplify matching of floating-point instructions that 1630// are VOP2 on SI and VOP3 on VI. 1631class SI2_VI3Alias <string name, VOP3_Real inst> : InstAlias < 1632 name#" $dst, $src0, $src1", 1633 !if(inst.Pfl.HasOMod, 1634 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0), 1635 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0)) 1636>, PredicateControl { 1637 let UseInstAsmMatchConverter = 0; 1638 let AsmVariantName = AMDGPUAsmVariants.VOP3; 1639} 1640 1641def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>; 1642def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>; 1643def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>; 1644def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>; 1645def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>; 1646 1647defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_vi>; 1648 1649} // End SubtargetPredicate = isGFX8GFX9 1650 1651let SubtargetPredicate = isGFX9Only in { 1652 1653defm : VOP2bInstAliases<V_ADD_U32_e32, V_ADD_CO_U32_e32_gfx9, "v_add_co_u32">; 1654defm : VOP2bInstAliases<V_ADDC_U32_e32, V_ADDC_CO_U32_e32_gfx9, "v_addc_co_u32">; 1655defm : VOP2bInstAliases<V_SUB_U32_e32, V_SUB_CO_U32_e32_gfx9, "v_sub_co_u32">; 1656defm : VOP2bInstAliases<V_SUBB_U32_e32, V_SUBB_CO_U32_e32_gfx9, "v_subb_co_u32">; 1657defm : VOP2bInstAliases<V_SUBREV_U32_e32, V_SUBREV_CO_U32_e32_gfx9, "v_subrev_co_u32">; 1658defm : VOP2bInstAliases<V_SUBBREV_U32_e32, V_SUBBREV_CO_U32_e32_gfx9, "v_subbrev_co_u32">; 1659 1660} // End SubtargetPredicate = isGFX9Only 1661 1662let SubtargetPredicate = HasDLInsts in { 1663 1664defm V_FMAC_F32 : VOP2_Real_e32e64_vi <0x3b>; 1665defm V_XNOR_B32 : VOP2_Real_e32e64_vi <0x3d>; 1666 1667} // End SubtargetPredicate = HasDLInsts 1668 1669let AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A" in { 1670 multiclass VOP2_Real_e32_gfx90a <bits<6> op> { 1671 def _e32_gfx90a : 1672 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX90A>, 1673 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 1674 } 1675 1676 multiclass VOP2_Real_e64_gfx90a <bits<10> op> { 1677 def _e64_gfx90a : 1678 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX90A>, 1679 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1680 } 1681 1682 multiclass Base_VOP2_Real_e32e64_gfx90a <bits<6> op> : 1683 VOP2_Real_e32_gfx90a<op>, 1684 VOP2_Real_e64_gfx90a<{0, 1, 0, 0, op{5-0}}>; 1685 1686 multiclass VOP2_Real_e32e64_gfx90a <bits<6> op> : 1687 Base_VOP2_Real_e32e64_gfx90a<op> { 1688 1689 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in 1690 def _dpp_gfx90a : 1691 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX90A>, 1692 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> { 1693 let DecoderNamespace = "SDWA9"; 1694 } 1695 } 1696} // End AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A" 1697 1698let SubtargetPredicate = isGFX90APlus in { 1699 defm V_FMAC_F64 : VOP2_Real_e32e64_gfx90a <0x4>; 1700 let IsSingle = 1 in { 1701 defm V_MUL_LEGACY_F32 : VOP2_Real_e64_gfx90a <0x2a1>; 1702 } 1703} // End SubtargetPredicate = isGFX90APlus 1704 1705multiclass VOP2_Real_DOT_ACC_gfx9<bits<6> op> : VOP2_Real_e32_vi<op> { 1706 def _dpp_vi : VOP2_DPP<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>; 1707} 1708 1709multiclass VOP2_Real_DOT_ACC_gfx10<bits<6> op> : 1710 VOP2_Real_e32_gfx10<op>, 1711 VOP2_Real_dpp_gfx10<op>, 1712 VOP2_Real_dpp8_gfx10<op>; 1713 1714let SubtargetPredicate = HasDot5Insts in { 1715 defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx9<0x37>; 1716 // NB: Opcode conflicts with V_DOT8C_I32_I4 1717 // This opcode exists in gfx 10.1* only 1718 defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx10<0x02>; 1719} 1720 1721let SubtargetPredicate = HasDot6Insts in { 1722 defm V_DOT4C_I32_I8 : VOP2_Real_DOT_ACC_gfx9<0x39>; 1723 defm V_DOT4C_I32_I8 : VOP2_Real_DOT_ACC_gfx10<0x0d>; 1724} 1725 1726let SubtargetPredicate = HasDot4Insts in { 1727 defm V_DOT2C_I32_I16 : VOP2_Real_DOT_ACC_gfx9<0x38>; 1728} 1729let SubtargetPredicate = HasDot3Insts in { 1730 defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx9<0x3a>; 1731} 1732 1733let SubtargetPredicate = HasPkFmacF16Inst in { 1734defm V_PK_FMAC_F16 : VOP2_Real_e32_vi<0x3c>; 1735} // End SubtargetPredicate = HasPkFmacF16Inst 1736 1737let SubtargetPredicate = HasDot3Insts in { 1738 // NB: Opcode conflicts with V_DOT2C_F32_F16 1739 let DecoderNamespace = "GFX10_B" in 1740 defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx10<0x02>; 1741} 1742