1//===-- VOP2Instructions.td - Vector Instruction Defintions ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// VOP2 Classes 12//===----------------------------------------------------------------------===// 13 14class VOP2e <bits<6> op, VOPProfile P> : Enc32 { 15 bits<8> vdst; 16 bits<9> src0; 17 bits<8> src1; 18 19 let Inst{8-0} = !if(P.HasSrc0, src0, 0); 20 let Inst{16-9} = !if(P.HasSrc1, src1, 0); 21 let Inst{24-17} = !if(P.EmitDst, vdst, 0); 22 let Inst{30-25} = op; 23 let Inst{31} = 0x0; //encoding 24} 25 26class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 { 27 bits<8> vdst; 28 bits<9> src0; 29 bits<8> src1; 30 bits<32> imm; 31 32 let Inst{8-0} = !if(P.HasSrc0, src0, 0); 33 let Inst{16-9} = !if(P.HasSrc1, src1, 0); 34 let Inst{24-17} = !if(P.EmitDst, vdst, 0); 35 let Inst{30-25} = op; 36 let Inst{31} = 0x0; // encoding 37 let Inst{63-32} = imm; 38} 39 40class VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> { 41 bits<8> vdst; 42 bits<8> src1; 43 44 let Inst{8-0} = 0xf9; // sdwa 45 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 46 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 47 let Inst{30-25} = op; 48 let Inst{31} = 0x0; // encoding 49} 50 51class VOP2_SDWA9Ae <bits<6> op, VOPProfile P> : VOP_SDWA9Ae <P> { 52 bits<8> vdst; 53 bits<9> src1; 54 55 let Inst{8-0} = 0xf9; // sdwa 56 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 57 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 58 let Inst{30-25} = op; 59 let Inst{31} = 0x0; // encoding 60 let Inst{63} = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr 61} 62 63class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> : 64 InstSI <P.Outs32, P.Ins32, "", pattern>, 65 VOP <opName>, 66 SIMCInstr <opName#suffix, SIEncodingFamily.NONE>, 67 MnemonicAlias<opName#suffix, opName> { 68 69 let isPseudo = 1; 70 let isCodeGenOnly = 1; 71 let UseNamedOperandTable = 1; 72 73 string Mnemonic = opName; 74 string AsmOperands = P.Asm32; 75 76 let Size = 4; 77 let mayLoad = 0; 78 let mayStore = 0; 79 let hasSideEffects = 0; 80 let SubtargetPredicate = isGCN; 81 82 let VOP2 = 1; 83 let VALU = 1; 84 let Uses = [EXEC]; 85 86 let AsmVariantName = AMDGPUAsmVariants.Default; 87 88 VOPProfile Pfl = P; 89} 90 91class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> : 92 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 93 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 94 95 let isPseudo = 0; 96 let isCodeGenOnly = 0; 97 98 let Constraints = ps.Constraints; 99 let DisableEncoding = ps.DisableEncoding; 100 101 // copy relevant pseudo op flags 102 let SubtargetPredicate = ps.SubtargetPredicate; 103 let AsmMatchConverter = ps.AsmMatchConverter; 104 let AsmVariantName = ps.AsmVariantName; 105 let Constraints = ps.Constraints; 106 let DisableEncoding = ps.DisableEncoding; 107 let TSFlags = ps.TSFlags; 108 let UseNamedOperandTable = ps.UseNamedOperandTable; 109 let Uses = ps.Uses; 110} 111 112class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : 113 VOP_SDWA_Pseudo <OpName, P, pattern> { 114 let AsmMatchConverter = "cvtSdwaVOP2"; 115} 116 117class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies { 118 list<dag> ret = !if(P.HasModifiers, 119 [(set P.DstVT:$vdst, 120 (node (P.Src0VT 121 !if(P.HasOMod, 122 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 123 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))), 124 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], 125 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]); 126} 127 128multiclass VOP2Inst <string opName, 129 VOPProfile P, 130 SDPatternOperator node = null_frag, 131 string revOp = opName> { 132 133 def _e32 : VOP2_Pseudo <opName, P>, 134 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>; 135 136 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>, 137 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>; 138 139 def _sdwa : VOP2_SDWA_Pseudo <opName, P>; 140} 141 142multiclass VOP2bInst <string opName, 143 VOPProfile P, 144 SDPatternOperator node = null_frag, 145 string revOp = opName, 146 bit useSGPRInput = !eq(P.NumSrcArgs, 3)> { 147 148 let SchedRW = [Write32Bit, WriteSALU] in { 149 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in { 150 def _e32 : VOP2_Pseudo <opName, P>, 151 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>; 152 153 def _sdwa : VOP2_SDWA_Pseudo <opName, P> { 154 let AsmMatchConverter = "cvtSdwaVOP2b"; 155 } 156 } 157 158 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>, 159 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>; 160 } 161} 162 163multiclass VOP2eInst <string opName, 164 VOPProfile P, 165 SDPatternOperator node = null_frag, 166 string revOp = opName, 167 bit useSGPRInput = !eq(P.NumSrcArgs, 3)> { 168 169 let SchedRW = [Write32Bit] in { 170 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in { 171 def _e32 : VOP2_Pseudo <opName, P>, 172 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>; 173 } 174 175 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>, 176 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>; 177 } 178} 179 180class VOP_MADAK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> { 181 field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm); 182 field dag Ins32 = (ins VCSrc_f32:$src0, VGPR_32:$src1, ImmOpType:$imm); 183 field bit HasExt = 0; 184 185 // Hack to stop printing _e64 186 let DstRC = RegisterOperand<VGPR_32>; 187 field string Asm32 = " $vdst, $src0, $src1, $imm"; 188} 189 190def VOP_MADAK_F16 : VOP_MADAK <f16>; 191def VOP_MADAK_F32 : VOP_MADAK <f32>; 192 193class VOP_MADMK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> { 194 field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm); 195 field dag Ins32 = (ins VCSrc_f32:$src0, ImmOpType:$imm, VGPR_32:$src1); 196 field bit HasExt = 0; 197 198 // Hack to stop printing _e64 199 let DstRC = RegisterOperand<VGPR_32>; 200 field string Asm32 = " $vdst, $src0, $imm, $src1"; 201} 202 203def VOP_MADMK_F16 : VOP_MADMK <f16>; 204def VOP_MADMK_F32 : VOP_MADMK <f32>; 205 206// FIXME: Remove src2_modifiers. It isn't used, so is wasting memory 207// and processing time but it makes it easier to convert to mad. 208class VOP_MAC <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> { 209 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2); 210 let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3, 211 0, HasModifiers, HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret; 212 let InsDPP = (ins DstRCDPP:$old, 213 Src0ModDPP:$src0_modifiers, Src0DPP:$src0, 214 Src1ModDPP:$src1_modifiers, Src1DPP:$src1, 215 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 216 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 217 218 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 219 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 220 VGPR_32:$src2, // stub argument 221 clampmod:$clamp, omod:$omod, 222 dst_sel:$dst_sel, dst_unused:$dst_unused, 223 src0_sel:$src0_sel, src1_sel:$src1_sel); 224 let Asm32 = getAsm32<1, 2, vt>.ret; 225 let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, vt>.ret; 226 let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt>.ret; 227 let AsmSDWA = getAsmSDWA<1, 2, vt>.ret; 228 let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt>.ret; 229 let HasSrc2 = 0; 230 let HasSrc2Mods = 0; 231 let HasExt = 1; 232 let HasSDWA9 = 0; 233} 234 235def VOP_MAC_F16 : VOP_MAC <f16> { 236 // FIXME: Move 'Asm64' definition to VOP_MAC, and use 'vt'. Currently it gives 237 // 'not a string initializer' error. 238 let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, f16>.ret; 239} 240 241def VOP_MAC_F32 : VOP_MAC <f32> { 242 // FIXME: Move 'Asm64' definition to VOP_MAC, and use 'vt'. Currently it gives 243 // 'not a string initializer' error. 244 let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, f32>.ret; 245} 246 247// Write out to vcc or arbitrary SGPR. 248def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped]> { 249 let Asm32 = "$vdst, vcc, $src0, $src1"; 250 let Asm64 = "$vdst, $sdst, $src0, $src1"; 251 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 252 let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 253 let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 254 let Outs32 = (outs DstRC:$vdst); 255 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst); 256} 257 258// Write out to vcc or arbitrary SGPR and read in from vcc or 259// arbitrary SGPR. 260def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> { 261 // We use VCSrc_b32 to exclude literal constants, even though the 262 // encoding normally allows them since the implicit VCC use means 263 // using one would always violate the constant bus 264 // restriction. SGPRs are still allowed because it should 265 // technically be possible to use VCC again as src0. 266 let Src0RC32 = VCSrc_b32; 267 let Asm32 = "$vdst, vcc, $src0, $src1, vcc"; 268 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2"; 269 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 270 let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 271 let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 272 let Outs32 = (outs DstRC:$vdst); 273 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst); 274 275 // Suppress src2 implied by type since the 32-bit encoding uses an 276 // implicit VCC use. 277 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1); 278 279 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 280 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 281 clampmod:$clamp, omod:$omod, 282 dst_sel:$dst_sel, dst_unused:$dst_unused, 283 src0_sel:$src0_sel, src1_sel:$src1_sel); 284 285 let InsDPP = (ins DstRCDPP:$old, 286 Src0Mod:$src0_modifiers, Src0DPP:$src0, 287 Src1Mod:$src1_modifiers, Src1DPP:$src1, 288 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 289 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 290 let HasExt = 1; 291 let HasSDWA9 = 1; 292} 293 294// Read in from vcc or arbitrary SGPR 295def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> { 296 let Src0RC32 = VCSrc_b32; // See comment in def VOP2b_I32_I1_I32_I32_I1 above. 297 let Asm32 = "$vdst, $src0, $src1, vcc"; 298 let Asm64 = "$vdst, $src0, $src1, $src2"; 299 let Outs32 = (outs DstRC:$vdst); 300 let Outs64 = (outs DstRC:$vdst); 301 302 // Suppress src2 implied by type since the 32-bit encoding uses an 303 // implicit VCC use. 304 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1); 305} 306 307def VOP_READLANE : VOPProfile<[i32, i32, i32]> { 308 let Outs32 = (outs SReg_32:$vdst); 309 let Outs64 = Outs32; 310 let Ins32 = (ins VGPR_32:$src0, SCSrc_b32:$src1); 311 let Ins64 = Ins32; 312 let Asm32 = " $vdst, $src0, $src1"; 313 let Asm64 = Asm32; 314 let HasExt = 0; 315 let HasSDWA9 = 0; 316} 317 318def VOP_WRITELANE : VOPProfile<[i32, i32, i32]> { 319 let Outs32 = (outs VGPR_32:$vdst); 320 let Outs64 = Outs32; 321 let Ins32 = (ins SCSrc_b32:$src0, SCSrc_b32:$src1); 322 let Ins64 = Ins32; 323 let Asm32 = " $vdst, $src0, $src1"; 324 let Asm64 = Asm32; 325 let HasExt = 0; 326 let HasSDWA9 = 0; 327} 328 329//===----------------------------------------------------------------------===// 330// VOP2 Instructions 331//===----------------------------------------------------------------------===// 332 333let SubtargetPredicate = isGCN in { 334 335defm V_CNDMASK_B32 : VOP2eInst <"v_cndmask_b32", VOP2e_I32_I32_I32_I1>; 336def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, [], "">; 337 338let isCommutable = 1 in { 339defm V_ADD_F32 : VOP2Inst <"v_add_f32", VOP_F32_F32_F32, fadd>; 340defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, fsub>; 341defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">; 342defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>; 343defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, fmul>; 344defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32, AMDGPUmul_i24>; 345defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_I32_I32_I32, AMDGPUmulhi_i24>; 346defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32, AMDGPUmul_u24>; 347defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_I32_I32_I32, AMDGPUmulhi_u24>; 348defm V_MIN_F32 : VOP2Inst <"v_min_f32", VOP_F32_F32_F32, fminnum>; 349defm V_MAX_F32 : VOP2Inst <"v_max_f32", VOP_F32_F32_F32, fmaxnum>; 350defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_I32_I32_I32>; 351defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_I32_I32_I32>; 352defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_I32_I32_I32>; 353defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_I32_I32_I32>; 354defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, null_frag, "v_lshr_b32">; 355defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, null_frag, "v_ashr_i32">; 356defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, null_frag, "v_lshl_b32">; 357defm V_AND_B32 : VOP2Inst <"v_and_b32", VOP_I32_I32_I32>; 358defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_I32_I32_I32>; 359defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_I32_I32_I32>; 360 361let Constraints = "$vdst = $src2", DisableEncoding="$src2", 362 isConvertibleToThreeAddress = 1 in { 363defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>; 364} 365 366def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32, [], "">; 367 368// No patterns so that the scalar instructions are always selected. 369// The scalar versions will be replaced with vector when needed later. 370 371// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in VI, 372// but the VI instructions behave the same as the SI versions. 373defm V_ADD_I32 : VOP2bInst <"v_add_i32", VOP2b_I32_I1_I32_I32>; 374defm V_SUB_I32 : VOP2bInst <"v_sub_i32", VOP2b_I32_I1_I32_I32>; 375defm V_SUBREV_I32 : VOP2bInst <"v_subrev_i32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_i32">; 376defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1>; 377defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1>; 378defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32">; 379 380 381let SubtargetPredicate = HasAddNoCarryInsts in { 382defm V_ADD_U32 : VOP2Inst <"v_add_u32", VOP_I32_I32_I32>; 383defm V_SUB_U32 : VOP2Inst <"v_sub_u32", VOP_I32_I32_I32>; 384defm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32, null_frag, "v_sub_u32">; 385} 386 387} // End isCommutable = 1 388 389// These are special and do not read the exec mask. 390let isConvergent = 1, Uses = []<Register> in { 391def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE, 392 [(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))], "">; 393 394def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE, [], "">; 395} // End isConvergent = 1 396 397defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_NO_EXT<VOP_I32_I32_I32>>; 398defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>>; 399defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_lo>; 400defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_hi>; 401defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_NO_EXT<VOP_F32_F32_I32>, AMDGPUldexp>; 402defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_NO_EXT<VOP_I32_F32_I32>>; // TODO: set "Uses = dst" 403defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_NO_EXT<VOP_I32_F32_F32>>; 404defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_NO_EXT<VOP_I32_F32_F32>>; 405defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_NO_EXT<VOP_I32_F32_F32>, AMDGPUpkrtz_f16_f32>; 406defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_NO_EXT<VOP_I32_I32_I32>>; 407defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT<VOP_I32_I32_I32>>; 408 409} // End SubtargetPredicate = isGCN 410 411def : GCNPat< 412 (AMDGPUadde i32:$src0, i32:$src1, i1:$src2), 413 (V_ADDC_U32_e64 $src0, $src1, $src2) 414>; 415 416def : GCNPat< 417 (AMDGPUsube i32:$src0, i32:$src1, i1:$src2), 418 (V_SUBB_U32_e64 $src0, $src1, $src2) 419>; 420 421// These instructions only exist on SI and CI 422let SubtargetPredicate = isSICI in { 423 424defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>; 425defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>; 426 427let isCommutable = 1 in { 428defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_F32_F32_F32>; 429defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_I32_I32_I32>; 430defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_I32_I32_I32>; 431defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_I32_I32_I32>; 432} // End isCommutable = 1 433 434} // End let SubtargetPredicate = SICI 435 436let SubtargetPredicate = Has16BitInsts in { 437 438def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16, [], "">; 439defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16>; 440defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16>; 441defm V_ASHRREV_I16 : VOP2Inst <"v_ashrrev_i16", VOP_I16_I16_I16>; 442defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>; 443 444let isCommutable = 1 in { 445defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, fadd>; 446defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, fsub>; 447defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">; 448defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, fmul>; 449def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">; 450defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16>; 451defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16>; 452defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16, null_frag, "v_sub_u16">; 453defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16>; 454defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum>; 455defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum>; 456defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16>; 457defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16>; 458defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16>; 459defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16>; 460 461let Constraints = "$vdst = $src2", DisableEncoding="$src2", 462 isConvertibleToThreeAddress = 1 in { 463defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>; 464} 465} // End isCommutable = 1 466 467} // End SubtargetPredicate = Has16BitInsts 468 469// Note: 16-bit instructions produce a 0 result in the high 16-bits. 470multiclass Arithmetic_i16_Pats <SDPatternOperator op, Instruction inst> { 471 472def : GCNPat< 473 (op i16:$src0, i16:$src1), 474 (inst $src0, $src1) 475>; 476 477def : GCNPat< 478 (i32 (zext (op i16:$src0, i16:$src1))), 479 (inst $src0, $src1) 480>; 481 482def : GCNPat< 483 (i64 (zext (op i16:$src0, i16:$src1))), 484 (REG_SEQUENCE VReg_64, 485 (inst $src0, $src1), sub0, 486 (V_MOV_B32_e32 (i32 0)), sub1) 487>; 488 489} 490 491multiclass Bits_OpsRev_i16_Pats <SDPatternOperator op, Instruction inst> { 492 493def : GCNPat< 494 (op i16:$src0, i16:$src1), 495 (inst $src1, $src0) 496>; 497 498def : GCNPat< 499 (i32 (zext (op i16:$src0, i16:$src1))), 500 (inst $src1, $src0) 501>; 502 503 504def : GCNPat< 505 (i64 (zext (op i16:$src0, i16:$src1))), 506 (REG_SEQUENCE VReg_64, 507 (inst $src1, $src0), sub0, 508 (V_MOV_B32_e32 (i32 0)), sub1) 509>; 510} 511 512class ZExt_i16_i1_Pat <SDNode ext> : GCNPat < 513 (i16 (ext i1:$src)), 514 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src) 515>; 516 517let Predicates = [Has16BitInsts] in { 518 519defm : Arithmetic_i16_Pats<add, V_ADD_U16_e64>; 520defm : Arithmetic_i16_Pats<mul, V_MUL_LO_U16_e64>; 521defm : Arithmetic_i16_Pats<sub, V_SUB_U16_e64>; 522defm : Arithmetic_i16_Pats<smin, V_MIN_I16_e64>; 523defm : Arithmetic_i16_Pats<smax, V_MAX_I16_e64>; 524defm : Arithmetic_i16_Pats<umin, V_MIN_U16_e64>; 525defm : Arithmetic_i16_Pats<umax, V_MAX_U16_e64>; 526 527def : GCNPat < 528 (and i16:$src0, i16:$src1), 529 (V_AND_B32_e64 $src0, $src1) 530>; 531 532def : GCNPat < 533 (or i16:$src0, i16:$src1), 534 (V_OR_B32_e64 $src0, $src1) 535>; 536 537def : GCNPat < 538 (xor i16:$src0, i16:$src1), 539 (V_XOR_B32_e64 $src0, $src1) 540>; 541 542defm : Bits_OpsRev_i16_Pats<shl, V_LSHLREV_B16_e64>; 543defm : Bits_OpsRev_i16_Pats<srl, V_LSHRREV_B16_e64>; 544defm : Bits_OpsRev_i16_Pats<sra, V_ASHRREV_I16_e64>; 545 546def : ZExt_i16_i1_Pat<zext>; 547def : ZExt_i16_i1_Pat<anyext>; 548 549def : GCNPat < 550 (i16 (sext i1:$src)), 551 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src) 552>; 553 554// Undo sub x, c -> add x, -c canonicalization since c is more likely 555// an inline immediate than -c. 556// TODO: Also do for 64-bit. 557def : GCNPat< 558 (add i16:$src0, (i16 NegSubInlineConst16:$src1)), 559 (V_SUB_U16_e64 $src0, NegSubInlineConst16:$src1) 560>; 561 562} // End Predicates = [Has16BitInsts] 563 564//===----------------------------------------------------------------------===// 565// SI 566//===----------------------------------------------------------------------===// 567 568let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in { 569 570multiclass VOP2_Real_si <bits<6> op> { 571 def _si : 572 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>, 573 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 574} 575 576multiclass VOP2_Real_MADK_si <bits<6> op> { 577 def _si : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>, 578 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 579} 580 581multiclass VOP2_Real_e32_si <bits<6> op> { 582 def _e32_si : 583 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>, 584 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 585} 586 587multiclass VOP2_Real_e32e64_si <bits<6> op> : VOP2_Real_e32_si<op> { 588 def _e64_si : 589 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 590 VOP3e_si <{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 591} 592 593multiclass VOP2be_Real_e32e64_si <bits<6> op> : VOP2_Real_e32_si<op> { 594 def _e64_si : 595 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 596 VOP3be_si <{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 597} 598 599} // End AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" 600 601defm V_CNDMASK_B32 : VOP2_Real_e32e64_si <0x0>; 602defm V_ADD_F32 : VOP2_Real_e32e64_si <0x3>; 603defm V_SUB_F32 : VOP2_Real_e32e64_si <0x4>; 604defm V_SUBREV_F32 : VOP2_Real_e32e64_si <0x5>; 605defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_si <0x7>; 606defm V_MUL_F32 : VOP2_Real_e32e64_si <0x8>; 607defm V_MUL_I32_I24 : VOP2_Real_e32e64_si <0x9>; 608defm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_si <0xa>; 609defm V_MUL_U32_U24 : VOP2_Real_e32e64_si <0xb>; 610defm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_si <0xc>; 611defm V_MIN_F32 : VOP2_Real_e32e64_si <0xf>; 612defm V_MAX_F32 : VOP2_Real_e32e64_si <0x10>; 613defm V_MIN_I32 : VOP2_Real_e32e64_si <0x11>; 614defm V_MAX_I32 : VOP2_Real_e32e64_si <0x12>; 615defm V_MIN_U32 : VOP2_Real_e32e64_si <0x13>; 616defm V_MAX_U32 : VOP2_Real_e32e64_si <0x14>; 617defm V_LSHRREV_B32 : VOP2_Real_e32e64_si <0x16>; 618defm V_ASHRREV_I32 : VOP2_Real_e32e64_si <0x18>; 619defm V_LSHLREV_B32 : VOP2_Real_e32e64_si <0x1a>; 620defm V_AND_B32 : VOP2_Real_e32e64_si <0x1b>; 621defm V_OR_B32 : VOP2_Real_e32e64_si <0x1c>; 622defm V_XOR_B32 : VOP2_Real_e32e64_si <0x1d>; 623defm V_MAC_F32 : VOP2_Real_e32e64_si <0x1f>; 624defm V_MADMK_F32 : VOP2_Real_MADK_si <0x20>; 625defm V_MADAK_F32 : VOP2_Real_MADK_si <0x21>; 626defm V_ADD_I32 : VOP2be_Real_e32e64_si <0x25>; 627defm V_SUB_I32 : VOP2be_Real_e32e64_si <0x26>; 628defm V_SUBREV_I32 : VOP2be_Real_e32e64_si <0x27>; 629defm V_ADDC_U32 : VOP2be_Real_e32e64_si <0x28>; 630defm V_SUBB_U32 : VOP2be_Real_e32e64_si <0x29>; 631defm V_SUBBREV_U32 : VOP2be_Real_e32e64_si <0x2a>; 632 633defm V_READLANE_B32 : VOP2_Real_si <0x01>; 634 635let InOperandList = (ins SSrc_b32:$src0, SCSrc_b32:$src1) in { 636defm V_WRITELANE_B32 : VOP2_Real_si <0x02>; 637} 638 639defm V_MAC_LEGACY_F32 : VOP2_Real_e32e64_si <0x6>; 640defm V_MIN_LEGACY_F32 : VOP2_Real_e32e64_si <0xd>; 641defm V_MAX_LEGACY_F32 : VOP2_Real_e32e64_si <0xe>; 642defm V_LSHR_B32 : VOP2_Real_e32e64_si <0x15>; 643defm V_ASHR_I32 : VOP2_Real_e32e64_si <0x17>; 644defm V_LSHL_B32 : VOP2_Real_e32e64_si <0x19>; 645 646defm V_BFM_B32 : VOP2_Real_e32e64_si <0x1e>; 647defm V_BCNT_U32_B32 : VOP2_Real_e32e64_si <0x22>; 648defm V_MBCNT_LO_U32_B32 : VOP2_Real_e32e64_si <0x23>; 649defm V_MBCNT_HI_U32_B32 : VOP2_Real_e32e64_si <0x24>; 650defm V_LDEXP_F32 : VOP2_Real_e32e64_si <0x2b>; 651defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e32e64_si <0x2c>; 652defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e32e64_si <0x2d>; 653defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e32e64_si <0x2e>; 654defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e32e64_si <0x2f>; 655defm V_CVT_PK_U16_U32 : VOP2_Real_e32e64_si <0x30>; 656defm V_CVT_PK_I16_I32 : VOP2_Real_e32e64_si <0x31>; 657 658 659//===----------------------------------------------------------------------===// 660// VI 661//===----------------------------------------------------------------------===// 662 663class VOP2_DPP <bits<6> op, VOP2_Pseudo ps, VOPProfile P = ps.Pfl> : 664 VOP_DPP <ps.OpName, P> { 665 let Defs = ps.Defs; 666 let Uses = ps.Uses; 667 let SchedRW = ps.SchedRW; 668 let hasSideEffects = ps.hasSideEffects; 669 670 bits<8> vdst; 671 bits<8> src1; 672 let Inst{8-0} = 0xfa; //dpp 673 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 674 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 675 let Inst{30-25} = op; 676 let Inst{31} = 0x0; //encoding 677} 678 679let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in { 680 681multiclass VOP32_Real_vi <bits<10> op> { 682 def _vi : 683 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>, 684 VOP3e_vi<op, !cast<VOP2_Pseudo>(NAME).Pfl>; 685} 686 687multiclass VOP2_Real_MADK_vi <bits<6> op> { 688 def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>, 689 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 690} 691 692multiclass VOP2_Real_e32_vi <bits<6> op> { 693 def _e32_vi : 694 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>, 695 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 696} 697 698multiclass VOP2_Real_e64_vi <bits<10> op> { 699 def _e64_vi : 700 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 701 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 702} 703 704multiclass VOP2_Real_e64only_vi <bits<10> op> { 705 def _e64_vi : 706 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 707 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 708 // Hack to stop printing _e64 709 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME#"_e64"); 710 let OutOperandList = (outs VGPR_32:$vdst); 711 let AsmString = ps.Mnemonic # " " # ps.AsmOperands; 712 } 713} 714 715multiclass Base_VOP2be_Real_e32e64_vi <bits<6> op> : VOP2_Real_e32_vi<op> { 716 def _e64_vi : 717 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 718 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 719} 720 721multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> : 722 VOP2_Real_e32_vi<op>, 723 VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>; 724 725} // End AssemblerPredicates = [isVI], DecoderNamespace = "VI" 726 727multiclass VOP2_SDWA_Real <bits<6> op> { 728 def _sdwa_vi : 729 VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 730 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 731} 732 733multiclass VOP2_SDWA9_Real <bits<6> op> { 734 def _sdwa_gfx9 : 735 VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 736 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 737} 738 739multiclass VOP2be_Real_e32e64_vi <bits<6> op> : 740 Base_VOP2be_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> { 741 // For now left dpp only for asm/dasm 742 // TODO: add corresponding pseudo 743 def _dpp : VOP2_DPP<op, !cast<VOP2_Pseudo>(NAME#"_e32")>; 744} 745 746multiclass VOP2_Real_e32e64_vi <bits<6> op> : 747 Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> { 748 // For now left dpp only for asm/dasm 749 // TODO: add corresponding pseudo 750 def _dpp : VOP2_DPP<op, !cast<VOP2_Pseudo>(NAME#"_e32")>; 751} 752 753defm V_CNDMASK_B32 : Base_VOP2_Real_e32e64_vi <0x0>; 754defm V_ADD_F32 : VOP2_Real_e32e64_vi <0x1>; 755defm V_SUB_F32 : VOP2_Real_e32e64_vi <0x2>; 756defm V_SUBREV_F32 : VOP2_Real_e32e64_vi <0x3>; 757defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_vi <0x4>; 758defm V_MUL_F32 : VOP2_Real_e32e64_vi <0x5>; 759defm V_MUL_I32_I24 : VOP2_Real_e32e64_vi <0x6>; 760defm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_vi <0x7>; 761defm V_MUL_U32_U24 : VOP2_Real_e32e64_vi <0x8>; 762defm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_vi <0x9>; 763defm V_MIN_F32 : VOP2_Real_e32e64_vi <0xa>; 764defm V_MAX_F32 : VOP2_Real_e32e64_vi <0xb>; 765defm V_MIN_I32 : VOP2_Real_e32e64_vi <0xc>; 766defm V_MAX_I32 : VOP2_Real_e32e64_vi <0xd>; 767defm V_MIN_U32 : VOP2_Real_e32e64_vi <0xe>; 768defm V_MAX_U32 : VOP2_Real_e32e64_vi <0xf>; 769defm V_LSHRREV_B32 : VOP2_Real_e32e64_vi <0x10>; 770defm V_ASHRREV_I32 : VOP2_Real_e32e64_vi <0x11>; 771defm V_LSHLREV_B32 : VOP2_Real_e32e64_vi <0x12>; 772defm V_AND_B32 : VOP2_Real_e32e64_vi <0x13>; 773defm V_OR_B32 : VOP2_Real_e32e64_vi <0x14>; 774defm V_XOR_B32 : VOP2_Real_e32e64_vi <0x15>; 775defm V_MAC_F32 : VOP2_Real_e32e64_vi <0x16>; 776defm V_MADMK_F32 : VOP2_Real_MADK_vi <0x17>; 777defm V_MADAK_F32 : VOP2_Real_MADK_vi <0x18>; 778defm V_ADD_I32 : VOP2be_Real_e32e64_vi <0x19>; 779defm V_SUB_I32 : VOP2be_Real_e32e64_vi <0x1a>; 780defm V_SUBREV_I32 : VOP2be_Real_e32e64_vi <0x1b>; 781defm V_ADDC_U32 : VOP2be_Real_e32e64_vi <0x1c>; 782defm V_SUBB_U32 : VOP2be_Real_e32e64_vi <0x1d>; 783defm V_SUBBREV_U32 : VOP2be_Real_e32e64_vi <0x1e>; 784 785defm V_READLANE_B32 : VOP32_Real_vi <0x289>; 786defm V_WRITELANE_B32 : VOP32_Real_vi <0x28a>; 787 788defm V_BFM_B32 : VOP2_Real_e64only_vi <0x293>; 789defm V_BCNT_U32_B32 : VOP2_Real_e64only_vi <0x28b>; 790defm V_MBCNT_LO_U32_B32 : VOP2_Real_e64only_vi <0x28c>; 791defm V_MBCNT_HI_U32_B32 : VOP2_Real_e64only_vi <0x28d>; 792defm V_LDEXP_F32 : VOP2_Real_e64only_vi <0x288>; 793defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64only_vi <0x1f0>; 794defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64only_vi <0x294>; 795defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64only_vi <0x295>; 796defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e64only_vi <0x296>; 797defm V_CVT_PK_U16_U32 : VOP2_Real_e64only_vi <0x297>; 798defm V_CVT_PK_I16_I32 : VOP2_Real_e64only_vi <0x298>; 799 800defm V_ADD_F16 : VOP2_Real_e32e64_vi <0x1f>; 801defm V_SUB_F16 : VOP2_Real_e32e64_vi <0x20>; 802defm V_SUBREV_F16 : VOP2_Real_e32e64_vi <0x21>; 803defm V_MUL_F16 : VOP2_Real_e32e64_vi <0x22>; 804defm V_MAC_F16 : VOP2_Real_e32e64_vi <0x23>; 805defm V_MADMK_F16 : VOP2_Real_MADK_vi <0x24>; 806defm V_MADAK_F16 : VOP2_Real_MADK_vi <0x25>; 807defm V_ADD_U16 : VOP2_Real_e32e64_vi <0x26>; 808defm V_SUB_U16 : VOP2_Real_e32e64_vi <0x27>; 809defm V_SUBREV_U16 : VOP2_Real_e32e64_vi <0x28>; 810defm V_MUL_LO_U16 : VOP2_Real_e32e64_vi <0x29>; 811defm V_LSHLREV_B16 : VOP2_Real_e32e64_vi <0x2a>; 812defm V_LSHRREV_B16 : VOP2_Real_e32e64_vi <0x2b>; 813defm V_ASHRREV_I16 : VOP2_Real_e32e64_vi <0x2c>; 814defm V_MAX_F16 : VOP2_Real_e32e64_vi <0x2d>; 815defm V_MIN_F16 : VOP2_Real_e32e64_vi <0x2e>; 816defm V_MAX_U16 : VOP2_Real_e32e64_vi <0x2f>; 817defm V_MAX_I16 : VOP2_Real_e32e64_vi <0x30>; 818defm V_MIN_U16 : VOP2_Real_e32e64_vi <0x31>; 819defm V_MIN_I16 : VOP2_Real_e32e64_vi <0x32>; 820defm V_LDEXP_F16 : VOP2_Real_e32e64_vi <0x33>; 821 822let SubtargetPredicate = isVI in { 823 824// Aliases to simplify matching of floating-point instructions that 825// are VOP2 on SI and VOP3 on VI. 826class SI2_VI3Alias <string name, VOP3_Real inst> : InstAlias < 827 name#" $dst, $src0, $src1", 828 !if(inst.Pfl.HasOMod, 829 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0), 830 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0)) 831>, PredicateControl { 832 let UseInstAsmMatchConverter = 0; 833 let AsmVariantName = AMDGPUAsmVariants.VOP3; 834} 835 836def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>; 837def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>; 838def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>; 839def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>; 840def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>; 841 842} // End SubtargetPredicate = isVI 843 844let SubtargetPredicate = HasAddNoCarryInsts in { 845defm V_ADD_U32 : VOP2_Real_e32e64_vi <0x34>; 846defm V_SUB_U32 : VOP2_Real_e32e64_vi <0x35>; 847defm V_SUBREV_U32 : VOP2_Real_e32e64_vi <0x36>; 848} 849