1//===-- VOP2Instructions.td - Vector Instruction Definitions --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// VOP2 Classes
11//===----------------------------------------------------------------------===//
12
13class VOP2e <bits<6> op, VOPProfile P> : Enc32 {
14  bits<8> vdst;
15  bits<9> src0;
16  bits<8> src1;
17
18  let Inst{8-0}   = !if(P.HasSrc0, src0, 0);
19  let Inst{16-9}  = !if(P.HasSrc1, src1, 0);
20  let Inst{24-17} = !if(P.EmitDst, vdst, 0);
21  let Inst{30-25} = op;
22  let Inst{31}    = 0x0; //encoding
23}
24
25class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 {
26  bits<8>  vdst;
27  bits<9>  src0;
28  bits<8>  src1;
29  bits<32> imm;
30
31  let Inst{8-0}   = !if(P.HasSrc0, src0, 0);
32  let Inst{16-9}  = !if(P.HasSrc1, src1, 0);
33  let Inst{24-17} = !if(P.EmitDst, vdst, 0);
34  let Inst{30-25} = op;
35  let Inst{31}    = 0x0; // encoding
36  let Inst{63-32} = imm;
37}
38
39class VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> {
40  bits<8> vdst;
41  bits<8> src1;
42
43  let Inst{8-0}   = 0xf9; // sdwa
44  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
45  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
46  let Inst{30-25} = op;
47  let Inst{31}    = 0x0; // encoding
48}
49
50class VOP2_SDWA9Ae <bits<6> op, VOPProfile P> : VOP_SDWA9Ae <P> {
51  bits<8> vdst;
52  bits<9> src1;
53
54  let Inst{8-0}   = 0xf9; // sdwa
55  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
56  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
57  let Inst{30-25} = op;
58  let Inst{31}    = 0x0; // encoding
59  let Inst{63}    = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr
60}
61
62class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> :
63  VOP_Pseudo <opName, suffix, P, P.Outs32, P.Ins32, "", pattern> {
64
65  let AsmOperands = P.Asm32;
66
67  let Size = 4;
68  let mayLoad = 0;
69  let mayStore = 0;
70  let hasSideEffects = 0;
71
72  let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
73
74  let mayRaiseFPException = ReadsModeReg;
75
76  let VOP2 = 1;
77  let VALU = 1;
78  let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
79
80  let AsmVariantName = AMDGPUAsmVariants.Default;
81}
82
83class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> :
84  InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
85  SIMCInstr <ps.PseudoInstr, EncodingFamily> {
86
87  let isPseudo = 0;
88  let isCodeGenOnly = 0;
89
90  let Constraints     = ps.Constraints;
91  let DisableEncoding = ps.DisableEncoding;
92
93  // copy relevant pseudo op flags
94  let SubtargetPredicate = ps.SubtargetPredicate;
95  let OtherPredicates    = ps.OtherPredicates;
96  let AsmMatchConverter  = ps.AsmMatchConverter;
97  let AsmVariantName     = ps.AsmVariantName;
98  let Constraints        = ps.Constraints;
99  let DisableEncoding    = ps.DisableEncoding;
100  let TSFlags            = ps.TSFlags;
101  let UseNamedOperandTable = ps.UseNamedOperandTable;
102  let Uses                 = ps.Uses;
103  let Defs                 = ps.Defs;
104}
105
106class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
107  VOP_SDWA_Pseudo <OpName, P, pattern> {
108  let AsmMatchConverter = "cvtSdwaVOP2";
109}
110
111class VOP2_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
112  VOP_DPP_Pseudo <OpName, P, pattern> {
113}
114
115
116class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies {
117  list<dag> ret = !if(P.HasModifiers,
118    [(set P.DstVT:$vdst,
119      (node (P.Src0VT
120              !if(P.HasOMod,
121                  (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
122                  (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
123            (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
124    [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
125}
126
127multiclass VOP2Inst_e32<string opName,
128                        VOPProfile P,
129                        SDPatternOperator node = null_frag,
130                        string revOp = opName,
131                        bit GFX9Renamed = 0> {
132  let renamedInGFX9 = GFX9Renamed in {
133    def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
134               Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
135  } // End renamedInGFX9 = GFX9Renamed
136}
137
138multiclass VOP2Inst_e64<string opName,
139                        VOPProfile P,
140                        SDPatternOperator node = null_frag,
141                        string revOp = opName,
142                        bit GFX9Renamed = 0> {
143  let renamedInGFX9 = GFX9Renamed in {
144    def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
145               Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
146  } // End renamedInGFX9 = GFX9Renamed
147}
148
149multiclass VOP2Inst_sdwa<string opName,
150                         VOPProfile P,
151                         SDPatternOperator node = null_frag,
152                         string revOp = opName,
153                         bit GFX9Renamed = 0> {
154  let renamedInGFX9 = GFX9Renamed in {
155    foreach _ = BoolToList<P.HasExtSDWA>.ret in
156      def _sdwa : VOP2_SDWA_Pseudo <opName, P>;
157  } // End renamedInGFX9 = GFX9Renamed
158}
159
160multiclass VOP2Inst<string opName,
161                    VOPProfile P,
162                    SDPatternOperator node = null_frag,
163                    string revOp = opName,
164                    bit GFX9Renamed = 0> :
165    VOP2Inst_e32<opName, P, node, revOp, GFX9Renamed>,
166    VOP2Inst_e64<opName, P, node, revOp, GFX9Renamed>,
167    VOP2Inst_sdwa<opName, P, node, revOp, GFX9Renamed> {
168  let renamedInGFX9 = GFX9Renamed in {
169    foreach _ = BoolToList<P.HasExtDPP>.ret in
170      def _dpp  : VOP2_DPP_Pseudo <opName, P>;
171  }
172}
173
174multiclass VOP2bInst <string opName,
175                      VOPProfile P,
176                      SDPatternOperator node = null_frag,
177                      string revOp = opName,
178                      bit GFX9Renamed = 0,
179                      bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
180  let renamedInGFX9 = GFX9Renamed in {
181    let SchedRW = [Write32Bit, WriteSALU] in {
182      let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
183        def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
184                   Commutable_REV<revOp#"_e32", !eq(revOp, opName)> {
185          let usesCustomInserter = !eq(P.NumSrcArgs, 2);
186        }
187
188        foreach _ = BoolToList<P.HasExtSDWA>.ret in
189          def _sdwa  : VOP2_SDWA_Pseudo <opName, P> {
190            let AsmMatchConverter = "cvtSdwaVOP2b";
191          }
192        foreach _ = BoolToList<P.HasExtDPP>.ret in
193          def _dpp  : VOP2_DPP_Pseudo <opName, P>;
194      }
195
196      def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
197                 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
198    }
199  }
200}
201
202class VOP2bInstAlias <VOP2_Pseudo ps, Instruction inst,
203                      string OpName, string opnd> :
204  InstAlias <OpName#" "#!subst("vcc", opnd, ps.Pfl.Asm32),
205             (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
206                   ps.Pfl.Src1RC32:$src1)>,
207  PredicateControl {
208}
209
210multiclass VOP2bInstAliases<VOP2_Pseudo ps, VOP2_Real inst, string OpName> {
211  let WaveSizePredicate = isWave32 in {
212    def : VOP2bInstAlias<ps, inst, OpName, "vcc_lo">;
213  }
214  let WaveSizePredicate = isWave64 in {
215    def : VOP2bInstAlias<ps, inst, OpName, "vcc">;
216  }
217}
218
219multiclass VOP2eInst <string opName,
220                      VOPProfile P,
221                      SDPatternOperator node = null_frag,
222                      string revOp = opName,
223                      bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
224
225  let SchedRW = [Write32Bit] in {
226    let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in {
227      def _e32 : VOP2_Pseudo <opName, P>,
228                 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
229
230      foreach _ = BoolToList<P.HasExtSDWA>.ret in
231        def _sdwa : VOP2_SDWA_Pseudo <opName, P> {
232          let AsmMatchConverter = "cvtSdwaVOP2e";
233        }
234
235      foreach _ = BoolToList<P.HasExtDPP>.ret in
236        def _dpp  : VOP2_DPP_Pseudo <opName, P>;
237    }
238
239    def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
240               Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
241  }
242}
243
244class VOP2eInstAlias <VOP2_Pseudo ps, Instruction inst, string opnd = ""> :
245  InstAlias <ps.OpName#" "#ps.Pfl.Asm32#", "#opnd,
246             (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
247                   ps.Pfl.Src1RC32:$src1)>, PredicateControl;
248
249class VOP2e64InstAlias <VOP3_Pseudo ps, Instruction inst> :
250  InstAlias <ps.OpName#" "#ps.Pfl.Asm64,
251             (inst ps.Pfl.DstRC:$vdst, VOPDstS64orS32:$sdst,
252                   ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, clampmod:$clamp)>,
253  PredicateControl;
254
255multiclass VOP2eInstAliases<VOP2_Pseudo ps, VOP2_Real inst> {
256  let WaveSizePredicate = isWave32 in {
257    def : VOP2eInstAlias<ps, inst, "vcc_lo">;
258  }
259  let WaveSizePredicate = isWave64 in {
260    def : VOP2eInstAlias<ps, inst, "vcc">;
261  }
262}
263
264class VOP_MADAK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
265  field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
266  field dag Ins32 = !if(!eq(vt.Size, 32),
267                        (ins VCSrc_f32:$src0, VGPR_32:$src1, ImmOpType:$imm),
268                        (ins VCSrc_f16:$src0, VGPR_32:$src1, ImmOpType:$imm));
269  field bit HasExt = 0;
270
271  // Hack to stop printing _e64
272  let DstRC = RegisterOperand<VGPR_32>;
273  field string Asm32 = " $vdst, $src0, $src1, $imm";
274}
275
276def VOP_MADAK_F16 : VOP_MADAK <f16>;
277def VOP_MADAK_F32 : VOP_MADAK <f32>;
278
279class VOP_MADMK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
280  field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
281  field dag Ins32 = (ins VCSrc_f32:$src0, ImmOpType:$imm, VGPR_32:$src1);
282  field bit HasExt = 0;
283
284  // Hack to stop printing _e64
285  let DstRC = RegisterOperand<VGPR_32>;
286  field string Asm32 = " $vdst, $src0, $imm, $src1";
287}
288
289def VOP_MADMK_F16 : VOP_MADMK <f16>;
290def VOP_MADMK_F32 : VOP_MADMK <f32>;
291
292class getRegisterOperandForVT<ValueType VT> {
293  RegisterOperand ret = RegisterOperand<getVregSrcForVT<VT>.ret>;
294}
295
296// FIXME: Remove src2_modifiers. It isn't used, so is wasting memory
297// and processing time but it makes it easier to convert to mad.
298class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, vt0]> {
299  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, getVregSrcForVT<Src2VT>.ret:$src2);
300  let Ins64 = getIns64<Src0RC64, Src1RC64, getRegisterOperandForVT<Src2VT>.ret, 3,
301                       0, HasModifiers, HasModifiers, HasOMod,
302                       Src0Mod, Src1Mod, Src2Mod>.ret;
303  let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
304                    Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
305                    getVregSrcForVT<Src2VT>.ret:$src2, // stub argument
306                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
307                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
308  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
309  let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
310                     Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
311                     getVregSrcForVT<Src2VT>.ret:$src2, // stub argument
312                     dpp8:$dpp8, FI:$fi);
313  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
314                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
315                     getVregSrcForVT<Src2VT>.ret:$src2, // stub argument
316                     clampmod:$clamp, omod:$omod,
317                     dst_sel:$dst_sel, dst_unused:$dst_unused,
318                     src0_sel:$src0_sel, src1_sel:$src1_sel);
319  let Asm32 = getAsm32<1, 2, vt0>.ret;
320  let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, vt0>.ret;
321  let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt0>.ret;
322  let AsmDPP16 = getAsmDPP16<1, 2, HasModifiers, vt0>.ret;
323  let AsmDPP8 = getAsmDPP8<1, 2, 0, vt0>.ret;
324  let AsmSDWA = getAsmSDWA<1, 2, vt0>.ret;
325  let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt0>.ret;
326  let HasSrc2 = 0;
327  let HasSrc2Mods = 0;
328
329  let HasExt = 1;
330  let HasExtDPP = 1;
331  let HasExtSDWA = 1;
332  let HasExtSDWA9 = 0;
333  let TieRegDPP = "$src2";
334}
335
336def VOP_MAC_F16 : VOP_MAC <f16>;
337def VOP_MAC_F32 : VOP_MAC <f32>;
338let HasExtDPP = 0 in
339def VOP_MAC_LEGACY_F32 : VOP_MAC <f32>;
340let HasExtSDWA = 0, HasExt64BitDPP = 1 in
341def VOP_MAC_F64 : VOP_MAC <f64>;
342
343class VOP_DOT_ACC<ValueType vt0, ValueType vt1> : VOP_MAC<vt0, vt1> {
344  let HasClamp = 0;
345  let HasExtSDWA = 0;
346  let HasOpSel = 0;
347  let IsPacked = 0;
348}
349
350def VOP_DOT_ACC_F32_V2F16 : VOP_DOT_ACC<f32, v2f16> {
351  let Src0ModDPP = FPVRegInputMods;
352  let Src1ModDPP = FPVRegInputMods;
353}
354
355def VOP_DOT_ACC_I32_I32   : VOP_DOT_ACC<i32, i32> {
356  let HasSrc0Mods = 1;
357  let HasSrc1Mods = 1;
358}
359
360// Write out to vcc or arbitrary SGPR.
361def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], 0, /*EnableClamp=*/1> {
362  let Asm32 = "$vdst, vcc, $src0, $src1";
363  let Asm64 = "$vdst, $sdst, $src0, $src1$clamp";
364  let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
365  let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
366  let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
367  let AsmDPP8 = "$vdst, vcc, $src0, $src1 $dpp8$fi";
368  let AsmDPP16 = AsmDPP#"$fi";
369  let Outs32 = (outs DstRC:$vdst);
370  let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
371}
372
373// Write out to vcc or arbitrary SGPR and read in from vcc or
374// arbitrary SGPR.
375def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], 0, /*EnableClamp=*/1> {
376  let Asm32 = "$vdst, vcc, $src0, $src1, vcc";
377  let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
378  let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
379  let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
380  let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
381  let AsmDPP8 = "$vdst, vcc, $src0, $src1, vcc $dpp8$fi";
382  let AsmDPP16 = AsmDPP#"$fi";
383  let Outs32 = (outs DstRC:$vdst);
384  let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
385
386  // Suppress src2 implied by type since the 32-bit encoding uses an
387  // implicit VCC use.
388  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
389
390  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
391                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
392                     clampmod:$clamp,
393                     dst_sel:$dst_sel, dst_unused:$dst_unused,
394                     src0_sel:$src0_sel, src1_sel:$src1_sel);
395
396  let InsDPP = (ins DstRCDPP:$old,
397                    Src0DPP:$src0,
398                    Src1DPP:$src1,
399                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
400                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
401  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
402
403  let HasExt = 1;
404  let HasExtDPP = 1;
405  let HasExtSDWA = 1;
406  let HasExtSDWA9 = 1;
407}
408
409// Read in from vcc or arbitrary SGPR.
410def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], /*EnableF32SrcMods=*/1> {
411  let Asm32 = "$vdst, $src0, $src1";
412  let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2";
413  let AsmSDWA = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
414  let AsmSDWA9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
415  let AsmDPP = "$vdst, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
416  let AsmDPP8 = "$vdst, $src0, $src1, vcc $dpp8$fi";
417  let AsmDPP16 = AsmDPP#"$fi";
418
419  let Outs32 = (outs DstRC:$vdst);
420  let Outs64 = (outs DstRC:$vdst);
421
422  // Suppress src2 implied by type since the 32-bit encoding uses an
423  // implicit VCC use.
424  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
425
426  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
427                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
428                     clampmod:$clamp,
429                     dst_sel:$dst_sel, dst_unused:$dst_unused,
430                     src0_sel:$src0_sel, src1_sel:$src1_sel);
431
432  let InsDPP = (ins DstRCDPP:$old,
433                    Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
434                    Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
435                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
436                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
437  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
438
439  let HasExt = 1;
440  let HasExtDPP = 1;
441  let HasExtSDWA = 1;
442  let HasExtSDWA9 = 1;
443}
444
445def VOP_READLANE : VOPProfile<[i32, i32, i32]> {
446  let Outs32 = (outs SReg_32:$vdst);
447  let Outs64 = Outs32;
448  let Ins32 = (ins VRegOrLds_32:$src0, SCSrc_b32:$src1);
449  let Ins64 = Ins32;
450  let Asm32 = " $vdst, $src0, $src1";
451  let Asm64 = Asm32;
452
453  let HasExt = 0;
454  let HasExtDPP = 0;
455  let HasExt64BitDPP = 0;
456  let HasExtSDWA = 0;
457  let HasExtSDWA9 = 0;
458}
459
460def VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> {
461  let Outs32 = (outs VGPR_32:$vdst);
462  let Outs64 = Outs32;
463  let Ins32 = (ins SCSrc_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in);
464  let Ins64 = Ins32;
465  let Asm32 = " $vdst, $src0, $src1";
466  let Asm64 = Asm32;
467  let HasSrc2 = 0;
468  let HasSrc2Mods = 0;
469
470  let HasExt = 0;
471  let HasExtDPP = 0;
472  let HasExt64BitDPP = 0;
473  let HasExtSDWA = 0;
474  let HasExtSDWA9 = 0;
475}
476
477//===----------------------------------------------------------------------===//
478// VOP2 Instructions
479//===----------------------------------------------------------------------===//
480
481defm V_CNDMASK_B32 : VOP2eInst <"v_cndmask_b32", VOP2e_I32_I32_I32_I1>;
482let SubtargetPredicate = HasMadMacF32Insts in
483def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, []>;
484
485let isCommutable = 1 in {
486defm V_ADD_F32 : VOP2Inst <"v_add_f32", VOP_F32_F32_F32, any_fadd>;
487defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, any_fsub>;
488defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">;
489defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>;
490defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, any_fmul>;
491defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32_ARITH, AMDGPUmul_i24>;
492defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_i24>;
493defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32_ARITH, AMDGPUmul_u24>;
494defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_u24>;
495defm V_MIN_F32 : VOP2Inst <"v_min_f32", VOP_F32_F32_F32, fminnum_like>;
496defm V_MAX_F32 : VOP2Inst <"v_max_f32", VOP_F32_F32_F32, fmaxnum_like>;
497defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smin>;
498defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smax>;
499defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umin>;
500defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umax>;
501defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, lshr_rev, "v_lshr_b32">;
502defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, ashr_rev, "v_ashr_i32">;
503defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, lshl_rev, "v_lshl_b32">;
504defm V_AND_B32 : VOP2Inst <"v_and_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, and>;
505defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, or>;
506defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, xor>;
507
508let mayRaiseFPException = 0 in {
509let OtherPredicates = [HasMadMacF32Insts] in {
510let Constraints = "$vdst = $src2", DisableEncoding="$src2",
511    isConvertibleToThreeAddress = 1 in {
512defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>;
513
514let SubtargetPredicate = isGFX6GFX7GFX10 in
515defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_MAC_LEGACY_F32>;
516} // End Constraints = "$vdst = $src2", DisableEncoding="$src2",
517  //     isConvertibleToThreeAddress = 1
518
519def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32, []>;
520} // End OtherPredicates = [HasMadMacF32Insts]
521} // End mayRaiseFPException = 0
522
523// No patterns so that the scalar instructions are always selected.
524// The scalar versions will be replaced with vector when needed later.
525defm V_ADD_CO_U32 : VOP2bInst <"v_add_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_add_co_u32", 1>;
526defm V_SUB_CO_U32 : VOP2bInst <"v_sub_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>;
527defm V_SUBREV_CO_U32 : VOP2bInst <"v_subrev_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>;
528defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_addc_u32", 1>;
529defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>;
530defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>;
531
532
533let SubtargetPredicate = HasAddNoCarryInsts in {
534defm V_ADD_U32 : VOP2Inst <"v_add_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_add_u32", 1>;
535defm V_SUB_U32 : VOP2Inst <"v_sub_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>;
536defm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>;
537}
538
539} // End isCommutable = 1
540
541// These are special and do not read the exec mask.
542let isConvergent = 1, Uses = []<Register> in {
543def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE,
544  [(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))]>;
545
546let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in {
547def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE,
548  [(set i32:$vdst, (int_amdgcn_writelane i32:$src0, i32:$src1, i32:$vdst_in))]>;
549} // End $vdst = $vdst_in, DisableEncoding $vdst_in
550} // End isConvergent = 1
551
552defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_NO_EXT<VOP_I32_I32_I32>>;
553defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, add_ctpop>;
554defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_lo>;
555defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_hi>;
556defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_NO_EXT<VOP_F32_F32_I32>, AMDGPUldexp>;
557defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_NO_EXT<VOP_I32_F32_I32>>; // TODO: set "Uses = dst"
558
559let ReadsModeReg = 0, mayRaiseFPException = 0 in {
560defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_i16_f32>;
561defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_u16_f32>;
562}
563
564defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_NO_EXT<VOP_V2F16_F32_F32>, AMDGPUpkrtz_f16_f32>;
565defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_u16_u32>;
566defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_i16_i32>;
567
568
569let SubtargetPredicate = isGFX6GFX7 in {
570defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>;
571defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>;
572} // End SubtargetPredicate = isGFX6GFX7
573
574let isCommutable = 1 in {
575let SubtargetPredicate = isGFX6GFX7 in {
576defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, srl>;
577defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, sra>;
578defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, shl>;
579} // End SubtargetPredicate = isGFX6GFX7
580} // End isCommutable = 1
581
582
583class DivergentBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :
584  GCNPat<
585      (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
586      !if(!cast<Commutable_REV>(Inst).IsOrig,
587        (Inst $src0, $src1),
588        (Inst $src1, $src0)
589      )
590  >;
591
592class DivergentClampingBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :
593  GCNPat<
594      (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
595      !if(!cast<Commutable_REV>(Inst).IsOrig,
596        (Inst $src0, $src1, 0),
597        (Inst $src1, $src0, 0)
598      )
599  >;
600
601def : DivergentBinOp<srl, V_LSHRREV_B32_e64>;
602def : DivergentBinOp<sra, V_ASHRREV_I32_e64>;
603def : DivergentBinOp<shl, V_LSHLREV_B32_e64>;
604
605let SubtargetPredicate = HasAddNoCarryInsts in {
606  def : DivergentClampingBinOp<add, V_ADD_U32_e64>;
607  def : DivergentClampingBinOp<sub, V_SUB_U32_e64>;
608}
609
610let SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] in {
611def : DivergentClampingBinOp<add, V_ADD_CO_U32_e64>;
612def : DivergentClampingBinOp<sub, V_SUB_CO_U32_e64>;
613}
614
615def : DivergentBinOp<adde, V_ADDC_U32_e32>;
616def : DivergentBinOp<sube, V_SUBB_U32_e32>;
617
618class divergent_i64_BinOp <SDPatternOperator Op, Instruction Inst> :
619  GCNPat<
620      (getDivergentFrag<Op>.ret i64:$src0, i64:$src1),
621      (REG_SEQUENCE VReg_64,
622        (Inst
623          (i32 (EXTRACT_SUBREG $src0, sub0)),
624          (i32 (EXTRACT_SUBREG $src1, sub0))
625        ), sub0,
626        (Inst
627          (i32 (EXTRACT_SUBREG $src0, sub1)),
628          (i32 (EXTRACT_SUBREG $src1, sub1))
629        ), sub1
630      )
631  >;
632
633def :  divergent_i64_BinOp <and, V_AND_B32_e32>;
634def :  divergent_i64_BinOp <or,  V_OR_B32_e32>;
635def :  divergent_i64_BinOp <xor, V_XOR_B32_e32>;
636
637let SubtargetPredicate = Has16BitInsts in {
638
639let FPDPRounding = 1 in {
640def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16, [], "">;
641defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>;
642} // End FPDPRounding = 1
643
644defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16, lshl_rev>;
645defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16, lshr_rev>;
646defm V_ASHRREV_I16 : VOP2Inst <"v_ashrrev_i16", VOP_I16_I16_I16, ashr_rev>;
647
648let isCommutable = 1 in {
649let FPDPRounding = 1 in {
650defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, any_fadd>;
651defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, any_fsub>;
652defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">;
653defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, any_fmul>;
654
655let mayRaiseFPException = 0 in {
656def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">;
657}
658
659} // End FPDPRounding = 1
660defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16_ARITH, add>;
661defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16_ARITH, sub>;
662defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16_ARITH, null_frag, "v_sub_u16">;
663defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16, mul>;
664defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum_like>;
665defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum_like>;
666defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16, umax>;
667defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16, smax>;
668defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16, umin>;
669defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16, smin>;
670
671let Constraints = "$vdst = $src2", DisableEncoding="$src2",
672    isConvertibleToThreeAddress = 1 in {
673defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>;
674}
675} // End isCommutable = 1
676
677} // End SubtargetPredicate = Has16BitInsts
678
679let SubtargetPredicate = HasDLInsts in {
680
681defm V_XNOR_B32 : VOP2Inst <"v_xnor_b32", VOP_I32_I32_I32>;
682
683let Constraints = "$vdst = $src2",
684    DisableEncoding = "$src2",
685    isConvertibleToThreeAddress = 1,
686    isCommutable = 1 in
687defm V_FMAC_F32 : VOP2Inst <"v_fmac_f32", VOP_MAC_F32>;
688
689} // End SubtargetPredicate = HasDLInsts
690
691let SubtargetPredicate = HasFmaLegacy32 in {
692
693let Constraints = "$vdst = $src2",
694    DisableEncoding = "$src2",
695    isConvertibleToThreeAddress = 1,
696    isCommutable = 1 in
697defm V_FMAC_LEGACY_F32 : VOP2Inst <"v_fmac_legacy_f32", VOP_MAC_LEGACY_F32>;
698
699} // End SubtargetPredicate = HasFmaLegacy32
700
701let SubtargetPredicate = isGFX90APlus,
702    Constraints = "$vdst = $src2",
703    DisableEncoding="$src2",
704    isConvertibleToThreeAddress = 1,
705    isCommutable = 1,
706    SchedRW = [WriteDoubleAdd] in
707defm V_FMAC_F64 : VOP2Inst <"v_fmac_f64", VOP_MAC_F64>;
708
709let Constraints = "$vdst = $src2",
710      DisableEncoding="$src2",
711      isConvertibleToThreeAddress = 1,
712      isCommutable = 1,
713      IsDOT = 1 in {
714  let SubtargetPredicate = HasDot5Insts in
715    defm V_DOT2C_F32_F16 : VOP2Inst<"v_dot2c_f32_f16", VOP_DOT_ACC_F32_V2F16>;
716  let SubtargetPredicate = HasDot6Insts in
717    defm V_DOT4C_I32_I8  : VOP2Inst<"v_dot4c_i32_i8",  VOP_DOT_ACC_I32_I32>;
718
719  let SubtargetPredicate = HasDot4Insts in
720    defm V_DOT2C_I32_I16 : VOP2Inst<"v_dot2c_i32_i16", VOP_DOT_ACC_I32_I32>;
721  let SubtargetPredicate = HasDot3Insts in
722    defm V_DOT8C_I32_I4  : VOP2Inst<"v_dot8c_i32_i4",  VOP_DOT_ACC_I32_I32>;
723}
724
725let AddedComplexity = 30 in {
726  def : GCNPat<
727    (f32 (AMDGPUfdot2 v2f16:$src0, v2f16:$src1, f32:$src2, (i1 DSTCLAMP.NONE))),
728    (f32 (V_DOT2C_F32_F16_e32 $src0, $src1, $src2))
729  > {
730    let SubtargetPredicate = HasDot5Insts;
731  }
732  def : GCNPat<
733    (i32 (int_amdgcn_sdot4 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
734    (i32 (V_DOT4C_I32_I8_e32 $src0, $src1, $src2))
735  > {
736    let SubtargetPredicate = HasDot6Insts;
737  }
738  def : GCNPat<
739    (i32 (int_amdgcn_sdot2 v2i16:$src0, v2i16:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
740    (i32 (V_DOT2C_I32_I16_e32 $src0, $src1, $src2))
741  > {
742    let SubtargetPredicate = HasDot4Insts;
743  }
744  def : GCNPat<
745    (i32 (int_amdgcn_sdot8 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
746    (i32 (V_DOT8C_I32_I4_e32 $src0, $src1, $src2))
747  > {
748    let SubtargetPredicate = HasDot3Insts;
749  }
750} // End AddedComplexity = 30
751
752let SubtargetPredicate = isGFX10Plus in {
753
754def V_FMAMK_F32 : VOP2_Pseudo<"v_fmamk_f32", VOP_MADMK_F32, [], "">;
755let FPDPRounding = 1 in
756def V_FMAMK_F16 : VOP2_Pseudo <"v_fmamk_f16", VOP_MADMK_F16, [], "">;
757
758let isCommutable = 1 in {
759def V_FMAAK_F32 : VOP2_Pseudo<"v_fmaak_f32", VOP_MADAK_F32, [], "">;
760let FPDPRounding = 1 in
761def V_FMAAK_F16 : VOP2_Pseudo <"v_fmaak_f16", VOP_MADAK_F16, [], "">;
762} // End isCommutable = 1
763
764let Constraints = "$vdst = $src2",
765    DisableEncoding="$src2",
766    isConvertibleToThreeAddress = 1,
767    isCommutable = 1 in {
768defm V_FMAC_F16 : VOP2Inst <"v_fmac_f16", VOP_MAC_F16>;
769}
770
771} // End SubtargetPredicate = isGFX10Plus
772
773let SubtargetPredicate = HasPkFmacF16Inst in {
774defm V_PK_FMAC_F16 : VOP2Inst<"v_pk_fmac_f16", VOP_V2F16_V2F16_V2F16>;
775} // End SubtargetPredicate = HasPkFmacF16Inst
776
777// Note: 16-bit instructions produce a 0 result in the high 16-bits
778// on GFX8 and GFX9 and preserve high 16 bits on GFX10+
779multiclass Arithmetic_i16_0Hi_Pats <SDPatternOperator op, Instruction inst> {
780
781def : GCNPat<
782  (i32 (zext (op i16:$src0, i16:$src1))),
783  (inst VSrc_b16:$src0, VSrc_b16:$src1)
784>;
785
786def : GCNPat<
787  (i64 (zext (op i16:$src0, i16:$src1))),
788   (REG_SEQUENCE VReg_64,
789     (inst $src0, $src1), sub0,
790     (V_MOV_B32_e32 (i32 0)), sub1)
791>;
792}
793
794class ZExt_i16_i1_Pat <SDNode ext> : GCNPat <
795  (i16 (ext i1:$src)),
796  (V_CNDMASK_B32_e64 (i32 0/*src0mod*/), (i32 0/*src0*/),
797                     (i32 0/*src1mod*/), (i32 1/*src1*/),
798                     $src)
799>;
800
801foreach vt = [i16, v2i16] in {
802def : GCNPat <
803  (and vt:$src0, vt:$src1),
804  (V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
805>;
806
807def : GCNPat <
808  (or vt:$src0, vt:$src1),
809  (V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
810>;
811
812def : GCNPat <
813  (xor vt:$src0, vt:$src1),
814  (V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
815>;
816}
817
818let Predicates = [Has16BitInsts] in {
819
820// Undo sub x, c -> add x, -c canonicalization since c is more likely
821// an inline immediate than -c.
822// TODO: Also do for 64-bit.
823def : GCNPat<
824  (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)),
825  (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)
826>;
827
828
829let Predicates = [Has16BitInsts, isGFX7GFX8GFX9] in {
830
831def : GCNPat<
832  (i32 (zext (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)))),
833  (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)
834>;
835
836defm : Arithmetic_i16_0Hi_Pats<add, V_ADD_U16_e64>;
837defm : Arithmetic_i16_0Hi_Pats<mul, V_MUL_LO_U16_e64>;
838defm : Arithmetic_i16_0Hi_Pats<sub, V_SUB_U16_e64>;
839defm : Arithmetic_i16_0Hi_Pats<smin, V_MIN_I16_e64>;
840defm : Arithmetic_i16_0Hi_Pats<smax, V_MAX_I16_e64>;
841defm : Arithmetic_i16_0Hi_Pats<umin, V_MIN_U16_e64>;
842defm : Arithmetic_i16_0Hi_Pats<umax, V_MAX_U16_e64>;
843defm : Arithmetic_i16_0Hi_Pats<lshl_rev, V_LSHLREV_B16_e64>;
844defm : Arithmetic_i16_0Hi_Pats<lshr_rev, V_LSHRREV_B16_e64>;
845defm : Arithmetic_i16_0Hi_Pats<ashr_rev, V_ASHRREV_I16_e64>;
846}  // End Predicates = [Has16BitInsts, isGFX7GFX8GFX9]
847
848def : ZExt_i16_i1_Pat<zext>;
849def : ZExt_i16_i1_Pat<anyext>;
850
851def : GCNPat <
852  (i16 (sext i1:$src)),
853  (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
854                     /*src1mod*/(i32 0), /*src1*/(i32 -1), $src)
855>;
856
857} // End Predicates = [Has16BitInsts]
858
859
860let SubtargetPredicate = HasIntClamp in {
861// Set clamp bit for saturation.
862def : VOPBinOpClampPat<uaddsat, V_ADD_CO_U32_e64, i32>;
863def : VOPBinOpClampPat<usubsat, V_SUB_CO_U32_e64, i32>;
864}
865
866let SubtargetPredicate = HasAddNoCarryInsts, OtherPredicates = [HasIntClamp] in {
867let AddedComplexity = 1 in { // Prefer over form with carry-out.
868def : VOPBinOpClampPat<uaddsat, V_ADD_U32_e64, i32>;
869def : VOPBinOpClampPat<usubsat, V_SUB_U32_e64, i32>;
870}
871}
872
873let SubtargetPredicate = Has16BitInsts, OtherPredicates = [HasIntClamp] in {
874def : VOPBinOpClampPat<uaddsat, V_ADD_U16_e64, i16>;
875def : VOPBinOpClampPat<usubsat, V_SUB_U16_e64, i16>;
876}
877
878//===----------------------------------------------------------------------===//
879// Target-specific instruction encodings.
880//===----------------------------------------------------------------------===//
881
882class VOP2_DPP<bits<6> op, VOP2_DPP_Pseudo ps,
883               string opName = ps.OpName, VOPProfile p = ps.Pfl,
884               bit IsDPP16 = 0> :
885    VOP_DPP<opName, p, IsDPP16> {
886  let hasSideEffects = ps.hasSideEffects;
887  let Defs = ps.Defs;
888  let SchedRW = ps.SchedRW;
889  let Uses = ps.Uses;
890
891  bits<8> vdst;
892  bits<8> src1;
893  let Inst{8-0}   = 0xfa;
894  let Inst{16-9}  = !if(p.HasSrc1, src1{7-0}, 0);
895  let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
896  let Inst{30-25} = op;
897  let Inst{31}    = 0x0;
898}
899
900class Base_VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps,
901                 string opName = ps.OpName, VOPProfile p = ps.Pfl> :
902    VOP2_DPP<op, ps, opName, p, 1> {
903  let AssemblerPredicate = HasDPP16;
904  let SubtargetPredicate = HasDPP16;
905  let OtherPredicates = ps.OtherPredicates;
906}
907
908class VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps,
909                 string opName = ps.OpName, VOPProfile p = ps.Pfl> :
910    Base_VOP2_DPP16<op, ps, opName, p>,
911    SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX10>;
912
913class VOP2_DPP8<bits<6> op, VOP2_Pseudo ps,
914                string opName = ps.OpName, VOPProfile p = ps.Pfl> :
915    VOP_DPP8<ps.OpName, p> {
916  let hasSideEffects = ps.hasSideEffects;
917  let Defs = ps.Defs;
918  let SchedRW = ps.SchedRW;
919  let Uses = ps.Uses;
920
921  bits<8> vdst;
922  bits<8> src1;
923
924  let Inst{8-0}   = fi;
925  let Inst{16-9}  = !if(p.HasSrc1, src1{7-0}, 0);
926  let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
927  let Inst{30-25} = op;
928  let Inst{31}    = 0x0;
929
930  let AssemblerPredicate = HasDPP8;
931  let SubtargetPredicate = HasDPP8;
932  let OtherPredicates = ps.OtherPredicates;
933}
934
935//===----------------------------------------------------------------------===//
936// GFX10.
937//===----------------------------------------------------------------------===//
938
939let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
940  //===------------------------------- VOP2 -------------------------------===//
941  multiclass VOP2Only_Real_MADK_gfx10<bits<6> op> {
942    def _gfx10 :
943      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX10>,
944      VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
945  }
946  multiclass VOP2Only_Real_MADK_gfx10_with_name<bits<6> op, string opName,
947                                                string asmName> {
948    def _gfx10 :
949        VOP2_Real<!cast<VOP2_Pseudo>(opName), SIEncodingFamily.GFX10>,
950        VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> {
951      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName);
952      let AsmString = asmName # ps.AsmOperands;
953    }
954  }
955  multiclass VOP2_Real_e32_gfx10<bits<6> op> {
956    def _e32_gfx10 :
957      VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,
958      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
959  }
960  multiclass VOP2_Real_e64_gfx10<bits<6> op> {
961    def _e64_gfx10 :
962      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
963      VOP3e_gfx10<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
964  }
965  multiclass VOP2_Real_sdwa_gfx10<bits<6> op> {
966    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
967    def _sdwa_gfx10 :
968      VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
969      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
970      let DecoderNamespace = "SDWA10";
971    }
972  }
973  multiclass VOP2_Real_dpp_gfx10<bits<6> op> {
974    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
975    def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
976      let DecoderNamespace = "SDWA10";
977    }
978  }
979  multiclass VOP2_Real_dpp8_gfx10<bits<6> op> {
980    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
981    def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(NAME#"_e32")> {
982      let DecoderNamespace = "DPP8";
983    }
984  }
985
986  //===------------------------- VOP2 (with name) -------------------------===//
987  multiclass VOP2_Real_e32_gfx10_with_name<bits<6> op, string opName,
988                                           string asmName> {
989    def _e32_gfx10 :
990      VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
991      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
992        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
993        let AsmString = asmName # ps.AsmOperands;
994      }
995  }
996  multiclass VOP2_Real_e64_gfx10_with_name<bits<6> op, string opName,
997                                           string asmName> {
998    def _e64_gfx10 :
999      VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
1000      VOP3e_gfx10<{0, 1, 0, 0, op{5-0}},
1001                  !cast<VOP3_Pseudo>(opName#"_e64").Pfl> {
1002        VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64");
1003        let AsmString = asmName # ps.AsmOperands;
1004      }
1005  }
1006  let DecoderNamespace = "SDWA10" in {
1007    multiclass VOP2_Real_sdwa_gfx10_with_name<bits<6> op, string opName,
1008                                              string asmName> {
1009      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1010      def _sdwa_gfx10 :
1011        VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1012        VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1013          VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1014          let AsmString = asmName # ps.AsmOperands;
1015        }
1016    }
1017    multiclass VOP2_Real_dpp_gfx10_with_name<bits<6> op, string opName,
1018                                             string asmName> {
1019      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1020      def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp")> {
1021        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
1022        let AsmString = asmName # ps.Pfl.AsmDPP16;
1023      }
1024    }
1025    multiclass VOP2_Real_dpp8_gfx10_with_name<bits<6> op, string opName,
1026                                              string asmName> {
1027      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1028      def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
1029        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
1030        let AsmString = asmName # ps.Pfl.AsmDPP8;
1031        let DecoderNamespace = "DPP8";
1032      }
1033    }
1034  } // End DecoderNamespace = "SDWA10"
1035
1036  //===------------------------------ VOP2be ------------------------------===//
1037  multiclass VOP2be_Real_e32_gfx10<bits<6> op, string opName, string asmName> {
1038    def _e32_gfx10 :
1039      VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
1040      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
1041        VOP2_Pseudo Ps = !cast<VOP2_Pseudo>(opName#"_e32");
1042        let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
1043      }
1044  }
1045  multiclass VOP2be_Real_e64_gfx10<bits<6> op, string opName, string asmName> {
1046    def _e64_gfx10 :
1047      VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
1048      VOP3be_gfx10<{0, 1, 0, 0, op{5-0}},
1049                   !cast<VOP3_Pseudo>(opName#"_e64").Pfl> {
1050        VOP3_Pseudo Ps = !cast<VOP3_Pseudo>(opName#"_e64");
1051        let AsmString = asmName # Ps.AsmOperands;
1052      }
1053  }
1054  multiclass VOP2be_Real_sdwa_gfx10<bits<6> op, string opName, string asmName> {
1055    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1056    def _sdwa_gfx10 :
1057      VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1058      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1059        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1060        let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
1061        let DecoderNamespace = "SDWA10";
1062      }
1063    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1064    def _sdwa_w32_gfx10 :
1065      Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1066      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1067        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1068        let AsmString = asmName # !subst("vcc", "vcc_lo", Ps.AsmOperands);
1069        let isAsmParserOnly = 1;
1070        let DecoderNamespace = "SDWA10";
1071        let WaveSizePredicate = isWave32;
1072      }
1073    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1074    def _sdwa_w64_gfx10 :
1075      Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1076      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1077        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1078        let AsmString = asmName # Ps.AsmOperands;
1079        let isAsmParserOnly = 1;
1080        let DecoderNamespace = "SDWA10";
1081        let WaveSizePredicate = isWave64;
1082      }
1083  }
1084  multiclass VOP2be_Real_dpp_gfx10<bits<6> op, string opName, string asmName> {
1085    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1086    def _dpp_gfx10 :
1087      VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1088        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1089        let AsmString = asmName # !subst(", vcc", "", AsmDPP);
1090        let DecoderNamespace = "SDWA10";
1091      }
1092    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1093    def _dpp_w32_gfx10 :
1094      Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1095        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1096        let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP);
1097        let isAsmParserOnly = 1;
1098        let WaveSizePredicate = isWave32;
1099      }
1100    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1101    def _dpp_w64_gfx10 :
1102      Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1103        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1104        let AsmString = asmName # AsmDPP;
1105        let isAsmParserOnly = 1;
1106        let WaveSizePredicate = isWave64;
1107      }
1108  }
1109  multiclass VOP2be_Real_dpp8_gfx10<bits<6> op, string opName, string asmName> {
1110    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1111    def _dpp8_gfx10 :
1112      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1113        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1114        let AsmString = asmName # !subst(", vcc", "", AsmDPP8);
1115        let DecoderNamespace = "DPP8";
1116      }
1117    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1118    def _dpp8_w32_gfx10 :
1119      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1120        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1121        let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8);
1122        let isAsmParserOnly = 1;
1123        let WaveSizePredicate = isWave32;
1124      }
1125    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1126    def _dpp8_w64_gfx10 :
1127      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1128        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1129        let AsmString = asmName # AsmDPP8;
1130        let isAsmParserOnly = 1;
1131        let WaveSizePredicate = isWave64;
1132      }
1133  }
1134
1135  //===----------------------------- VOP3Only -----------------------------===//
1136  multiclass VOP3Only_Real_gfx10<bits<10> op> {
1137    def _e64_gfx10 :
1138      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1139      VOP3e_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1140  }
1141
1142  //===---------------------------- VOP3beOnly ----------------------------===//
1143  multiclass VOP3beOnly_Real_gfx10<bits<10> op> {
1144    def _e64_gfx10 :
1145      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1146      VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1147  }
1148} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
1149
1150multiclass VOP2be_Real_gfx10<bits<6> op, string opName, string asmName> :
1151  VOP2be_Real_e32_gfx10<op, opName, asmName>,
1152  VOP2be_Real_e64_gfx10<op, opName, asmName>,
1153  VOP2be_Real_sdwa_gfx10<op, opName, asmName>,
1154  VOP2be_Real_dpp_gfx10<op, opName, asmName>,
1155  VOP2be_Real_dpp8_gfx10<op, opName, asmName>;
1156
1157multiclass VOP2e_Real_gfx10<bits<6> op, string opName, string asmName> :
1158  VOP2_Real_e32_gfx10<op>,
1159  VOP2_Real_e64_gfx10<op>,
1160  VOP2be_Real_sdwa_gfx10<op, opName, asmName>,
1161  VOP2be_Real_dpp_gfx10<op, opName, asmName>,
1162  VOP2be_Real_dpp8_gfx10<op, opName, asmName>;
1163
1164multiclass VOP2_Real_gfx10<bits<6> op> :
1165  VOP2_Real_e32_gfx10<op>, VOP2_Real_e64_gfx10<op>,
1166  VOP2_Real_sdwa_gfx10<op>, VOP2_Real_dpp_gfx10<op>, VOP2_Real_dpp8_gfx10<op>;
1167
1168multiclass VOP2_Real_gfx10_with_name<bits<6> op, string opName,
1169                                     string asmName> :
1170  VOP2_Real_e32_gfx10_with_name<op, opName, asmName>,
1171  VOP2_Real_e64_gfx10_with_name<op, opName, asmName>,
1172  VOP2_Real_sdwa_gfx10_with_name<op, opName, asmName>,
1173  VOP2_Real_dpp_gfx10_with_name<op, opName, asmName>,
1174  VOP2_Real_dpp8_gfx10_with_name<op, opName, asmName>;
1175
1176// NB: Same opcode as v_mac_legacy_f32
1177let DecoderNamespace = "GFX10_B" in
1178defm V_FMAC_LEGACY_F32 : VOP2_Real_gfx10<0x006>;
1179
1180defm V_XNOR_B32        : VOP2_Real_gfx10<0x01e>;
1181defm V_FMAC_F32        : VOP2_Real_gfx10<0x02b>;
1182defm V_FMAMK_F32       : VOP2Only_Real_MADK_gfx10<0x02c>;
1183defm V_FMAAK_F32       : VOP2Only_Real_MADK_gfx10<0x02d>;
1184defm V_ADD_F16         : VOP2_Real_gfx10<0x032>;
1185defm V_SUB_F16         : VOP2_Real_gfx10<0x033>;
1186defm V_SUBREV_F16      : VOP2_Real_gfx10<0x034>;
1187defm V_MUL_F16         : VOP2_Real_gfx10<0x035>;
1188defm V_FMAC_F16        : VOP2_Real_gfx10<0x036>;
1189defm V_FMAMK_F16       : VOP2Only_Real_MADK_gfx10<0x037>;
1190defm V_FMAAK_F16       : VOP2Only_Real_MADK_gfx10<0x038>;
1191defm V_MAX_F16         : VOP2_Real_gfx10<0x039>;
1192defm V_MIN_F16         : VOP2_Real_gfx10<0x03a>;
1193defm V_LDEXP_F16       : VOP2_Real_gfx10<0x03b>;
1194defm V_PK_FMAC_F16     : VOP2_Real_e32_gfx10<0x03c>;
1195
1196// VOP2 no carry-in, carry-out.
1197defm V_ADD_NC_U32 :
1198  VOP2_Real_gfx10_with_name<0x025, "V_ADD_U32", "v_add_nc_u32">;
1199defm V_SUB_NC_U32 :
1200  VOP2_Real_gfx10_with_name<0x026, "V_SUB_U32", "v_sub_nc_u32">;
1201defm V_SUBREV_NC_U32 :
1202  VOP2_Real_gfx10_with_name<0x027, "V_SUBREV_U32", "v_subrev_nc_u32">;
1203
1204// VOP2 carry-in, carry-out.
1205defm V_ADD_CO_CI_U32 :
1206  VOP2be_Real_gfx10<0x028, "V_ADDC_U32", "v_add_co_ci_u32">;
1207defm V_SUB_CO_CI_U32 :
1208  VOP2be_Real_gfx10<0x029, "V_SUBB_U32", "v_sub_co_ci_u32">;
1209defm V_SUBREV_CO_CI_U32 :
1210  VOP2be_Real_gfx10<0x02a, "V_SUBBREV_U32", "v_subrev_co_ci_u32">;
1211
1212defm V_CNDMASK_B32 :
1213  VOP2e_Real_gfx10<0x001, "V_CNDMASK_B32", "v_cndmask_b32">;
1214
1215// VOP3 only.
1216defm V_BFM_B32            : VOP3Only_Real_gfx10<0x363>;
1217defm V_BCNT_U32_B32       : VOP3Only_Real_gfx10<0x364>;
1218defm V_MBCNT_LO_U32_B32   : VOP3Only_Real_gfx10<0x365>;
1219defm V_MBCNT_HI_U32_B32   : VOP3Only_Real_gfx10<0x366>;
1220defm V_LDEXP_F32          : VOP3Only_Real_gfx10<0x362>;
1221defm V_CVT_PKNORM_I16_F32 : VOP3Only_Real_gfx10<0x368>;
1222defm V_CVT_PKNORM_U16_F32 : VOP3Only_Real_gfx10<0x369>;
1223defm V_CVT_PK_U16_U32     : VOP3Only_Real_gfx10<0x36a>;
1224defm V_CVT_PK_I16_I32     : VOP3Only_Real_gfx10<0x36b>;
1225
1226// VOP3 carry-out.
1227defm V_ADD_CO_U32 : VOP3beOnly_Real_gfx10<0x30f>;
1228defm V_SUB_CO_U32 : VOP3beOnly_Real_gfx10<0x310>;
1229defm V_SUBREV_CO_U32 : VOP3beOnly_Real_gfx10<0x319>;
1230
1231let SubtargetPredicate = isGFX10Plus in {
1232  defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx10>;
1233
1234  defm : VOP2bInstAliases<
1235    V_ADDC_U32_e32, V_ADD_CO_CI_U32_e32_gfx10, "v_add_co_ci_u32">;
1236  defm : VOP2bInstAliases<
1237    V_SUBB_U32_e32, V_SUB_CO_CI_U32_e32_gfx10, "v_sub_co_ci_u32">;
1238  defm : VOP2bInstAliases<
1239    V_SUBBREV_U32_e32, V_SUBREV_CO_CI_U32_e32_gfx10, "v_subrev_co_ci_u32">;
1240} // End SubtargetPredicate = isGFX10Plus
1241
1242//===----------------------------------------------------------------------===//
1243// GFX6, GFX7, GFX10.
1244//===----------------------------------------------------------------------===//
1245
1246class VOP2_DPPe <bits<6> op, VOP2_DPP_Pseudo ps, VOPProfile P = ps.Pfl> :
1247  VOP_DPPe <P> {
1248  bits<8> vdst;
1249  bits<8> src1;
1250  let Inst{8-0}   = 0xfa; //dpp
1251  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
1252  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
1253  let Inst{30-25} = op;
1254  let Inst{31}    = 0x0; //encoding
1255}
1256
1257let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
1258  multiclass VOP2_Lane_Real_gfx6_gfx7<bits<6> op> {
1259    def _gfx6_gfx7 :
1260      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1261      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1262  }
1263  multiclass VOP2Only_Real_MADK_gfx6_gfx7<bits<6> op> {
1264    def _gfx6_gfx7 :
1265      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1266      VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1267  }
1268  multiclass VOP2_Real_e32_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1269    def _e32_gfx6_gfx7 :
1270      VOP2_Real<!cast<VOP2_Pseudo>(PseudoName#"_e32"), SIEncodingFamily.SI>,
1271      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(PseudoName#"_e32").Pfl>;
1272  }
1273  multiclass VOP2_Real_e64_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1274    def _e64_gfx6_gfx7 :
1275      VOP3_Real<!cast<VOP3_Pseudo>(PseudoName#"_e64"), SIEncodingFamily.SI>,
1276      VOP3e_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(PseudoName#"_e64").Pfl>;
1277  }
1278  multiclass VOP2be_Real_e64_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1279    def _e64_gfx6_gfx7 :
1280      VOP3_Real<!cast<VOP3_Pseudo>(PseudoName#"_e64"), SIEncodingFamily.SI>,
1281      VOP3be_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(PseudoName#"_e64").Pfl>;
1282  }
1283} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
1284
1285multiclass VOP2Only_Real_MADK_gfx6_gfx7_gfx10<bits<6> op> :
1286  VOP2Only_Real_MADK_gfx6_gfx7<op>, VOP2Only_Real_MADK_gfx10<op>;
1287
1288multiclass VOP2_Real_gfx6_gfx7<bits<6> op> :
1289  VOP2_Real_e32_gfx6_gfx7<op>, VOP2_Real_e64_gfx6_gfx7<op>;
1290
1291multiclass VOP2_Real_gfx6_gfx7_gfx10<bits<6> op> :
1292  VOP2_Real_gfx6_gfx7<op>, VOP2_Real_gfx10<op>;
1293
1294multiclass VOP2be_Real_gfx6_gfx7<bits<6> op> :
1295  VOP2_Real_e32_gfx6_gfx7<op>, VOP2be_Real_e64_gfx6_gfx7<op>;
1296
1297multiclass VOP2be_Real_gfx6_gfx7_with_name<bits<6> op,
1298  string PseudoName, string asmName>  {
1299  defvar ps32 = !cast<VOP2_Pseudo>(PseudoName#"_e32");
1300  defvar ps64 = !cast<VOP3_Pseudo>(PseudoName#"_e64");
1301
1302  let AsmString = asmName # ps32.AsmOperands in {
1303    defm "" : VOP2_Real_e32_gfx6_gfx7<op, PseudoName>;
1304  }
1305
1306   let AsmString = asmName # ps64.AsmOperands in {
1307    defm "" : VOP2be_Real_e64_gfx6_gfx7<op, PseudoName>;
1308  }
1309}
1310
1311defm V_CNDMASK_B32        : VOP2_Real_gfx6_gfx7<0x000>;
1312defm V_MIN_LEGACY_F32     : VOP2_Real_gfx6_gfx7<0x00d>;
1313defm V_MAX_LEGACY_F32     : VOP2_Real_gfx6_gfx7<0x00e>;
1314defm V_LSHR_B32           : VOP2_Real_gfx6_gfx7<0x015>;
1315defm V_ASHR_I32           : VOP2_Real_gfx6_gfx7<0x017>;
1316defm V_LSHL_B32           : VOP2_Real_gfx6_gfx7<0x019>;
1317defm V_BFM_B32            : VOP2_Real_gfx6_gfx7<0x01e>;
1318defm V_BCNT_U32_B32       : VOP2_Real_gfx6_gfx7<0x022>;
1319defm V_MBCNT_LO_U32_B32   : VOP2_Real_gfx6_gfx7<0x023>;
1320defm V_MBCNT_HI_U32_B32   : VOP2_Real_gfx6_gfx7<0x024>;
1321defm V_LDEXP_F32          : VOP2_Real_gfx6_gfx7<0x02b>;
1322defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_gfx6_gfx7<0x02c>;
1323defm V_CVT_PKNORM_I16_F32 : VOP2_Real_gfx6_gfx7<0x02d>;
1324defm V_CVT_PKNORM_U16_F32 : VOP2_Real_gfx6_gfx7<0x02e>;
1325defm V_CVT_PK_U16_U32     : VOP2_Real_gfx6_gfx7<0x030>;
1326defm V_CVT_PK_I16_I32     : VOP2_Real_gfx6_gfx7<0x031>;
1327
1328// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in
1329// VI, but the VI instructions behave the same as the SI versions.
1330defm V_ADD_I32            : VOP2be_Real_gfx6_gfx7_with_name<0x025, "V_ADD_CO_U32", "v_add_i32">;
1331defm V_SUB_I32            : VOP2be_Real_gfx6_gfx7_with_name<0x026, "V_SUB_CO_U32", "v_sub_i32">;
1332defm V_SUBREV_I32         : VOP2be_Real_gfx6_gfx7_with_name<0x027, "V_SUBREV_CO_U32", "v_subrev_i32">;
1333defm V_ADDC_U32           : VOP2be_Real_gfx6_gfx7<0x028>;
1334defm V_SUBB_U32           : VOP2be_Real_gfx6_gfx7<0x029>;
1335defm V_SUBBREV_U32        : VOP2be_Real_gfx6_gfx7<0x02a>;
1336
1337defm V_READLANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x001>;
1338
1339let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
1340  defm V_WRITELANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x002>;
1341} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)
1342
1343let SubtargetPredicate = isGFX6GFX7 in {
1344  defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx6_gfx7>;
1345  defm : VOP2eInstAliases<V_ADD_CO_U32_e32, V_ADD_I32_e32_gfx6_gfx7>;
1346  defm : VOP2eInstAliases<V_SUB_CO_U32_e32, V_SUB_I32_e32_gfx6_gfx7>;
1347  defm : VOP2eInstAliases<V_SUBREV_CO_U32_e32, V_SUBREV_I32_e32_gfx6_gfx7>;
1348
1349  def : VOP2e64InstAlias<V_ADD_CO_U32_e64, V_ADD_I32_e64_gfx6_gfx7>;
1350  def : VOP2e64InstAlias<V_SUB_CO_U32_e64, V_SUB_I32_e64_gfx6_gfx7>;
1351  def : VOP2e64InstAlias<V_SUBREV_CO_U32_e64, V_SUBREV_I32_e64_gfx6_gfx7>;
1352} // End SubtargetPredicate = isGFX6GFX7
1353
1354defm V_ADD_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x003>;
1355defm V_SUB_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x004>;
1356defm V_SUBREV_F32         : VOP2_Real_gfx6_gfx7_gfx10<0x005>;
1357defm V_MAC_LEGACY_F32     : VOP2_Real_gfx6_gfx7_gfx10<0x006>;
1358defm V_MUL_LEGACY_F32     : VOP2_Real_gfx6_gfx7_gfx10<0x007>;
1359defm V_MUL_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x008>;
1360defm V_MUL_I32_I24        : VOP2_Real_gfx6_gfx7_gfx10<0x009>;
1361defm V_MUL_HI_I32_I24     : VOP2_Real_gfx6_gfx7_gfx10<0x00a>;
1362defm V_MUL_U32_U24        : VOP2_Real_gfx6_gfx7_gfx10<0x00b>;
1363defm V_MUL_HI_U32_U24     : VOP2_Real_gfx6_gfx7_gfx10<0x00c>;
1364defm V_MIN_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x00f>;
1365defm V_MAX_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x010>;
1366defm V_MIN_I32            : VOP2_Real_gfx6_gfx7_gfx10<0x011>;
1367defm V_MAX_I32            : VOP2_Real_gfx6_gfx7_gfx10<0x012>;
1368defm V_MIN_U32            : VOP2_Real_gfx6_gfx7_gfx10<0x013>;
1369defm V_MAX_U32            : VOP2_Real_gfx6_gfx7_gfx10<0x014>;
1370defm V_LSHRREV_B32        : VOP2_Real_gfx6_gfx7_gfx10<0x016>;
1371defm V_ASHRREV_I32        : VOP2_Real_gfx6_gfx7_gfx10<0x018>;
1372defm V_LSHLREV_B32        : VOP2_Real_gfx6_gfx7_gfx10<0x01a>;
1373defm V_AND_B32            : VOP2_Real_gfx6_gfx7_gfx10<0x01b>;
1374defm V_OR_B32             : VOP2_Real_gfx6_gfx7_gfx10<0x01c>;
1375defm V_XOR_B32            : VOP2_Real_gfx6_gfx7_gfx10<0x01d>;
1376defm V_MAC_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x01f>;
1377defm V_CVT_PKRTZ_F16_F32  : VOP2_Real_gfx6_gfx7_gfx10<0x02f>;
1378defm V_MADMK_F32          : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x020>;
1379defm V_MADAK_F32          : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x021>;
1380
1381//===----------------------------------------------------------------------===//
1382// GFX8, GFX9 (VI).
1383//===----------------------------------------------------------------------===//
1384
1385let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {
1386
1387multiclass VOP2_Real_MADK_vi <bits<6> op> {
1388  def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,
1389            VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1390}
1391
1392multiclass VOP2_Real_e32_vi <bits<6> op> {
1393  def _e32_vi :
1394    VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
1395    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
1396}
1397
1398multiclass VOP2_Real_e64_vi <bits<10> op> {
1399  def _e64_vi :
1400    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
1401    VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1402}
1403
1404multiclass VOP2_Real_e64only_vi <bits<10> op> {
1405  def _e64_vi :
1406    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
1407    VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1408      // Hack to stop printing _e64
1409      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME#"_e64");
1410      let OutOperandList = (outs VGPR_32:$vdst);
1411      let AsmString = ps.Mnemonic # " " # ps.AsmOperands;
1412    }
1413}
1414
1415multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> :
1416  VOP2_Real_e32_vi<op>,
1417  VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>;
1418
1419} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8"
1420
1421multiclass VOP2_SDWA_Real <bits<6> op> {
1422  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA>.ret in
1423  def _sdwa_vi :
1424    VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1425    VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1426}
1427
1428multiclass VOP2_SDWA9_Real <bits<6> op> {
1429  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
1430  def _sdwa_gfx9 :
1431    VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1432    VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1433}
1434
1435let AssemblerPredicate = isGFX8Only in {
1436
1437multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName> {
1438  def _e32_vi :
1439    VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.VI>,
1440    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
1441      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32");
1442      let AsmString = AsmName # ps.AsmOperands;
1443      let DecoderNamespace = "GFX8";
1444    }
1445  def _e64_vi :
1446    VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.VI>,
1447    VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
1448      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64");
1449      let AsmString = AsmName # ps.AsmOperands;
1450      let DecoderNamespace = "GFX8";
1451    }
1452  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA>.ret in
1453    def _sdwa_vi :
1454      VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>,
1455      VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {
1456        VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa");
1457        let AsmString = AsmName # ps.AsmOperands;
1458      }
1459  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in
1460    def _dpp_vi :
1461      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.VI>,
1462      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> {
1463        VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp");
1464        let AsmString = AsmName # ps.AsmOperands;
1465      }
1466}
1467}
1468
1469let AssemblerPredicate = isGFX9Only in {
1470
1471multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> {
1472  def _e32_gfx9 :
1473    VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.GFX9>,
1474    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
1475      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32");
1476      let AsmString = AsmName # ps.AsmOperands;
1477      let DecoderNamespace = "GFX9";
1478    }
1479  def _e64_gfx9 :
1480    VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>,
1481    VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
1482      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64");
1483      let AsmString = AsmName # ps.AsmOperands;
1484      let DecoderNamespace = "GFX9";
1485    }
1486  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA9>.ret in
1487    def _sdwa_gfx9 :
1488      VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>,
1489      VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {
1490        VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa");
1491        let AsmString = AsmName # ps.AsmOperands;
1492      }
1493  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in
1494    def _dpp_gfx9 :
1495      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.GFX9>,
1496      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> {
1497        VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp");
1498        let AsmString = AsmName # ps.AsmOperands;
1499        let DecoderNamespace = "SDWA9";
1500      }
1501}
1502
1503multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> {
1504  def _e32_gfx9 :
1505    VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX9>,
1506    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>{
1507      let DecoderNamespace = "GFX9";
1508    }
1509  def _e64_gfx9 :
1510    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>,
1511    VOP3e_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1512      let DecoderNamespace = "GFX9";
1513    }
1514  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
1515    def _sdwa_gfx9 :
1516      VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1517      VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
1518      }
1519  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
1520    def _dpp_gfx9 :
1521      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,
1522      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
1523        let DecoderNamespace = "SDWA9";
1524      }
1525}
1526
1527} // AssemblerPredicate = isGFX9Only
1528
1529multiclass VOP2_Real_e32e64_vi <bits<6> op> :
1530  Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> {
1531
1532  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
1533    def _dpp_vi :
1534      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.VI>,
1535      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;
1536}
1537
1538defm V_CNDMASK_B32        : VOP2_Real_e32e64_vi <0x0>;
1539defm V_ADD_F32            : VOP2_Real_e32e64_vi <0x1>;
1540defm V_SUB_F32            : VOP2_Real_e32e64_vi <0x2>;
1541defm V_SUBREV_F32         : VOP2_Real_e32e64_vi <0x3>;
1542let AssemblerPredicate = isGCN3ExcludingGFX90A in
1543defm V_MUL_LEGACY_F32     : VOP2_Real_e32e64_vi <0x4>;
1544defm V_MUL_F32            : VOP2_Real_e32e64_vi <0x5>;
1545defm V_MUL_I32_I24        : VOP2_Real_e32e64_vi <0x6>;
1546defm V_MUL_HI_I32_I24     : VOP2_Real_e32e64_vi <0x7>;
1547defm V_MUL_U32_U24        : VOP2_Real_e32e64_vi <0x8>;
1548defm V_MUL_HI_U32_U24     : VOP2_Real_e32e64_vi <0x9>;
1549defm V_MIN_F32            : VOP2_Real_e32e64_vi <0xa>;
1550defm V_MAX_F32            : VOP2_Real_e32e64_vi <0xb>;
1551defm V_MIN_I32            : VOP2_Real_e32e64_vi <0xc>;
1552defm V_MAX_I32            : VOP2_Real_e32e64_vi <0xd>;
1553defm V_MIN_U32            : VOP2_Real_e32e64_vi <0xe>;
1554defm V_MAX_U32            : VOP2_Real_e32e64_vi <0xf>;
1555defm V_LSHRREV_B32        : VOP2_Real_e32e64_vi <0x10>;
1556defm V_ASHRREV_I32        : VOP2_Real_e32e64_vi <0x11>;
1557defm V_LSHLREV_B32        : VOP2_Real_e32e64_vi <0x12>;
1558defm V_AND_B32            : VOP2_Real_e32e64_vi <0x13>;
1559defm V_OR_B32             : VOP2_Real_e32e64_vi <0x14>;
1560defm V_XOR_B32            : VOP2_Real_e32e64_vi <0x15>;
1561defm V_MAC_F32            : VOP2_Real_e32e64_vi <0x16>;
1562defm V_MADMK_F32          : VOP2_Real_MADK_vi <0x17>;
1563defm V_MADAK_F32          : VOP2_Real_MADK_vi <0x18>;
1564
1565defm V_ADD_U32            : VOP2be_Real_e32e64_vi_only <0x19, "V_ADD_CO_U32",     "v_add_u32">;
1566defm V_SUB_U32            : VOP2be_Real_e32e64_vi_only <0x1a, "V_SUB_CO_U32",     "v_sub_u32">;
1567defm V_SUBREV_U32         : VOP2be_Real_e32e64_vi_only <0x1b, "V_SUBREV_CO_U32",  "v_subrev_u32">;
1568defm V_ADDC_U32           : VOP2be_Real_e32e64_vi_only <0x1c, "V_ADDC_U32",    "v_addc_u32">;
1569defm V_SUBB_U32           : VOP2be_Real_e32e64_vi_only <0x1d, "V_SUBB_U32",    "v_subb_u32">;
1570defm V_SUBBREV_U32        : VOP2be_Real_e32e64_vi_only <0x1e, "V_SUBBREV_U32", "v_subbrev_u32">;
1571
1572defm V_ADD_CO_U32         : VOP2be_Real_e32e64_gfx9 <0x19, "V_ADD_CO_U32",     "v_add_co_u32">;
1573defm V_SUB_CO_U32         : VOP2be_Real_e32e64_gfx9 <0x1a, "V_SUB_CO_U32",     "v_sub_co_u32">;
1574defm V_SUBREV_CO_U32      : VOP2be_Real_e32e64_gfx9 <0x1b, "V_SUBREV_CO_U32",  "v_subrev_co_u32">;
1575defm V_ADDC_CO_U32        : VOP2be_Real_e32e64_gfx9 <0x1c, "V_ADDC_U32",    "v_addc_co_u32">;
1576defm V_SUBB_CO_U32        : VOP2be_Real_e32e64_gfx9 <0x1d, "V_SUBB_U32",    "v_subb_co_u32">;
1577defm V_SUBBREV_CO_U32     : VOP2be_Real_e32e64_gfx9 <0x1e, "V_SUBBREV_U32", "v_subbrev_co_u32">;
1578
1579defm V_ADD_U32            : VOP2_Real_e32e64_gfx9 <0x34>;
1580defm V_SUB_U32            : VOP2_Real_e32e64_gfx9 <0x35>;
1581defm V_SUBREV_U32         : VOP2_Real_e32e64_gfx9 <0x36>;
1582
1583defm V_BFM_B32            : VOP2_Real_e64only_vi <0x293>;
1584defm V_BCNT_U32_B32       : VOP2_Real_e64only_vi <0x28b>;
1585defm V_MBCNT_LO_U32_B32   : VOP2_Real_e64only_vi <0x28c>;
1586defm V_MBCNT_HI_U32_B32   : VOP2_Real_e64only_vi <0x28d>;
1587defm V_LDEXP_F32          : VOP2_Real_e64only_vi <0x288>;
1588defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64only_vi <0x1f0>;
1589defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64only_vi <0x294>;
1590defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64only_vi <0x295>;
1591defm V_CVT_PKRTZ_F16_F32  : VOP2_Real_e64only_vi <0x296>;
1592defm V_CVT_PK_U16_U32     : VOP2_Real_e64only_vi <0x297>;
1593defm V_CVT_PK_I16_I32     : VOP2_Real_e64only_vi <0x298>;
1594
1595defm V_ADD_F16            : VOP2_Real_e32e64_vi <0x1f>;
1596defm V_SUB_F16            : VOP2_Real_e32e64_vi <0x20>;
1597defm V_SUBREV_F16         : VOP2_Real_e32e64_vi <0x21>;
1598defm V_MUL_F16            : VOP2_Real_e32e64_vi <0x22>;
1599defm V_MAC_F16            : VOP2_Real_e32e64_vi <0x23>;
1600defm V_MADMK_F16          : VOP2_Real_MADK_vi <0x24>;
1601defm V_MADAK_F16          : VOP2_Real_MADK_vi <0x25>;
1602defm V_ADD_U16            : VOP2_Real_e32e64_vi <0x26>;
1603defm V_SUB_U16            : VOP2_Real_e32e64_vi <0x27>;
1604defm V_SUBREV_U16         : VOP2_Real_e32e64_vi <0x28>;
1605defm V_MUL_LO_U16         : VOP2_Real_e32e64_vi <0x29>;
1606defm V_LSHLREV_B16        : VOP2_Real_e32e64_vi <0x2a>;
1607defm V_LSHRREV_B16        : VOP2_Real_e32e64_vi <0x2b>;
1608defm V_ASHRREV_I16        : VOP2_Real_e32e64_vi <0x2c>;
1609defm V_MAX_F16            : VOP2_Real_e32e64_vi <0x2d>;
1610defm V_MIN_F16            : VOP2_Real_e32e64_vi <0x2e>;
1611defm V_MAX_U16            : VOP2_Real_e32e64_vi <0x2f>;
1612defm V_MAX_I16            : VOP2_Real_e32e64_vi <0x30>;
1613defm V_MIN_U16            : VOP2_Real_e32e64_vi <0x31>;
1614defm V_MIN_I16            : VOP2_Real_e32e64_vi <0x32>;
1615defm V_LDEXP_F16          : VOP2_Real_e32e64_vi <0x33>;
1616
1617let SubtargetPredicate = isGFX8GFX9 in {
1618
1619// Aliases to simplify matching of floating-point instructions that
1620// are VOP2 on SI and VOP3 on VI.
1621class SI2_VI3Alias <string name, VOP3_Real inst> : InstAlias <
1622  name#" $dst, $src0, $src1",
1623  !if(inst.Pfl.HasOMod,
1624      (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0),
1625      (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0))
1626>, PredicateControl {
1627  let UseInstAsmMatchConverter = 0;
1628  let AsmVariantName = AMDGPUAsmVariants.VOP3;
1629}
1630
1631def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>;
1632def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>;
1633def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>;
1634def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;
1635def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;
1636
1637defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_vi>;
1638
1639} // End SubtargetPredicate = isGFX8GFX9
1640
1641let SubtargetPredicate = isGFX9Only in {
1642
1643defm : VOP2bInstAliases<V_ADD_U32_e32,     V_ADD_CO_U32_e32_gfx9,     "v_add_co_u32">;
1644defm : VOP2bInstAliases<V_ADDC_U32_e32,    V_ADDC_CO_U32_e32_gfx9,    "v_addc_co_u32">;
1645defm : VOP2bInstAliases<V_SUB_U32_e32,     V_SUB_CO_U32_e32_gfx9,     "v_sub_co_u32">;
1646defm : VOP2bInstAliases<V_SUBB_U32_e32,    V_SUBB_CO_U32_e32_gfx9,    "v_subb_co_u32">;
1647defm : VOP2bInstAliases<V_SUBREV_U32_e32,  V_SUBREV_CO_U32_e32_gfx9,  "v_subrev_co_u32">;
1648defm : VOP2bInstAliases<V_SUBBREV_U32_e32, V_SUBBREV_CO_U32_e32_gfx9, "v_subbrev_co_u32">;
1649
1650} // End SubtargetPredicate = isGFX9Only
1651
1652let SubtargetPredicate = HasDLInsts in {
1653
1654defm V_FMAC_F32 : VOP2_Real_e32e64_vi <0x3b>;
1655defm V_XNOR_B32 : VOP2_Real_e32e64_vi <0x3d>;
1656
1657} // End SubtargetPredicate = HasDLInsts
1658
1659let AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A" in {
1660  multiclass VOP2_Real_e32_gfx90a <bits<6> op> {
1661    def _e32_gfx90a :
1662      VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX90A>,
1663      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
1664  }
1665
1666  multiclass VOP2_Real_e64_gfx90a <bits<10> op> {
1667    def _e64_gfx90a :
1668      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX90A>,
1669      VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1670  }
1671
1672  multiclass Base_VOP2_Real_e32e64_gfx90a <bits<6> op> :
1673    VOP2_Real_e32_gfx90a<op>,
1674    VOP2_Real_e64_gfx90a<{0, 1, 0, 0, op{5-0}}>;
1675
1676  multiclass VOP2_Real_e32e64_gfx90a <bits<6> op> :
1677    Base_VOP2_Real_e32e64_gfx90a<op> {
1678
1679    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
1680      def _dpp_gfx90a :
1681        VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX90A>,
1682        VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
1683          let DecoderNamespace = "SDWA9";
1684        }
1685  }
1686} // End AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A"
1687
1688let SubtargetPredicate = isGFX90APlus in {
1689  defm V_FMAC_F64       : VOP2_Real_e32e64_gfx90a <0x4>;
1690  defm V_MUL_LEGACY_F32 : VOP2_Real_e64_gfx90a <0x2a1>;
1691} // End SubtargetPredicate = isGFX90APlus
1692
1693multiclass VOP2_Real_DOT_ACC_gfx9<bits<6> op> : VOP2_Real_e32_vi<op> {
1694  def _dpp_vi : VOP2_DPP<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;
1695}
1696
1697multiclass VOP2_Real_DOT_ACC_gfx10<bits<6> op> :
1698  VOP2_Real_e32_gfx10<op>,
1699  VOP2_Real_dpp_gfx10<op>,
1700  VOP2_Real_dpp8_gfx10<op>;
1701
1702let SubtargetPredicate = HasDot5Insts in {
1703  defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx9<0x37>;
1704  // NB: Opcode conflicts with V_DOT8C_I32_I4
1705  // This opcode exists in gfx 10.1* only
1706  defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx10<0x02>;
1707}
1708
1709let SubtargetPredicate = HasDot6Insts in {
1710  defm V_DOT4C_I32_I8  : VOP2_Real_DOT_ACC_gfx9<0x39>;
1711  defm V_DOT4C_I32_I8  : VOP2_Real_DOT_ACC_gfx10<0x0d>;
1712}
1713
1714let SubtargetPredicate = HasDot4Insts in {
1715  defm V_DOT2C_I32_I16 : VOP2_Real_DOT_ACC_gfx9<0x38>;
1716}
1717let SubtargetPredicate = HasDot3Insts in {
1718  defm V_DOT8C_I32_I4  : VOP2_Real_DOT_ACC_gfx9<0x3a>;
1719}
1720
1721let SubtargetPredicate = HasPkFmacF16Inst in {
1722defm V_PK_FMAC_F16 : VOP2_Real_e32_vi<0x3c>;
1723} // End SubtargetPredicate = HasPkFmacF16Inst
1724
1725let SubtargetPredicate = HasDot3Insts in {
1726  // NB: Opcode conflicts with V_DOT2C_F32_F16
1727  let DecoderNamespace = "GFX10_B" in
1728  defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx10<0x02>;
1729}
1730