1//===-- VOP2Instructions.td - Vector Instruction Definitions --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// VOP2 Classes
11//===----------------------------------------------------------------------===//
12
13class VOP2e <bits<6> op, VOPProfile P> : Enc32 {
14  bits<8> vdst;
15  bits<9> src0;
16  bits<8> src1;
17
18  let Inst{8-0}   = !if(P.HasSrc0, src0, 0);
19  let Inst{16-9}  = !if(P.HasSrc1, src1, 0);
20  let Inst{24-17} = !if(P.EmitDst, vdst, 0);
21  let Inst{30-25} = op;
22  let Inst{31}    = 0x0; //encoding
23}
24
25class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 {
26  bits<8>  vdst;
27  bits<9>  src0;
28  bits<8>  src1;
29  bits<32> imm;
30
31  let Inst{8-0}   = !if(P.HasSrc0, src0, 0);
32  let Inst{16-9}  = !if(P.HasSrc1, src1, 0);
33  let Inst{24-17} = !if(P.EmitDst, vdst, 0);
34  let Inst{30-25} = op;
35  let Inst{31}    = 0x0; // encoding
36  let Inst{63-32} = imm;
37}
38
39class VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> {
40  bits<8> vdst;
41  bits<8> src1;
42
43  let Inst{8-0}   = 0xf9; // sdwa
44  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
45  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
46  let Inst{30-25} = op;
47  let Inst{31}    = 0x0; // encoding
48}
49
50class VOP2_SDWA9Ae <bits<6> op, VOPProfile P> : VOP_SDWA9Ae <P> {
51  bits<8> vdst;
52  bits<9> src1;
53
54  let Inst{8-0}   = 0xf9; // sdwa
55  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
56  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
57  let Inst{30-25} = op;
58  let Inst{31}    = 0x0; // encoding
59  let Inst{63}    = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr
60}
61
62class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> :
63  VOP_Pseudo <opName, suffix, P, P.Outs32, P.Ins32, "", pattern> {
64
65  let AsmOperands = P.Asm32;
66
67  let Size = 4;
68  let mayLoad = 0;
69  let mayStore = 0;
70  let hasSideEffects = 0;
71
72  let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
73
74  let mayRaiseFPException = ReadsModeReg;
75
76  let VOP2 = 1;
77  let VALU = 1;
78  let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
79
80  let AsmVariantName = AMDGPUAsmVariants.Default;
81}
82
83class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> :
84  InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
85  SIMCInstr <ps.PseudoInstr, EncodingFamily> {
86
87  let isPseudo = 0;
88  let isCodeGenOnly = 0;
89
90  let Constraints     = ps.Constraints;
91  let DisableEncoding = ps.DisableEncoding;
92
93  // copy relevant pseudo op flags
94  let SubtargetPredicate = ps.SubtargetPredicate;
95  let OtherPredicates    = ps.OtherPredicates;
96  let AsmMatchConverter  = ps.AsmMatchConverter;
97  let AsmVariantName     = ps.AsmVariantName;
98  let Constraints        = ps.Constraints;
99  let DisableEncoding    = ps.DisableEncoding;
100  let TSFlags            = ps.TSFlags;
101  let UseNamedOperandTable = ps.UseNamedOperandTable;
102  let Uses                 = ps.Uses;
103  let Defs                 = ps.Defs;
104  let SchedRW              = ps.SchedRW;
105}
106
107class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
108  VOP_SDWA_Pseudo <OpName, P, pattern> {
109  let AsmMatchConverter = "cvtSdwaVOP2";
110}
111
112class VOP2_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
113  VOP_DPP_Pseudo <OpName, P, pattern> {
114}
115
116
117class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies {
118  list<dag> ret = !if(P.HasModifiers,
119    [(set P.DstVT:$vdst,
120      (node (P.Src0VT
121              !if(P.HasOMod,
122                  (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
123                  (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
124            (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
125    [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
126}
127
128multiclass VOP2Inst_e32<string opName,
129                        VOPProfile P,
130                        SDPatternOperator node = null_frag,
131                        string revOp = opName,
132                        bit GFX9Renamed = 0> {
133  let renamedInGFX9 = GFX9Renamed in {
134    def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
135               Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
136  } // End renamedInGFX9 = GFX9Renamed
137}
138
139multiclass VOP2Inst_e64<string opName,
140                        VOPProfile P,
141                        SDPatternOperator node = null_frag,
142                        string revOp = opName,
143                        bit GFX9Renamed = 0> {
144  let renamedInGFX9 = GFX9Renamed in {
145    def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
146               Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
147  } // End renamedInGFX9 = GFX9Renamed
148}
149
150multiclass VOP2Inst_sdwa<string opName,
151                         VOPProfile P,
152                         SDPatternOperator node = null_frag,
153                         string revOp = opName,
154                         bit GFX9Renamed = 0> {
155  let renamedInGFX9 = GFX9Renamed in {
156    foreach _ = BoolToList<P.HasExtSDWA>.ret in
157      def _sdwa : VOP2_SDWA_Pseudo <opName, P>;
158  } // End renamedInGFX9 = GFX9Renamed
159}
160
161multiclass VOP2Inst<string opName,
162                    VOPProfile P,
163                    SDPatternOperator node = null_frag,
164                    string revOp = opName,
165                    bit GFX9Renamed = 0> :
166    VOP2Inst_e32<opName, P, node, revOp, GFX9Renamed>,
167    VOP2Inst_e64<opName, P, node, revOp, GFX9Renamed>,
168    VOP2Inst_sdwa<opName, P, node, revOp, GFX9Renamed> {
169  let renamedInGFX9 = GFX9Renamed in {
170    foreach _ = BoolToList<P.HasExtDPP>.ret in
171      def _dpp  : VOP2_DPP_Pseudo <opName, P>;
172  }
173}
174
175multiclass VOP2bInst <string opName,
176                      VOPProfile P,
177                      SDPatternOperator node = null_frag,
178                      string revOp = opName,
179                      bit GFX9Renamed = 0,
180                      bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
181  let renamedInGFX9 = GFX9Renamed in {
182    let SchedRW = [Write32Bit, WriteSALU] in {
183      let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
184        def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
185                   Commutable_REV<revOp#"_e32", !eq(revOp, opName)> {
186          let usesCustomInserter = !eq(P.NumSrcArgs, 2);
187        }
188
189        foreach _ = BoolToList<P.HasExtSDWA>.ret in
190          def _sdwa  : VOP2_SDWA_Pseudo <opName, P> {
191            let AsmMatchConverter = "cvtSdwaVOP2b";
192          }
193        foreach _ = BoolToList<P.HasExtDPP>.ret in
194          def _dpp  : VOP2_DPP_Pseudo <opName, P>;
195      }
196
197      def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
198                 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
199    }
200  }
201}
202
203class VOP2bInstAlias <VOP2_Pseudo ps, Instruction inst,
204                      string OpName, string opnd> :
205  InstAlias <OpName#" "#!subst("vcc", opnd, ps.Pfl.Asm32),
206             (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
207                   ps.Pfl.Src1RC32:$src1)>,
208  PredicateControl {
209}
210
211multiclass VOP2bInstAliases<VOP2_Pseudo ps, VOP2_Real inst, string OpName> {
212  let WaveSizePredicate = isWave32 in {
213    def : VOP2bInstAlias<ps, inst, OpName, "vcc_lo">;
214  }
215  let WaveSizePredicate = isWave64 in {
216    def : VOP2bInstAlias<ps, inst, OpName, "vcc">;
217  }
218}
219
220multiclass VOP2eInst <string opName,
221                      VOPProfile P,
222                      SDPatternOperator node = null_frag,
223                      string revOp = opName,
224                      bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
225
226  let SchedRW = [Write32Bit] in {
227    let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in {
228      def _e32 : VOP2_Pseudo <opName, P>,
229                 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
230
231      foreach _ = BoolToList<P.HasExtSDWA>.ret in
232        def _sdwa : VOP2_SDWA_Pseudo <opName, P> {
233          let AsmMatchConverter = "cvtSdwaVOP2e";
234        }
235
236      foreach _ = BoolToList<P.HasExtDPP>.ret in
237        def _dpp  : VOP2_DPP_Pseudo <opName, P>;
238    }
239
240    def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
241               Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
242  }
243}
244
245class VOP2eInstAlias <VOP2_Pseudo ps, Instruction inst, string opnd = ""> :
246  InstAlias <ps.OpName#" "#ps.Pfl.Asm32#", "#opnd,
247             (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
248                   ps.Pfl.Src1RC32:$src1)>, PredicateControl;
249
250class VOP2e64InstAlias <VOP3_Pseudo ps, Instruction inst> :
251  InstAlias <ps.OpName#" "#ps.Pfl.Asm64,
252             (inst ps.Pfl.DstRC:$vdst, VOPDstS64orS32:$sdst,
253                   ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, clampmod:$clamp)>,
254  PredicateControl;
255
256multiclass VOP2eInstAliases<VOP2_Pseudo ps, VOP2_Real inst> {
257  let WaveSizePredicate = isWave32 in {
258    def : VOP2eInstAlias<ps, inst, "vcc_lo">;
259  }
260  let WaveSizePredicate = isWave64 in {
261    def : VOP2eInstAlias<ps, inst, "vcc">;
262  }
263}
264
265class VOP_MADAK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
266  field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
267  field dag Ins32 = !if(!eq(vt.Size, 32),
268                        (ins VCSrc_f32:$src0, VGPR_32:$src1, ImmOpType:$imm),
269                        (ins VCSrc_f16:$src0, VGPR_32:$src1, ImmOpType:$imm));
270  field bit HasExt = 0;
271
272  // Hack to stop printing _e64
273  let DstRC = RegisterOperand<VGPR_32>;
274  field string Asm32 = " $vdst, $src0, $src1, $imm";
275}
276
277def VOP_MADAK_F16 : VOP_MADAK <f16>;
278def VOP_MADAK_F32 : VOP_MADAK <f32>;
279
280class VOP_MADMK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
281  field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
282  field dag Ins32 = (ins VCSrc_f32:$src0, ImmOpType:$imm, VGPR_32:$src1);
283  field bit HasExt = 0;
284
285  // Hack to stop printing _e64
286  let DstRC = RegisterOperand<VGPR_32>;
287  field string Asm32 = " $vdst, $src0, $imm, $src1";
288}
289
290def VOP_MADMK_F16 : VOP_MADMK <f16>;
291def VOP_MADMK_F32 : VOP_MADMK <f32>;
292
293class getRegisterOperandForVT<ValueType VT> {
294  RegisterOperand ret = RegisterOperand<getVregSrcForVT<VT>.ret>;
295}
296
297// FIXME: Remove src2_modifiers. It isn't used, so is wasting memory
298// and processing time but it makes it easier to convert to mad.
299class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, vt0]> {
300  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, getVregSrcForVT<Src2VT>.ret:$src2);
301  let Ins64 = getIns64<Src0RC64, Src1RC64, getRegisterOperandForVT<Src2VT>.ret, 3,
302                       0, HasModifiers, HasModifiers, HasOMod,
303                       Src0Mod, Src1Mod, Src2Mod>.ret;
304  let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
305                    Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
306                    getVregSrcForVT<Src2VT>.ret:$src2, // stub argument
307                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
308                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
309  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
310  let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
311                     Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
312                     getVregSrcForVT<Src2VT>.ret:$src2, // stub argument
313                     dpp8:$dpp8, FI:$fi);
314  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
315                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
316                     getVregSrcForVT<Src2VT>.ret:$src2, // stub argument
317                     clampmod:$clamp, omod:$omod,
318                     dst_sel:$dst_sel, dst_unused:$dst_unused,
319                     src0_sel:$src0_sel, src1_sel:$src1_sel);
320  let Asm32 = getAsm32<1, 2, vt0>.ret;
321  let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, vt0>.ret;
322  let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt0>.ret;
323  let AsmDPP16 = getAsmDPP16<1, 2, HasModifiers, vt0>.ret;
324  let AsmDPP8 = getAsmDPP8<1, 2, 0, vt0>.ret;
325  let AsmSDWA = getAsmSDWA<1, 2, vt0>.ret;
326  let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt0>.ret;
327  let HasSrc2 = 0;
328  let HasSrc2Mods = 0;
329
330  let HasExt = 1;
331  let HasExtDPP = 1;
332  let HasExtSDWA = 1;
333  let HasExtSDWA9 = 0;
334  let TieRegDPP = "$src2";
335}
336
337def VOP_MAC_F16 : VOP_MAC <f16>;
338def VOP_MAC_F32 : VOP_MAC <f32>;
339let HasExtDPP = 0 in
340def VOP_MAC_LEGACY_F32 : VOP_MAC <f32>;
341let HasExtSDWA = 0, HasExt64BitDPP = 1 in
342def VOP_MAC_F64 : VOP_MAC <f64>;
343
344class VOP_DOT_ACC<ValueType vt0, ValueType vt1> : VOP_MAC<vt0, vt1> {
345  let HasClamp = 0;
346  let HasExtSDWA = 0;
347  let HasOpSel = 0;
348  let IsPacked = 0;
349}
350
351def VOP_DOT_ACC_F32_V2F16 : VOP_DOT_ACC<f32, v2f16> {
352  let Src0ModDPP = FPVRegInputMods;
353  let Src1ModDPP = FPVRegInputMods;
354}
355
356def VOP_DOT_ACC_I32_I32   : VOP_DOT_ACC<i32, i32> {
357  let HasSrc0Mods = 1;
358  let HasSrc1Mods = 1;
359}
360
361// Write out to vcc or arbitrary SGPR.
362def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], 0, /*EnableClamp=*/1> {
363  let Asm32 = "$vdst, vcc, $src0, $src1";
364  let Asm64 = "$vdst, $sdst, $src0, $src1$clamp";
365  let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
366  let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
367  let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
368  let AsmDPP8 = "$vdst, vcc, $src0, $src1 $dpp8$fi";
369  let AsmDPP16 = AsmDPP#"$fi";
370  let Outs32 = (outs DstRC:$vdst);
371  let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
372}
373
374// Write out to vcc or arbitrary SGPR and read in from vcc or
375// arbitrary SGPR.
376def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], 0, /*EnableClamp=*/1> {
377  let Asm32 = "$vdst, vcc, $src0, $src1, vcc";
378  let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
379  let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
380  let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
381  let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
382  let AsmDPP8 = "$vdst, vcc, $src0, $src1, vcc $dpp8$fi";
383  let AsmDPP16 = AsmDPP#"$fi";
384  let Outs32 = (outs DstRC:$vdst);
385  let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
386
387  // Suppress src2 implied by type since the 32-bit encoding uses an
388  // implicit VCC use.
389  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
390
391  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
392                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
393                     clampmod:$clamp,
394                     dst_sel:$dst_sel, dst_unused:$dst_unused,
395                     src0_sel:$src0_sel, src1_sel:$src1_sel);
396
397  let InsDPP = (ins DstRCDPP:$old,
398                    Src0DPP:$src0,
399                    Src1DPP:$src1,
400                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
401                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
402  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
403
404  let HasExt = 1;
405  let HasExtDPP = 1;
406  let HasExtSDWA = 1;
407  let HasExtSDWA9 = 1;
408}
409
410// Read in from vcc or arbitrary SGPR.
411def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], /*EnableF32SrcMods=*/1> {
412  let Asm32 = "$vdst, $src0, $src1";
413  let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2";
414  let AsmSDWA = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
415  let AsmSDWA9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
416  let AsmDPP = "$vdst, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
417  let AsmDPP8 = "$vdst, $src0, $src1, vcc $dpp8$fi";
418  let AsmDPP16 = AsmDPP#"$fi";
419
420  let Outs32 = (outs DstRC:$vdst);
421  let Outs64 = (outs DstRC:$vdst);
422
423  // Suppress src2 implied by type since the 32-bit encoding uses an
424  // implicit VCC use.
425  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
426
427  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
428                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
429                     clampmod:$clamp,
430                     dst_sel:$dst_sel, dst_unused:$dst_unused,
431                     src0_sel:$src0_sel, src1_sel:$src1_sel);
432
433  let InsDPP = (ins DstRCDPP:$old,
434                    Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
435                    Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
436                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
437                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
438  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
439
440  let HasExt = 1;
441  let HasExtDPP = 1;
442  let HasExtSDWA = 1;
443  let HasExtSDWA9 = 1;
444}
445
446def VOP_READLANE : VOPProfile<[i32, i32, i32]> {
447  let Outs32 = (outs SReg_32:$vdst);
448  let Outs64 = Outs32;
449  let Ins32 = (ins VRegOrLds_32:$src0, SCSrc_b32:$src1);
450  let Ins64 = Ins32;
451  let Asm32 = " $vdst, $src0, $src1";
452  let Asm64 = Asm32;
453
454  let HasExt = 0;
455  let HasExtDPP = 0;
456  let HasExt64BitDPP = 0;
457  let HasExtSDWA = 0;
458  let HasExtSDWA9 = 0;
459}
460
461def VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> {
462  let Outs32 = (outs VGPR_32:$vdst);
463  let Outs64 = Outs32;
464  let Ins32 = (ins SCSrc_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in);
465  let Ins64 = Ins32;
466  let Asm32 = " $vdst, $src0, $src1";
467  let Asm64 = Asm32;
468  let HasSrc2 = 0;
469  let HasSrc2Mods = 0;
470
471  let HasExt = 0;
472  let HasExtDPP = 0;
473  let HasExt64BitDPP = 0;
474  let HasExtSDWA = 0;
475  let HasExtSDWA9 = 0;
476}
477
478//===----------------------------------------------------------------------===//
479// VOP2 Instructions
480//===----------------------------------------------------------------------===//
481
482defm V_CNDMASK_B32 : VOP2eInst <"v_cndmask_b32", VOP2e_I32_I32_I32_I1>;
483let SubtargetPredicate = HasMadMacF32Insts in
484def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, []>;
485
486let isCommutable = 1 in {
487defm V_ADD_F32 : VOP2Inst <"v_add_f32", VOP_F32_F32_F32, any_fadd>;
488defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, any_fsub>;
489defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">;
490defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>;
491defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, any_fmul>;
492defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32_ARITH, AMDGPUmul_i24>;
493defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_i24>;
494defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32_ARITH, AMDGPUmul_u24>;
495defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_u24>;
496defm V_MIN_F32 : VOP2Inst <"v_min_f32", VOP_F32_F32_F32, fminnum_like>;
497defm V_MAX_F32 : VOP2Inst <"v_max_f32", VOP_F32_F32_F32, fmaxnum_like>;
498defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smin>;
499defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smax>;
500defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umin>;
501defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umax>;
502defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, lshr_rev, "v_lshr_b32">;
503defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, ashr_rev, "v_ashr_i32">;
504defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, lshl_rev, "v_lshl_b32">;
505defm V_AND_B32 : VOP2Inst <"v_and_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, and>;
506defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, or>;
507defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, xor>;
508
509let mayRaiseFPException = 0 in {
510let OtherPredicates = [HasMadMacF32Insts] in {
511let Constraints = "$vdst = $src2", DisableEncoding="$src2",
512    isConvertibleToThreeAddress = 1 in {
513defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>;
514
515let SubtargetPredicate = isGFX6GFX7GFX10 in
516defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_MAC_LEGACY_F32>;
517} // End Constraints = "$vdst = $src2", DisableEncoding="$src2",
518  //     isConvertibleToThreeAddress = 1
519
520def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32, []>;
521} // End OtherPredicates = [HasMadMacF32Insts]
522} // End mayRaiseFPException = 0
523
524// No patterns so that the scalar instructions are always selected.
525// The scalar versions will be replaced with vector when needed later.
526defm V_ADD_CO_U32 : VOP2bInst <"v_add_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_add_co_u32", 1>;
527defm V_SUB_CO_U32 : VOP2bInst <"v_sub_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>;
528defm V_SUBREV_CO_U32 : VOP2bInst <"v_subrev_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>;
529defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_addc_u32", 1>;
530defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>;
531defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>;
532
533
534let SubtargetPredicate = HasAddNoCarryInsts in {
535defm V_ADD_U32 : VOP2Inst <"v_add_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_add_u32", 1>;
536defm V_SUB_U32 : VOP2Inst <"v_sub_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>;
537defm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>;
538}
539
540} // End isCommutable = 1
541
542// These are special and do not read the exec mask.
543let isConvergent = 1, Uses = []<Register> in {
544def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE,
545  [(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))]>;
546
547let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in {
548def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE,
549  [(set i32:$vdst, (int_amdgcn_writelane i32:$src0, i32:$src1, i32:$vdst_in))]>;
550} // End $vdst = $vdst_in, DisableEncoding $vdst_in
551} // End isConvergent = 1
552
553defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_NO_EXT<VOP_I32_I32_I32>>;
554defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, add_ctpop>;
555defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_lo>;
556defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_hi>;
557defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_NO_EXT<VOP_F32_F32_I32>, AMDGPUldexp>;
558defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_NO_EXT<VOP_I32_F32_I32>>; // TODO: set "Uses = dst"
559
560let ReadsModeReg = 0, mayRaiseFPException = 0 in {
561defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_i16_f32>;
562defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_u16_f32>;
563}
564
565defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_NO_EXT<VOP_V2F16_F32_F32>, AMDGPUpkrtz_f16_f32>;
566defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_u16_u32>;
567defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_i16_i32>;
568
569
570let SubtargetPredicate = isGFX6GFX7 in {
571defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>;
572defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>;
573} // End SubtargetPredicate = isGFX6GFX7
574
575let isCommutable = 1 in {
576let SubtargetPredicate = isGFX6GFX7 in {
577defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, srl>;
578defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, sra>;
579defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, shl>;
580} // End SubtargetPredicate = isGFX6GFX7
581} // End isCommutable = 1
582
583
584class DivergentBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :
585  GCNPat<
586      (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
587      !if(!cast<Commutable_REV>(Inst).IsOrig,
588        (Inst $src0, $src1),
589        (Inst $src1, $src0)
590      )
591  >;
592
593class DivergentClampingBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :
594  GCNPat<
595      (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
596      !if(!cast<Commutable_REV>(Inst).IsOrig,
597        (Inst $src0, $src1, 0),
598        (Inst $src1, $src0, 0)
599      )
600  >;
601
602def : DivergentBinOp<srl, V_LSHRREV_B32_e64>;
603def : DivergentBinOp<sra, V_ASHRREV_I32_e64>;
604def : DivergentBinOp<shl, V_LSHLREV_B32_e64>;
605
606let SubtargetPredicate = HasAddNoCarryInsts in {
607  def : DivergentClampingBinOp<add, V_ADD_U32_e64>;
608  def : DivergentClampingBinOp<sub, V_SUB_U32_e64>;
609}
610
611let SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] in {
612def : DivergentClampingBinOp<add, V_ADD_CO_U32_e64>;
613def : DivergentClampingBinOp<sub, V_SUB_CO_U32_e64>;
614}
615
616def : DivergentBinOp<adde, V_ADDC_U32_e32>;
617def : DivergentBinOp<sube, V_SUBB_U32_e32>;
618
619class divergent_i64_BinOp <SDPatternOperator Op, Instruction Inst> :
620  GCNPat<
621      (getDivergentFrag<Op>.ret i64:$src0, i64:$src1),
622      (REG_SEQUENCE VReg_64,
623        (Inst
624          (i32 (EXTRACT_SUBREG $src0, sub0)),
625          (i32 (EXTRACT_SUBREG $src1, sub0))
626        ), sub0,
627        (Inst
628          (i32 (EXTRACT_SUBREG $src0, sub1)),
629          (i32 (EXTRACT_SUBREG $src1, sub1))
630        ), sub1
631      )
632  >;
633
634def :  divergent_i64_BinOp <and, V_AND_B32_e32>;
635def :  divergent_i64_BinOp <or,  V_OR_B32_e32>;
636def :  divergent_i64_BinOp <xor, V_XOR_B32_e32>;
637
638let SubtargetPredicate = Has16BitInsts in {
639
640let FPDPRounding = 1 in {
641def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16, [], "">;
642defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>;
643} // End FPDPRounding = 1
644
645defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16, lshl_rev>;
646defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16, lshr_rev>;
647defm V_ASHRREV_I16 : VOP2Inst <"v_ashrrev_i16", VOP_I16_I16_I16, ashr_rev>;
648
649let isCommutable = 1 in {
650let FPDPRounding = 1 in {
651defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, any_fadd>;
652defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, any_fsub>;
653defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">;
654defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, any_fmul>;
655
656let mayRaiseFPException = 0 in {
657def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">;
658}
659
660} // End FPDPRounding = 1
661defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16_ARITH, add>;
662defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16_ARITH, sub>;
663defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16_ARITH, null_frag, "v_sub_u16">;
664defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16, mul>;
665defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum_like>;
666defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum_like>;
667defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16, umax>;
668defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16, smax>;
669defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16, umin>;
670defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16, smin>;
671
672let Constraints = "$vdst = $src2", DisableEncoding="$src2",
673    isConvertibleToThreeAddress = 1 in {
674defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>;
675}
676} // End isCommutable = 1
677
678} // End SubtargetPredicate = Has16BitInsts
679
680let SubtargetPredicate = HasDLInsts in {
681
682defm V_XNOR_B32 : VOP2Inst <"v_xnor_b32", VOP_I32_I32_I32, xnor>;
683
684let Constraints = "$vdst = $src2",
685    DisableEncoding = "$src2",
686    isConvertibleToThreeAddress = 1,
687    isCommutable = 1 in
688defm V_FMAC_F32 : VOP2Inst <"v_fmac_f32", VOP_MAC_F32>;
689
690} // End SubtargetPredicate = HasDLInsts
691
692let SubtargetPredicate = HasFmaLegacy32 in {
693
694let Constraints = "$vdst = $src2",
695    DisableEncoding = "$src2",
696    isConvertibleToThreeAddress = 1,
697    isCommutable = 1 in
698defm V_FMAC_LEGACY_F32 : VOP2Inst <"v_fmac_legacy_f32", VOP_MAC_LEGACY_F32>;
699
700} // End SubtargetPredicate = HasFmaLegacy32
701
702let SubtargetPredicate = isGFX90APlus,
703    Constraints = "$vdst = $src2",
704    DisableEncoding="$src2",
705    isConvertibleToThreeAddress = 1,
706    isCommutable = 1,
707    SchedRW = [WriteDoubleAdd] in
708defm V_FMAC_F64 : VOP2Inst <"v_fmac_f64", VOP_MAC_F64>;
709
710let Constraints = "$vdst = $src2",
711      DisableEncoding="$src2",
712      isConvertibleToThreeAddress = 1,
713      isCommutable = 1,
714      IsDOT = 1 in {
715  let SubtargetPredicate = HasDot5Insts in
716    defm V_DOT2C_F32_F16 : VOP2Inst<"v_dot2c_f32_f16", VOP_DOT_ACC_F32_V2F16>;
717  let SubtargetPredicate = HasDot6Insts in
718    defm V_DOT4C_I32_I8  : VOP2Inst<"v_dot4c_i32_i8",  VOP_DOT_ACC_I32_I32>;
719
720  let SubtargetPredicate = HasDot4Insts in
721    defm V_DOT2C_I32_I16 : VOP2Inst<"v_dot2c_i32_i16", VOP_DOT_ACC_I32_I32>;
722  let SubtargetPredicate = HasDot3Insts in
723    defm V_DOT8C_I32_I4  : VOP2Inst<"v_dot8c_i32_i4",  VOP_DOT_ACC_I32_I32>;
724}
725
726let AddedComplexity = 30 in {
727  def : GCNPat<
728    (f32 (AMDGPUfdot2 v2f16:$src0, v2f16:$src1, f32:$src2, (i1 DSTCLAMP.NONE))),
729    (f32 (V_DOT2C_F32_F16_e32 $src0, $src1, $src2))
730  > {
731    let SubtargetPredicate = HasDot5Insts;
732  }
733  def : GCNPat<
734    (i32 (int_amdgcn_sdot4 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
735    (i32 (V_DOT4C_I32_I8_e32 $src0, $src1, $src2))
736  > {
737    let SubtargetPredicate = HasDot6Insts;
738  }
739  def : GCNPat<
740    (i32 (int_amdgcn_sdot2 v2i16:$src0, v2i16:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
741    (i32 (V_DOT2C_I32_I16_e32 $src0, $src1, $src2))
742  > {
743    let SubtargetPredicate = HasDot4Insts;
744  }
745  def : GCNPat<
746    (i32 (int_amdgcn_sdot8 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
747    (i32 (V_DOT8C_I32_I4_e32 $src0, $src1, $src2))
748  > {
749    let SubtargetPredicate = HasDot3Insts;
750  }
751} // End AddedComplexity = 30
752
753let SubtargetPredicate = isGFX10Plus in {
754
755def V_FMAMK_F32 : VOP2_Pseudo<"v_fmamk_f32", VOP_MADMK_F32, [], "">;
756let FPDPRounding = 1 in
757def V_FMAMK_F16 : VOP2_Pseudo <"v_fmamk_f16", VOP_MADMK_F16, [], "">;
758
759let isCommutable = 1 in {
760def V_FMAAK_F32 : VOP2_Pseudo<"v_fmaak_f32", VOP_MADAK_F32, [], "">;
761let FPDPRounding = 1 in
762def V_FMAAK_F16 : VOP2_Pseudo <"v_fmaak_f16", VOP_MADAK_F16, [], "">;
763} // End isCommutable = 1
764
765let Constraints = "$vdst = $src2",
766    DisableEncoding="$src2",
767    isConvertibleToThreeAddress = 1,
768    isCommutable = 1 in {
769defm V_FMAC_F16 : VOP2Inst <"v_fmac_f16", VOP_MAC_F16>;
770}
771
772} // End SubtargetPredicate = isGFX10Plus
773
774let SubtargetPredicate = HasPkFmacF16Inst in {
775defm V_PK_FMAC_F16 : VOP2Inst<"v_pk_fmac_f16", VOP_V2F16_V2F16_V2F16>;
776} // End SubtargetPredicate = HasPkFmacF16Inst
777
778// Note: 16-bit instructions produce a 0 result in the high 16-bits
779// on GFX8 and GFX9 and preserve high 16 bits on GFX10+
780multiclass Arithmetic_i16_0Hi_Pats <SDPatternOperator op, Instruction inst> {
781
782def : GCNPat<
783  (i32 (zext (op i16:$src0, i16:$src1))),
784  (inst VSrc_b16:$src0, VSrc_b16:$src1)
785>;
786
787def : GCNPat<
788  (i64 (zext (op i16:$src0, i16:$src1))),
789   (REG_SEQUENCE VReg_64,
790     (inst $src0, $src1), sub0,
791     (V_MOV_B32_e32 (i32 0)), sub1)
792>;
793}
794
795class ZExt_i16_i1_Pat <SDNode ext> : GCNPat <
796  (i16 (ext i1:$src)),
797  (V_CNDMASK_B32_e64 (i32 0/*src0mod*/), (i32 0/*src0*/),
798                     (i32 0/*src1mod*/), (i32 1/*src1*/),
799                     $src)
800>;
801
802foreach vt = [i16, v2i16] in {
803def : GCNPat <
804  (and vt:$src0, vt:$src1),
805  (V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
806>;
807
808def : GCNPat <
809  (or vt:$src0, vt:$src1),
810  (V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
811>;
812
813def : GCNPat <
814  (xor vt:$src0, vt:$src1),
815  (V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
816>;
817}
818
819let Predicates = [Has16BitInsts] in {
820
821// Undo sub x, c -> add x, -c canonicalization since c is more likely
822// an inline immediate than -c.
823// TODO: Also do for 64-bit.
824def : GCNPat<
825  (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)),
826  (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)
827>;
828
829
830let Predicates = [Has16BitInsts, isGFX7GFX8GFX9] in {
831
832def : GCNPat<
833  (i32 (zext (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)))),
834  (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)
835>;
836
837defm : Arithmetic_i16_0Hi_Pats<add, V_ADD_U16_e64>;
838defm : Arithmetic_i16_0Hi_Pats<mul, V_MUL_LO_U16_e64>;
839defm : Arithmetic_i16_0Hi_Pats<sub, V_SUB_U16_e64>;
840defm : Arithmetic_i16_0Hi_Pats<smin, V_MIN_I16_e64>;
841defm : Arithmetic_i16_0Hi_Pats<smax, V_MAX_I16_e64>;
842defm : Arithmetic_i16_0Hi_Pats<umin, V_MIN_U16_e64>;
843defm : Arithmetic_i16_0Hi_Pats<umax, V_MAX_U16_e64>;
844defm : Arithmetic_i16_0Hi_Pats<lshl_rev, V_LSHLREV_B16_e64>;
845defm : Arithmetic_i16_0Hi_Pats<lshr_rev, V_LSHRREV_B16_e64>;
846defm : Arithmetic_i16_0Hi_Pats<ashr_rev, V_ASHRREV_I16_e64>;
847}  // End Predicates = [Has16BitInsts, isGFX7GFX8GFX9]
848
849def : ZExt_i16_i1_Pat<zext>;
850def : ZExt_i16_i1_Pat<anyext>;
851
852def : GCNPat <
853  (i16 (sext i1:$src)),
854  (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
855                     /*src1mod*/(i32 0), /*src1*/(i32 -1), $src)
856>;
857
858} // End Predicates = [Has16BitInsts]
859
860
861let SubtargetPredicate = HasIntClamp in {
862// Set clamp bit for saturation.
863def : VOPBinOpClampPat<uaddsat, V_ADD_CO_U32_e64, i32>;
864def : VOPBinOpClampPat<usubsat, V_SUB_CO_U32_e64, i32>;
865}
866
867let SubtargetPredicate = HasAddNoCarryInsts, OtherPredicates = [HasIntClamp] in {
868let AddedComplexity = 1 in { // Prefer over form with carry-out.
869def : VOPBinOpClampPat<uaddsat, V_ADD_U32_e64, i32>;
870def : VOPBinOpClampPat<usubsat, V_SUB_U32_e64, i32>;
871}
872}
873
874let SubtargetPredicate = Has16BitInsts, OtherPredicates = [HasIntClamp] in {
875def : VOPBinOpClampPat<uaddsat, V_ADD_U16_e64, i16>;
876def : VOPBinOpClampPat<usubsat, V_SUB_U16_e64, i16>;
877}
878
879//===----------------------------------------------------------------------===//
880// Target-specific instruction encodings.
881//===----------------------------------------------------------------------===//
882
883class VOP2_DPP<bits<6> op, VOP2_DPP_Pseudo ps,
884               string opName = ps.OpName, VOPProfile p = ps.Pfl,
885               bit IsDPP16 = 0> :
886    VOP_DPP<opName, p, IsDPP16> {
887  let hasSideEffects = ps.hasSideEffects;
888  let Defs = ps.Defs;
889  let SchedRW = ps.SchedRW;
890  let Uses = ps.Uses;
891
892  bits<8> vdst;
893  bits<8> src1;
894  let Inst{8-0}   = 0xfa;
895  let Inst{16-9}  = !if(p.HasSrc1, src1{7-0}, 0);
896  let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
897  let Inst{30-25} = op;
898  let Inst{31}    = 0x0;
899}
900
901class Base_VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps,
902                 string opName = ps.OpName, VOPProfile p = ps.Pfl> :
903    VOP2_DPP<op, ps, opName, p, 1> {
904  let AssemblerPredicate = HasDPP16;
905  let SubtargetPredicate = HasDPP16;
906  let OtherPredicates = ps.OtherPredicates;
907}
908
909class VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps,
910                 string opName = ps.OpName, VOPProfile p = ps.Pfl> :
911    Base_VOP2_DPP16<op, ps, opName, p>,
912    SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX10>;
913
914class VOP2_DPP8<bits<6> op, VOP2_Pseudo ps,
915                string opName = ps.OpName, VOPProfile p = ps.Pfl> :
916    VOP_DPP8<ps.OpName, p> {
917  let hasSideEffects = ps.hasSideEffects;
918  let Defs = ps.Defs;
919  let SchedRW = ps.SchedRW;
920  let Uses = ps.Uses;
921
922  bits<8> vdst;
923  bits<8> src1;
924
925  let Inst{8-0}   = fi;
926  let Inst{16-9}  = !if(p.HasSrc1, src1{7-0}, 0);
927  let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
928  let Inst{30-25} = op;
929  let Inst{31}    = 0x0;
930
931  let AssemblerPredicate = HasDPP8;
932  let SubtargetPredicate = HasDPP8;
933  let OtherPredicates = ps.OtherPredicates;
934}
935
936//===----------------------------------------------------------------------===//
937// GFX10.
938//===----------------------------------------------------------------------===//
939
940let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
941  //===------------------------------- VOP2 -------------------------------===//
942  multiclass VOP2Only_Real_MADK_gfx10<bits<6> op> {
943    def _gfx10 :
944      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX10>,
945      VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
946  }
947  multiclass VOP2Only_Real_MADK_gfx10_with_name<bits<6> op, string opName,
948                                                string asmName> {
949    def _gfx10 :
950        VOP2_Real<!cast<VOP2_Pseudo>(opName), SIEncodingFamily.GFX10>,
951        VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> {
952      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName);
953      let AsmString = asmName # ps.AsmOperands;
954    }
955  }
956  multiclass VOP2_Real_e32_gfx10<bits<6> op> {
957    def _e32_gfx10 :
958      VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,
959      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
960  }
961  multiclass VOP2_Real_e64_gfx10<bits<6> op> {
962    def _e64_gfx10 :
963      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
964      VOP3e_gfx10<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
965  }
966  multiclass VOP2_Real_sdwa_gfx10<bits<6> op> {
967    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
968    def _sdwa_gfx10 :
969      VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
970      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
971      let DecoderNamespace = "SDWA10";
972    }
973  }
974  multiclass VOP2_Real_dpp_gfx10<bits<6> op> {
975    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
976    def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
977      let DecoderNamespace = "SDWA10";
978    }
979  }
980  multiclass VOP2_Real_dpp8_gfx10<bits<6> op> {
981    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
982    def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(NAME#"_e32")> {
983      let DecoderNamespace = "DPP8";
984    }
985  }
986
987  //===------------------------- VOP2 (with name) -------------------------===//
988  multiclass VOP2_Real_e32_gfx10_with_name<bits<6> op, string opName,
989                                           string asmName> {
990    def _e32_gfx10 :
991      VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
992      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
993        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
994        let AsmString = asmName # ps.AsmOperands;
995      }
996  }
997  multiclass VOP2_Real_e64_gfx10_with_name<bits<6> op, string opName,
998                                           string asmName> {
999    def _e64_gfx10 :
1000      VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
1001      VOP3e_gfx10<{0, 1, 0, 0, op{5-0}},
1002                  !cast<VOP3_Pseudo>(opName#"_e64").Pfl> {
1003        VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64");
1004        let AsmString = asmName # ps.AsmOperands;
1005      }
1006  }
1007  let DecoderNamespace = "SDWA10" in {
1008    multiclass VOP2_Real_sdwa_gfx10_with_name<bits<6> op, string opName,
1009                                              string asmName> {
1010      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1011      def _sdwa_gfx10 :
1012        VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1013        VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1014          VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1015          let AsmString = asmName # ps.AsmOperands;
1016        }
1017    }
1018    multiclass VOP2_Real_dpp_gfx10_with_name<bits<6> op, string opName,
1019                                             string asmName> {
1020      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1021      def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp")> {
1022        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
1023        let AsmString = asmName # ps.Pfl.AsmDPP16;
1024      }
1025    }
1026    multiclass VOP2_Real_dpp8_gfx10_with_name<bits<6> op, string opName,
1027                                              string asmName> {
1028      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1029      def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
1030        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
1031        let AsmString = asmName # ps.Pfl.AsmDPP8;
1032        let DecoderNamespace = "DPP8";
1033      }
1034    }
1035  } // End DecoderNamespace = "SDWA10"
1036
1037  //===------------------------------ VOP2be ------------------------------===//
1038  multiclass VOP2be_Real_e32_gfx10<bits<6> op, string opName, string asmName> {
1039    def _e32_gfx10 :
1040      VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
1041      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
1042        VOP2_Pseudo Ps = !cast<VOP2_Pseudo>(opName#"_e32");
1043        let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
1044      }
1045  }
1046  multiclass VOP2be_Real_e64_gfx10<bits<6> op, string opName, string asmName> {
1047    def _e64_gfx10 :
1048      VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
1049      VOP3be_gfx10<{0, 1, 0, 0, op{5-0}},
1050                   !cast<VOP3_Pseudo>(opName#"_e64").Pfl> {
1051        VOP3_Pseudo Ps = !cast<VOP3_Pseudo>(opName#"_e64");
1052        let AsmString = asmName # Ps.AsmOperands;
1053      }
1054  }
1055  multiclass VOP2be_Real_sdwa_gfx10<bits<6> op, string opName, string asmName> {
1056    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1057    def _sdwa_gfx10 :
1058      VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1059      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1060        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1061        let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
1062        let DecoderNamespace = "SDWA10";
1063      }
1064    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1065    def _sdwa_w32_gfx10 :
1066      Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1067      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1068        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1069        let AsmString = asmName # !subst("vcc", "vcc_lo", Ps.AsmOperands);
1070        let isAsmParserOnly = 1;
1071        let DecoderNamespace = "SDWA10";
1072        let WaveSizePredicate = isWave32;
1073      }
1074    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1075    def _sdwa_w64_gfx10 :
1076      Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1077      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1078        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1079        let AsmString = asmName # Ps.AsmOperands;
1080        let isAsmParserOnly = 1;
1081        let DecoderNamespace = "SDWA10";
1082        let WaveSizePredicate = isWave64;
1083      }
1084  }
1085  multiclass VOP2be_Real_dpp_gfx10<bits<6> op, string opName, string asmName> {
1086    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1087    def _dpp_gfx10 :
1088      VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1089        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1090        let AsmString = asmName # !subst(", vcc", "", AsmDPP);
1091        let DecoderNamespace = "SDWA10";
1092      }
1093    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1094    def _dpp_w32_gfx10 :
1095      Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1096        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1097        let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP);
1098        let isAsmParserOnly = 1;
1099        let WaveSizePredicate = isWave32;
1100      }
1101    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1102    def _dpp_w64_gfx10 :
1103      Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1104        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1105        let AsmString = asmName # AsmDPP;
1106        let isAsmParserOnly = 1;
1107        let WaveSizePredicate = isWave64;
1108      }
1109  }
1110  multiclass VOP2be_Real_dpp8_gfx10<bits<6> op, string opName, string asmName> {
1111    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1112    def _dpp8_gfx10 :
1113      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1114        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1115        let AsmString = asmName # !subst(", vcc", "", AsmDPP8);
1116        let DecoderNamespace = "DPP8";
1117      }
1118    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1119    def _dpp8_w32_gfx10 :
1120      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1121        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1122        let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8);
1123        let isAsmParserOnly = 1;
1124        let WaveSizePredicate = isWave32;
1125      }
1126    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1127    def _dpp8_w64_gfx10 :
1128      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1129        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1130        let AsmString = asmName # AsmDPP8;
1131        let isAsmParserOnly = 1;
1132        let WaveSizePredicate = isWave64;
1133      }
1134  }
1135
1136  //===----------------------------- VOP3Only -----------------------------===//
1137  multiclass VOP3Only_Real_gfx10<bits<10> op> {
1138    def _e64_gfx10 :
1139      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1140      VOP3e_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1141  }
1142
1143  //===---------------------------- VOP3beOnly ----------------------------===//
1144  multiclass VOP3beOnly_Real_gfx10<bits<10> op> {
1145    def _e64_gfx10 :
1146      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1147      VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1148  }
1149} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
1150
1151multiclass VOP2be_Real_gfx10<bits<6> op, string opName, string asmName> :
1152  VOP2be_Real_e32_gfx10<op, opName, asmName>,
1153  VOP2be_Real_e64_gfx10<op, opName, asmName>,
1154  VOP2be_Real_sdwa_gfx10<op, opName, asmName>,
1155  VOP2be_Real_dpp_gfx10<op, opName, asmName>,
1156  VOP2be_Real_dpp8_gfx10<op, opName, asmName>;
1157
1158multiclass VOP2e_Real_gfx10<bits<6> op, string opName, string asmName> :
1159  VOP2_Real_e32_gfx10<op>,
1160  VOP2_Real_e64_gfx10<op>,
1161  VOP2be_Real_sdwa_gfx10<op, opName, asmName>,
1162  VOP2be_Real_dpp_gfx10<op, opName, asmName>,
1163  VOP2be_Real_dpp8_gfx10<op, opName, asmName>;
1164
1165multiclass VOP2_Real_gfx10<bits<6> op> :
1166  VOP2_Real_e32_gfx10<op>, VOP2_Real_e64_gfx10<op>,
1167  VOP2_Real_sdwa_gfx10<op>, VOP2_Real_dpp_gfx10<op>, VOP2_Real_dpp8_gfx10<op>;
1168
1169multiclass VOP2_Real_gfx10_with_name<bits<6> op, string opName,
1170                                     string asmName> :
1171  VOP2_Real_e32_gfx10_with_name<op, opName, asmName>,
1172  VOP2_Real_e64_gfx10_with_name<op, opName, asmName>,
1173  VOP2_Real_sdwa_gfx10_with_name<op, opName, asmName>,
1174  VOP2_Real_dpp_gfx10_with_name<op, opName, asmName>,
1175  VOP2_Real_dpp8_gfx10_with_name<op, opName, asmName>;
1176
1177// NB: Same opcode as v_mac_legacy_f32
1178let DecoderNamespace = "GFX10_B" in
1179defm V_FMAC_LEGACY_F32 : VOP2_Real_gfx10<0x006>;
1180
1181defm V_XNOR_B32        : VOP2_Real_gfx10<0x01e>;
1182defm V_FMAC_F32        : VOP2_Real_gfx10<0x02b>;
1183defm V_FMAMK_F32       : VOP2Only_Real_MADK_gfx10<0x02c>;
1184defm V_FMAAK_F32       : VOP2Only_Real_MADK_gfx10<0x02d>;
1185defm V_ADD_F16         : VOP2_Real_gfx10<0x032>;
1186defm V_SUB_F16         : VOP2_Real_gfx10<0x033>;
1187defm V_SUBREV_F16      : VOP2_Real_gfx10<0x034>;
1188defm V_MUL_F16         : VOP2_Real_gfx10<0x035>;
1189defm V_FMAC_F16        : VOP2_Real_gfx10<0x036>;
1190defm V_FMAMK_F16       : VOP2Only_Real_MADK_gfx10<0x037>;
1191defm V_FMAAK_F16       : VOP2Only_Real_MADK_gfx10<0x038>;
1192defm V_MAX_F16         : VOP2_Real_gfx10<0x039>;
1193defm V_MIN_F16         : VOP2_Real_gfx10<0x03a>;
1194defm V_LDEXP_F16       : VOP2_Real_gfx10<0x03b>;
1195defm V_PK_FMAC_F16     : VOP2_Real_e32_gfx10<0x03c>;
1196
1197// VOP2 no carry-in, carry-out.
1198defm V_ADD_NC_U32 :
1199  VOP2_Real_gfx10_with_name<0x025, "V_ADD_U32", "v_add_nc_u32">;
1200defm V_SUB_NC_U32 :
1201  VOP2_Real_gfx10_with_name<0x026, "V_SUB_U32", "v_sub_nc_u32">;
1202defm V_SUBREV_NC_U32 :
1203  VOP2_Real_gfx10_with_name<0x027, "V_SUBREV_U32", "v_subrev_nc_u32">;
1204
1205// VOP2 carry-in, carry-out.
1206defm V_ADD_CO_CI_U32 :
1207  VOP2be_Real_gfx10<0x028, "V_ADDC_U32", "v_add_co_ci_u32">;
1208defm V_SUB_CO_CI_U32 :
1209  VOP2be_Real_gfx10<0x029, "V_SUBB_U32", "v_sub_co_ci_u32">;
1210defm V_SUBREV_CO_CI_U32 :
1211  VOP2be_Real_gfx10<0x02a, "V_SUBBREV_U32", "v_subrev_co_ci_u32">;
1212
1213defm V_CNDMASK_B32 :
1214  VOP2e_Real_gfx10<0x001, "V_CNDMASK_B32", "v_cndmask_b32">;
1215
1216// VOP3 only.
1217defm V_BFM_B32            : VOP3Only_Real_gfx10<0x363>;
1218defm V_BCNT_U32_B32       : VOP3Only_Real_gfx10<0x364>;
1219defm V_MBCNT_LO_U32_B32   : VOP3Only_Real_gfx10<0x365>;
1220defm V_MBCNT_HI_U32_B32   : VOP3Only_Real_gfx10<0x366>;
1221defm V_LDEXP_F32          : VOP3Only_Real_gfx10<0x362>;
1222defm V_CVT_PKNORM_I16_F32 : VOP3Only_Real_gfx10<0x368>;
1223defm V_CVT_PKNORM_U16_F32 : VOP3Only_Real_gfx10<0x369>;
1224defm V_CVT_PK_U16_U32     : VOP3Only_Real_gfx10<0x36a>;
1225defm V_CVT_PK_I16_I32     : VOP3Only_Real_gfx10<0x36b>;
1226
1227// VOP3 carry-out.
1228defm V_ADD_CO_U32 : VOP3beOnly_Real_gfx10<0x30f>;
1229defm V_SUB_CO_U32 : VOP3beOnly_Real_gfx10<0x310>;
1230defm V_SUBREV_CO_U32 : VOP3beOnly_Real_gfx10<0x319>;
1231
1232let SubtargetPredicate = isGFX10Plus in {
1233  defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx10>;
1234
1235  defm : VOP2bInstAliases<
1236    V_ADDC_U32_e32, V_ADD_CO_CI_U32_e32_gfx10, "v_add_co_ci_u32">;
1237  defm : VOP2bInstAliases<
1238    V_SUBB_U32_e32, V_SUB_CO_CI_U32_e32_gfx10, "v_sub_co_ci_u32">;
1239  defm : VOP2bInstAliases<
1240    V_SUBBREV_U32_e32, V_SUBREV_CO_CI_U32_e32_gfx10, "v_subrev_co_ci_u32">;
1241} // End SubtargetPredicate = isGFX10Plus
1242
1243//===----------------------------------------------------------------------===//
1244// GFX6, GFX7, GFX10.
1245//===----------------------------------------------------------------------===//
1246
1247class VOP2_DPPe <bits<6> op, VOP2_DPP_Pseudo ps, VOPProfile P = ps.Pfl> :
1248  VOP_DPPe <P> {
1249  bits<8> vdst;
1250  bits<8> src1;
1251  let Inst{8-0}   = 0xfa; //dpp
1252  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
1253  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
1254  let Inst{30-25} = op;
1255  let Inst{31}    = 0x0; //encoding
1256}
1257
1258let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
1259  multiclass VOP2_Lane_Real_gfx6_gfx7<bits<6> op> {
1260    def _gfx6_gfx7 :
1261      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1262      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1263  }
1264  multiclass VOP2Only_Real_MADK_gfx6_gfx7<bits<6> op> {
1265    def _gfx6_gfx7 :
1266      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1267      VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1268  }
1269  multiclass VOP2_Real_e32_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1270    def _e32_gfx6_gfx7 :
1271      VOP2_Real<!cast<VOP2_Pseudo>(PseudoName#"_e32"), SIEncodingFamily.SI>,
1272      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(PseudoName#"_e32").Pfl>;
1273  }
1274  multiclass VOP2_Real_e64_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1275    def _e64_gfx6_gfx7 :
1276      VOP3_Real<!cast<VOP3_Pseudo>(PseudoName#"_e64"), SIEncodingFamily.SI>,
1277      VOP3e_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(PseudoName#"_e64").Pfl>;
1278  }
1279  multiclass VOP2be_Real_e64_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1280    def _e64_gfx6_gfx7 :
1281      VOP3_Real<!cast<VOP3_Pseudo>(PseudoName#"_e64"), SIEncodingFamily.SI>,
1282      VOP3be_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(PseudoName#"_e64").Pfl>;
1283  }
1284} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
1285
1286multiclass VOP2Only_Real_MADK_gfx6_gfx7_gfx10<bits<6> op> :
1287  VOP2Only_Real_MADK_gfx6_gfx7<op>, VOP2Only_Real_MADK_gfx10<op>;
1288
1289multiclass VOP2_Real_gfx6_gfx7<bits<6> op> :
1290  VOP2_Real_e32_gfx6_gfx7<op>, VOP2_Real_e64_gfx6_gfx7<op>;
1291
1292multiclass VOP2_Real_gfx6_gfx7_gfx10<bits<6> op> :
1293  VOP2_Real_gfx6_gfx7<op>, VOP2_Real_gfx10<op>;
1294
1295multiclass VOP2be_Real_gfx6_gfx7<bits<6> op> :
1296  VOP2_Real_e32_gfx6_gfx7<op>, VOP2be_Real_e64_gfx6_gfx7<op>;
1297
1298multiclass VOP2be_Real_gfx6_gfx7_with_name<bits<6> op,
1299  string PseudoName, string asmName>  {
1300  defvar ps32 = !cast<VOP2_Pseudo>(PseudoName#"_e32");
1301  defvar ps64 = !cast<VOP3_Pseudo>(PseudoName#"_e64");
1302
1303  let AsmString = asmName # ps32.AsmOperands in {
1304    defm "" : VOP2_Real_e32_gfx6_gfx7<op, PseudoName>;
1305  }
1306
1307   let AsmString = asmName # ps64.AsmOperands in {
1308    defm "" : VOP2be_Real_e64_gfx6_gfx7<op, PseudoName>;
1309  }
1310}
1311
1312defm V_CNDMASK_B32        : VOP2_Real_gfx6_gfx7<0x000>;
1313defm V_MIN_LEGACY_F32     : VOP2_Real_gfx6_gfx7<0x00d>;
1314defm V_MAX_LEGACY_F32     : VOP2_Real_gfx6_gfx7<0x00e>;
1315defm V_LSHR_B32           : VOP2_Real_gfx6_gfx7<0x015>;
1316defm V_ASHR_I32           : VOP2_Real_gfx6_gfx7<0x017>;
1317defm V_LSHL_B32           : VOP2_Real_gfx6_gfx7<0x019>;
1318defm V_BFM_B32            : VOP2_Real_gfx6_gfx7<0x01e>;
1319defm V_BCNT_U32_B32       : VOP2_Real_gfx6_gfx7<0x022>;
1320defm V_MBCNT_LO_U32_B32   : VOP2_Real_gfx6_gfx7<0x023>;
1321defm V_MBCNT_HI_U32_B32   : VOP2_Real_gfx6_gfx7<0x024>;
1322defm V_LDEXP_F32          : VOP2_Real_gfx6_gfx7<0x02b>;
1323defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_gfx6_gfx7<0x02c>;
1324defm V_CVT_PKNORM_I16_F32 : VOP2_Real_gfx6_gfx7<0x02d>;
1325defm V_CVT_PKNORM_U16_F32 : VOP2_Real_gfx6_gfx7<0x02e>;
1326defm V_CVT_PK_U16_U32     : VOP2_Real_gfx6_gfx7<0x030>;
1327defm V_CVT_PK_I16_I32     : VOP2_Real_gfx6_gfx7<0x031>;
1328
1329// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in
1330// VI, but the VI instructions behave the same as the SI versions.
1331defm V_ADD_I32            : VOP2be_Real_gfx6_gfx7_with_name<0x025, "V_ADD_CO_U32", "v_add_i32">;
1332defm V_SUB_I32            : VOP2be_Real_gfx6_gfx7_with_name<0x026, "V_SUB_CO_U32", "v_sub_i32">;
1333defm V_SUBREV_I32         : VOP2be_Real_gfx6_gfx7_with_name<0x027, "V_SUBREV_CO_U32", "v_subrev_i32">;
1334defm V_ADDC_U32           : VOP2be_Real_gfx6_gfx7<0x028>;
1335defm V_SUBB_U32           : VOP2be_Real_gfx6_gfx7<0x029>;
1336defm V_SUBBREV_U32        : VOP2be_Real_gfx6_gfx7<0x02a>;
1337
1338defm V_READLANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x001>;
1339
1340let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
1341  defm V_WRITELANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x002>;
1342} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)
1343
1344let SubtargetPredicate = isGFX6GFX7 in {
1345  defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx6_gfx7>;
1346  defm : VOP2eInstAliases<V_ADD_CO_U32_e32, V_ADD_I32_e32_gfx6_gfx7>;
1347  defm : VOP2eInstAliases<V_SUB_CO_U32_e32, V_SUB_I32_e32_gfx6_gfx7>;
1348  defm : VOP2eInstAliases<V_SUBREV_CO_U32_e32, V_SUBREV_I32_e32_gfx6_gfx7>;
1349
1350  def : VOP2e64InstAlias<V_ADD_CO_U32_e64, V_ADD_I32_e64_gfx6_gfx7>;
1351  def : VOP2e64InstAlias<V_SUB_CO_U32_e64, V_SUB_I32_e64_gfx6_gfx7>;
1352  def : VOP2e64InstAlias<V_SUBREV_CO_U32_e64, V_SUBREV_I32_e64_gfx6_gfx7>;
1353} // End SubtargetPredicate = isGFX6GFX7
1354
1355defm V_ADD_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x003>;
1356defm V_SUB_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x004>;
1357defm V_SUBREV_F32         : VOP2_Real_gfx6_gfx7_gfx10<0x005>;
1358defm V_MAC_LEGACY_F32     : VOP2_Real_gfx6_gfx7_gfx10<0x006>;
1359defm V_MUL_LEGACY_F32     : VOP2_Real_gfx6_gfx7_gfx10<0x007>;
1360defm V_MUL_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x008>;
1361defm V_MUL_I32_I24        : VOP2_Real_gfx6_gfx7_gfx10<0x009>;
1362defm V_MUL_HI_I32_I24     : VOP2_Real_gfx6_gfx7_gfx10<0x00a>;
1363defm V_MUL_U32_U24        : VOP2_Real_gfx6_gfx7_gfx10<0x00b>;
1364defm V_MUL_HI_U32_U24     : VOP2_Real_gfx6_gfx7_gfx10<0x00c>;
1365defm V_MIN_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x00f>;
1366defm V_MAX_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x010>;
1367defm V_MIN_I32            : VOP2_Real_gfx6_gfx7_gfx10<0x011>;
1368defm V_MAX_I32            : VOP2_Real_gfx6_gfx7_gfx10<0x012>;
1369defm V_MIN_U32            : VOP2_Real_gfx6_gfx7_gfx10<0x013>;
1370defm V_MAX_U32            : VOP2_Real_gfx6_gfx7_gfx10<0x014>;
1371defm V_LSHRREV_B32        : VOP2_Real_gfx6_gfx7_gfx10<0x016>;
1372defm V_ASHRREV_I32        : VOP2_Real_gfx6_gfx7_gfx10<0x018>;
1373defm V_LSHLREV_B32        : VOP2_Real_gfx6_gfx7_gfx10<0x01a>;
1374defm V_AND_B32            : VOP2_Real_gfx6_gfx7_gfx10<0x01b>;
1375defm V_OR_B32             : VOP2_Real_gfx6_gfx7_gfx10<0x01c>;
1376defm V_XOR_B32            : VOP2_Real_gfx6_gfx7_gfx10<0x01d>;
1377defm V_MAC_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x01f>;
1378defm V_CVT_PKRTZ_F16_F32  : VOP2_Real_gfx6_gfx7_gfx10<0x02f>;
1379defm V_MADMK_F32          : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x020>;
1380defm V_MADAK_F32          : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x021>;
1381
1382//===----------------------------------------------------------------------===//
1383// GFX8, GFX9 (VI).
1384//===----------------------------------------------------------------------===//
1385
1386let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {
1387
1388multiclass VOP2_Real_MADK_vi <bits<6> op> {
1389  def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,
1390            VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1391}
1392
1393multiclass VOP2_Real_e32_vi <bits<6> op> {
1394  def _e32_vi :
1395    VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
1396    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
1397}
1398
1399multiclass VOP2_Real_e64_vi <bits<10> op> {
1400  def _e64_vi :
1401    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
1402    VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1403}
1404
1405multiclass VOP2_Real_e64only_vi <bits<10> op> {
1406  def _e64_vi :
1407    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
1408    VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1409      // Hack to stop printing _e64
1410      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME#"_e64");
1411      let OutOperandList = (outs VGPR_32:$vdst);
1412      let AsmString = ps.Mnemonic # " " # ps.AsmOperands;
1413    }
1414}
1415
1416multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> :
1417  VOP2_Real_e32_vi<op>,
1418  VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>;
1419
1420} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8"
1421
1422multiclass VOP2_SDWA_Real <bits<6> op> {
1423  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA>.ret in
1424  def _sdwa_vi :
1425    VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1426    VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1427}
1428
1429multiclass VOP2_SDWA9_Real <bits<6> op> {
1430  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
1431  def _sdwa_gfx9 :
1432    VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1433    VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1434}
1435
1436let AssemblerPredicate = isGFX8Only in {
1437
1438multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName> {
1439  def _e32_vi :
1440    VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.VI>,
1441    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
1442      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32");
1443      let AsmString = AsmName # ps.AsmOperands;
1444      let DecoderNamespace = "GFX8";
1445    }
1446  def _e64_vi :
1447    VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.VI>,
1448    VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
1449      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64");
1450      let AsmString = AsmName # ps.AsmOperands;
1451      let DecoderNamespace = "GFX8";
1452    }
1453  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA>.ret in
1454    def _sdwa_vi :
1455      VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>,
1456      VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {
1457        VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa");
1458        let AsmString = AsmName # ps.AsmOperands;
1459      }
1460  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in
1461    def _dpp_vi :
1462      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.VI>,
1463      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> {
1464        VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp");
1465        let AsmString = AsmName # ps.AsmOperands;
1466      }
1467}
1468}
1469
1470let AssemblerPredicate = isGFX9Only in {
1471
1472multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> {
1473  def _e32_gfx9 :
1474    VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.GFX9>,
1475    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
1476      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32");
1477      let AsmString = AsmName # ps.AsmOperands;
1478      let DecoderNamespace = "GFX9";
1479    }
1480  def _e64_gfx9 :
1481    VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>,
1482    VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
1483      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64");
1484      let AsmString = AsmName # ps.AsmOperands;
1485      let DecoderNamespace = "GFX9";
1486    }
1487  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA9>.ret in
1488    def _sdwa_gfx9 :
1489      VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>,
1490      VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {
1491        VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa");
1492        let AsmString = AsmName # ps.AsmOperands;
1493      }
1494  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in
1495    def _dpp_gfx9 :
1496      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.GFX9>,
1497      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> {
1498        VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp");
1499        let AsmString = AsmName # ps.AsmOperands;
1500        let DecoderNamespace = "SDWA9";
1501      }
1502}
1503
1504multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> {
1505  def _e32_gfx9 :
1506    VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX9>,
1507    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>{
1508      let DecoderNamespace = "GFX9";
1509    }
1510  def _e64_gfx9 :
1511    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>,
1512    VOP3e_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1513      let DecoderNamespace = "GFX9";
1514    }
1515  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
1516    def _sdwa_gfx9 :
1517      VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1518      VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
1519      }
1520  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
1521    def _dpp_gfx9 :
1522      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,
1523      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
1524        let DecoderNamespace = "SDWA9";
1525      }
1526}
1527
1528} // AssemblerPredicate = isGFX9Only
1529
1530multiclass VOP2_Real_e32e64_vi <bits<6> op> :
1531  Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> {
1532
1533  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
1534    def _dpp_vi :
1535      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.VI>,
1536      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;
1537}
1538
1539defm V_CNDMASK_B32        : VOP2_Real_e32e64_vi <0x0>;
1540defm V_ADD_F32            : VOP2_Real_e32e64_vi <0x1>;
1541defm V_SUB_F32            : VOP2_Real_e32e64_vi <0x2>;
1542defm V_SUBREV_F32         : VOP2_Real_e32e64_vi <0x3>;
1543let AssemblerPredicate = isGCN3ExcludingGFX90A in
1544defm V_MUL_LEGACY_F32     : VOP2_Real_e32e64_vi <0x4>;
1545defm V_MUL_F32            : VOP2_Real_e32e64_vi <0x5>;
1546defm V_MUL_I32_I24        : VOP2_Real_e32e64_vi <0x6>;
1547defm V_MUL_HI_I32_I24     : VOP2_Real_e32e64_vi <0x7>;
1548defm V_MUL_U32_U24        : VOP2_Real_e32e64_vi <0x8>;
1549defm V_MUL_HI_U32_U24     : VOP2_Real_e32e64_vi <0x9>;
1550defm V_MIN_F32            : VOP2_Real_e32e64_vi <0xa>;
1551defm V_MAX_F32            : VOP2_Real_e32e64_vi <0xb>;
1552defm V_MIN_I32            : VOP2_Real_e32e64_vi <0xc>;
1553defm V_MAX_I32            : VOP2_Real_e32e64_vi <0xd>;
1554defm V_MIN_U32            : VOP2_Real_e32e64_vi <0xe>;
1555defm V_MAX_U32            : VOP2_Real_e32e64_vi <0xf>;
1556defm V_LSHRREV_B32        : VOP2_Real_e32e64_vi <0x10>;
1557defm V_ASHRREV_I32        : VOP2_Real_e32e64_vi <0x11>;
1558defm V_LSHLREV_B32        : VOP2_Real_e32e64_vi <0x12>;
1559defm V_AND_B32            : VOP2_Real_e32e64_vi <0x13>;
1560defm V_OR_B32             : VOP2_Real_e32e64_vi <0x14>;
1561defm V_XOR_B32            : VOP2_Real_e32e64_vi <0x15>;
1562defm V_MAC_F32            : VOP2_Real_e32e64_vi <0x16>;
1563defm V_MADMK_F32          : VOP2_Real_MADK_vi <0x17>;
1564defm V_MADAK_F32          : VOP2_Real_MADK_vi <0x18>;
1565
1566defm V_ADD_U32            : VOP2be_Real_e32e64_vi_only <0x19, "V_ADD_CO_U32",     "v_add_u32">;
1567defm V_SUB_U32            : VOP2be_Real_e32e64_vi_only <0x1a, "V_SUB_CO_U32",     "v_sub_u32">;
1568defm V_SUBREV_U32         : VOP2be_Real_e32e64_vi_only <0x1b, "V_SUBREV_CO_U32",  "v_subrev_u32">;
1569defm V_ADDC_U32           : VOP2be_Real_e32e64_vi_only <0x1c, "V_ADDC_U32",    "v_addc_u32">;
1570defm V_SUBB_U32           : VOP2be_Real_e32e64_vi_only <0x1d, "V_SUBB_U32",    "v_subb_u32">;
1571defm V_SUBBREV_U32        : VOP2be_Real_e32e64_vi_only <0x1e, "V_SUBBREV_U32", "v_subbrev_u32">;
1572
1573defm V_ADD_CO_U32         : VOP2be_Real_e32e64_gfx9 <0x19, "V_ADD_CO_U32",     "v_add_co_u32">;
1574defm V_SUB_CO_U32         : VOP2be_Real_e32e64_gfx9 <0x1a, "V_SUB_CO_U32",     "v_sub_co_u32">;
1575defm V_SUBREV_CO_U32      : VOP2be_Real_e32e64_gfx9 <0x1b, "V_SUBREV_CO_U32",  "v_subrev_co_u32">;
1576defm V_ADDC_CO_U32        : VOP2be_Real_e32e64_gfx9 <0x1c, "V_ADDC_U32",    "v_addc_co_u32">;
1577defm V_SUBB_CO_U32        : VOP2be_Real_e32e64_gfx9 <0x1d, "V_SUBB_U32",    "v_subb_co_u32">;
1578defm V_SUBBREV_CO_U32     : VOP2be_Real_e32e64_gfx9 <0x1e, "V_SUBBREV_U32", "v_subbrev_co_u32">;
1579
1580defm V_ADD_U32            : VOP2_Real_e32e64_gfx9 <0x34>;
1581defm V_SUB_U32            : VOP2_Real_e32e64_gfx9 <0x35>;
1582defm V_SUBREV_U32         : VOP2_Real_e32e64_gfx9 <0x36>;
1583
1584defm V_BFM_B32            : VOP2_Real_e64only_vi <0x293>;
1585defm V_BCNT_U32_B32       : VOP2_Real_e64only_vi <0x28b>;
1586defm V_MBCNT_LO_U32_B32   : VOP2_Real_e64only_vi <0x28c>;
1587defm V_MBCNT_HI_U32_B32   : VOP2_Real_e64only_vi <0x28d>;
1588defm V_LDEXP_F32          : VOP2_Real_e64only_vi <0x288>;
1589defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64only_vi <0x1f0>;
1590defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64only_vi <0x294>;
1591defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64only_vi <0x295>;
1592defm V_CVT_PKRTZ_F16_F32  : VOP2_Real_e64only_vi <0x296>;
1593defm V_CVT_PK_U16_U32     : VOP2_Real_e64only_vi <0x297>;
1594defm V_CVT_PK_I16_I32     : VOP2_Real_e64only_vi <0x298>;
1595
1596defm V_ADD_F16            : VOP2_Real_e32e64_vi <0x1f>;
1597defm V_SUB_F16            : VOP2_Real_e32e64_vi <0x20>;
1598defm V_SUBREV_F16         : VOP2_Real_e32e64_vi <0x21>;
1599defm V_MUL_F16            : VOP2_Real_e32e64_vi <0x22>;
1600defm V_MAC_F16            : VOP2_Real_e32e64_vi <0x23>;
1601defm V_MADMK_F16          : VOP2_Real_MADK_vi <0x24>;
1602defm V_MADAK_F16          : VOP2_Real_MADK_vi <0x25>;
1603defm V_ADD_U16            : VOP2_Real_e32e64_vi <0x26>;
1604defm V_SUB_U16            : VOP2_Real_e32e64_vi <0x27>;
1605defm V_SUBREV_U16         : VOP2_Real_e32e64_vi <0x28>;
1606defm V_MUL_LO_U16         : VOP2_Real_e32e64_vi <0x29>;
1607defm V_LSHLREV_B16        : VOP2_Real_e32e64_vi <0x2a>;
1608defm V_LSHRREV_B16        : VOP2_Real_e32e64_vi <0x2b>;
1609defm V_ASHRREV_I16        : VOP2_Real_e32e64_vi <0x2c>;
1610defm V_MAX_F16            : VOP2_Real_e32e64_vi <0x2d>;
1611defm V_MIN_F16            : VOP2_Real_e32e64_vi <0x2e>;
1612defm V_MAX_U16            : VOP2_Real_e32e64_vi <0x2f>;
1613defm V_MAX_I16            : VOP2_Real_e32e64_vi <0x30>;
1614defm V_MIN_U16            : VOP2_Real_e32e64_vi <0x31>;
1615defm V_MIN_I16            : VOP2_Real_e32e64_vi <0x32>;
1616defm V_LDEXP_F16          : VOP2_Real_e32e64_vi <0x33>;
1617
1618let SubtargetPredicate = isGFX8GFX9 in {
1619
1620// Aliases to simplify matching of floating-point instructions that
1621// are VOP2 on SI and VOP3 on VI.
1622class SI2_VI3Alias <string name, VOP3_Real inst> : InstAlias <
1623  name#" $dst, $src0, $src1",
1624  !if(inst.Pfl.HasOMod,
1625      (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0),
1626      (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0))
1627>, PredicateControl {
1628  let UseInstAsmMatchConverter = 0;
1629  let AsmVariantName = AMDGPUAsmVariants.VOP3;
1630}
1631
1632def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>;
1633def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>;
1634def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>;
1635def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;
1636def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;
1637
1638defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_vi>;
1639
1640} // End SubtargetPredicate = isGFX8GFX9
1641
1642let SubtargetPredicate = isGFX9Only in {
1643
1644defm : VOP2bInstAliases<V_ADD_U32_e32,     V_ADD_CO_U32_e32_gfx9,     "v_add_co_u32">;
1645defm : VOP2bInstAliases<V_ADDC_U32_e32,    V_ADDC_CO_U32_e32_gfx9,    "v_addc_co_u32">;
1646defm : VOP2bInstAliases<V_SUB_U32_e32,     V_SUB_CO_U32_e32_gfx9,     "v_sub_co_u32">;
1647defm : VOP2bInstAliases<V_SUBB_U32_e32,    V_SUBB_CO_U32_e32_gfx9,    "v_subb_co_u32">;
1648defm : VOP2bInstAliases<V_SUBREV_U32_e32,  V_SUBREV_CO_U32_e32_gfx9,  "v_subrev_co_u32">;
1649defm : VOP2bInstAliases<V_SUBBREV_U32_e32, V_SUBBREV_CO_U32_e32_gfx9, "v_subbrev_co_u32">;
1650
1651} // End SubtargetPredicate = isGFX9Only
1652
1653let SubtargetPredicate = HasDLInsts in {
1654
1655defm V_FMAC_F32 : VOP2_Real_e32e64_vi <0x3b>;
1656defm V_XNOR_B32 : VOP2_Real_e32e64_vi <0x3d>;
1657
1658} // End SubtargetPredicate = HasDLInsts
1659
1660let AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A" in {
1661  multiclass VOP2_Real_e32_gfx90a <bits<6> op> {
1662    def _e32_gfx90a :
1663      VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX90A>,
1664      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
1665  }
1666
1667  multiclass VOP2_Real_e64_gfx90a <bits<10> op> {
1668    def _e64_gfx90a :
1669      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX90A>,
1670      VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1671  }
1672
1673  multiclass Base_VOP2_Real_e32e64_gfx90a <bits<6> op> :
1674    VOP2_Real_e32_gfx90a<op>,
1675    VOP2_Real_e64_gfx90a<{0, 1, 0, 0, op{5-0}}>;
1676
1677  multiclass VOP2_Real_e32e64_gfx90a <bits<6> op> :
1678    Base_VOP2_Real_e32e64_gfx90a<op> {
1679
1680    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
1681      def _dpp_gfx90a :
1682        VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX90A>,
1683        VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
1684          let DecoderNamespace = "SDWA9";
1685        }
1686  }
1687} // End AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A"
1688
1689let SubtargetPredicate = isGFX90APlus in {
1690  defm V_FMAC_F64       : VOP2_Real_e32e64_gfx90a <0x4>;
1691  defm V_MUL_LEGACY_F32 : VOP2_Real_e64_gfx90a <0x2a1>;
1692} // End SubtargetPredicate = isGFX90APlus
1693
1694multiclass VOP2_Real_DOT_ACC_gfx9<bits<6> op> : VOP2_Real_e32_vi<op> {
1695  def _dpp_vi : VOP2_DPP<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;
1696}
1697
1698multiclass VOP2_Real_DOT_ACC_gfx10<bits<6> op> :
1699  VOP2_Real_e32_gfx10<op>,
1700  VOP2_Real_dpp_gfx10<op>,
1701  VOP2_Real_dpp8_gfx10<op>;
1702
1703let SubtargetPredicate = HasDot5Insts in {
1704  defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx9<0x37>;
1705  // NB: Opcode conflicts with V_DOT8C_I32_I4
1706  // This opcode exists in gfx 10.1* only
1707  defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx10<0x02>;
1708}
1709
1710let SubtargetPredicate = HasDot6Insts in {
1711  defm V_DOT4C_I32_I8  : VOP2_Real_DOT_ACC_gfx9<0x39>;
1712  defm V_DOT4C_I32_I8  : VOP2_Real_DOT_ACC_gfx10<0x0d>;
1713}
1714
1715let SubtargetPredicate = HasDot4Insts in {
1716  defm V_DOT2C_I32_I16 : VOP2_Real_DOT_ACC_gfx9<0x38>;
1717}
1718let SubtargetPredicate = HasDot3Insts in {
1719  defm V_DOT8C_I32_I4  : VOP2_Real_DOT_ACC_gfx9<0x3a>;
1720}
1721
1722let SubtargetPredicate = HasPkFmacF16Inst in {
1723defm V_PK_FMAC_F16 : VOP2_Real_e32_vi<0x3c>;
1724} // End SubtargetPredicate = HasPkFmacF16Inst
1725
1726let SubtargetPredicate = HasDot3Insts in {
1727  // NB: Opcode conflicts with V_DOT2C_F32_F16
1728  let DecoderNamespace = "GFX10_B" in
1729  defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx10<0x02>;
1730}
1731