1//===-- VOP2Instructions.td - Vector Instruction Defintions ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// VOP2 Classes 12//===----------------------------------------------------------------------===// 13 14class VOP2e <bits<6> op, VOPProfile P> : Enc32 { 15 bits<8> vdst; 16 bits<9> src0; 17 bits<8> src1; 18 19 let Inst{8-0} = !if(P.HasSrc0, src0, 0); 20 let Inst{16-9} = !if(P.HasSrc1, src1, 0); 21 let Inst{24-17} = !if(P.EmitDst, vdst, 0); 22 let Inst{30-25} = op; 23 let Inst{31} = 0x0; //encoding 24} 25 26class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 { 27 bits<8> vdst; 28 bits<9> src0; 29 bits<8> src1; 30 bits<32> imm; 31 32 let Inst{8-0} = !if(P.HasSrc0, src0, 0); 33 let Inst{16-9} = !if(P.HasSrc1, src1, 0); 34 let Inst{24-17} = !if(P.EmitDst, vdst, 0); 35 let Inst{30-25} = op; 36 let Inst{31} = 0x0; // encoding 37 let Inst{63-32} = imm; 38} 39 40class VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> { 41 bits<8> vdst; 42 bits<8> src1; 43 44 let Inst{8-0} = 0xf9; // sdwa 45 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 46 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 47 let Inst{30-25} = op; 48 let Inst{31} = 0x0; // encoding 49} 50 51class VOP2_SDWA9Ae <bits<6> op, VOPProfile P> : VOP_SDWA9Ae <P> { 52 bits<8> vdst; 53 bits<9> src1; 54 55 let Inst{8-0} = 0xf9; // sdwa 56 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 57 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 58 let Inst{30-25} = op; 59 let Inst{31} = 0x0; // encoding 60 let Inst{63} = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr 61} 62 63class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> : 64 VOP_Pseudo <opName, suffix, P, P.Outs32, P.Ins32, "", pattern> { 65 66 let AsmOperands = P.Asm32; 67 68 let Size = 4; 69 let mayLoad = 0; 70 let mayStore = 0; 71 let hasSideEffects = 0; 72 let SubtargetPredicate = isGCN; 73 74 let VOP2 = 1; 75 let VALU = 1; 76 let Uses = [EXEC]; 77 78 let AsmVariantName = AMDGPUAsmVariants.Default; 79} 80 81class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> : 82 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 83 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 84 85 let isPseudo = 0; 86 let isCodeGenOnly = 0; 87 88 let Constraints = ps.Constraints; 89 let DisableEncoding = ps.DisableEncoding; 90 91 // copy relevant pseudo op flags 92 let SubtargetPredicate = ps.SubtargetPredicate; 93 let AsmMatchConverter = ps.AsmMatchConverter; 94 let AsmVariantName = ps.AsmVariantName; 95 let Constraints = ps.Constraints; 96 let DisableEncoding = ps.DisableEncoding; 97 let TSFlags = ps.TSFlags; 98 let UseNamedOperandTable = ps.UseNamedOperandTable; 99 let Uses = ps.Uses; 100 let Defs = ps.Defs; 101} 102 103class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : 104 VOP_SDWA_Pseudo <OpName, P, pattern> { 105 let AsmMatchConverter = "cvtSdwaVOP2"; 106} 107 108class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies { 109 list<dag> ret = !if(P.HasModifiers, 110 [(set P.DstVT:$vdst, 111 (node (P.Src0VT 112 !if(P.HasOMod, 113 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 114 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))), 115 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], 116 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]); 117} 118 119multiclass VOP2Inst_e32<string opName, 120 VOPProfile P, 121 SDPatternOperator node = null_frag, 122 string revOp = opName, 123 bit GFX9Renamed = 0> { 124 let renamedInGFX9 = GFX9Renamed in { 125 def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>, 126 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>; 127 } // End renamedInGFX9 = GFX9Renamed 128} 129 130multiclass VOP2Inst_e64<string opName, 131 VOPProfile P, 132 SDPatternOperator node = null_frag, 133 string revOp = opName, 134 bit GFX9Renamed = 0> { 135 let renamedInGFX9 = GFX9Renamed in { 136 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>, 137 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>; 138 } // End renamedInGFX9 = GFX9Renamed 139} 140 141multiclass VOP2Inst_sdwa<string opName, 142 VOPProfile P, 143 SDPatternOperator node = null_frag, 144 string revOp = opName, 145 bit GFX9Renamed = 0> { 146 let renamedInGFX9 = GFX9Renamed in { 147 def _sdwa : VOP2_SDWA_Pseudo <opName, P>; 148 } // End renamedInGFX9 = GFX9Renamed 149} 150 151multiclass VOP2Inst<string opName, 152 VOPProfile P, 153 SDPatternOperator node = null_frag, 154 string revOp = opName, 155 bit GFX9Renamed = 0> : 156 VOP2Inst_e32<opName, P, node, revOp, GFX9Renamed>, 157 VOP2Inst_e64<opName, P, node, revOp, GFX9Renamed>, 158 VOP2Inst_sdwa<opName, P, node, revOp, GFX9Renamed>; 159 160multiclass VOP2bInst <string opName, 161 VOPProfile P, 162 SDPatternOperator node = null_frag, 163 string revOp = opName, 164 bit GFX9Renamed = 0, 165 bit useSGPRInput = !eq(P.NumSrcArgs, 3)> { 166 let renamedInGFX9 = GFX9Renamed in { 167 let SchedRW = [Write32Bit, WriteSALU] in { 168 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in { 169 def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>, 170 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>; 171 172 def _sdwa : VOP2_SDWA_Pseudo <opName, P> { 173 let AsmMatchConverter = "cvtSdwaVOP2b"; 174 } 175 } 176 177 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>, 178 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>; 179 } 180 } 181} 182 183multiclass VOP2eInst <string opName, 184 VOPProfile P, 185 SDPatternOperator node = null_frag, 186 string revOp = opName, 187 bit useSGPRInput = !eq(P.NumSrcArgs, 3)> { 188 189 let SchedRW = [Write32Bit] in { 190 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in { 191 def _e32 : VOP2_Pseudo <opName, P>, 192 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>; 193 194 def _sdwa : VOP2_SDWA_Pseudo <opName, P> { 195 let AsmMatchConverter = "cvtSdwaVOP2b"; 196 } 197 } 198 199 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>, 200 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>; 201 } 202} 203 204class VOP_MADAK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> { 205 field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm); 206 field dag Ins32 = (ins VCSrc_f32:$src0, VGPR_32:$src1, ImmOpType:$imm); 207 field bit HasExt = 0; 208 209 // Hack to stop printing _e64 210 let DstRC = RegisterOperand<VGPR_32>; 211 field string Asm32 = " $vdst, $src0, $src1, $imm"; 212} 213 214def VOP_MADAK_F16 : VOP_MADAK <f16>; 215def VOP_MADAK_F32 : VOP_MADAK <f32>; 216 217class VOP_MADMK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> { 218 field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm); 219 field dag Ins32 = (ins VCSrc_f32:$src0, ImmOpType:$imm, VGPR_32:$src1); 220 field bit HasExt = 0; 221 222 // Hack to stop printing _e64 223 let DstRC = RegisterOperand<VGPR_32>; 224 field string Asm32 = " $vdst, $src0, $imm, $src1"; 225} 226 227def VOP_MADMK_F16 : VOP_MADMK <f16>; 228def VOP_MADMK_F32 : VOP_MADMK <f32>; 229 230// FIXME: Remove src2_modifiers. It isn't used, so is wasting memory 231// and processing time but it makes it easier to convert to mad. 232class VOP_MAC <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> { 233 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2); 234 let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3, 235 0, HasModifiers, HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret; 236 let InsDPP = (ins DstRCDPP:$old, 237 Src0ModDPP:$src0_modifiers, Src0DPP:$src0, 238 Src1ModDPP:$src1_modifiers, Src1DPP:$src1, 239 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 240 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 241 242 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 243 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 244 VGPR_32:$src2, // stub argument 245 clampmod:$clamp, omod:$omod, 246 dst_sel:$dst_sel, dst_unused:$dst_unused, 247 src0_sel:$src0_sel, src1_sel:$src1_sel); 248 let Asm32 = getAsm32<1, 2, vt>.ret; 249 let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, vt>.ret; 250 let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt>.ret; 251 let AsmSDWA = getAsmSDWA<1, 2, vt>.ret; 252 let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt>.ret; 253 let HasSrc2 = 0; 254 let HasSrc2Mods = 0; 255 256 let HasExt = 1; 257 let HasExtDPP = 1; 258 let HasExtSDWA = 1; 259 let HasExtSDWA9 = 0; 260} 261 262def VOP_MAC_F16 : VOP_MAC <f16>; 263def VOP_MAC_F32 : VOP_MAC <f32>; 264 265// Write out to vcc or arbitrary SGPR. 266def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped]> { 267 let Asm32 = "$vdst, vcc, $src0, $src1"; 268 let Asm64 = "$vdst, $sdst, $src0, $src1"; 269 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 270 let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 271 let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 272 let Outs32 = (outs DstRC:$vdst); 273 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst); 274} 275 276// Write out to vcc or arbitrary SGPR and read in from vcc or 277// arbitrary SGPR. 278def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> { 279 // We use VCSrc_b32 to exclude literal constants, even though the 280 // encoding normally allows them since the implicit VCC use means 281 // using one would always violate the constant bus 282 // restriction. SGPRs are still allowed because it should 283 // technically be possible to use VCC again as src0. 284 let Src0RC32 = VCSrc_b32; 285 let Asm32 = "$vdst, vcc, $src0, $src1, vcc"; 286 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2"; 287 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 288 let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 289 let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 290 let Outs32 = (outs DstRC:$vdst); 291 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst); 292 293 // Suppress src2 implied by type since the 32-bit encoding uses an 294 // implicit VCC use. 295 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1); 296 297 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 298 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 299 clampmod:$clamp, 300 dst_sel:$dst_sel, dst_unused:$dst_unused, 301 src0_sel:$src0_sel, src1_sel:$src1_sel); 302 303 let InsDPP = (ins DstRCDPP:$old, 304 Src0DPP:$src0, 305 Src1DPP:$src1, 306 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 307 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 308 let HasExt = 1; 309 let HasExtDPP = 1; 310 let HasExtSDWA = 1; 311 let HasExtSDWA9 = 1; 312} 313 314// Read in from vcc or arbitrary SGPR 315def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> { 316 let Src0RC32 = VCSrc_b32; // See comment in def VOP2b_I32_I1_I32_I32_I1 above. 317 let Asm32 = "$vdst, $src0, $src1, vcc"; 318 let Asm64 = "$vdst, $src0, $src1, $src2"; 319 let AsmSDWA = "$vdst, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 320 let AsmSDWA9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 321 let AsmDPP = "$vdst, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 322 323 let Outs32 = (outs DstRC:$vdst); 324 let Outs64 = (outs DstRC:$vdst); 325 326 // Suppress src2 implied by type since the 32-bit encoding uses an 327 // implicit VCC use. 328 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1); 329 330 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 331 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 332 clampmod:$clamp, 333 dst_sel:$dst_sel, dst_unused:$dst_unused, 334 src0_sel:$src0_sel, src1_sel:$src1_sel); 335 336 let InsDPP = (ins DstRCDPP:$old, 337 Src0DPP:$src0, 338 Src1DPP:$src1, 339 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 340 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 341 let HasExt = 1; 342 let HasExtDPP = 1; 343 let HasExtSDWA = 1; 344 let HasExtSDWA9 = 1; 345} 346 347def VOP_READLANE : VOPProfile<[i32, i32, i32]> { 348 let Outs32 = (outs SReg_32:$vdst); 349 let Outs64 = Outs32; 350 let Ins32 = (ins VGPR_32:$src0, SCSrc_b32:$src1); 351 let Ins64 = Ins32; 352 let Asm32 = " $vdst, $src0, $src1"; 353 let Asm64 = Asm32; 354 355 let HasExt = 0; 356 let HasExtDPP = 0; 357 let HasExtSDWA = 0; 358 let HasExtSDWA9 = 0; 359} 360 361def VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> { 362 let Outs32 = (outs VGPR_32:$vdst); 363 let Outs64 = Outs32; 364 let Ins32 = (ins SCSrc_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in); 365 let Ins64 = Ins32; 366 let Asm32 = " $vdst, $src0, $src1"; 367 let Asm64 = Asm32; 368 let HasSrc2 = 0; 369 let HasSrc2Mods = 0; 370 371 let HasExt = 0; 372 let HasExtDPP = 0; 373 let HasExtSDWA = 0; 374 let HasExtSDWA9 = 0; 375} 376 377//===----------------------------------------------------------------------===// 378// VOP2 Instructions 379//===----------------------------------------------------------------------===// 380 381let SubtargetPredicate = isGCN, Predicates = [isGCN] in { 382 383defm V_CNDMASK_B32 : VOP2eInst <"v_cndmask_b32", VOP2e_I32_I32_I32_I1>; 384def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, []>; 385 386let isCommutable = 1 in { 387defm V_ADD_F32 : VOP2Inst <"v_add_f32", VOP_F32_F32_F32, fadd>; 388defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, fsub>; 389defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">; 390defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>; 391defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, fmul>; 392defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmul_i24>; 393defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_i24>; 394defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmul_u24>; 395defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_u24>; 396defm V_MIN_F32 : VOP2Inst <"v_min_f32", VOP_F32_F32_F32, fminnum_like>; 397defm V_MAX_F32 : VOP2Inst <"v_max_f32", VOP_F32_F32_F32, fmaxnum_like>; 398defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smin>; 399defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smax>; 400defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umin>; 401defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umax>; 402defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, null_frag, "v_lshr_b32">; 403defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, null_frag, "v_ashr_i32">; 404defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, null_frag, "v_lshl_b32">; 405defm V_AND_B32 : VOP2Inst <"v_and_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, and>; 406defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, or>; 407defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, xor>; 408 409let Constraints = "$vdst = $src2", DisableEncoding="$src2", 410 isConvertibleToThreeAddress = 1 in { 411defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>; 412} 413 414def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32, []>; 415 416// No patterns so that the scalar instructions are always selected. 417// The scalar versions will be replaced with vector when needed later. 418 419// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in VI, 420// but the VI instructions behave the same as the SI versions. 421defm V_ADD_I32 : VOP2bInst <"v_add_i32", VOP2b_I32_I1_I32_I32, null_frag, "v_add_i32", 1>; 422defm V_SUB_I32 : VOP2bInst <"v_sub_i32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_i32", 1>; 423defm V_SUBREV_I32 : VOP2bInst <"v_subrev_i32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_i32", 1>; 424defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_addc_u32", 1>; 425defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>; 426defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>; 427 428 429let SubtargetPredicate = HasAddNoCarryInsts in { 430defm V_ADD_U32 : VOP2Inst <"v_add_u32", VOP_I32_I32_I32, null_frag, "v_add_u32", 1>; 431defm V_SUB_U32 : VOP2Inst <"v_sub_u32", VOP_I32_I32_I32, null_frag, "v_sub_u32", 1>; 432defm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32, null_frag, "v_sub_u32", 1>; 433} 434 435} // End isCommutable = 1 436 437// These are special and do not read the exec mask. 438let isConvergent = 1, Uses = []<Register> in { 439def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE, 440 [(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))]>; 441 442let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in { 443def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE, 444 [(set i32:$vdst, (int_amdgcn_writelane i32:$src0, i32:$src1, i32:$vdst_in))]>; 445} // End $vdst = $vdst_in, DisableEncoding $vdst_in 446} // End isConvergent = 1 447 448defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_NO_EXT<VOP_I32_I32_I32>>; 449defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>>; 450defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_lo>; 451defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_hi>; 452defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_NO_EXT<VOP_F32_F32_I32>, AMDGPUldexp>; 453defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_NO_EXT<VOP_I32_F32_I32>>; // TODO: set "Uses = dst" 454defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_i16_f32>; 455defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_u16_f32>; 456defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_NO_EXT<VOP_V2F16_F32_F32>, AMDGPUpkrtz_f16_f32>; 457defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_u16_u32>; 458defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_i16_i32>; 459 460} // End SubtargetPredicate = isGCN, Predicates = [isGCN] 461 462def : GCNPat< 463 (AMDGPUadde i32:$src0, i32:$src1, i1:$src2), 464 (V_ADDC_U32_e64 $src0, $src1, $src2) 465>; 466 467def : GCNPat< 468 (AMDGPUsube i32:$src0, i32:$src1, i1:$src2), 469 (V_SUBB_U32_e64 $src0, $src1, $src2) 470>; 471 472// These instructions only exist on SI and CI 473let SubtargetPredicate = isSICI, Predicates = [isSICI] in { 474 475defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>; 476defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>; 477 478let isCommutable = 1 in { 479defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_F32_F32_F32>; 480defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, srl>; 481defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, sra>; 482defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, shl>; 483} // End isCommutable = 1 484 485} // End let SubtargetPredicate = SICI, Predicates = [isSICI] 486 487class DivergentBinOp<SDPatternOperator Op, VOP_Pseudo Inst> : 488 GCNPat< 489 (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1), 490 !if(!cast<Commutable_REV>(Inst).IsOrig, 491 (Inst $src0, $src1), 492 (Inst $src1, $src0) 493 ) 494 >; 495 496let AddedComplexity = 1 in { 497 def : DivergentBinOp<srl, V_LSHRREV_B32_e64>; 498 def : DivergentBinOp<sra, V_ASHRREV_I32_e64>; 499 def : DivergentBinOp<shl, V_LSHLREV_B32_e64>; 500} 501 502let SubtargetPredicate = HasAddNoCarryInsts in { 503 def : DivergentBinOp<add, V_ADD_U32_e32>; 504 def : DivergentBinOp<sub, V_SUB_U32_e32>; 505 def : DivergentBinOp<sub, V_SUBREV_U32_e32>; 506} 507 508 509def : DivergentBinOp<add, V_ADD_I32_e32>; 510 511def : DivergentBinOp<add, V_ADD_I32_e64>; 512def : DivergentBinOp<sub, V_SUB_I32_e32>; 513 514def : DivergentBinOp<sub, V_SUBREV_I32_e32>; 515 516def : DivergentBinOp<srl, V_LSHRREV_B32_e32>; 517def : DivergentBinOp<sra, V_ASHRREV_I32_e32>; 518def : DivergentBinOp<shl, V_LSHLREV_B32_e32>; 519def : DivergentBinOp<adde, V_ADDC_U32_e32>; 520def : DivergentBinOp<sube, V_SUBB_U32_e32>; 521 522class divergent_i64_BinOp <SDPatternOperator Op, Instruction Inst> : 523 GCNPat< 524 (getDivergentFrag<Op>.ret i64:$src0, i64:$src1), 525 (REG_SEQUENCE VReg_64, 526 (Inst 527 (i32 (EXTRACT_SUBREG $src0, sub0)), 528 (i32 (EXTRACT_SUBREG $src1, sub0)) 529 ), sub0, 530 (Inst 531 (i32 (EXTRACT_SUBREG $src0, sub1)), 532 (i32 (EXTRACT_SUBREG $src1, sub1)) 533 ), sub1 534 ) 535 >; 536 537def : divergent_i64_BinOp <and, V_AND_B32_e32>; 538def : divergent_i64_BinOp <or, V_OR_B32_e32>; 539def : divergent_i64_BinOp <xor, V_XOR_B32_e32>; 540 541let SubtargetPredicate = Has16BitInsts in { 542 543def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16, [], "">; 544defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16>; 545defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16>; 546defm V_ASHRREV_I16 : VOP2Inst <"v_ashrrev_i16", VOP_I16_I16_I16>; 547defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>; 548 549let isCommutable = 1 in { 550defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, fadd>; 551defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, fsub>; 552defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">; 553defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, fmul>; 554def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">; 555defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16>; 556defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16>; 557defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16, null_frag, "v_sub_u16">; 558defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16>; 559defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum_like>; 560defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum_like>; 561defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16>; 562defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16>; 563defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16>; 564defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16>; 565 566let Constraints = "$vdst = $src2", DisableEncoding="$src2", 567 isConvertibleToThreeAddress = 1 in { 568defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>; 569} 570} // End isCommutable = 1 571 572} // End SubtargetPredicate = Has16BitInsts 573 574let SubtargetPredicate = HasDLInsts in { 575 576defm V_XNOR_B32 : VOP2Inst <"v_xnor_b32", VOP_I32_I32_I32>; 577 578let Constraints = "$vdst = $src2", 579 DisableEncoding="$src2", 580 isConvertibleToThreeAddress = 1, 581 isCommutable = 1 in { 582defm V_FMAC_F32 : VOP2Inst <"v_fmac_f32", VOP_MAC_F32>; 583} 584 585} // End SubtargetPredicate = HasDLInsts 586 587// Note: 16-bit instructions produce a 0 result in the high 16-bits. 588multiclass Arithmetic_i16_Pats <SDPatternOperator op, Instruction inst> { 589 590def : GCNPat< 591 (op i16:$src0, i16:$src1), 592 (inst $src0, $src1) 593>; 594 595def : GCNPat< 596 (i32 (zext (op i16:$src0, i16:$src1))), 597 (inst $src0, $src1) 598>; 599 600def : GCNPat< 601 (i64 (zext (op i16:$src0, i16:$src1))), 602 (REG_SEQUENCE VReg_64, 603 (inst $src0, $src1), sub0, 604 (V_MOV_B32_e32 (i32 0)), sub1) 605>; 606 607} 608 609multiclass Bits_OpsRev_i16_Pats <SDPatternOperator op, Instruction inst> { 610 611def : GCNPat< 612 (op i16:$src0, i16:$src1), 613 (inst $src1, $src0) 614>; 615 616def : GCNPat< 617 (i32 (zext (op i16:$src0, i16:$src1))), 618 (inst $src1, $src0) 619>; 620 621 622def : GCNPat< 623 (i64 (zext (op i16:$src0, i16:$src1))), 624 (REG_SEQUENCE VReg_64, 625 (inst $src1, $src0), sub0, 626 (V_MOV_B32_e32 (i32 0)), sub1) 627>; 628} 629 630class ZExt_i16_i1_Pat <SDNode ext> : GCNPat < 631 (i16 (ext i1:$src)), 632 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src) 633>; 634 635let Predicates = [Has16BitInsts] in { 636 637defm : Arithmetic_i16_Pats<add, V_ADD_U16_e64>; 638defm : Arithmetic_i16_Pats<mul, V_MUL_LO_U16_e64>; 639defm : Arithmetic_i16_Pats<sub, V_SUB_U16_e64>; 640defm : Arithmetic_i16_Pats<smin, V_MIN_I16_e64>; 641defm : Arithmetic_i16_Pats<smax, V_MAX_I16_e64>; 642defm : Arithmetic_i16_Pats<umin, V_MIN_U16_e64>; 643defm : Arithmetic_i16_Pats<umax, V_MAX_U16_e64>; 644 645def : GCNPat < 646 (and i16:$src0, i16:$src1), 647 (V_AND_B32_e64 $src0, $src1) 648>; 649 650def : GCNPat < 651 (or i16:$src0, i16:$src1), 652 (V_OR_B32_e64 $src0, $src1) 653>; 654 655def : GCNPat < 656 (xor i16:$src0, i16:$src1), 657 (V_XOR_B32_e64 $src0, $src1) 658>; 659 660defm : Bits_OpsRev_i16_Pats<shl, V_LSHLREV_B16_e64>; 661defm : Bits_OpsRev_i16_Pats<srl, V_LSHRREV_B16_e64>; 662defm : Bits_OpsRev_i16_Pats<sra, V_ASHRREV_I16_e64>; 663 664def : ZExt_i16_i1_Pat<zext>; 665def : ZExt_i16_i1_Pat<anyext>; 666 667def : GCNPat < 668 (i16 (sext i1:$src)), 669 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src) 670>; 671 672// Undo sub x, c -> add x, -c canonicalization since c is more likely 673// an inline immediate than -c. 674// TODO: Also do for 64-bit. 675def : GCNPat< 676 (add i16:$src0, (i16 NegSubInlineConst16:$src1)), 677 (V_SUB_U16_e64 $src0, NegSubInlineConst16:$src1) 678>; 679 680} // End Predicates = [Has16BitInsts] 681 682//===----------------------------------------------------------------------===// 683// SI 684//===----------------------------------------------------------------------===// 685 686let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in { 687 688multiclass VOP2_Real_si <bits<6> op> { 689 def _si : 690 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>, 691 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 692} 693 694multiclass VOP2_Real_MADK_si <bits<6> op> { 695 def _si : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>, 696 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 697} 698 699multiclass VOP2_Real_e32_si <bits<6> op> { 700 def _e32_si : 701 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>, 702 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 703} 704 705multiclass VOP2_Real_e32e64_si <bits<6> op> : VOP2_Real_e32_si<op> { 706 def _e64_si : 707 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 708 VOP3e_si <{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 709} 710 711multiclass VOP2be_Real_e32e64_si <bits<6> op> : VOP2_Real_e32_si<op> { 712 def _e64_si : 713 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 714 VOP3be_si <{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 715} 716 717} // End AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" 718 719defm V_CNDMASK_B32 : VOP2_Real_e32e64_si <0x0>; 720defm V_ADD_F32 : VOP2_Real_e32e64_si <0x3>; 721defm V_SUB_F32 : VOP2_Real_e32e64_si <0x4>; 722defm V_SUBREV_F32 : VOP2_Real_e32e64_si <0x5>; 723defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_si <0x7>; 724defm V_MUL_F32 : VOP2_Real_e32e64_si <0x8>; 725defm V_MUL_I32_I24 : VOP2_Real_e32e64_si <0x9>; 726defm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_si <0xa>; 727defm V_MUL_U32_U24 : VOP2_Real_e32e64_si <0xb>; 728defm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_si <0xc>; 729defm V_MIN_F32 : VOP2_Real_e32e64_si <0xf>; 730defm V_MAX_F32 : VOP2_Real_e32e64_si <0x10>; 731defm V_MIN_I32 : VOP2_Real_e32e64_si <0x11>; 732defm V_MAX_I32 : VOP2_Real_e32e64_si <0x12>; 733defm V_MIN_U32 : VOP2_Real_e32e64_si <0x13>; 734defm V_MAX_U32 : VOP2_Real_e32e64_si <0x14>; 735defm V_LSHRREV_B32 : VOP2_Real_e32e64_si <0x16>; 736defm V_ASHRREV_I32 : VOP2_Real_e32e64_si <0x18>; 737defm V_LSHLREV_B32 : VOP2_Real_e32e64_si <0x1a>; 738defm V_AND_B32 : VOP2_Real_e32e64_si <0x1b>; 739defm V_OR_B32 : VOP2_Real_e32e64_si <0x1c>; 740defm V_XOR_B32 : VOP2_Real_e32e64_si <0x1d>; 741defm V_MAC_F32 : VOP2_Real_e32e64_si <0x1f>; 742defm V_MADMK_F32 : VOP2_Real_MADK_si <0x20>; 743defm V_MADAK_F32 : VOP2_Real_MADK_si <0x21>; 744defm V_ADD_I32 : VOP2be_Real_e32e64_si <0x25>; 745defm V_SUB_I32 : VOP2be_Real_e32e64_si <0x26>; 746defm V_SUBREV_I32 : VOP2be_Real_e32e64_si <0x27>; 747defm V_ADDC_U32 : VOP2be_Real_e32e64_si <0x28>; 748defm V_SUBB_U32 : VOP2be_Real_e32e64_si <0x29>; 749defm V_SUBBREV_U32 : VOP2be_Real_e32e64_si <0x2a>; 750 751defm V_READLANE_B32 : VOP2_Real_si <0x01>; 752 753let InOperandList = (ins SSrc_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in) in { 754defm V_WRITELANE_B32 : VOP2_Real_si <0x02>; 755} 756 757defm V_MAC_LEGACY_F32 : VOP2_Real_e32e64_si <0x6>; 758defm V_MIN_LEGACY_F32 : VOP2_Real_e32e64_si <0xd>; 759defm V_MAX_LEGACY_F32 : VOP2_Real_e32e64_si <0xe>; 760defm V_LSHR_B32 : VOP2_Real_e32e64_si <0x15>; 761defm V_ASHR_I32 : VOP2_Real_e32e64_si <0x17>; 762defm V_LSHL_B32 : VOP2_Real_e32e64_si <0x19>; 763 764defm V_BFM_B32 : VOP2_Real_e32e64_si <0x1e>; 765defm V_BCNT_U32_B32 : VOP2_Real_e32e64_si <0x22>; 766defm V_MBCNT_LO_U32_B32 : VOP2_Real_e32e64_si <0x23>; 767defm V_MBCNT_HI_U32_B32 : VOP2_Real_e32e64_si <0x24>; 768defm V_LDEXP_F32 : VOP2_Real_e32e64_si <0x2b>; 769defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e32e64_si <0x2c>; 770defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e32e64_si <0x2d>; 771defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e32e64_si <0x2e>; 772defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e32e64_si <0x2f>; 773defm V_CVT_PK_U16_U32 : VOP2_Real_e32e64_si <0x30>; 774defm V_CVT_PK_I16_I32 : VOP2_Real_e32e64_si <0x31>; 775 776 777//===----------------------------------------------------------------------===// 778// VI 779//===----------------------------------------------------------------------===// 780 781class VOP2_DPP <bits<6> op, VOP2_Pseudo ps, string OpName = ps.OpName, VOPProfile P = ps.Pfl> : 782 VOP_DPP <OpName, P> { 783 let Defs = ps.Defs; 784 let Uses = ps.Uses; 785 let SchedRW = ps.SchedRW; 786 let hasSideEffects = ps.hasSideEffects; 787 788 bits<8> vdst; 789 bits<8> src1; 790 let Inst{8-0} = 0xfa; //dpp 791 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 792 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 793 let Inst{30-25} = op; 794 let Inst{31} = 0x0; //encoding 795} 796 797let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in { 798 799multiclass VOP2_Real_MADK_vi <bits<6> op> { 800 def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>, 801 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 802} 803 804multiclass VOP2_Real_e32_vi <bits<6> op> { 805 def _e32_vi : 806 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>, 807 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 808} 809 810multiclass VOP2_Real_e64_vi <bits<10> op> { 811 def _e64_vi : 812 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 813 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 814} 815 816multiclass VOP2_Real_e64only_vi <bits<10> op> { 817 def _e64_vi : 818 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 819 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 820 // Hack to stop printing _e64 821 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME#"_e64"); 822 let OutOperandList = (outs VGPR_32:$vdst); 823 let AsmString = ps.Mnemonic # " " # ps.AsmOperands; 824 } 825} 826 827multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> : 828 VOP2_Real_e32_vi<op>, 829 VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>; 830 831} // End AssemblerPredicates = [isVI], DecoderNamespace = "VI" 832 833multiclass VOP2_SDWA_Real <bits<6> op> { 834 def _sdwa_vi : 835 VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 836 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 837} 838 839multiclass VOP2_SDWA9_Real <bits<6> op> { 840 def _sdwa_gfx9 : 841 VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 842 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 843} 844 845let AssemblerPredicates = [isVIOnly] in { 846 847multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName> { 848 def _e32_vi : 849 VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.VI>, 850 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> { 851 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32"); 852 let AsmString = AsmName # ps.AsmOperands; 853 let DecoderNamespace = "VI"; 854 } 855 def _e64_vi : 856 VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.VI>, 857 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> { 858 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64"); 859 let AsmString = AsmName # ps.AsmOperands; 860 let DecoderNamespace = "VI"; 861 } 862 def _sdwa_vi : 863 VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>, 864 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> { 865 VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa"); 866 let AsmString = AsmName # ps.AsmOperands; 867 } 868 def _dpp : 869 VOP2_DPP<op, !cast<VOP2_Pseudo>(OpName#"_e32"), AsmName>; 870} 871} 872 873let AssemblerPredicates = [isGFX9] in { 874 875multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> { 876 def _e32_gfx9 : 877 VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.GFX9>, 878 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> { 879 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32"); 880 let AsmString = AsmName # ps.AsmOperands; 881 let DecoderNamespace = "GFX9"; 882 } 883 def _e64_gfx9 : 884 VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>, 885 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> { 886 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64"); 887 let AsmString = AsmName # ps.AsmOperands; 888 let DecoderNamespace = "GFX9"; 889 } 890 def _sdwa_gfx9 : 891 VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>, 892 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> { 893 VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa"); 894 let AsmString = AsmName # ps.AsmOperands; 895 } 896 def _dpp_gfx9 : 897 VOP2_DPP<op, !cast<VOP2_Pseudo>(OpName#"_e32"), AsmName> { 898 let DecoderNamespace = "SDWA9"; 899 } 900} 901 902multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> { 903 def _e32_gfx9 : 904 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX9>, 905 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>{ 906 let DecoderNamespace = "GFX9"; 907 } 908 def _e64_gfx9 : 909 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>, 910 VOP3e_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 911 let DecoderNamespace = "GFX9"; 912 } 913 def _sdwa_gfx9 : 914 VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 915 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> { 916 } 917 def _dpp_gfx9 : 918 VOP2_DPP<op, !cast<VOP2_Pseudo>(NAME#"_e32")> { 919 let DecoderNamespace = "SDWA9"; 920 } 921} 922 923} // AssemblerPredicates = [isGFX9] 924 925multiclass VOP2_Real_e32e64_vi <bits<6> op> : 926 Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> { 927 // For now left dpp only for asm/dasm 928 // TODO: add corresponding pseudo 929 def _dpp : VOP2_DPP<op, !cast<VOP2_Pseudo>(NAME#"_e32")>; 930} 931 932defm V_CNDMASK_B32 : VOP2_Real_e32e64_vi <0x0>; 933defm V_ADD_F32 : VOP2_Real_e32e64_vi <0x1>; 934defm V_SUB_F32 : VOP2_Real_e32e64_vi <0x2>; 935defm V_SUBREV_F32 : VOP2_Real_e32e64_vi <0x3>; 936defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_vi <0x4>; 937defm V_MUL_F32 : VOP2_Real_e32e64_vi <0x5>; 938defm V_MUL_I32_I24 : VOP2_Real_e32e64_vi <0x6>; 939defm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_vi <0x7>; 940defm V_MUL_U32_U24 : VOP2_Real_e32e64_vi <0x8>; 941defm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_vi <0x9>; 942defm V_MIN_F32 : VOP2_Real_e32e64_vi <0xa>; 943defm V_MAX_F32 : VOP2_Real_e32e64_vi <0xb>; 944defm V_MIN_I32 : VOP2_Real_e32e64_vi <0xc>; 945defm V_MAX_I32 : VOP2_Real_e32e64_vi <0xd>; 946defm V_MIN_U32 : VOP2_Real_e32e64_vi <0xe>; 947defm V_MAX_U32 : VOP2_Real_e32e64_vi <0xf>; 948defm V_LSHRREV_B32 : VOP2_Real_e32e64_vi <0x10>; 949defm V_ASHRREV_I32 : VOP2_Real_e32e64_vi <0x11>; 950defm V_LSHLREV_B32 : VOP2_Real_e32e64_vi <0x12>; 951defm V_AND_B32 : VOP2_Real_e32e64_vi <0x13>; 952defm V_OR_B32 : VOP2_Real_e32e64_vi <0x14>; 953defm V_XOR_B32 : VOP2_Real_e32e64_vi <0x15>; 954defm V_MAC_F32 : VOP2_Real_e32e64_vi <0x16>; 955defm V_MADMK_F32 : VOP2_Real_MADK_vi <0x17>; 956defm V_MADAK_F32 : VOP2_Real_MADK_vi <0x18>; 957 958defm V_ADD_U32 : VOP2be_Real_e32e64_vi_only <0x19, "V_ADD_I32", "v_add_u32">; 959defm V_SUB_U32 : VOP2be_Real_e32e64_vi_only <0x1a, "V_SUB_I32", "v_sub_u32">; 960defm V_SUBREV_U32 : VOP2be_Real_e32e64_vi_only <0x1b, "V_SUBREV_I32", "v_subrev_u32">; 961defm V_ADDC_U32 : VOP2be_Real_e32e64_vi_only <0x1c, "V_ADDC_U32", "v_addc_u32">; 962defm V_SUBB_U32 : VOP2be_Real_e32e64_vi_only <0x1d, "V_SUBB_U32", "v_subb_u32">; 963defm V_SUBBREV_U32 : VOP2be_Real_e32e64_vi_only <0x1e, "V_SUBBREV_U32", "v_subbrev_u32">; 964 965defm V_ADD_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x19, "V_ADD_I32", "v_add_co_u32">; 966defm V_SUB_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1a, "V_SUB_I32", "v_sub_co_u32">; 967defm V_SUBREV_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1b, "V_SUBREV_I32", "v_subrev_co_u32">; 968defm V_ADDC_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1c, "V_ADDC_U32", "v_addc_co_u32">; 969defm V_SUBB_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1d, "V_SUBB_U32", "v_subb_co_u32">; 970defm V_SUBBREV_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1e, "V_SUBBREV_U32", "v_subbrev_co_u32">; 971 972defm V_ADD_U32 : VOP2_Real_e32e64_gfx9 <0x34>; 973defm V_SUB_U32 : VOP2_Real_e32e64_gfx9 <0x35>; 974defm V_SUBREV_U32 : VOP2_Real_e32e64_gfx9 <0x36>; 975 976defm V_BFM_B32 : VOP2_Real_e64only_vi <0x293>; 977defm V_BCNT_U32_B32 : VOP2_Real_e64only_vi <0x28b>; 978defm V_MBCNT_LO_U32_B32 : VOP2_Real_e64only_vi <0x28c>; 979defm V_MBCNT_HI_U32_B32 : VOP2_Real_e64only_vi <0x28d>; 980defm V_LDEXP_F32 : VOP2_Real_e64only_vi <0x288>; 981defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64only_vi <0x1f0>; 982defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64only_vi <0x294>; 983defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64only_vi <0x295>; 984defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e64only_vi <0x296>; 985defm V_CVT_PK_U16_U32 : VOP2_Real_e64only_vi <0x297>; 986defm V_CVT_PK_I16_I32 : VOP2_Real_e64only_vi <0x298>; 987 988defm V_ADD_F16 : VOP2_Real_e32e64_vi <0x1f>; 989defm V_SUB_F16 : VOP2_Real_e32e64_vi <0x20>; 990defm V_SUBREV_F16 : VOP2_Real_e32e64_vi <0x21>; 991defm V_MUL_F16 : VOP2_Real_e32e64_vi <0x22>; 992defm V_MAC_F16 : VOP2_Real_e32e64_vi <0x23>; 993defm V_MADMK_F16 : VOP2_Real_MADK_vi <0x24>; 994defm V_MADAK_F16 : VOP2_Real_MADK_vi <0x25>; 995defm V_ADD_U16 : VOP2_Real_e32e64_vi <0x26>; 996defm V_SUB_U16 : VOP2_Real_e32e64_vi <0x27>; 997defm V_SUBREV_U16 : VOP2_Real_e32e64_vi <0x28>; 998defm V_MUL_LO_U16 : VOP2_Real_e32e64_vi <0x29>; 999defm V_LSHLREV_B16 : VOP2_Real_e32e64_vi <0x2a>; 1000defm V_LSHRREV_B16 : VOP2_Real_e32e64_vi <0x2b>; 1001defm V_ASHRREV_I16 : VOP2_Real_e32e64_vi <0x2c>; 1002defm V_MAX_F16 : VOP2_Real_e32e64_vi <0x2d>; 1003defm V_MIN_F16 : VOP2_Real_e32e64_vi <0x2e>; 1004defm V_MAX_U16 : VOP2_Real_e32e64_vi <0x2f>; 1005defm V_MAX_I16 : VOP2_Real_e32e64_vi <0x30>; 1006defm V_MIN_U16 : VOP2_Real_e32e64_vi <0x31>; 1007defm V_MIN_I16 : VOP2_Real_e32e64_vi <0x32>; 1008defm V_LDEXP_F16 : VOP2_Real_e32e64_vi <0x33>; 1009 1010let SubtargetPredicate = isVI in { 1011 1012// Aliases to simplify matching of floating-point instructions that 1013// are VOP2 on SI and VOP3 on VI. 1014class SI2_VI3Alias <string name, VOP3_Real inst> : InstAlias < 1015 name#" $dst, $src0, $src1", 1016 !if(inst.Pfl.HasOMod, 1017 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0), 1018 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0)) 1019>, PredicateControl { 1020 let UseInstAsmMatchConverter = 0; 1021 let AsmVariantName = AMDGPUAsmVariants.VOP3; 1022} 1023 1024def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>; 1025def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>; 1026def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>; 1027def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>; 1028def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>; 1029 1030} // End SubtargetPredicate = isVI 1031 1032let SubtargetPredicate = HasDLInsts in { 1033 1034defm V_FMAC_F32 : VOP2_Real_e32e64_vi <0x3b>; 1035defm V_XNOR_B32 : VOP2_Real_e32e64_vi <0x3d>; 1036 1037} // End SubtargetPredicate = HasDLInsts 1038