1//===-- VOP2Instructions.td - Vector Instruction Definitions --------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// VOP2 Classes 11//===----------------------------------------------------------------------===// 12 13class VOP2e <bits<6> op, VOPProfile P> : Enc32 { 14 bits<8> vdst; 15 bits<9> src0; 16 bits<8> src1; 17 18 let Inst{8-0} = !if(P.HasSrc0, src0, 0); 19 let Inst{16-9} = !if(P.HasSrc1, src1, 0); 20 let Inst{24-17} = !if(P.EmitDst, vdst, 0); 21 let Inst{30-25} = op; 22 let Inst{31} = 0x0; //encoding 23} 24 25class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 { 26 bits<8> vdst; 27 bits<9> src0; 28 bits<8> src1; 29 bits<32> imm; 30 31 let Inst{8-0} = !if(P.HasSrc0, src0, 0); 32 let Inst{16-9} = !if(P.HasSrc1, src1, 0); 33 let Inst{24-17} = !if(P.EmitDst, vdst, 0); 34 let Inst{30-25} = op; 35 let Inst{31} = 0x0; // encoding 36 let Inst{63-32} = imm; 37} 38 39class VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> { 40 bits<8> vdst; 41 bits<8> src1; 42 43 let Inst{8-0} = 0xf9; // sdwa 44 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 45 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 46 let Inst{30-25} = op; 47 let Inst{31} = 0x0; // encoding 48} 49 50class VOP2_SDWA9Ae <bits<6> op, VOPProfile P> : VOP_SDWA9Ae <P> { 51 bits<8> vdst; 52 bits<9> src1; 53 54 let Inst{8-0} = 0xf9; // sdwa 55 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 56 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 57 let Inst{30-25} = op; 58 let Inst{31} = 0x0; // encoding 59 let Inst{63} = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr 60} 61 62class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> : 63 VOP_Pseudo <opName, suffix, P, P.Outs32, P.Ins32, "", pattern> { 64 65 let AsmOperands = P.Asm32; 66 67 let Size = 4; 68 let mayLoad = 0; 69 let mayStore = 0; 70 let hasSideEffects = 0; 71 72 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 73 74 let mayRaiseFPException = ReadsModeReg; 75 76 let VOP2 = 1; 77 let VALU = 1; 78 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 79 80 let AsmVariantName = AMDGPUAsmVariants.Default; 81} 82 83class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily, string real_name = ps.Mnemonic> : 84 VOP_Real <ps>, 85 InstSI <ps.OutOperandList, ps.InOperandList, real_name # ps.AsmOperands, []>, 86 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 87 88 let VALU = 1; 89 let VOP2 = 1; 90 let isPseudo = 0; 91 let isCodeGenOnly = 0; 92 93 let Constraints = ps.Constraints; 94 let DisableEncoding = ps.DisableEncoding; 95 96 // copy relevant pseudo op flags 97 let SubtargetPredicate = ps.SubtargetPredicate; 98 let OtherPredicates = ps.OtherPredicates; 99 let AsmMatchConverter = ps.AsmMatchConverter; 100 let AsmVariantName = ps.AsmVariantName; 101 let Constraints = ps.Constraints; 102 let DisableEncoding = ps.DisableEncoding; 103 let TSFlags = ps.TSFlags; 104 let UseNamedOperandTable = ps.UseNamedOperandTable; 105 let Uses = ps.Uses; 106 let Defs = ps.Defs; 107 let SchedRW = ps.SchedRW; 108 let mayLoad = ps.mayLoad; 109 let mayStore = ps.mayStore; 110} 111 112class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : 113 VOP_SDWA_Pseudo <OpName, P, pattern> { 114 let AsmMatchConverter = "cvtSdwaVOP2"; 115} 116 117class VOP2_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : 118 VOP_DPP_Pseudo <OpName, P, pattern> { 119} 120 121 122class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies { 123 list<dag> ret = !if(P.HasModifiers, 124 [(set P.DstVT:$vdst, 125 (node (P.Src0VT 126 !if(P.HasOMod, 127 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 128 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))), 129 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], 130 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]); 131} 132 133multiclass VOP2Inst_e32<string opName, 134 VOPProfile P, 135 SDPatternOperator node = null_frag, 136 string revOp = opName, 137 bit GFX9Renamed = 0> { 138 let renamedInGFX9 = GFX9Renamed in { 139 def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>, 140 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>; 141 } // End renamedInGFX9 = GFX9Renamed 142} 143multiclass 144 VOP2Inst_e32_VOPD<string opName, VOPProfile P, bits<5> VOPDOp, 145 string VOPDName, SDPatternOperator node = null_frag, 146 string revOp = opName, bit GFX9Renamed = 0> { 147 defm NAME : VOP2Inst_e32<opName, P, node, revOp, GFX9Renamed>, 148 VOPD_Component<VOPDOp, VOPDName>; 149} 150multiclass VOP2Inst_e64<string opName, 151 VOPProfile P, 152 SDPatternOperator node = null_frag, 153 string revOp = opName, 154 bit GFX9Renamed = 0> { 155 let renamedInGFX9 = GFX9Renamed in { 156 def _e64 : VOP3InstBase <opName, P, node, 1>, 157 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>; 158 159 let SubtargetPredicate = isGFX11Plus in { 160 foreach _ = BoolToList<P.HasExtVOP3DPP>.ret in 161 def _e64_dpp : VOP3_DPP_Pseudo <opName, P>; 162 } // End SubtargetPredicate = isGFX11Plus 163 } // End renamedInGFX9 = GFX9Renamed 164} 165 166multiclass VOP2Inst_sdwa<string opName, 167 VOPProfile P, 168 bit GFX9Renamed = 0> { 169 let renamedInGFX9 = GFX9Renamed in { 170 foreach _ = BoolToList<P.HasExtSDWA>.ret in 171 def _sdwa : VOP2_SDWA_Pseudo <opName, P>; 172 } // End renamedInGFX9 = GFX9Renamed 173} 174 175multiclass VOP2Inst<string opName, 176 VOPProfile P, 177 SDPatternOperator node = null_frag, 178 string revOp = opName, 179 bit GFX9Renamed = 0> : 180 VOP2Inst_e32<opName, P, node, revOp, GFX9Renamed>, 181 VOP2Inst_e64<opName, P, node, revOp, GFX9Renamed>, 182 VOP2Inst_sdwa<opName, P, GFX9Renamed> { 183 let renamedInGFX9 = GFX9Renamed in { 184 foreach _ = BoolToList<P.HasExtDPP>.ret in 185 def _dpp : VOP2_DPP_Pseudo <opName, P>; 186 } 187} 188 189multiclass VOP2Inst_VOPD<string opName, 190 VOPProfile P, 191 bits<5> VOPDOp, 192 string VOPDName, 193 SDPatternOperator node = null_frag, 194 string revOp = opName, 195 bit GFX9Renamed = 0> : 196 VOP2Inst_e32_VOPD<opName, P, VOPDOp, VOPDName, node, revOp, GFX9Renamed>, 197 VOP2Inst_e64<opName, P, node, revOp, GFX9Renamed>, 198 VOP2Inst_sdwa<opName, P, GFX9Renamed> { 199 let renamedInGFX9 = GFX9Renamed in { 200 foreach _ = BoolToList<P.HasExtDPP>.ret in 201 def _dpp : VOP2_DPP_Pseudo <opName, P>; 202 } 203} 204 205multiclass VOP2bInst <string opName, 206 VOPProfile P, 207 SDPatternOperator node = null_frag, 208 string revOp = opName, 209 bit GFX9Renamed = 0, 210 bit useSGPRInput = !eq(P.NumSrcArgs, 3)> { 211 let renamedInGFX9 = GFX9Renamed in { 212 let SchedRW = [Write32Bit, WriteSALU] in { 213 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in { 214 def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>, 215 Commutable_REV<revOp#"_e32", !eq(revOp, opName)> { 216 let usesCustomInserter = true; 217 } 218 219 foreach _ = BoolToList<P.HasExtSDWA>.ret in 220 def _sdwa : VOP2_SDWA_Pseudo <opName, P> { 221 let AsmMatchConverter = "cvtSdwaVOP2b"; 222 } 223 foreach _ = BoolToList<P.HasExtDPP>.ret in 224 def _dpp : VOP2_DPP_Pseudo <opName, P>; 225 } // End Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] 226 227 def _e64 : VOP3InstBase <opName, P, node, 1>, 228 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>; 229 230 let SubtargetPredicate = isGFX11Plus in { 231 foreach _ = BoolToList<P.HasExtVOP3DPP>.ret in 232 def _e64_dpp : VOP3_DPP_Pseudo <opName, P>; 233 } // End SubtargetPredicate = isGFX11Plus 234 } 235 } 236} 237 238class VOP2bInstAlias <VOP2_Pseudo ps, Instruction inst, 239 string OpName, string opnd> : 240 InstAlias <OpName#" "#!subst("vcc", opnd, ps.Pfl.Asm32), 241 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0, 242 ps.Pfl.Src1RC32:$src1)>, 243 PredicateControl { 244} 245 246multiclass VOP2bInstAliases<VOP2_Pseudo ps, VOP2_Real inst, string OpName> { 247 let WaveSizePredicate = isWave32 in { 248 def : VOP2bInstAlias<ps, inst, OpName, "vcc_lo">; 249 } 250 let WaveSizePredicate = isWave64 in { 251 def : VOP2bInstAlias<ps, inst, OpName, "vcc">; 252 } 253} 254 255multiclass 256 VOP2eInst_Base<string opName, VOPProfile P, bits<5> VOPDOp, string VOPDName, 257 SDPatternOperator node, string revOp, bit useSGPRInput> { 258 259 let SchedRW = [Write32Bit] in { 260 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in { 261 if !eq(VOPDOp, -1) then 262 def _e32 : VOP2_Pseudo <opName, P>, 263 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>; 264 else 265 def _e32 : VOP2_Pseudo <opName, P>, 266 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>, 267 VOPD_Component<VOPDOp, VOPDName>; 268 269 foreach _ = BoolToList<P.HasExtSDWA>.ret in 270 def _sdwa : VOP2_SDWA_Pseudo <opName, P> { 271 let AsmMatchConverter = "cvtSdwaVOP2e"; 272 } 273 274 foreach _ = BoolToList<P.HasExtDPP>.ret in 275 def _dpp : VOP2_DPP_Pseudo <opName, P>; 276 } 277 278 def _e64 : VOP3InstBase <opName, P, node, 1>, 279 Commutable_REV<revOp#"_e64", !eq(revOp, opName)> { 280 let isReMaterializable = 1; 281 } 282 283 let SubtargetPredicate = isGFX11Plus in { 284 foreach _ = BoolToList<P.HasExtVOP3DPP>.ret in 285 def _e64_dpp : VOP3_DPP_Pseudo <opName, P>; 286 } // End SubtargetPredicate = isGFX11Plus 287 } 288} 289 290multiclass 291 VOP2eInst<string opName, VOPProfile P, SDPatternOperator node = null_frag, 292 string revOp = opName, bit useSGPRInput = !eq(P.NumSrcArgs, 3)> 293 : VOP2eInst_Base<opName, P, -1, "", node, revOp, useSGPRInput>; 294 295multiclass 296 VOP2eInst_VOPD<string opName, VOPProfile P, bits<5> VOPDOp, string VOPDName, 297 SDPatternOperator node = null_frag, string revOp = opName, 298 bit useSGPRInput = !eq(P.NumSrcArgs, 3)> 299 : VOP2eInst_Base<opName, P, VOPDOp, VOPDName, node, revOp, useSGPRInput>; 300 301class VOP2eInstAlias <VOP2_Pseudo ps, Instruction inst, string opnd = ""> : 302 InstAlias <ps.OpName#" "#ps.Pfl.Asm32#", "#opnd, 303 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0, 304 ps.Pfl.Src1RC32:$src1)>, PredicateControl; 305 306class VOP2e64InstAlias <VOP3_Pseudo ps, Instruction inst> : 307 InstAlias <ps.OpName#" "#ps.Pfl.Asm64, 308 (inst ps.Pfl.DstRC:$vdst, VOPDstS64orS32:$sdst, 309 ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, clampmod:$clamp)>, 310 PredicateControl; 311 312multiclass VOP2eInstAliases<VOP2_Pseudo ps, VOP2_Real inst> { 313 let WaveSizePredicate = isWave32 in { 314 def : VOP2eInstAlias<ps, inst, "vcc_lo">; 315 } 316 let WaveSizePredicate = isWave64 in { 317 def : VOP2eInstAlias<ps, inst, "vcc">; 318 } 319} 320 321class VOP_MADK_Base<ValueType vt> : VOPProfile <[vt, vt, vt, vt]> { 322 string AsmVOPDXDeferred = ?; 323} 324 325class VOP_MADAK <ValueType vt> : VOP_MADK_Base<vt> { 326 field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm); 327 field dag Ins32 = !if(!eq(vt.Size, 32), 328 (ins VSrc_f32_Deferred:$src0, VGPR_32:$src1, ImmOpType:$imm), 329 (ins VSrc_f16_Deferred:$src0, VGPR_32:$src1, ImmOpType:$imm)); 330 field dag InsVOPDX = (ins VSrc_f32_Deferred:$src0X, VGPR_32:$vsrc1X, ImmOpType:$imm); 331 // Note that both src0X and imm are deferred 332 let InsVOPDXDeferred = (ins VSrc_f32_Deferred:$src0X, VGPR_32:$vsrc1X, ImmOpType:$immDeferred); 333 field dag InsVOPDY = (ins VSrc_f32_Deferred:$src0Y, VGPR_32:$vsrc1Y, ImmOpType:$imm); 334 335 field string Asm32 = "$vdst, $src0, $src1, $imm"; 336 field string AsmVOPDX = "$vdstX, $src0X, $vsrc1X, $imm"; 337 let AsmVOPDXDeferred = "$vdstX, $src0X, $vsrc1X, $immDeferred"; 338 field string AsmVOPDY = "$vdstY, $src0Y, $vsrc1Y, $imm"; 339 field bit HasExt = 0; 340 let IsSingle = 1; 341} 342 343def VOP_MADAK_F16 : VOP_MADAK <f16>; 344def VOP_MADAK_F32 : VOP_MADAK <f32>; 345 346class VOP_MADMK <ValueType vt> : VOP_MADK_Base<vt> { 347 field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm); 348 field dag Ins32 = (ins VSrc_f32_Deferred:$src0, ImmOpType:$imm, VGPR_32:$src1); 349 field dag InsVOPDX = (ins VSrc_f32_Deferred:$src0X, ImmOpType:$imm, VGPR_32:$vsrc1X); 350 let InsVOPDXDeferred = (ins VSrc_f32_Deferred:$src0X, ImmOpType:$immDeferred, VGPR_32:$vsrc1X); 351 field dag InsVOPDY = (ins VSrc_f32_Deferred:$src0Y, ImmOpType:$imm, VGPR_32:$vsrc1Y); 352 353 field string Asm32 = "$vdst, $src0, $imm, $src1"; 354 field string AsmVOPDX = "$vdstX, $src0X, $imm, $vsrc1X"; 355 let AsmVOPDXDeferred = "$vdstX, $src0X, $immDeferred, $vsrc1X"; 356 field string AsmVOPDY = "$vdstY, $src0Y, $imm, $vsrc1Y"; 357 field bit HasExt = 0; 358 let IsSingle = 1; 359} 360 361def VOP_MADMK_F16 : VOP_MADMK <f16>; 362def VOP_MADMK_F32 : VOP_MADMK <f32>; 363 364class getRegisterOperandForVT<ValueType VT> { 365 RegisterOperand ret = RegisterOperand<getVregSrcForVT<VT>.ret>; 366} 367 368// FIXME: Remove src2_modifiers. It isn't used, so is wasting memory 369// and processing time but it makes it easier to convert to mad. 370class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, vt0]> { 371 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, getVregSrcForVT<Src2VT>.ret:$src2); 372 let Ins64 = getIns64<Src0RC64, Src1RC64, getRegisterOperandForVT<Src2VT>.ret, 3, 373 0, HasModifiers, HasModifiers, HasOMod, 374 Src0Mod, Src1Mod, Src2Mod>.ret; 375 let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, 376 Src1ModDPP:$src1_modifiers, Src1DPP:$src1, 377 getVregSrcForVT<Src2VT>.ret:$src2, // stub argument 378 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 379 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 380 let InsDPP16 = !con(InsDPP, (ins FI:$fi)); 381 let InsVOP3Base = getIns64<Src0VOP3DPP, Src1RC64, RegisterOperand<VGPR_32>, 3, 382 0, HasModifiers, HasModifiers, HasOMod, 383 Src0Mod, Src1Mod, Src2Mod>.ret; 384 385 let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, 386 Src1ModDPP:$src1_modifiers, Src1DPP:$src1, 387 getVregSrcForVT<Src2VT>.ret:$src2, // stub argument 388 dpp8:$dpp8, FI:$fi); 389 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 390 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 391 getVregSrcForVT<Src2VT>.ret:$src2, // stub argument 392 clampmod:$clamp, omod:$omod, 393 dst_sel:$dst_sel, dst_unused:$dst_unused, 394 src0_sel:$src0_sel, src1_sel:$src1_sel); 395 let Asm32 = getAsm32<1, 2, vt0>.ret; 396 let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, vt0>.ret; 397 let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt0>.ret; 398 let AsmDPP16 = getAsmDPP16<1, 2, HasModifiers, vt0>.ret; 399 let AsmDPP8 = getAsmDPP8<1, 2, 0, vt0>.ret; 400 let AsmSDWA = getAsmSDWA<1, 2, vt0>.ret; 401 let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt0>.ret; 402 let HasSrc2 = 0; 403 let HasSrc2Mods = 0; 404 405 let HasExt = 1; 406 let HasExtDPP = 1; 407 let HasExt32BitDPP = 1; 408 let HasExtSDWA = 1; 409 let HasExtSDWA9 = 0; 410 let TieRegDPP = "$src2"; 411} 412 413def VOP_MAC_F16 : VOP_MAC <f16>; 414def VOP_MAC_F32 : VOP_MAC <f32>; 415let HasExtDPP = 0, HasExt32BitDPP = 0 in 416def VOP_MAC_LEGACY_F32 : VOP_MAC <f32>; 417let HasExtSDWA = 0, HasExt32BitDPP = 0, HasExt64BitDPP = 1 in 418def VOP_MAC_F64 : VOP_MAC <f64>; 419 420class VOP_DOT_ACC<ValueType vt0, ValueType vt1> : VOP_MAC<vt0, vt1> { 421 let HasClamp = 0; 422 let HasExtSDWA = 0; 423 let HasOpSel = 0; 424 let IsPacked = 0; 425} 426 427def VOP_DOT_ACC_F32_V2F16 : VOP_DOT_ACC<f32, v2f16> { 428 let Src0ModDPP = FPVRegInputMods; 429 let Src1ModDPP = FPVRegInputMods; 430} 431 432def VOP_DOT_ACC_I32_I32 : VOP_DOT_ACC<i32, i32> { 433 let HasExtVOP3DPP = 0; 434 let HasSrc0Mods = 1; 435 let HasSrc1Mods = 1; 436} 437 438// Write out to vcc or arbitrary SGPR. 439def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], 0, /*EnableClamp=*/1> { 440 let Asm32 = "$vdst, vcc, $src0, $src1"; 441 let Asm64 = "$vdst, $sdst, $src0, $src1$clamp"; 442 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 443 let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 444 let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 445 let AsmDPP8 = "$vdst, vcc, $src0, $src1 $dpp8$fi"; 446 let AsmDPP16 = AsmDPP#"$fi"; 447 let AsmVOP3DPPBase = Asm64; 448 let InsDPP = (ins DstRCDPP:$old, 449 Src0DPP:$src0, 450 Src1DPP:$src1, 451 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 452 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 453 let InsDPP16 = !con(InsDPP, (ins FI:$fi)); 454 let InsDPP8 = (ins DstRCDPP:$old, 455 Src0DPP:$src0, 456 Src1DPP:$src1, 457 dpp8:$dpp8, FI:$fi); 458 let Outs32 = (outs DstRC:$vdst); 459 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 460 let OutsVOP3DPP = Outs64; 461 let OutsVOP3DPP8 = Outs64; 462} 463 464// Write out to vcc or arbitrary SGPR and read in from vcc or 465// arbitrary SGPR. 466def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], 0, /*EnableClamp=*/1> { 467 let HasSrc2Mods = 0; 468 let Asm32 = "$vdst, vcc, $src0, $src1, vcc"; 469 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp"; 470 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 471 let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 472 let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 473 let AsmDPP8 = "$vdst, vcc, $src0, $src1, vcc $dpp8$fi"; 474 let AsmDPP16 = AsmDPP#"$fi"; 475 let Outs32 = (outs DstRC:$vdst); 476 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 477 let AsmVOP3DPPBase = Asm64; 478 let OutsVOP3DPP = Outs64; 479 let OutsVOP3DPP8 = Outs64; 480 481 // Suppress src2 implied by type since the 32-bit encoding uses an 482 // implicit VCC use. 483 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1); 484 485 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 486 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 487 clampmod:$clamp, 488 dst_sel:$dst_sel, dst_unused:$dst_unused, 489 src0_sel:$src0_sel, src1_sel:$src1_sel); 490 491 let InsDPP = (ins DstRCDPP:$old, 492 Src0DPP:$src0, 493 Src1DPP:$src1, 494 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 495 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 496 let InsDPP16 = !con(InsDPP, (ins FI:$fi)); 497 let InsDPP8 = (ins DstRCDPP:$old, 498 Src0DPP:$src0, 499 Src1DPP:$src1, 500 dpp8:$dpp8, FI:$fi); 501 502 let HasExt = 1; 503 let HasExtDPP = 1; 504 let HasExt32BitDPP = 1; 505 let HasExtSDWA = 1; 506 let HasExtSDWA9 = 1; 507} 508 509// Read in from vcc or arbitrary SGPR. 510class VOP2e_SGPR<list<ValueType> ArgVT> : VOPProfile<ArgVT, /*EnableF32SrcMods=*/1> { 511 let Asm32 = "$vdst, $src0, $src1"; 512 let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2"; 513 let AsmSDWA = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 514 let AsmSDWA9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 515 let AsmDPP = "$vdst, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 516 let AsmDPP8 = "$vdst, $src0, $src1, vcc $dpp8$fi"; 517 let AsmDPP16 = AsmDPP#"$fi"; 518 let AsmVOP3DPPBase = Asm64; 519 520 let Outs32 = (outs DstRC:$vdst); 521 let Outs64 = (outs DstRC:$vdst); 522 523 // Suppress src2 implied by type since the 32-bit encoding uses an 524 // implicit VCC use. 525 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1); 526 527 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 528 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 529 clampmod:$clamp, 530 dst_sel:$dst_sel, dst_unused:$dst_unused, 531 src0_sel:$src0_sel, src1_sel:$src1_sel); 532 533 let InsDPP = (ins DstRCDPP:$old, 534 Src0ModDPP:$src0_modifiers, Src0DPP:$src0, 535 Src1ModDPP:$src1_modifiers, Src1DPP:$src1, 536 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 537 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 538 let InsDPP16 = !con(InsDPP, (ins FI:$fi)); 539 let InsDPP8 = (ins DstRCDPP:$old, 540 Src0ModDPP:$src0_modifiers, Src0DPP:$src0, 541 Src1ModDPP:$src1_modifiers, Src1DPP:$src1, 542 dpp8:$dpp8, FI:$fi); 543 544 let HasExt = 1; 545 let HasExtDPP = 1; 546 let HasExt32BitDPP = 1; 547 let HasExtSDWA = 1; 548 let HasExtSDWA9 = 1; 549} 550 551def VOP2e_I32_I32_I32_I1 : VOP2e_SGPR<[i32, i32, i32, i1]>; 552def VOP2e_I16_I16_I16_I1 : VOP2e_SGPR<[i16, i16, i16, i1]>; 553 554def VOP_READLANE : VOPProfile<[i32, i32, i32, untyped]> { 555 let Outs32 = (outs SReg_32:$vdst); 556 let Outs64 = Outs32; 557 let Ins32 = (ins VRegOrLds_32:$src0, SCSrc_b32:$src1); 558 let Ins64 = Ins32; 559 let Asm32 = " $vdst, $src0, $src1"; 560 let Asm64 = Asm32; 561 562 let HasExt = 0; 563 let HasExtDPP = 0; 564 let HasExt32BitDPP = 0; 565 let HasExt64BitDPP = 0; 566 let HasExtSDWA = 0; 567 let HasExtSDWA9 = 0; 568} 569 570def VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> { 571 let Outs32 = (outs VGPR_32:$vdst); 572 let Outs64 = Outs32; 573 let Ins32 = (ins SCSrc_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in); 574 let Ins64 = Ins32; 575 let Asm32 = " $vdst, $src0, $src1"; 576 let Asm64 = Asm32; 577 let HasSrc2 = 0; 578 let HasSrc2Mods = 0; 579 580 let HasExt = 0; 581 let HasExtDPP = 0; 582 let HasExt32BitDPP = 0; 583 let HasExt64BitDPP = 0; 584 let HasExtSDWA = 0; 585 let HasExtSDWA9 = 0; 586} 587 588//===----------------------------------------------------------------------===// 589// VOP2 Instructions 590//===----------------------------------------------------------------------===// 591 592let SubtargetPredicate = isGFX11Plus in 593defm V_CNDMASK_B16 : VOP2eInst <"v_cndmask_b16", VOP2e_I16_I16_I16_I1>; 594defm V_CNDMASK_B32 : VOP2eInst_VOPD <"v_cndmask_b32", VOP2e_I32_I32_I32_I1, 0x9, "v_cndmask_b32">; 595let SubtargetPredicate = HasMadMacF32Insts, isReMaterializable = 1 in 596def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, []>; 597 598let isCommutable = 1 in { 599let isReMaterializable = 1 in { 600defm V_ADD_F32 : VOP2Inst_VOPD <"v_add_f32", VOP_F32_F32_F32, 0x4, "v_add_f32", any_fadd>; 601defm V_SUB_F32 : VOP2Inst_VOPD <"v_sub_f32", VOP_F32_F32_F32, 0x5, "v_sub_f32", any_fsub>; 602defm V_SUBREV_F32 : VOP2Inst_VOPD <"v_subrev_f32", VOP_F32_F32_F32, 0x6, "v_subrev_f32", null_frag, "v_sub_f32">; 603defm V_MUL_LEGACY_F32 : VOP2Inst_VOPD <"v_mul_legacy_f32", VOP_F32_F32_F32, 0x7, "v_mul_dx9_zero_f32", AMDGPUfmul_legacy>; 604defm V_MUL_F32 : VOP2Inst_VOPD <"v_mul_f32", VOP_F32_F32_F32, 0x3, "v_mul_f32", any_fmul>; 605defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32_ARITH, AMDGPUmul_i24>; 606defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_I32_I32_I32, AMDGPUmulhi_i24>; 607defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32_ARITH, AMDGPUmul_u24>; 608defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_I32_I32_I32, AMDGPUmulhi_u24>; 609defm V_MIN_F32 : VOP2Inst_VOPD <"v_min_f32", VOP_F32_F32_F32, 0xb, "v_min_f32", fminnum_like>; 610defm V_MAX_F32 : VOP2Inst_VOPD <"v_max_f32", VOP_F32_F32_F32, 0xa, "v_max_f32", fmaxnum_like>; 611defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smin>; 612defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smax>; 613defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umin>; 614defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umax>; 615defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, clshr_rev_32, "v_lshr_b32">; 616defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, cashr_rev_32, "v_ashr_i32">; 617defm V_LSHLREV_B32 : VOP2Inst_VOPD <"v_lshlrev_b32", VOP_I32_I32_I32, 0x11, "v_lshlrev_b32", clshl_rev_32, "v_lshl_b32">; 618defm V_AND_B32 : VOP2Inst_VOPD <"v_and_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, 0x12, "v_and_b32", and>; 619defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, or>; 620defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, xor>; 621} // End isReMaterializable = 1 622 623let mayRaiseFPException = 0 in { 624let OtherPredicates = [HasMadMacF32Insts] in { 625let Constraints = "$vdst = $src2", DisableEncoding="$src2", 626 isConvertibleToThreeAddress = 1 in { 627defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>; 628 629let SubtargetPredicate = isGFX6GFX7GFX10 in 630defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_MAC_LEGACY_F32>; 631} // End Constraints = "$vdst = $src2", DisableEncoding="$src2", 632 // isConvertibleToThreeAddress = 1 633 634let isReMaterializable = 1 in 635def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32, []>; 636} // End OtherPredicates = [HasMadMacF32Insts] 637} // End mayRaiseFPException = 0 638 639// No patterns so that the scalar instructions are always selected. 640// The scalar versions will be replaced with vector when needed later. 641defm V_ADD_CO_U32 : VOP2bInst <"v_add_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_add_co_u32", 1>; 642defm V_SUB_CO_U32 : VOP2bInst <"v_sub_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>; 643defm V_SUBREV_CO_U32 : VOP2bInst <"v_subrev_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>; 644defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_addc_u32", 1>; 645defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>; 646defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>; 647 648 649let SubtargetPredicate = HasAddNoCarryInsts, isReMaterializable = 1 in { 650defm V_ADD_U32 : VOP2Inst_VOPD <"v_add_u32", VOP_I32_I32_I32_ARITH, 0x10, "v_add_nc_u32", null_frag, "v_add_u32", 1>; 651defm V_SUB_U32 : VOP2Inst <"v_sub_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>; 652defm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>; 653} 654 655} // End isCommutable = 1 656 657// These are special and do not read the exec mask. 658let isConvergent = 1, Uses = []<Register> in { 659def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE, 660 [(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))]>; 661 662let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in { 663def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE, 664 [(set i32:$vdst, (int_amdgcn_writelane i32:$src0, i32:$src1, i32:$vdst_in))]>; 665} // End $vdst = $vdst_in, DisableEncoding $vdst_in 666} // End isConvergent = 1 667 668let isReMaterializable = 1 in { 669defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_I32_I32_I32>; 670defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_I32_I32_I32, add_ctpop>; 671defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_I32_I32_I32, int_amdgcn_mbcnt_lo>; 672defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_I32_I32_I32, int_amdgcn_mbcnt_hi>; 673defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_F32_F32_I32, AMDGPUldexp>; 674 675let ReadsModeReg = 0, mayRaiseFPException = 0 in { 676defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_V2I16_F32_F32, AMDGPUpknorm_i16_f32>; 677defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_V2I16_F32_F32, AMDGPUpknorm_u16_f32>; 678} 679 680defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_V2F16_F32_F32, AMDGPUpkrtz_f16_f32>; 681defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_V2I16_I32_I32, AMDGPUpk_u16_u32>; 682defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_V2I16_I32_I32, AMDGPUpk_i16_i32>; 683 684 685let SubtargetPredicate = isGFX6GFX7 in { 686defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>; 687defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>; 688} // End SubtargetPredicate = isGFX6GFX7 689 690let isCommutable = 1 in { 691let SubtargetPredicate = isGFX6GFX7 in { 692defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, csrl_32>; 693defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, csra_32>; 694defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, cshl_32>; 695} // End SubtargetPredicate = isGFX6GFX7 696} // End isCommutable = 1 697} // End isReMaterializable = 1 698 699defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_NO_EXT<VOP_I32_F32_I32>>; // TODO: set "Uses = dst" 700 701class DivergentBinOp<SDPatternOperator Op, VOP_Pseudo Inst> : 702 GCNPat< 703 (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1), 704 !if(!cast<Commutable_REV>(Inst).IsOrig, 705 (Inst $src0, $src1), 706 (Inst $src1, $src0) 707 ) 708 >; 709 710class DivergentClampingBinOp<SDPatternOperator Op, VOP_Pseudo Inst> : 711 GCNPat< 712 (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1), 713 !if(!cast<Commutable_REV>(Inst).IsOrig, 714 (Inst $src0, $src1, 0), 715 (Inst $src1, $src0, 0) 716 ) 717 >; 718 719def : DivergentBinOp<csrl_32, V_LSHRREV_B32_e64>; 720def : DivergentBinOp<csra_32, V_ASHRREV_I32_e64>; 721def : DivergentBinOp<cshl_32, V_LSHLREV_B32_e64>; 722 723let SubtargetPredicate = HasAddNoCarryInsts in { 724 def : DivergentClampingBinOp<add, V_ADD_U32_e64>; 725 def : DivergentClampingBinOp<sub, V_SUB_U32_e64>; 726} 727 728let SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] in { 729def : DivergentClampingBinOp<add, V_ADD_CO_U32_e64>; 730def : DivergentClampingBinOp<sub, V_SUB_CO_U32_e64>; 731} 732 733def : DivergentBinOp<adde, V_ADDC_U32_e32>; 734def : DivergentBinOp<sube, V_SUBB_U32_e32>; 735 736class divergent_i64_BinOp <SDPatternOperator Op, Instruction Inst> : 737 GCNPat< 738 (getDivergentFrag<Op>.ret i64:$src0, i64:$src1), 739 (REG_SEQUENCE VReg_64, 740 (Inst 741 (i32 (EXTRACT_SUBREG $src0, sub0)), 742 (i32 (EXTRACT_SUBREG $src1, sub0)) 743 ), sub0, 744 (Inst 745 (i32 (EXTRACT_SUBREG $src0, sub1)), 746 (i32 (EXTRACT_SUBREG $src1, sub1)) 747 ), sub1 748 ) 749 >; 750 751def : divergent_i64_BinOp <and, V_AND_B32_e64>; 752def : divergent_i64_BinOp <or, V_OR_B32_e64>; 753def : divergent_i64_BinOp <xor, V_XOR_B32_e64>; 754 755 756let SubtargetPredicate = Has16BitInsts in { 757 758let FPDPRounding = 1 in { 759def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16, [], "">; 760defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>; 761} // End FPDPRounding = 1 762 763defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16, clshl_rev_16>; 764defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16, clshr_rev_16>; 765defm V_ASHRREV_I16 : VOP2Inst <"v_ashrrev_i16", VOP_I16_I16_I16, cashr_rev_16>; 766 767let isCommutable = 1 in { 768let FPDPRounding = 1 in { 769defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, any_fadd>; 770defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, any_fsub>; 771defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">; 772defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, any_fmul>; 773 774let mayRaiseFPException = 0 in { 775def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">; 776} 777 778} // End FPDPRounding = 1 779defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16, mul>; 780defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum_like>; 781defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum_like>; 782defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16, umax>; 783defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16, smax>; 784defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16, umin>; 785defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16, smin>; 786 787let SubtargetPredicate = isGFX8GFX9 in { 788 defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16_ARITH, add>; 789 defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16_ARITH, sub>; 790 defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16_ARITH, null_frag, "v_sub_u16">; 791} 792 793let Constraints = "$vdst = $src2", DisableEncoding="$src2", 794 isConvertibleToThreeAddress = 1 in { 795defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>; 796} 797} // End isCommutable = 1 798 799} // End SubtargetPredicate = Has16BitInsts 800 801let SubtargetPredicate = HasDLInsts in { 802 803let isReMaterializable = 1 in 804defm V_XNOR_B32 : VOP2Inst <"v_xnor_b32", VOP_I32_I32_I32, xnor>; 805 806def : GCNPat< 807 (i32 (DivergentUnaryFrag<not> (xor_oneuse i32:$src0, i32:$src1))), 808 (i32 (V_XNOR_B32_e64 $src0, $src1)) 809>; 810 811def : GCNPat< 812 (i32 (DivergentBinFrag<xor_oneuse> (not i32:$src0), i32:$src1)), 813 (i32 (V_XNOR_B32_e64 $src0, $src1)) 814>; 815 816def : GCNPat< 817 (i64 (DivergentUnaryFrag<not> (xor_oneuse i64:$src0, i64:$src1))), 818 (REG_SEQUENCE VReg_64, (i32 (V_XNOR_B32_e64 819 (i32 (EXTRACT_SUBREG $src0, sub0)), 820 (i32 (EXTRACT_SUBREG $src1, sub0)))), sub0, 821 (i32 (V_XNOR_B32_e64 822 (i32 (EXTRACT_SUBREG $src0, sub1)), 823 (i32 (EXTRACT_SUBREG $src1, sub1)))), sub1) 824>; 825 826def : GCNPat< 827 (i64 (DivergentBinFrag<xor_oneuse> (not i64:$src0), i64:$src1)), 828 (REG_SEQUENCE VReg_64, (i32 (V_XNOR_B32_e64 829 (i32 (EXTRACT_SUBREG $src0, sub0)), 830 (i32 (EXTRACT_SUBREG $src1, sub0)))), sub0, 831 (i32 (V_XNOR_B32_e64 832 (i32 (EXTRACT_SUBREG $src0, sub1)), 833 (i32 (EXTRACT_SUBREG $src1, sub1)))), sub1) 834>; 835 836let Constraints = "$vdst = $src2", 837 DisableEncoding = "$src2", 838 isConvertibleToThreeAddress = 1, 839 isCommutable = 1 in 840defm V_FMAC_F32 : VOP2Inst_VOPD <"v_fmac_f32", VOP_MAC_F32, 0x0, "v_fmac_f32">; 841 842} // End SubtargetPredicate = HasDLInsts 843 844let SubtargetPredicate = HasFmaLegacy32 in { 845 846let Constraints = "$vdst = $src2", 847 DisableEncoding = "$src2", 848 isConvertibleToThreeAddress = 1, 849 isCommutable = 1 in 850defm V_FMAC_LEGACY_F32 : VOP2Inst <"v_fmac_legacy_f32", VOP_MAC_LEGACY_F32>; 851 852} // End SubtargetPredicate = HasFmaLegacy32 853 854let SubtargetPredicate = isGFX90APlus, 855 Constraints = "$vdst = $src2", 856 DisableEncoding="$src2", 857 isConvertibleToThreeAddress = 1, 858 isCommutable = 1, 859 SchedRW = [WriteDoubleAdd] in 860defm V_FMAC_F64 : VOP2Inst <"v_fmac_f64", VOP_MAC_F64>; 861 862let Constraints = "$vdst = $src2", 863 DisableEncoding="$src2", 864 isConvertibleToThreeAddress = 1, 865 isCommutable = 1, 866 IsDOT = 1 in { 867 let SubtargetPredicate = HasDot5Insts in 868 defm V_DOT2C_F32_F16 : VOP2Inst_VOPD<"v_dot2c_f32_f16", VOP_DOT_ACC_F32_V2F16, 0xc, "v_dot2acc_f32_f16">; 869 let SubtargetPredicate = HasDot6Insts in 870 defm V_DOT4C_I32_I8 : VOP2Inst<"v_dot4c_i32_i8", VOP_DOT_ACC_I32_I32>; 871 872 let SubtargetPredicate = HasDot4Insts in 873 defm V_DOT2C_I32_I16 : VOP2Inst<"v_dot2c_i32_i16", VOP_DOT_ACC_I32_I32>; 874 let SubtargetPredicate = HasDot3Insts in 875 defm V_DOT8C_I32_I4 : VOP2Inst<"v_dot8c_i32_i4", VOP_DOT_ACC_I32_I32>; 876} 877 878let AddedComplexity = 30 in { 879 def : GCNPat< 880 (f32 (AMDGPUfdot2 v2f16:$src0, v2f16:$src1, f32:$src2, (i1 DSTCLAMP.NONE))), 881 (f32 (V_DOT2C_F32_F16_e32 $src0, $src1, $src2)) 882 > { 883 let SubtargetPredicate = HasDot5Insts; 884 } 885 def : GCNPat< 886 (i32 (int_amdgcn_sdot4 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))), 887 (i32 (V_DOT4C_I32_I8_e32 $src0, $src1, $src2)) 888 > { 889 let SubtargetPredicate = HasDot6Insts; 890 } 891 def : GCNPat< 892 (i32 (int_amdgcn_sdot2 v2i16:$src0, v2i16:$src1, i32:$src2, (i1 DSTCLAMP.NONE))), 893 (i32 (V_DOT2C_I32_I16_e32 $src0, $src1, $src2)) 894 > { 895 let SubtargetPredicate = HasDot4Insts; 896 } 897 def : GCNPat< 898 (i32 (int_amdgcn_sdot8 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))), 899 (i32 (V_DOT8C_I32_I4_e32 $src0, $src1, $src2)) 900 > { 901 let SubtargetPredicate = HasDot3Insts; 902 } 903} // End AddedComplexity = 30 904 905let SubtargetPredicate = HasFmaakFmamkF32Insts, isReMaterializable = 1 in { 906def V_FMAMK_F32 : VOP2_Pseudo<"v_fmamk_f32", VOP_MADMK_F32, [], "">, VOPD_Component<0x2, "v_fmamk_f32">; 907 908let isCommutable = 1 in 909def V_FMAAK_F32 : VOP2_Pseudo<"v_fmaak_f32", VOP_MADAK_F32, [], "">, VOPD_Component<0x1, "v_fmaak_f32">; 910} 911 912let SubtargetPredicate = isGFX10Plus in { 913 914let FPDPRounding = 1 in { 915def V_FMAMK_F16 : VOP2_Pseudo <"v_fmamk_f16", VOP_MADMK_F16, [], "">; 916 917let isCommutable = 1 in 918def V_FMAAK_F16 : VOP2_Pseudo <"v_fmaak_f16", VOP_MADAK_F16, [], "">; 919} // End FPDPRounding = 1 920 921let Constraints = "$vdst = $src2", 922 DisableEncoding="$src2", 923 isConvertibleToThreeAddress = 1, 924 isCommutable = 1 in { 925defm V_FMAC_F16 : VOP2Inst <"v_fmac_f16", VOP_MAC_F16>; 926} 927 928} // End SubtargetPredicate = isGFX10Plus 929 930let SubtargetPredicate = HasPkFmacF16Inst in { 931defm V_PK_FMAC_F16 : VOP2Inst<"v_pk_fmac_f16", VOP_V2F16_V2F16_V2F16>; 932} // End SubtargetPredicate = HasPkFmacF16Inst 933 934// Note: 16-bit instructions produce a 0 result in the high 16-bits 935// on GFX8 and GFX9 and preserve high 16 bits on GFX10+ 936multiclass Arithmetic_i16_0Hi_Pats <SDPatternOperator op, Instruction inst> { 937 938def : GCNPat< 939 (i32 (zext (op i16:$src0, i16:$src1))), 940 (inst VSrc_b16:$src0, VSrc_b16:$src1) 941>; 942 943def : GCNPat< 944 (i64 (zext (op i16:$src0, i16:$src1))), 945 (REG_SEQUENCE VReg_64, 946 (inst $src0, $src1), sub0, 947 (V_MOV_B32_e32 (i32 0)), sub1) 948>; 949} 950 951class ZExt_i16_i1_Pat <SDNode ext> : GCNPat < 952 (i16 (ext i1:$src)), 953 (V_CNDMASK_B32_e64 (i32 0/*src0mod*/), (i32 0/*src0*/), 954 (i32 0/*src1mod*/), (i32 1/*src1*/), 955 $src) 956>; 957 958foreach vt = [i16, v2i16] in { 959def : GCNPat < 960 (and vt:$src0, vt:$src1), 961 (V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1) 962>; 963 964def : GCNPat < 965 (or vt:$src0, vt:$src1), 966 (V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1) 967>; 968 969def : GCNPat < 970 (xor vt:$src0, vt:$src1), 971 (V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1) 972>; 973} 974 975let Predicates = [Has16BitInsts, isGFX8GFX9] in { 976 977// Undo sub x, c -> add x, -c canonicalization since c is more likely 978// an inline immediate than -c. 979// TODO: Also do for 64-bit. 980def : GCNPat< 981 (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)), 982 (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1) 983>; 984 985def : GCNPat< 986 (i32 (zext (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)))), 987 (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1) 988>; 989 990defm : Arithmetic_i16_0Hi_Pats<add, V_ADD_U16_e64>; 991defm : Arithmetic_i16_0Hi_Pats<mul, V_MUL_LO_U16_e64>; 992defm : Arithmetic_i16_0Hi_Pats<sub, V_SUB_U16_e64>; 993defm : Arithmetic_i16_0Hi_Pats<smin, V_MIN_I16_e64>; 994defm : Arithmetic_i16_0Hi_Pats<smax, V_MAX_I16_e64>; 995defm : Arithmetic_i16_0Hi_Pats<umin, V_MIN_U16_e64>; 996defm : Arithmetic_i16_0Hi_Pats<umax, V_MAX_U16_e64>; 997defm : Arithmetic_i16_0Hi_Pats<clshl_rev_16, V_LSHLREV_B16_e64>; 998defm : Arithmetic_i16_0Hi_Pats<clshr_rev_16, V_LSHRREV_B16_e64>; 999defm : Arithmetic_i16_0Hi_Pats<cashr_rev_16, V_ASHRREV_I16_e64>; 1000 1001} // End Predicates = [Has16BitInsts, isGFX8GFX9] 1002 1003let Predicates = [Has16BitInsts] in { 1004 1005def : ZExt_i16_i1_Pat<zext>; 1006def : ZExt_i16_i1_Pat<anyext>; 1007 1008def : GCNPat < 1009 (i16 (sext i1:$src)), 1010 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0), 1011 /*src1mod*/(i32 0), /*src1*/(i32 -1), $src) 1012>; 1013 1014} // End Predicates = [Has16BitInsts] 1015 1016 1017let SubtargetPredicate = HasIntClamp in { 1018// Set clamp bit for saturation. 1019def : VOPBinOpClampPat<uaddsat, V_ADD_CO_U32_e64, i32>; 1020def : VOPBinOpClampPat<usubsat, V_SUB_CO_U32_e64, i32>; 1021} 1022 1023let SubtargetPredicate = HasAddNoCarryInsts, OtherPredicates = [HasIntClamp] in { 1024let AddedComplexity = 1 in { // Prefer over form with carry-out. 1025def : VOPBinOpClampPat<uaddsat, V_ADD_U32_e64, i32>; 1026def : VOPBinOpClampPat<usubsat, V_SUB_U32_e64, i32>; 1027} 1028} 1029 1030let SubtargetPredicate = Has16BitInsts, OtherPredicates = [HasIntClamp] in { 1031def : VOPBinOpClampPat<uaddsat, V_ADD_U16_e64, i16>; 1032def : VOPBinOpClampPat<usubsat, V_SUB_U16_e64, i16>; 1033} 1034 1035let SubtargetPredicate = isGFX11Plus in { 1036 let isCommutable = 1 in { 1037 defm V_AND_B16 : VOP2Inst <"v_and_b16", VOP_I16_I16_I16, and>; 1038 defm V_OR_B16 : VOP2Inst <"v_or_b16", VOP_I16_I16_I16, or>; 1039 defm V_XOR_B16 : VOP2Inst <"v_xor_b16", VOP_I16_I16_I16, xor>; 1040 } // End isCommutable = 1 1041} // End SubtargetPredicate = isGFX11Plus 1042 1043//===----------------------------------------------------------------------===// 1044// DPP Encodings 1045//===----------------------------------------------------------------------===// 1046 1047class VOP2_DPP<bits<6> op, VOP2_DPP_Pseudo ps, 1048 string opName = ps.OpName, VOPProfile p = ps.Pfl, 1049 bit IsDPP16 = 0> : 1050 VOP_DPP<opName, p, IsDPP16> { 1051 let hasSideEffects = ps.hasSideEffects; 1052 let Defs = ps.Defs; 1053 let SchedRW = ps.SchedRW; 1054 let Uses = ps.Uses; 1055 1056 bits<8> vdst; 1057 bits<8> src1; 1058 let Inst{8-0} = 0xfa; 1059 let Inst{16-9} = !if(p.HasSrc1, src1{7-0}, 0); 1060 let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0); 1061 let Inst{30-25} = op; 1062 let Inst{31} = 0x0; 1063} 1064 1065class Base_VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps, 1066 string opName = ps.OpName, VOPProfile p = ps.Pfl> : 1067 VOP2_DPP<op, ps, opName, p, 1> { 1068 let AssemblerPredicate = HasDPP16; 1069 let SubtargetPredicate = HasDPP16; 1070 let OtherPredicates = ps.OtherPredicates; 1071} 1072 1073class VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps, int subtarget, 1074 string opName = ps.OpName, VOPProfile p = ps.Pfl> : 1075 Base_VOP2_DPP16<op, ps, opName, p>, 1076 SIMCInstr <ps.PseudoInstr, subtarget>; 1077 1078class VOP2_DPP8<bits<6> op, VOP2_Pseudo ps, 1079 VOPProfile p = ps.Pfl> : 1080 VOP_DPP8<ps.OpName, p> { 1081 let hasSideEffects = ps.hasSideEffects; 1082 let Defs = ps.Defs; 1083 let SchedRW = ps.SchedRW; 1084 let Uses = ps.Uses; 1085 1086 bits<8> vdst; 1087 bits<8> src1; 1088 1089 let Inst{8-0} = fi; 1090 let Inst{16-9} = !if(p.HasSrc1, src1{7-0}, 0); 1091 let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0); 1092 let Inst{30-25} = op; 1093 let Inst{31} = 0x0; 1094 1095 let OtherPredicates = ps.OtherPredicates; 1096} 1097 1098//===----------------------------------------------------------------------===// 1099// GFX11. 1100//===----------------------------------------------------------------------===// 1101 1102let AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" in { 1103 //===------------------------------- VOP2 -------------------------------===// 1104 multiclass VOP2Only_Real_MADK_gfx11<bits<6> op> { 1105 def _gfx11 : 1106 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX11>, 1107 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 1108 } 1109 multiclass VOP2_Real_e32_gfx11<bits<6> op> { 1110 def _e32_gfx11 : 1111 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX11>, 1112 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 1113 } 1114 multiclass VOP2Only_Real_e32_gfx11<bits<6> op> { 1115 let IsSingle = 1 in 1116 defm NAME: VOP2_Real_e32_gfx11<op>; 1117 } 1118 multiclass VOP2_Real_e64_gfx11<bits<6> op> { 1119 def _e64_gfx11 : 1120 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX11>, 1121 VOP3e_gfx11<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1122 } 1123 multiclass VOP2_Real_dpp_gfx11<bits<6> op> { 1124 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in 1125 def _dpp_gfx11 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX11> { 1126 let DecoderNamespace = "DPPGFX11"; 1127 } 1128 } 1129 multiclass VOP2_Real_dpp8_gfx11<bits<6> op> { 1130 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in 1131 def _dpp8_gfx11 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(NAME#"_e32")> { 1132 let DecoderNamespace = "DPP8GFX11"; 1133 } 1134 } 1135 1136 //===------------------------- VOP2 (with name) -------------------------===// 1137 multiclass VOP2_Real_e32_with_name_gfx11<bits<6> op, string opName, 1138 string asmName, bit single = 0> { 1139 defvar ps = !cast<VOP2_Pseudo>(opName#"_e32"); 1140 def _e32_gfx11 : 1141 VOP2_Real<ps, SIEncodingFamily.GFX11, asmName>, 1142 VOP2e<op{5-0}, ps.Pfl>, 1143 MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX11Plus]> { 1144 let AsmString = asmName # ps.AsmOperands; 1145 let IsSingle = single; 1146 } 1147 } 1148 multiclass VOP2_Real_e64_with_name_gfx11<bits<6> op, string opName, 1149 string asmName> { 1150 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1151 def _e64_gfx11 : 1152 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1153 VOP3e_gfx11<{0, 1, 0, 0, op{5-0}}, ps.Pfl>, 1154 MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX11Plus]> { 1155 let AsmString = asmName # ps.AsmOperands; 1156 } 1157 } 1158 1159 multiclass VOP2_Real_dpp_with_name_gfx11<bits<6> op, string opName, 1160 string asmName> { 1161 defvar ps = !cast<VOP2_Pseudo>(opName#"_e32"); 1162 foreach _ = BoolToList<ps.Pfl.HasExtDPP>.ret in 1163 def _dpp_gfx11 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), 1164 SIEncodingFamily.GFX11> { 1165 let AsmString = asmName # ps.Pfl.AsmDPP16; 1166 let DecoderNamespace = "DPPGFX11"; 1167 } 1168 } 1169 multiclass VOP2_Real_dpp8_with_name_gfx11<bits<6> op, string opName, 1170 string asmName> { 1171 defvar ps = !cast<VOP2_Pseudo>(opName#"_e32"); 1172 foreach _ = BoolToList<ps.Pfl.HasExtDPP>.ret in 1173 def _dpp8_gfx11 : VOP2_DPP8<op, ps> { 1174 let AsmString = asmName # ps.Pfl.AsmDPP8; 1175 let DecoderNamespace = "DPP8GFX11"; 1176 } 1177 } 1178 1179 //===------------------------------ VOP2be ------------------------------===// 1180 multiclass VOP2be_Real_e32_gfx11<bits<6> op, string opName, string asmName> { 1181 defvar ps = !cast<VOP2_Pseudo>(opName#"_e32"); 1182 def _e32_gfx11 : 1183 VOP2_Real<ps, SIEncodingFamily.GFX11>, 1184 VOP2e<op{5-0}, ps.Pfl> { 1185 let AsmString = asmName # !subst(", vcc", "", ps.AsmOperands); 1186 } 1187 } 1188 multiclass VOP2be_Real_dpp_gfx11<bits<6> op, string opName, string asmName> { 1189 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1190 def _dpp_gfx11 : 1191 VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), SIEncodingFamily.GFX11, asmName> { 1192 string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16; 1193 let AsmString = asmName # !subst(", vcc", "", AsmDPP); 1194 let DecoderNamespace = "DPPGFX11"; 1195 } 1196 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1197 def _dpp_w32_gfx11 : 1198 Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> { 1199 string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16; 1200 let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP); 1201 let isAsmParserOnly = 1; 1202 let WaveSizePredicate = isWave32; 1203 } 1204 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1205 def _dpp_w64_gfx11 : 1206 Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> { 1207 string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16; 1208 let AsmString = asmName # AsmDPP; 1209 let isAsmParserOnly = 1; 1210 let WaveSizePredicate = isWave64; 1211 } 1212 } 1213 multiclass VOP2be_Real_dpp8_gfx11<bits<6> op, string opName, string asmName> { 1214 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1215 def _dpp8_gfx11 : 1216 VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> { 1217 string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8; 1218 let AsmString = asmName # !subst(", vcc", "", AsmDPP8); 1219 let DecoderNamespace = "DPP8GFX11"; 1220 } 1221 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1222 def _dpp8_w32_gfx11 : 1223 VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> { 1224 string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8; 1225 let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8); 1226 let isAsmParserOnly = 1; 1227 let WaveSizePredicate = isWave32; 1228 } 1229 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1230 def _dpp8_w64_gfx11 : 1231 VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> { 1232 string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8; 1233 let AsmString = asmName # AsmDPP8; 1234 let isAsmParserOnly = 1; 1235 let WaveSizePredicate = isWave64; 1236 } 1237 } 1238 1239} // End AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" 1240 1241// We don't want to override separate decoderNamespaces within these 1242multiclass VOP2_Realtriple_e64_gfx11<bits<6> op> { 1243 defm NAME : VOP3_Realtriple_gfx11<{0, 1, 0, 0, op{5-0}}, /*isSingle=*/ 0, NAME> ; 1244} 1245multiclass VOP2_Realtriple_e64_with_name_gfx11<bits<6> op, string opName, 1246 string asmName> { 1247 defm NAME : VOP3_Realtriple_with_name_gfx11<{0, 1, 0, 0, op{5-0}}, opName, asmName> ; 1248} 1249 1250multiclass VOP2be_Real_gfx11<bits<6> op, string opName, string asmName> : 1251 VOP2be_Real_e32_gfx11<op, opName, asmName>, 1252 VOP3be_Realtriple_gfx11<{0, 1, 0, 0, op{5-0}}, /*isSingle=*/ 0, opName, asmName>, 1253 VOP2be_Real_dpp_gfx11<op, opName, asmName>, 1254 VOP2be_Real_dpp8_gfx11<op, opName, asmName>; 1255 1256// Only for CNDMASK 1257multiclass VOP2e_Real_gfx11<bits<6> op, string opName, string asmName> : 1258 VOP2_Real_e32_gfx11<op>, 1259 VOP2_Realtriple_e64_gfx11<op>, 1260 VOP2be_Real_dpp_gfx11<op, opName, asmName>, 1261 VOP2be_Real_dpp8_gfx11<op, opName, asmName>; 1262 1263multiclass VOP2Only_Real_gfx11<bits<6> op> : 1264 VOP2Only_Real_e32_gfx11<op>, 1265 VOP2_Real_dpp_gfx11<op>, 1266 VOP2_Real_dpp8_gfx11<op>; 1267 1268multiclass VOP2_Real_NO_VOP3_gfx11<bits<6> op> : 1269 VOP2_Real_e32_gfx11<op>, VOP2_Real_dpp_gfx11<op>, VOP2_Real_dpp8_gfx11<op>; 1270 1271multiclass VOP2_Real_FULL_gfx11<bits<6> op> : 1272 VOP2_Realtriple_e64_gfx11<op>, VOP2_Real_NO_VOP3_gfx11<op>; 1273 1274multiclass VOP2_Real_NO_VOP3_with_name_gfx11<bits<6> op, string opName, 1275 string asmName, bit isSingle = 0> : 1276 VOP2_Real_e32_with_name_gfx11<op, opName, asmName, isSingle>, 1277 VOP2_Real_dpp_with_name_gfx11<op, opName, asmName>, 1278 VOP2_Real_dpp8_with_name_gfx11<op, opName, asmName>; 1279 1280multiclass VOP2_Real_FULL_with_name_gfx11<bits<6> op, string opName, 1281 string asmName> : 1282 VOP2_Realtriple_e64_with_name_gfx11<op, opName, asmName>, 1283 VOP2_Real_NO_VOP3_with_name_gfx11<op, opName, asmName>; 1284 1285multiclass VOP2_Real_NO_DPP_gfx11<bits<6> op> : 1286 VOP2_Real_e32_gfx11<op>, VOP2_Real_e64_gfx11<op>; 1287 1288multiclass VOP2_Real_NO_DPP_with_name_gfx11<bits<6> op, string opName, 1289 string asmName> : 1290 VOP2_Real_e32_with_name_gfx11<op, opName, asmName>, 1291 VOP2_Real_e64_with_name_gfx11<op, opName, asmName>; 1292 1293defm V_CNDMASK_B32 : VOP2e_Real_gfx11<0x001, "V_CNDMASK_B32", 1294 "v_cndmask_b32">; 1295defm V_DOT2ACC_F32_F16 : VOP2_Real_NO_VOP3_with_name_gfx11<0x002, 1296 "V_DOT2C_F32_F16", "v_dot2acc_f32_f16", 1>; 1297defm V_FMAC_DX9_ZERO_F32 : VOP2_Real_NO_DPP_with_name_gfx11<0x006, 1298 "V_FMAC_LEGACY_F32", "v_fmac_dx9_zero_f32">; 1299defm V_MUL_DX9_ZERO_F32 : VOP2_Real_FULL_with_name_gfx11<0x007, 1300 "V_MUL_LEGACY_F32", "v_mul_dx9_zero_f32">; 1301defm V_LSHLREV_B32 : VOP2_Real_FULL_gfx11<0x018>; 1302defm V_LSHRREV_B32 : VOP2_Real_FULL_gfx11<0x019>; 1303defm V_ASHRREV_I32 : VOP2_Real_FULL_gfx11<0x01a>; 1304defm V_ADD_CO_CI_U32 : 1305 VOP2be_Real_gfx11<0x020, "V_ADDC_U32", "v_add_co_ci_u32">; 1306defm V_SUB_CO_CI_U32 : 1307 VOP2be_Real_gfx11<0x021, "V_SUBB_U32", "v_sub_co_ci_u32">; 1308defm V_SUBREV_CO_CI_U32 : 1309 VOP2be_Real_gfx11<0x022, "V_SUBBREV_U32", "v_subrev_co_ci_u32">; 1310 1311defm V_CVT_PK_RTZ_F16_F32 : VOP2_Real_FULL_with_name_gfx11<0x02f, 1312 "V_CVT_PKRTZ_F16_F32", "v_cvt_pk_rtz_f16_f32">; 1313defm V_PK_FMAC_F16 : VOP2Only_Real_gfx11<0x03c>; 1314 1315// VOP3 only. 1316defm V_CNDMASK_B16 : VOP3Only_Realtriple_gfx11<0x25d>; 1317defm V_LDEXP_F32 : VOP3Only_Realtriple_gfx11<0x31c>; 1318defm V_BFM_B32 : VOP3Only_Realtriple_gfx11<0x31d>; 1319defm V_BCNT_U32_B32 : VOP3Only_Realtriple_gfx11<0x31e>; 1320defm V_MBCNT_LO_U32_B32 : VOP3Only_Realtriple_gfx11<0x31f>; 1321defm V_MBCNT_HI_U32_B32 : VOP3Only_Realtriple_gfx11<0x320>; 1322defm V_CVT_PKNORM_I16_F32 : VOP3Only_Realtriple_gfx11<0x321>; 1323defm V_CVT_PKNORM_U16_F32 : VOP3Only_Realtriple_gfx11<0x322>; 1324defm V_CVT_PK_U16_U32 : VOP3Only_Realtriple_gfx11<0x323>; 1325defm V_CVT_PK_I16_I32 : VOP3Only_Realtriple_gfx11<0x324>; 1326defm V_ADD_CO_U32 : VOP3beOnly_Realtriple_gfx11<0x300>; 1327defm V_SUB_CO_U32 : VOP3beOnly_Realtriple_gfx11<0x301>; 1328defm V_SUBREV_CO_U32 : VOP3beOnly_Realtriple_gfx11<0x302>; 1329 1330let SubtargetPredicate = isGFX11Plus in { 1331 defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx11>; 1332 1333 defm : VOP2bInstAliases< 1334 V_ADDC_U32_e32, V_ADD_CO_CI_U32_e32_gfx11, "v_add_co_ci_u32">; 1335 defm : VOP2bInstAliases< 1336 V_SUBB_U32_e32, V_SUB_CO_CI_U32_e32_gfx11, "v_sub_co_ci_u32">; 1337 defm : VOP2bInstAliases< 1338 V_SUBBREV_U32_e32, V_SUBREV_CO_CI_U32_e32_gfx11, "v_subrev_co_ci_u32">; 1339} // End SubtargetPredicate = isGFX11Plus 1340 1341//===----------------------------------------------------------------------===// 1342// GFX10. 1343//===----------------------------------------------------------------------===// 1344 1345let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in { 1346 //===------------------------------- VOP2 -------------------------------===// 1347 multiclass VOP2Only_Real_MADK_gfx10<bits<6> op> { 1348 def _gfx10 : 1349 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX10>, 1350 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 1351 } 1352 multiclass VOP2Only_Real_MADK_gfx10_with_name<bits<6> op, string opName, 1353 string asmName> { 1354 def _gfx10 : 1355 VOP2_Real<!cast<VOP2_Pseudo>(opName), SIEncodingFamily.GFX10>, 1356 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> { 1357 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName); 1358 let AsmString = asmName # ps.AsmOperands; 1359 } 1360 } 1361 multiclass VOP2_Real_e32_gfx10<bits<6> op> { 1362 def _e32_gfx10 : 1363 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>, 1364 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 1365 } 1366 multiclass VOP2_Real_e64_gfx10<bits<6> op> { 1367 def _e64_gfx10 : 1368 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 1369 VOP3e_gfx10<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1370 } 1371 multiclass VOP2_Real_sdwa_gfx10<bits<6> op> { 1372 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in 1373 def _sdwa_gfx10 : 1374 VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 1375 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> { 1376 let DecoderNamespace = "SDWA10"; 1377 } 1378 } 1379 multiclass VOP2_Real_dpp_gfx10<bits<6> op> { 1380 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExt32BitDPP>.ret in 1381 def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX10> { 1382 let DecoderNamespace = "SDWA10"; 1383 } 1384 } 1385 multiclass VOP2_Real_dpp8_gfx10<bits<6> op> { 1386 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExt32BitDPP>.ret in 1387 def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(NAME#"_e32")> { 1388 let DecoderNamespace = "DPP8"; 1389 } 1390 } 1391 1392 //===------------------------- VOP2 (with name) -------------------------===// 1393 multiclass VOP2_Real_e32_gfx10_with_name<bits<6> op, string opName, 1394 string asmName> { 1395 def _e32_gfx10 : 1396 VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>, 1397 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> { 1398 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32"); 1399 let AsmString = asmName # ps.AsmOperands; 1400 } 1401 } 1402 multiclass VOP2_Real_e64_gfx10_with_name<bits<6> op, string opName, 1403 string asmName> { 1404 def _e64_gfx10 : 1405 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>, 1406 VOP3e_gfx10<{0, 1, 0, 0, op{5-0}}, 1407 !cast<VOP3_Pseudo>(opName#"_e64").Pfl> { 1408 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1409 let AsmString = asmName # ps.AsmOperands; 1410 } 1411 } 1412 let DecoderNamespace = "SDWA10" in { 1413 multiclass VOP2_Real_sdwa_gfx10_with_name<bits<6> op, string opName, 1414 string asmName> { 1415 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in 1416 def _sdwa_gfx10 : 1417 VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>, 1418 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> { 1419 VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa"); 1420 let AsmString = asmName # ps.AsmOperands; 1421 } 1422 } 1423 multiclass VOP2_Real_dpp_gfx10_with_name<bits<6> op, string opName, 1424 string asmName> { 1425 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP>.ret in 1426 def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), SIEncodingFamily.GFX10> { 1427 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32"); 1428 let AsmString = asmName # ps.Pfl.AsmDPP16; 1429 } 1430 } 1431 multiclass VOP2_Real_dpp8_gfx10_with_name<bits<6> op, string opName, 1432 string asmName> { 1433 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP>.ret in 1434 def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> { 1435 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32"); 1436 let AsmString = asmName # ps.Pfl.AsmDPP8; 1437 let DecoderNamespace = "DPP8"; 1438 } 1439 } 1440 } // End DecoderNamespace = "SDWA10" 1441 1442 //===------------------------------ VOP2be ------------------------------===// 1443 multiclass VOP2be_Real_e32_gfx10<bits<6> op, string opName, string asmName> { 1444 def _e32_gfx10 : 1445 VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>, 1446 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> { 1447 VOP2_Pseudo Ps = !cast<VOP2_Pseudo>(opName#"_e32"); 1448 let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands); 1449 } 1450 } 1451 multiclass VOP2be_Real_e64_gfx10<bits<6> op, string opName, string asmName> { 1452 def _e64_gfx10 : 1453 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>, 1454 VOP3be_gfx10<{0, 1, 0, 0, op{5-0}}, 1455 !cast<VOP3_Pseudo>(opName#"_e64").Pfl> { 1456 VOP3_Pseudo Ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1457 let AsmString = asmName # Ps.AsmOperands; 1458 } 1459 } 1460 multiclass VOP2be_Real_sdwa_gfx10<bits<6> op, string opName, string asmName> { 1461 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in 1462 def _sdwa_gfx10 : 1463 VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>, 1464 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> { 1465 VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa"); 1466 let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands); 1467 let DecoderNamespace = "SDWA10"; 1468 } 1469 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in 1470 def _sdwa_w32_gfx10 : 1471 Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>, 1472 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> { 1473 VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa"); 1474 let AsmString = asmName # !subst("vcc", "vcc_lo", Ps.AsmOperands); 1475 let isAsmParserOnly = 1; 1476 let DecoderNamespace = "SDWA10"; 1477 let WaveSizePredicate = isWave32; 1478 } 1479 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in 1480 def _sdwa_w64_gfx10 : 1481 Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>, 1482 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> { 1483 VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa"); 1484 let AsmString = asmName # Ps.AsmOperands; 1485 let isAsmParserOnly = 1; 1486 let DecoderNamespace = "SDWA10"; 1487 let WaveSizePredicate = isWave64; 1488 } 1489 } 1490 multiclass VOP2be_Real_dpp_gfx10<bits<6> op, string opName, string asmName> { 1491 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP>.ret in 1492 def _dpp_gfx10 : 1493 VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), SIEncodingFamily.GFX10, asmName> { 1494 string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16; 1495 let AsmString = asmName # !subst(", vcc", "", AsmDPP); 1496 let DecoderNamespace = "SDWA10"; 1497 } 1498 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP>.ret in 1499 def _dpp_w32_gfx10 : 1500 Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> { 1501 string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16; 1502 let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP); 1503 let isAsmParserOnly = 1; 1504 let WaveSizePredicate = isWave32; 1505 } 1506 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP>.ret in 1507 def _dpp_w64_gfx10 : 1508 Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> { 1509 string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16; 1510 let AsmString = asmName # AsmDPP; 1511 let isAsmParserOnly = 1; 1512 let WaveSizePredicate = isWave64; 1513 } 1514 } 1515 multiclass VOP2be_Real_dpp8_gfx10<bits<6> op, string opName, string asmName> { 1516 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP>.ret in 1517 def _dpp8_gfx10 : 1518 VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> { 1519 string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8; 1520 let AsmString = asmName # !subst(", vcc", "", AsmDPP8); 1521 let DecoderNamespace = "DPP8"; 1522 } 1523 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP>.ret in 1524 def _dpp8_w32_gfx10 : 1525 VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> { 1526 string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8; 1527 let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8); 1528 let isAsmParserOnly = 1; 1529 let WaveSizePredicate = isWave32; 1530 } 1531 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP>.ret in 1532 def _dpp8_w64_gfx10 : 1533 VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> { 1534 string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8; 1535 let AsmString = asmName # AsmDPP8; 1536 let isAsmParserOnly = 1; 1537 let WaveSizePredicate = isWave64; 1538 } 1539 } 1540 1541 //===----------------------------- VOP3Only -----------------------------===// 1542 multiclass VOP3Only_Real_gfx10<bits<10> op> { 1543 def _e64_gfx10 : 1544 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 1545 VOP3e_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1546 let IsSingle = 1; 1547 } 1548 } 1549 1550 //===---------------------------- VOP3beOnly ----------------------------===// 1551 multiclass VOP3beOnly_Real_gfx10<bits<10> op> { 1552 def _e64_gfx10 : 1553 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 1554 VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1555 let IsSingle = 1; 1556 } 1557 } 1558} // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" 1559 1560multiclass VOP2Only_Real_MADK_gfx10_gfx11<bits<6> op> : 1561 VOP2Only_Real_MADK_gfx10<op>, VOP2Only_Real_MADK_gfx11<op>; 1562 1563multiclass VOP2be_Real_gfx10<bits<6> op, string opName, string asmName> : 1564 VOP2be_Real_e32_gfx10<op, opName, asmName>, 1565 VOP2be_Real_e64_gfx10<op, opName, asmName>, 1566 VOP2be_Real_sdwa_gfx10<op, opName, asmName>, 1567 VOP2be_Real_dpp_gfx10<op, opName, asmName>, 1568 VOP2be_Real_dpp8_gfx10<op, opName, asmName>; 1569 1570multiclass VOP2e_Real_gfx10<bits<6> op, string opName, string asmName> : 1571 VOP2_Real_e32_gfx10<op>, 1572 VOP2_Real_e64_gfx10<op>, 1573 VOP2be_Real_sdwa_gfx10<op, opName, asmName>, 1574 VOP2be_Real_dpp_gfx10<op, opName, asmName>, 1575 VOP2be_Real_dpp8_gfx10<op, opName, asmName>; 1576 1577multiclass VOP2_Real_gfx10<bits<6> op> : 1578 VOP2_Real_e32_gfx10<op>, VOP2_Real_e64_gfx10<op>, 1579 VOP2_Real_sdwa_gfx10<op>, VOP2_Real_dpp_gfx10<op>, VOP2_Real_dpp8_gfx10<op>; 1580 1581multiclass VOP2_Real_gfx10_gfx11<bits<6> op> : 1582 VOP2_Real_gfx10<op>, VOP2_Real_FULL_gfx11<op>; 1583 1584multiclass VOP2_Real_with_name_gfx10<bits<6> op, string opName, 1585 string asmName> : 1586 VOP2_Real_e32_gfx10_with_name<op, opName, asmName>, 1587 VOP2_Real_e64_gfx10_with_name<op, opName, asmName>, 1588 VOP2_Real_sdwa_gfx10_with_name<op, opName, asmName>, 1589 VOP2_Real_dpp_gfx10_with_name<op, opName, asmName>, 1590 VOP2_Real_dpp8_gfx10_with_name<op, opName, asmName>; 1591 1592multiclass VOP2_Real_with_name_gfx10_gfx11<bits<6> op, string opName, 1593 string asmName> : 1594 VOP2_Real_with_name_gfx10<op, opName, asmName>, 1595 VOP2_Real_FULL_with_name_gfx11<op, opName, asmName>; 1596 1597// NB: Same opcode as v_mac_legacy_f32 1598let DecoderNamespace = "GFX10_B" in 1599defm V_FMAC_LEGACY_F32 : VOP2_Real_gfx10<0x006>; 1600 1601defm V_XNOR_B32 : VOP2_Real_gfx10_gfx11<0x01e>; 1602defm V_FMAC_F32 : VOP2_Real_gfx10_gfx11<0x02b>; 1603defm V_FMAMK_F32 : VOP2Only_Real_MADK_gfx10_gfx11<0x02c>; 1604defm V_FMAAK_F32 : VOP2Only_Real_MADK_gfx10_gfx11<0x02d>; 1605defm V_ADD_F16 : VOP2_Real_gfx10_gfx11<0x032>; 1606defm V_SUB_F16 : VOP2_Real_gfx10_gfx11<0x033>; 1607defm V_SUBREV_F16 : VOP2_Real_gfx10_gfx11<0x034>; 1608defm V_MUL_F16 : VOP2_Real_gfx10_gfx11<0x035>; 1609defm V_FMAC_F16 : VOP2_Real_gfx10_gfx11<0x036>; 1610defm V_FMAMK_F16 : VOP2Only_Real_MADK_gfx10_gfx11<0x037>; 1611defm V_FMAAK_F16 : VOP2Only_Real_MADK_gfx10_gfx11<0x038>; 1612defm V_MAX_F16 : VOP2_Real_gfx10_gfx11<0x039>; 1613defm V_MIN_F16 : VOP2_Real_gfx10_gfx11<0x03a>; 1614defm V_LDEXP_F16 : VOP2_Real_gfx10_gfx11<0x03b>; 1615 1616let IsSingle = 1 in { 1617 defm V_PK_FMAC_F16 : VOP2_Real_e32_gfx10<0x03c>; 1618} 1619 1620// VOP2 no carry-in, carry-out. 1621defm V_ADD_NC_U32 : 1622 VOP2_Real_with_name_gfx10_gfx11<0x025, "V_ADD_U32", "v_add_nc_u32">; 1623defm V_SUB_NC_U32 : 1624 VOP2_Real_with_name_gfx10_gfx11<0x026, "V_SUB_U32", "v_sub_nc_u32">; 1625defm V_SUBREV_NC_U32 : 1626 VOP2_Real_with_name_gfx10_gfx11<0x027, "V_SUBREV_U32", "v_subrev_nc_u32">; 1627 1628// VOP2 carry-in, carry-out. 1629defm V_ADD_CO_CI_U32 : 1630 VOP2be_Real_gfx10<0x028, "V_ADDC_U32", "v_add_co_ci_u32">; 1631defm V_SUB_CO_CI_U32 : 1632 VOP2be_Real_gfx10<0x029, "V_SUBB_U32", "v_sub_co_ci_u32">; 1633defm V_SUBREV_CO_CI_U32 : 1634 VOP2be_Real_gfx10<0x02a, "V_SUBBREV_U32", "v_subrev_co_ci_u32">; 1635 1636defm V_CNDMASK_B32 : 1637 VOP2e_Real_gfx10<0x001, "V_CNDMASK_B32", "v_cndmask_b32">; 1638 1639// VOP3 only. 1640defm V_BFM_B32 : VOP3Only_Real_gfx10<0x363>; 1641defm V_BCNT_U32_B32 : VOP3Only_Real_gfx10<0x364>; 1642defm V_MBCNT_LO_U32_B32 : VOP3Only_Real_gfx10<0x365>; 1643defm V_MBCNT_HI_U32_B32 : VOP3Only_Real_gfx10<0x366>; 1644defm V_LDEXP_F32 : VOP3Only_Real_gfx10<0x362>; 1645defm V_CVT_PKNORM_I16_F32 : VOP3Only_Real_gfx10<0x368>; 1646defm V_CVT_PKNORM_U16_F32 : VOP3Only_Real_gfx10<0x369>; 1647defm V_CVT_PK_U16_U32 : VOP3Only_Real_gfx10<0x36a>; 1648defm V_CVT_PK_I16_I32 : VOP3Only_Real_gfx10<0x36b>; 1649 1650// VOP3 carry-out. 1651defm V_ADD_CO_U32 : VOP3beOnly_Real_gfx10<0x30f>; 1652defm V_SUB_CO_U32 : VOP3beOnly_Real_gfx10<0x310>; 1653defm V_SUBREV_CO_U32 : VOP3beOnly_Real_gfx10<0x319>; 1654 1655let SubtargetPredicate = isGFX10Only in { 1656 defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx10>; 1657 1658 defm : VOP2bInstAliases< 1659 V_ADDC_U32_e32, V_ADD_CO_CI_U32_e32_gfx10, "v_add_co_ci_u32">; 1660 defm : VOP2bInstAliases< 1661 V_SUBB_U32_e32, V_SUB_CO_CI_U32_e32_gfx10, "v_sub_co_ci_u32">; 1662 defm : VOP2bInstAliases< 1663 V_SUBBREV_U32_e32, V_SUBREV_CO_CI_U32_e32_gfx10, "v_subrev_co_ci_u32">; 1664} // End SubtargetPredicate = isGFX10Only 1665 1666//===----------------------------------------------------------------------===// 1667// GFX6, GFX7, GFX10, GFX11 1668//===----------------------------------------------------------------------===// 1669 1670class VOP2_DPPe <bits<6> op, VOP2_DPP_Pseudo ps, VOPProfile P = ps.Pfl> : 1671 VOP_DPPe <P> { 1672 bits<8> vdst; 1673 bits<8> src1; 1674 let Inst{8-0} = 0xfa; //dpp 1675 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 1676 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 1677 let Inst{30-25} = op; 1678 let Inst{31} = 0x0; //encoding 1679} 1680 1681let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in { 1682 multiclass VOP2_Lane_Real_gfx6_gfx7<bits<6> op> { 1683 def _gfx6_gfx7 : 1684 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>, 1685 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 1686 } 1687 multiclass VOP2Only_Real_MADK_gfx6_gfx7<bits<6> op> { 1688 def _gfx6_gfx7 : 1689 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>, 1690 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 1691 } 1692 multiclass VOP2_Real_e32_gfx6_gfx7<bits<6> op, string opName = NAME> { 1693 def _e32_gfx6_gfx7 : 1694 VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.SI>, 1695 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl>; 1696 } 1697 multiclass VOP2_Real_e64_gfx6_gfx7<bits<6> op, string opName = NAME> { 1698 def _e64_gfx6_gfx7 : 1699 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.SI>, 1700 VOP3e_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(opName#"_e64").Pfl>; 1701 } 1702 multiclass VOP2be_Real_e64_gfx6_gfx7<bits<6> op, string opName = NAME> { 1703 def _e64_gfx6_gfx7 : 1704 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.SI>, 1705 VOP3be_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(opName#"_e64").Pfl>; 1706 } 1707} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" 1708 1709multiclass VOP2Only_Real_MADK_gfx6_gfx7_gfx10<bits<6> op> : 1710 VOP2Only_Real_MADK_gfx6_gfx7<op>, VOP2Only_Real_MADK_gfx10<op>; 1711 1712multiclass VOP2_Real_gfx6_gfx7<bits<6> op> : 1713 VOP2_Real_e32_gfx6_gfx7<op>, VOP2_Real_e64_gfx6_gfx7<op>; 1714 1715multiclass VOP2_Real_gfx6_gfx7_gfx10<bits<6> op> : 1716 VOP2_Real_gfx6_gfx7<op>, VOP2_Real_gfx10<op>; 1717 1718multiclass VOP2_Real_gfx6_gfx7_gfx10_gfx11<bits<6> op> : 1719 VOP2_Real_gfx6_gfx7_gfx10<op>, VOP2_Real_FULL_gfx11<op>; 1720 1721multiclass VOP2be_Real_gfx6_gfx7<bits<6> op> : 1722 VOP2_Real_e32_gfx6_gfx7<op>, VOP2be_Real_e64_gfx6_gfx7<op>; 1723 1724multiclass VOP2be_Real_gfx6_gfx7_with_name<bits<6> op, 1725 string opName, string asmName> { 1726 defvar ps32 = !cast<VOP2_Pseudo>(opName#"_e32"); 1727 defvar ps64 = !cast<VOP3_Pseudo>(opName#"_e64"); 1728 1729 let AsmString = asmName # ps32.AsmOperands in { 1730 defm "" : VOP2_Real_e32_gfx6_gfx7<op, opName>; 1731 } 1732 1733 let AsmString = asmName # ps64.AsmOperands in { 1734 defm "" : VOP2be_Real_e64_gfx6_gfx7<op, opName>; 1735 } 1736} 1737 1738defm V_CNDMASK_B32 : VOP2_Real_gfx6_gfx7<0x000>; 1739defm V_MIN_LEGACY_F32 : VOP2_Real_gfx6_gfx7<0x00d>; 1740defm V_MAX_LEGACY_F32 : VOP2_Real_gfx6_gfx7<0x00e>; 1741defm V_LSHR_B32 : VOP2_Real_gfx6_gfx7<0x015>; 1742defm V_ASHR_I32 : VOP2_Real_gfx6_gfx7<0x017>; 1743defm V_LSHL_B32 : VOP2_Real_gfx6_gfx7<0x019>; 1744defm V_BFM_B32 : VOP2_Real_gfx6_gfx7<0x01e>; 1745defm V_BCNT_U32_B32 : VOP2_Real_gfx6_gfx7<0x022>; 1746defm V_MBCNT_LO_U32_B32 : VOP2_Real_gfx6_gfx7<0x023>; 1747defm V_MBCNT_HI_U32_B32 : VOP2_Real_gfx6_gfx7<0x024>; 1748defm V_LDEXP_F32 : VOP2_Real_gfx6_gfx7<0x02b>; 1749defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_gfx6_gfx7<0x02c>; 1750defm V_CVT_PKNORM_I16_F32 : VOP2_Real_gfx6_gfx7<0x02d>; 1751defm V_CVT_PKNORM_U16_F32 : VOP2_Real_gfx6_gfx7<0x02e>; 1752defm V_CVT_PK_U16_U32 : VOP2_Real_gfx6_gfx7<0x030>; 1753defm V_CVT_PK_I16_I32 : VOP2_Real_gfx6_gfx7<0x031>; 1754 1755// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in 1756// VI, but the VI instructions behave the same as the SI versions. 1757defm V_ADD_I32 : VOP2be_Real_gfx6_gfx7_with_name<0x025, "V_ADD_CO_U32", "v_add_i32">; 1758defm V_SUB_I32 : VOP2be_Real_gfx6_gfx7_with_name<0x026, "V_SUB_CO_U32", "v_sub_i32">; 1759defm V_SUBREV_I32 : VOP2be_Real_gfx6_gfx7_with_name<0x027, "V_SUBREV_CO_U32", "v_subrev_i32">; 1760defm V_ADDC_U32 : VOP2be_Real_gfx6_gfx7<0x028>; 1761defm V_SUBB_U32 : VOP2be_Real_gfx6_gfx7<0x029>; 1762defm V_SUBBREV_U32 : VOP2be_Real_gfx6_gfx7<0x02a>; 1763 1764defm V_READLANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x001>; 1765 1766let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in { 1767 defm V_WRITELANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x002>; 1768} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) 1769 1770let SubtargetPredicate = isGFX6GFX7 in { 1771 defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx6_gfx7>; 1772 defm : VOP2eInstAliases<V_ADD_CO_U32_e32, V_ADD_I32_e32_gfx6_gfx7>; 1773 defm : VOP2eInstAliases<V_SUB_CO_U32_e32, V_SUB_I32_e32_gfx6_gfx7>; 1774 defm : VOP2eInstAliases<V_SUBREV_CO_U32_e32, V_SUBREV_I32_e32_gfx6_gfx7>; 1775 1776 def : VOP2e64InstAlias<V_ADD_CO_U32_e64, V_ADD_I32_e64_gfx6_gfx7>; 1777 def : VOP2e64InstAlias<V_SUB_CO_U32_e64, V_SUB_I32_e64_gfx6_gfx7>; 1778 def : VOP2e64InstAlias<V_SUBREV_CO_U32_e64, V_SUBREV_I32_e64_gfx6_gfx7>; 1779} // End SubtargetPredicate = isGFX6GFX7 1780 1781defm V_ADD_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x003>; 1782defm V_SUB_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x004>; 1783defm V_SUBREV_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x005>; 1784defm V_MAC_LEGACY_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x006>; 1785defm V_MUL_LEGACY_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x007>; 1786defm V_MUL_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x008>; 1787defm V_MUL_I32_I24 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x009>; 1788defm V_MUL_HI_I32_I24 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x00a>; 1789defm V_MUL_U32_U24 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x00b>; 1790defm V_MUL_HI_U32_U24 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x00c>; 1791defm V_MIN_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x00f>; 1792defm V_MAX_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x010>; 1793defm V_MIN_I32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x011>; 1794defm V_MAX_I32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x012>; 1795defm V_MIN_U32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x013>; 1796defm V_MAX_U32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x014>; 1797defm V_LSHRREV_B32 : VOP2_Real_gfx6_gfx7_gfx10<0x016>; 1798defm V_ASHRREV_I32 : VOP2_Real_gfx6_gfx7_gfx10<0x018>; 1799defm V_LSHLREV_B32 : VOP2_Real_gfx6_gfx7_gfx10<0x01a>; 1800defm V_AND_B32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x01b>; 1801defm V_OR_B32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x01c>; 1802defm V_XOR_B32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x01d>; 1803defm V_MAC_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x01f>; 1804defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x02f>; 1805defm V_MADMK_F32 : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x020>; 1806defm V_MADAK_F32 : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x021>; 1807 1808//===----------------------------------------------------------------------===// 1809// GFX8, GFX9 (VI). 1810//===----------------------------------------------------------------------===// 1811 1812let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in { 1813 1814multiclass VOP2_Real_MADK_vi <bits<6> op> { 1815 def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>, 1816 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 1817} 1818 1819multiclass VOP2_Real_MADK_gfx940 <bits<6> op> { 1820 def _gfx940 : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX940>, 1821 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl> { 1822 let DecoderNamespace = "GFX9"; 1823 } 1824} 1825 1826multiclass VOP2_Real_e32_vi <bits<6> op> { 1827 def _e32_vi : 1828 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>, 1829 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 1830} 1831 1832multiclass VOP2_Real_e64_vi <bits<10> op> { 1833 def _e64_vi : 1834 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1835 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1836} 1837 1838multiclass VOP2_Real_e64only_vi <bits<10> op> { 1839 def _e64_vi : 1840 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1841 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1842 let IsSingle = 1; 1843 } 1844} 1845 1846multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> : 1847 VOP2_Real_e32_vi<op>, 1848 VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>; 1849 1850} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" 1851 1852multiclass VOP2_SDWA_Real <bits<6> op> { 1853 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA>.ret in 1854 def _sdwa_vi : 1855 VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 1856 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 1857} 1858 1859multiclass VOP2_SDWA9_Real <bits<6> op> { 1860 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in 1861 def _sdwa_gfx9 : 1862 VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 1863 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 1864} 1865 1866let AssemblerPredicate = isGFX8Only in { 1867 1868multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName> { 1869 def _e32_vi : 1870 VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.VI>, 1871 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> { 1872 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32"); 1873 let AsmString = AsmName # ps.AsmOperands; 1874 let DecoderNamespace = "GFX8"; 1875 } 1876 def _e64_vi : 1877 VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.VI>, 1878 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> { 1879 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64"); 1880 let AsmString = AsmName # ps.AsmOperands; 1881 let DecoderNamespace = "GFX8"; 1882 } 1883 foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA>.ret in 1884 def _sdwa_vi : 1885 VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>, 1886 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> { 1887 VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa"); 1888 let AsmString = AsmName # ps.AsmOperands; 1889 } 1890 foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in 1891 def _dpp_vi : 1892 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.VI>, 1893 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> { 1894 VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp"); 1895 let AsmString = AsmName # ps.AsmOperands; 1896 } 1897} 1898} 1899 1900let AssemblerPredicate = isGFX9Only in { 1901 1902multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> { 1903 def _e32_gfx9 : 1904 VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.GFX9>, 1905 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> { 1906 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32"); 1907 let AsmString = AsmName # ps.AsmOperands; 1908 let DecoderNamespace = "GFX9"; 1909 } 1910 def _e64_gfx9 : 1911 VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>, 1912 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> { 1913 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64"); 1914 let AsmString = AsmName # ps.AsmOperands; 1915 let DecoderNamespace = "GFX9"; 1916 } 1917 foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA9>.ret in 1918 def _sdwa_gfx9 : 1919 VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>, 1920 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> { 1921 VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa"); 1922 let AsmString = AsmName # ps.AsmOperands; 1923 } 1924 foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in 1925 def _dpp_gfx9 : 1926 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.GFX9>, 1927 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> { 1928 VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp"); 1929 let AsmString = AsmName # ps.AsmOperands; 1930 let DecoderNamespace = "SDWA9"; 1931 } 1932} 1933 1934multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> { 1935 def _e32_gfx9 : 1936 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX9>, 1937 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>{ 1938 let DecoderNamespace = "GFX9"; 1939 } 1940 def _e64_gfx9 : 1941 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>, 1942 VOP3e_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1943 let DecoderNamespace = "GFX9"; 1944 } 1945 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in 1946 def _sdwa_gfx9 : 1947 VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 1948 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> { 1949 } 1950 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in 1951 def _dpp_gfx9 : 1952 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>, 1953 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> { 1954 let DecoderNamespace = "SDWA9"; 1955 } 1956} 1957 1958} // AssemblerPredicate = isGFX9Only 1959 1960multiclass VOP2_Real_e32e64_vi <bits<6> op> : 1961 Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> { 1962 1963 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in 1964 def _dpp_vi : 1965 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.VI>, 1966 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>; 1967} 1968 1969defm V_CNDMASK_B32 : VOP2_Real_e32e64_vi <0x0>; 1970defm V_ADD_F32 : VOP2_Real_e32e64_vi <0x1>; 1971defm V_SUB_F32 : VOP2_Real_e32e64_vi <0x2>; 1972defm V_SUBREV_F32 : VOP2_Real_e32e64_vi <0x3>; 1973let AssemblerPredicate = isGCN3ExcludingGFX90A in 1974defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_vi <0x4>; 1975defm V_MUL_F32 : VOP2_Real_e32e64_vi <0x5>; 1976defm V_MUL_I32_I24 : VOP2_Real_e32e64_vi <0x6>; 1977defm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_vi <0x7>; 1978defm V_MUL_U32_U24 : VOP2_Real_e32e64_vi <0x8>; 1979defm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_vi <0x9>; 1980defm V_MIN_F32 : VOP2_Real_e32e64_vi <0xa>; 1981defm V_MAX_F32 : VOP2_Real_e32e64_vi <0xb>; 1982defm V_MIN_I32 : VOP2_Real_e32e64_vi <0xc>; 1983defm V_MAX_I32 : VOP2_Real_e32e64_vi <0xd>; 1984defm V_MIN_U32 : VOP2_Real_e32e64_vi <0xe>; 1985defm V_MAX_U32 : VOP2_Real_e32e64_vi <0xf>; 1986defm V_LSHRREV_B32 : VOP2_Real_e32e64_vi <0x10>; 1987defm V_ASHRREV_I32 : VOP2_Real_e32e64_vi <0x11>; 1988defm V_LSHLREV_B32 : VOP2_Real_e32e64_vi <0x12>; 1989defm V_AND_B32 : VOP2_Real_e32e64_vi <0x13>; 1990defm V_OR_B32 : VOP2_Real_e32e64_vi <0x14>; 1991defm V_XOR_B32 : VOP2_Real_e32e64_vi <0x15>; 1992defm V_MAC_F32 : VOP2_Real_e32e64_vi <0x16>; 1993defm V_MADMK_F32 : VOP2_Real_MADK_vi <0x17>; 1994defm V_MADAK_F32 : VOP2_Real_MADK_vi <0x18>; 1995 1996defm V_ADD_U32 : VOP2be_Real_e32e64_vi_only <0x19, "V_ADD_CO_U32", "v_add_u32">; 1997defm V_SUB_U32 : VOP2be_Real_e32e64_vi_only <0x1a, "V_SUB_CO_U32", "v_sub_u32">; 1998defm V_SUBREV_U32 : VOP2be_Real_e32e64_vi_only <0x1b, "V_SUBREV_CO_U32", "v_subrev_u32">; 1999defm V_ADDC_U32 : VOP2be_Real_e32e64_vi_only <0x1c, "V_ADDC_U32", "v_addc_u32">; 2000defm V_SUBB_U32 : VOP2be_Real_e32e64_vi_only <0x1d, "V_SUBB_U32", "v_subb_u32">; 2001defm V_SUBBREV_U32 : VOP2be_Real_e32e64_vi_only <0x1e, "V_SUBBREV_U32", "v_subbrev_u32">; 2002 2003defm V_ADD_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x19, "V_ADD_CO_U32", "v_add_co_u32">; 2004defm V_SUB_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1a, "V_SUB_CO_U32", "v_sub_co_u32">; 2005defm V_SUBREV_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1b, "V_SUBREV_CO_U32", "v_subrev_co_u32">; 2006defm V_ADDC_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1c, "V_ADDC_U32", "v_addc_co_u32">; 2007defm V_SUBB_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1d, "V_SUBB_U32", "v_subb_co_u32">; 2008defm V_SUBBREV_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1e, "V_SUBBREV_U32", "v_subbrev_co_u32">; 2009 2010defm V_ADD_U32 : VOP2_Real_e32e64_gfx9 <0x34>; 2011defm V_SUB_U32 : VOP2_Real_e32e64_gfx9 <0x35>; 2012defm V_SUBREV_U32 : VOP2_Real_e32e64_gfx9 <0x36>; 2013 2014defm V_BFM_B32 : VOP2_Real_e64only_vi <0x293>; 2015defm V_BCNT_U32_B32 : VOP2_Real_e64only_vi <0x28b>; 2016defm V_MBCNT_LO_U32_B32 : VOP2_Real_e64only_vi <0x28c>; 2017defm V_MBCNT_HI_U32_B32 : VOP2_Real_e64only_vi <0x28d>; 2018defm V_LDEXP_F32 : VOP2_Real_e64only_vi <0x288>; 2019defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64only_vi <0x1f0>; 2020defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64only_vi <0x294>; 2021defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64only_vi <0x295>; 2022defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e64only_vi <0x296>; 2023defm V_CVT_PK_U16_U32 : VOP2_Real_e64only_vi <0x297>; 2024defm V_CVT_PK_I16_I32 : VOP2_Real_e64only_vi <0x298>; 2025 2026defm V_ADD_F16 : VOP2_Real_e32e64_vi <0x1f>; 2027defm V_SUB_F16 : VOP2_Real_e32e64_vi <0x20>; 2028defm V_SUBREV_F16 : VOP2_Real_e32e64_vi <0x21>; 2029defm V_MUL_F16 : VOP2_Real_e32e64_vi <0x22>; 2030defm V_MAC_F16 : VOP2_Real_e32e64_vi <0x23>; 2031defm V_MADMK_F16 : VOP2_Real_MADK_vi <0x24>; 2032defm V_MADAK_F16 : VOP2_Real_MADK_vi <0x25>; 2033defm V_ADD_U16 : VOP2_Real_e32e64_vi <0x26>; 2034defm V_SUB_U16 : VOP2_Real_e32e64_vi <0x27>; 2035defm V_SUBREV_U16 : VOP2_Real_e32e64_vi <0x28>; 2036defm V_MUL_LO_U16 : VOP2_Real_e32e64_vi <0x29>; 2037defm V_LSHLREV_B16 : VOP2_Real_e32e64_vi <0x2a>; 2038defm V_LSHRREV_B16 : VOP2_Real_e32e64_vi <0x2b>; 2039defm V_ASHRREV_I16 : VOP2_Real_e32e64_vi <0x2c>; 2040defm V_MAX_F16 : VOP2_Real_e32e64_vi <0x2d>; 2041defm V_MIN_F16 : VOP2_Real_e32e64_vi <0x2e>; 2042defm V_MAX_U16 : VOP2_Real_e32e64_vi <0x2f>; 2043defm V_MAX_I16 : VOP2_Real_e32e64_vi <0x30>; 2044defm V_MIN_U16 : VOP2_Real_e32e64_vi <0x31>; 2045defm V_MIN_I16 : VOP2_Real_e32e64_vi <0x32>; 2046defm V_LDEXP_F16 : VOP2_Real_e32e64_vi <0x33>; 2047 2048let SubtargetPredicate = isGFX8GFX9 in { 2049 2050// Aliases to simplify matching of floating-point instructions that 2051// are VOP2 on SI and VOP3 on VI. 2052class SI2_VI3Alias <string name, VOP3_Real inst> : InstAlias < 2053 name#" $dst, $src0, $src1", 2054 !if(inst.Pfl.HasOMod, 2055 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0), 2056 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0)) 2057>, PredicateControl { 2058 let UseInstAsmMatchConverter = 0; 2059 let AsmVariantName = AMDGPUAsmVariants.VOP3; 2060} 2061 2062def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>; 2063def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>; 2064def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>; 2065def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>; 2066def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>; 2067 2068defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_vi>; 2069 2070} // End SubtargetPredicate = isGFX8GFX9 2071 2072let SubtargetPredicate = isGFX9Only in { 2073 2074defm : VOP2bInstAliases<V_ADD_U32_e32, V_ADD_CO_U32_e32_gfx9, "v_add_co_u32">; 2075defm : VOP2bInstAliases<V_ADDC_U32_e32, V_ADDC_CO_U32_e32_gfx9, "v_addc_co_u32">; 2076defm : VOP2bInstAliases<V_SUB_U32_e32, V_SUB_CO_U32_e32_gfx9, "v_sub_co_u32">; 2077defm : VOP2bInstAliases<V_SUBB_U32_e32, V_SUBB_CO_U32_e32_gfx9, "v_subb_co_u32">; 2078defm : VOP2bInstAliases<V_SUBREV_U32_e32, V_SUBREV_CO_U32_e32_gfx9, "v_subrev_co_u32">; 2079defm : VOP2bInstAliases<V_SUBBREV_U32_e32, V_SUBBREV_CO_U32_e32_gfx9, "v_subbrev_co_u32">; 2080 2081} // End SubtargetPredicate = isGFX9Only 2082 2083let SubtargetPredicate = HasDLInsts in { 2084 2085defm V_FMAC_F32 : VOP2_Real_e32e64_vi <0x3b>; 2086defm V_XNOR_B32 : VOP2_Real_e32e64_vi <0x3d>; 2087 2088} // End SubtargetPredicate = HasDLInsts 2089 2090let AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A" in { 2091 multiclass VOP2_Real_e32_gfx90a <bits<6> op> { 2092 def _e32_gfx90a : 2093 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX90A>, 2094 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 2095 } 2096 2097 multiclass VOP2_Real_e64_gfx90a <bits<10> op> { 2098 def _e64_gfx90a : 2099 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX90A>, 2100 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 2101 } 2102 2103 multiclass Base_VOP2_Real_e32e64_gfx90a <bits<6> op> : 2104 VOP2_Real_e32_gfx90a<op>, 2105 VOP2_Real_e64_gfx90a<{0, 1, 0, 0, op{5-0}}>; 2106 2107 multiclass VOP2_Real_e32e64_gfx90a <bits<6> op> : 2108 Base_VOP2_Real_e32e64_gfx90a<op> { 2109 2110 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in 2111 def _dpp_gfx90a : 2112 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX90A>, 2113 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> { 2114 let DecoderNamespace = "SDWA9"; 2115 } 2116 } 2117} // End AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A" 2118 2119let SubtargetPredicate = isGFX90APlus in { 2120 defm V_FMAC_F64 : VOP2_Real_e32e64_gfx90a <0x4>; 2121 let IsSingle = 1 in { 2122 defm V_MUL_LEGACY_F32 : VOP2_Real_e64_gfx90a <0x2a1>; 2123 } 2124} // End SubtargetPredicate = isGFX90APlus 2125 2126let SubtargetPredicate = HasFmaakFmamkF32Insts in { 2127defm V_FMAMK_F32 : VOP2_Real_MADK_gfx940 <0x17>; 2128defm V_FMAAK_F32 : VOP2_Real_MADK_gfx940 <0x18>; 2129} 2130 2131multiclass VOP2_Real_DOT_ACC_gfx9<bits<6> op> : VOP2_Real_e32_vi<op> { 2132 def _dpp_vi : VOP2_DPP<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>; 2133} 2134 2135multiclass VOP2_Real_DOT_ACC_gfx10<bits<6> op> : 2136 VOP2_Real_e32_gfx10<op>, 2137 VOP2_Real_dpp_gfx10<op>, 2138 VOP2_Real_dpp8_gfx10<op>; 2139 2140let SubtargetPredicate = HasDot5Insts in { 2141 defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx9<0x37>; 2142 // NB: Opcode conflicts with V_DOT8C_I32_I4 2143 // This opcode exists in gfx 10.1* only 2144 defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx10<0x02>; 2145} 2146 2147let SubtargetPredicate = HasDot6Insts in { 2148 defm V_DOT4C_I32_I8 : VOP2_Real_DOT_ACC_gfx9<0x39>; 2149 defm V_DOT4C_I32_I8 : VOP2_Real_DOT_ACC_gfx10<0x0d>; 2150} 2151 2152let SubtargetPredicate = HasDot4Insts in { 2153 defm V_DOT2C_I32_I16 : VOP2_Real_DOT_ACC_gfx9<0x38>; 2154} 2155let SubtargetPredicate = HasDot3Insts in { 2156 defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx9<0x3a>; 2157} 2158 2159let SubtargetPredicate = HasPkFmacF16Inst in { 2160defm V_PK_FMAC_F16 : VOP2_Real_e32_vi<0x3c>; 2161} // End SubtargetPredicate = HasPkFmacF16Inst 2162 2163let SubtargetPredicate = HasDot3Insts in { 2164 // NB: Opcode conflicts with V_DOT2C_F32_F16 2165 let DecoderNamespace = "GFX10_B" in 2166 defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx10<0x02>; 2167} 2168