1//===-- VOP2Instructions.td - Vector Instruction Definitions --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// VOP2 Classes
11//===----------------------------------------------------------------------===//
12
13class VOP2e <bits<6> op, VOPProfile P> : Enc32 {
14  bits<8> vdst;
15  bits<9> src0;
16  bits<8> src1;
17
18  let Inst{8-0}   = !if(P.HasSrc0, src0, 0);
19  let Inst{16-9}  = !if(P.HasSrc1, src1, 0);
20  let Inst{24-17} = !if(P.EmitDst, vdst, 0);
21  let Inst{30-25} = op;
22  let Inst{31}    = 0x0; //encoding
23}
24
25class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 {
26  bits<8>  vdst;
27  bits<9>  src0;
28  bits<8>  src1;
29  bits<32> imm;
30
31  let Inst{8-0}   = !if(P.HasSrc0, src0, 0);
32  let Inst{16-9}  = !if(P.HasSrc1, src1, 0);
33  let Inst{24-17} = !if(P.EmitDst, vdst, 0);
34  let Inst{30-25} = op;
35  let Inst{31}    = 0x0; // encoding
36  let Inst{63-32} = imm;
37}
38
39class VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> {
40  bits<8> vdst;
41  bits<8> src1;
42
43  let Inst{8-0}   = 0xf9; // sdwa
44  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
45  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
46  let Inst{30-25} = op;
47  let Inst{31}    = 0x0; // encoding
48}
49
50class VOP2_SDWA9Ae <bits<6> op, VOPProfile P> : VOP_SDWA9Ae <P> {
51  bits<8> vdst;
52  bits<9> src1;
53
54  let Inst{8-0}   = 0xf9; // sdwa
55  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
56  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
57  let Inst{30-25} = op;
58  let Inst{31}    = 0x0; // encoding
59  let Inst{63}    = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr
60}
61
62class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> :
63  VOP_Pseudo <opName, suffix, P, P.Outs32, P.Ins32, "", pattern> {
64
65  let AsmOperands = P.Asm32;
66
67  let Size = 4;
68  let mayLoad = 0;
69  let mayStore = 0;
70  let hasSideEffects = 0;
71
72  let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
73
74  let mayRaiseFPException = ReadsModeReg;
75
76  let VOP2 = 1;
77  let VALU = 1;
78  let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
79
80  let AsmVariantName = AMDGPUAsmVariants.Default;
81}
82
83class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> :
84  InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
85  SIMCInstr <ps.PseudoInstr, EncodingFamily> {
86
87  let isPseudo = 0;
88  let isCodeGenOnly = 0;
89
90  let Constraints     = ps.Constraints;
91  let DisableEncoding = ps.DisableEncoding;
92
93  // copy relevant pseudo op flags
94  let SubtargetPredicate = ps.SubtargetPredicate;
95  let OtherPredicates    = ps.OtherPredicates;
96  let AsmMatchConverter  = ps.AsmMatchConverter;
97  let AsmVariantName     = ps.AsmVariantName;
98  let Constraints        = ps.Constraints;
99  let DisableEncoding    = ps.DisableEncoding;
100  let TSFlags            = ps.TSFlags;
101  let UseNamedOperandTable = ps.UseNamedOperandTable;
102  let Uses                 = ps.Uses;
103  let Defs                 = ps.Defs;
104}
105
106class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
107  VOP_SDWA_Pseudo <OpName, P, pattern> {
108  let AsmMatchConverter = "cvtSdwaVOP2";
109}
110
111class VOP2_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
112  VOP_DPP_Pseudo <OpName, P, pattern> {
113}
114
115
116class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies {
117  list<dag> ret = !if(P.HasModifiers,
118    [(set P.DstVT:$vdst,
119      (node (P.Src0VT
120              !if(P.HasOMod,
121                  (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
122                  (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
123            (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
124    [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
125}
126
127multiclass VOP2Inst_e32<string opName,
128                        VOPProfile P,
129                        SDPatternOperator node = null_frag,
130                        string revOp = opName,
131                        bit GFX9Renamed = 0> {
132  let renamedInGFX9 = GFX9Renamed in {
133    def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
134               Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
135  } // End renamedInGFX9 = GFX9Renamed
136}
137
138multiclass VOP2Inst_e64<string opName,
139                        VOPProfile P,
140                        SDPatternOperator node = null_frag,
141                        string revOp = opName,
142                        bit GFX9Renamed = 0> {
143  let renamedInGFX9 = GFX9Renamed in {
144    def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
145               Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
146  } // End renamedInGFX9 = GFX9Renamed
147}
148
149multiclass VOP2Inst_sdwa<string opName,
150                         VOPProfile P,
151                         SDPatternOperator node = null_frag,
152                         string revOp = opName,
153                         bit GFX9Renamed = 0> {
154  let renamedInGFX9 = GFX9Renamed in {
155    foreach _ = BoolToList<P.HasExtSDWA>.ret in
156      def _sdwa : VOP2_SDWA_Pseudo <opName, P>;
157  } // End renamedInGFX9 = GFX9Renamed
158}
159
160multiclass VOP2Inst<string opName,
161                    VOPProfile P,
162                    SDPatternOperator node = null_frag,
163                    string revOp = opName,
164                    bit GFX9Renamed = 0> :
165    VOP2Inst_e32<opName, P, node, revOp, GFX9Renamed>,
166    VOP2Inst_e64<opName, P, node, revOp, GFX9Renamed>,
167    VOP2Inst_sdwa<opName, P, node, revOp, GFX9Renamed> {
168  let renamedInGFX9 = GFX9Renamed in {
169    foreach _ = BoolToList<P.HasExtDPP>.ret in
170      def _dpp  : VOP2_DPP_Pseudo <opName, P>;
171  }
172}
173
174multiclass VOP2bInst <string opName,
175                      VOPProfile P,
176                      SDPatternOperator node = null_frag,
177                      string revOp = opName,
178                      bit GFX9Renamed = 0,
179                      bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
180  let renamedInGFX9 = GFX9Renamed in {
181    let SchedRW = [Write32Bit, WriteSALU] in {
182      let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
183        def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
184                   Commutable_REV<revOp#"_e32", !eq(revOp, opName)> {
185          let usesCustomInserter = !eq(P.NumSrcArgs, 2);
186        }
187
188        foreach _ = BoolToList<P.HasExtSDWA>.ret in
189          def _sdwa  : VOP2_SDWA_Pseudo <opName, P> {
190            let AsmMatchConverter = "cvtSdwaVOP2b";
191          }
192        foreach _ = BoolToList<P.HasExtDPP>.ret in
193          def _dpp  : VOP2_DPP_Pseudo <opName, P>;
194      }
195
196      def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
197                 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
198    }
199  }
200}
201
202class VOP2bInstAlias <VOP2_Pseudo ps, Instruction inst,
203                      string OpName, string opnd> :
204  InstAlias <OpName#" "#!subst("vcc", opnd, ps.Pfl.Asm32),
205             (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
206                   ps.Pfl.Src1RC32:$src1)>,
207  PredicateControl {
208}
209
210multiclass VOP2bInstAliases<VOP2_Pseudo ps, VOP2_Real inst, string OpName> {
211  let WaveSizePredicate = isWave32 in {
212    def : VOP2bInstAlias<ps, inst, OpName, "vcc_lo">;
213  }
214  let WaveSizePredicate = isWave64 in {
215    def : VOP2bInstAlias<ps, inst, OpName, "vcc">;
216  }
217}
218
219multiclass VOP2eInst <string opName,
220                      VOPProfile P,
221                      SDPatternOperator node = null_frag,
222                      string revOp = opName,
223                      bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
224
225  let SchedRW = [Write32Bit] in {
226    let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in {
227      def _e32 : VOP2_Pseudo <opName, P>,
228                 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
229
230      foreach _ = BoolToList<P.HasExtSDWA>.ret in
231        def _sdwa : VOP2_SDWA_Pseudo <opName, P> {
232          let AsmMatchConverter = "cvtSdwaVOP2e";
233        }
234
235      foreach _ = BoolToList<P.HasExtDPP>.ret in
236        def _dpp  : VOP2_DPP_Pseudo <opName, P>;
237    }
238
239    def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
240               Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
241  }
242}
243
244class VOP2eInstAlias <VOP2_Pseudo ps, Instruction inst, string opnd = ""> :
245  InstAlias <ps.OpName#" "#ps.Pfl.Asm32#", "#opnd,
246             (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
247                   ps.Pfl.Src1RC32:$src1)>, PredicateControl;
248
249class VOP2e64InstAlias <VOP3_Pseudo ps, Instruction inst> :
250  InstAlias <ps.OpName#" "#ps.Pfl.Asm64,
251             (inst ps.Pfl.DstRC:$vdst, VOPDstS64orS32:$sdst,
252                   ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, clampmod:$clamp)>,
253  PredicateControl;
254
255multiclass VOP2eInstAliases<VOP2_Pseudo ps, VOP2_Real inst> {
256  let WaveSizePredicate = isWave32 in {
257    def : VOP2eInstAlias<ps, inst, "vcc_lo">;
258  }
259  let WaveSizePredicate = isWave64 in {
260    def : VOP2eInstAlias<ps, inst, "vcc">;
261  }
262}
263
264class VOP_MADAK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
265  field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
266  field dag Ins32 = !if(!eq(vt.Size, 32),
267                        (ins VCSrc_f32:$src0, VGPR_32:$src1, ImmOpType:$imm),
268                        (ins VCSrc_f16:$src0, VGPR_32:$src1, ImmOpType:$imm));
269  field bit HasExt = 0;
270
271  // Hack to stop printing _e64
272  let DstRC = RegisterOperand<VGPR_32>;
273  field string Asm32 = " $vdst, $src0, $src1, $imm";
274}
275
276def VOP_MADAK_F16 : VOP_MADAK <f16>;
277def VOP_MADAK_F32 : VOP_MADAK <f32>;
278
279class VOP_MADMK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
280  field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
281  field dag Ins32 = (ins VCSrc_f32:$src0, ImmOpType:$imm, VGPR_32:$src1);
282  field bit HasExt = 0;
283
284  // Hack to stop printing _e64
285  let DstRC = RegisterOperand<VGPR_32>;
286  field string Asm32 = " $vdst, $src0, $imm, $src1";
287}
288
289def VOP_MADMK_F16 : VOP_MADMK <f16>;
290def VOP_MADMK_F32 : VOP_MADMK <f32>;
291
292// FIXME: Remove src2_modifiers. It isn't used, so is wasting memory
293// and processing time but it makes it easier to convert to mad.
294class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, vt0]> {
295  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
296  let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
297                       0, HasModifiers, HasModifiers, HasOMod,
298                       Src0Mod, Src1Mod, Src2Mod>.ret;
299  let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
300                    Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
301                    VGPR_32:$src2, // stub argument
302                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
303                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
304  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
305
306  let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
307                     Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
308                     VGPR_32:$src2, // stub argument
309                     dpp8:$dpp8, FI:$fi);
310
311  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
312                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
313                     VGPR_32:$src2, // stub argument
314                     clampmod:$clamp, omod:$omod,
315                     dst_sel:$dst_sel, dst_unused:$dst_unused,
316                     src0_sel:$src0_sel, src1_sel:$src1_sel);
317  let Asm32 = getAsm32<1, 2, vt0>.ret;
318  let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, vt0>.ret;
319  let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt0>.ret;
320  let AsmDPP16 = getAsmDPP16<1, 2, HasModifiers, vt0>.ret;
321  let AsmDPP8 = getAsmDPP8<1, 2, 0, vt0>.ret;
322  let AsmSDWA = getAsmSDWA<1, 2, vt0>.ret;
323  let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt0>.ret;
324  let HasSrc2 = 0;
325  let HasSrc2Mods = 0;
326
327  let HasExt = 1;
328  let HasExtDPP = 1;
329  let HasExtSDWA = 1;
330  let HasExtSDWA9 = 0;
331  let TieRegDPP = "$src2";
332}
333
334def VOP_MAC_F16 : VOP_MAC <f16>;
335def VOP_MAC_F32 : VOP_MAC <f32>;
336let HasExtDPP = 0 in
337def VOP_MAC_LEGACY_F32 : VOP_MAC <f32>;
338
339class VOP_DOT_ACC<ValueType vt0, ValueType vt1> : VOP_MAC<vt0, vt1> {
340  let HasClamp = 0;
341  let HasExtSDWA = 0;
342  let HasModifiers = 1;
343  let HasOpSel = 0;
344  let IsPacked = 0;
345}
346
347def VOP_DOT_ACC_F32_V2F16 : VOP_DOT_ACC<f32, v2f16> {
348  let Src0ModDPP = FPVRegInputMods;
349  let Src1ModDPP = FPVRegInputMods;
350}
351def VOP_DOT_ACC_I32_I32   : VOP_DOT_ACC<i32, i32>;
352
353// Write out to vcc or arbitrary SGPR.
354def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], 0, /*EnableClamp=*/1> {
355  let Asm32 = "$vdst, vcc, $src0, $src1";
356  let Asm64 = "$vdst, $sdst, $src0, $src1$clamp";
357  let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
358  let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
359  let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
360  let AsmDPP8 = "$vdst, vcc, $src0, $src1 $dpp8$fi";
361  let AsmDPP16 = AsmDPP#"$fi";
362  let Outs32 = (outs DstRC:$vdst);
363  let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
364}
365
366// Write out to vcc or arbitrary SGPR and read in from vcc or
367// arbitrary SGPR.
368def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], 0, /*EnableClamp=*/1> {
369  let Asm32 = "$vdst, vcc, $src0, $src1, vcc";
370  let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
371  let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
372  let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
373  let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
374  let AsmDPP8 = "$vdst, vcc, $src0, $src1, vcc $dpp8$fi";
375  let AsmDPP16 = AsmDPP#"$fi";
376  let Outs32 = (outs DstRC:$vdst);
377  let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
378
379  // Suppress src2 implied by type since the 32-bit encoding uses an
380  // implicit VCC use.
381  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
382
383  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
384                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
385                     clampmod:$clamp,
386                     dst_sel:$dst_sel, dst_unused:$dst_unused,
387                     src0_sel:$src0_sel, src1_sel:$src1_sel);
388
389  let InsDPP = (ins DstRCDPP:$old,
390                    Src0DPP:$src0,
391                    Src1DPP:$src1,
392                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
393                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
394  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
395
396  let HasExt = 1;
397  let HasExtDPP = 1;
398  let HasExtSDWA = 1;
399  let HasExtSDWA9 = 1;
400}
401
402// Read in from vcc or arbitrary SGPR.
403def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], /*EnableF32SrcMods=*/1> {
404  let Asm32 = "$vdst, $src0, $src1";
405  let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2";
406  let AsmSDWA = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
407  let AsmSDWA9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
408  let AsmDPP = "$vdst, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
409  let AsmDPP8 = "$vdst, $src0, $src1, vcc $dpp8$fi";
410  let AsmDPP16 = AsmDPP#"$fi";
411
412  let Outs32 = (outs DstRC:$vdst);
413  let Outs64 = (outs DstRC:$vdst);
414
415  // Suppress src2 implied by type since the 32-bit encoding uses an
416  // implicit VCC use.
417  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
418
419  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
420                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
421                     clampmod:$clamp,
422                     dst_sel:$dst_sel, dst_unused:$dst_unused,
423                     src0_sel:$src0_sel, src1_sel:$src1_sel);
424
425  let InsDPP = (ins DstRCDPP:$old,
426                    Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
427                    Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
428                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
429                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
430  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
431
432  let HasExt = 1;
433  let HasExtDPP = 1;
434  let HasExtSDWA = 1;
435  let HasExtSDWA9 = 1;
436}
437
438def VOP_READLANE : VOPProfile<[i32, i32, i32]> {
439  let Outs32 = (outs SReg_32:$vdst);
440  let Outs64 = Outs32;
441  let Ins32 = (ins VRegOrLds_32:$src0, SCSrc_b32:$src1);
442  let Ins64 = Ins32;
443  let Asm32 = " $vdst, $src0, $src1";
444  let Asm64 = Asm32;
445
446  let HasExt = 0;
447  let HasExtDPP = 0;
448  let HasExtSDWA = 0;
449  let HasExtSDWA9 = 0;
450}
451
452def VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> {
453  let Outs32 = (outs VGPR_32:$vdst);
454  let Outs64 = Outs32;
455  let Ins32 = (ins SCSrc_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in);
456  let Ins64 = Ins32;
457  let Asm32 = " $vdst, $src0, $src1";
458  let Asm64 = Asm32;
459  let HasSrc2 = 0;
460  let HasSrc2Mods = 0;
461
462  let HasExt = 0;
463  let HasExtDPP = 0;
464  let HasExtSDWA = 0;
465  let HasExtSDWA9 = 0;
466}
467
468//===----------------------------------------------------------------------===//
469// VOP2 Instructions
470//===----------------------------------------------------------------------===//
471
472defm V_CNDMASK_B32 : VOP2eInst <"v_cndmask_b32", VOP2e_I32_I32_I32_I1>;
473let SubtargetPredicate = HasMadMacF32Insts in
474def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, []>;
475
476let isCommutable = 1 in {
477defm V_ADD_F32 : VOP2Inst <"v_add_f32", VOP_F32_F32_F32, any_fadd>;
478defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, any_fsub>;
479defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">;
480defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>;
481defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, any_fmul>;
482defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32_ARITH, AMDGPUmul_i24>;
483defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_i24>;
484defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32_ARITH, AMDGPUmul_u24>;
485defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_u24>;
486defm V_MIN_F32 : VOP2Inst <"v_min_f32", VOP_F32_F32_F32, fminnum_like>;
487defm V_MAX_F32 : VOP2Inst <"v_max_f32", VOP_F32_F32_F32, fmaxnum_like>;
488defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smin>;
489defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smax>;
490defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umin>;
491defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umax>;
492defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, lshr_rev, "v_lshr_b32">;
493defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, ashr_rev, "v_ashr_i32">;
494defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, lshl_rev, "v_lshl_b32">;
495defm V_AND_B32 : VOP2Inst <"v_and_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, and>;
496defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, or>;
497defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, xor>;
498
499let mayRaiseFPException = 0 in {
500let OtherPredicates = [HasMadMacF32Insts] in {
501let Constraints = "$vdst = $src2", DisableEncoding="$src2",
502    isConvertibleToThreeAddress = 1 in {
503defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>;
504
505let SubtargetPredicate = isGFX6GFX7GFX10 in
506defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_MAC_LEGACY_F32>;
507} // End Constraints = "$vdst = $src2", DisableEncoding="$src2",
508  //     isConvertibleToThreeAddress = 1
509
510def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32, []>;
511} // End OtherPredicates = [HasMadMacF32Insts]
512} // End mayRaiseFPException = 0
513
514// No patterns so that the scalar instructions are always selected.
515// The scalar versions will be replaced with vector when needed later.
516defm V_ADD_CO_U32 : VOP2bInst <"v_add_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_add_co_u32", 1>;
517defm V_SUB_CO_U32 : VOP2bInst <"v_sub_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>;
518defm V_SUBREV_CO_U32 : VOP2bInst <"v_subrev_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>;
519defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_addc_u32", 1>;
520defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>;
521defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>;
522
523
524let SubtargetPredicate = HasAddNoCarryInsts in {
525defm V_ADD_U32 : VOP2Inst <"v_add_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_add_u32", 1>;
526defm V_SUB_U32 : VOP2Inst <"v_sub_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>;
527defm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>;
528}
529
530} // End isCommutable = 1
531
532// These are special and do not read the exec mask.
533let isConvergent = 1, Uses = []<Register> in {
534def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE,
535  [(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))]>;
536
537let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in {
538def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE,
539  [(set i32:$vdst, (int_amdgcn_writelane i32:$src0, i32:$src1, i32:$vdst_in))]>;
540} // End $vdst = $vdst_in, DisableEncoding $vdst_in
541} // End isConvergent = 1
542
543defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_NO_EXT<VOP_I32_I32_I32>>;
544defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, add_ctpop>;
545defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_lo>;
546defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_hi>;
547defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_NO_EXT<VOP_F32_F32_I32>, AMDGPUldexp>;
548defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_NO_EXT<VOP_I32_F32_I32>>; // TODO: set "Uses = dst"
549
550let ReadsModeReg = 0, mayRaiseFPException = 0 in {
551defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_i16_f32>;
552defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_u16_f32>;
553}
554
555defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_NO_EXT<VOP_V2F16_F32_F32>, AMDGPUpkrtz_f16_f32>;
556defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_u16_u32>;
557defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_i16_i32>;
558
559
560let SubtargetPredicate = isGFX6GFX7 in {
561defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>;
562defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>;
563} // End SubtargetPredicate = isGFX6GFX7
564
565let isCommutable = 1 in {
566let SubtargetPredicate = isGFX6GFX7 in {
567defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, srl>;
568defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, sra>;
569defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, shl>;
570} // End SubtargetPredicate = isGFX6GFX7
571} // End isCommutable = 1
572
573
574class DivergentBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :
575  GCNPat<
576      (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
577      !if(!cast<Commutable_REV>(Inst).IsOrig,
578        (Inst $src0, $src1),
579        (Inst $src1, $src0)
580      )
581  >;
582
583class DivergentClampingBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :
584  GCNPat<
585      (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
586      !if(!cast<Commutable_REV>(Inst).IsOrig,
587        (Inst $src0, $src1, 0),
588        (Inst $src1, $src0, 0)
589      )
590  >;
591
592def : DivergentBinOp<srl, V_LSHRREV_B32_e64>;
593def : DivergentBinOp<sra, V_ASHRREV_I32_e64>;
594def : DivergentBinOp<shl, V_LSHLREV_B32_e64>;
595
596let SubtargetPredicate = HasAddNoCarryInsts in {
597  def : DivergentClampingBinOp<add, V_ADD_U32_e64>;
598  def : DivergentClampingBinOp<sub, V_SUB_U32_e64>;
599}
600
601let SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] in {
602def : DivergentClampingBinOp<add, V_ADD_CO_U32_e64>;
603def : DivergentClampingBinOp<sub, V_SUB_CO_U32_e64>;
604}
605
606def : DivergentBinOp<adde, V_ADDC_U32_e32>;
607def : DivergentBinOp<sube, V_SUBB_U32_e32>;
608
609class divergent_i64_BinOp <SDPatternOperator Op, Instruction Inst> :
610  GCNPat<
611      (getDivergentFrag<Op>.ret i64:$src0, i64:$src1),
612      (REG_SEQUENCE VReg_64,
613        (Inst
614          (i32 (EXTRACT_SUBREG $src0, sub0)),
615          (i32 (EXTRACT_SUBREG $src1, sub0))
616        ), sub0,
617        (Inst
618          (i32 (EXTRACT_SUBREG $src0, sub1)),
619          (i32 (EXTRACT_SUBREG $src1, sub1))
620        ), sub1
621      )
622  >;
623
624def :  divergent_i64_BinOp <and, V_AND_B32_e32>;
625def :  divergent_i64_BinOp <or,  V_OR_B32_e32>;
626def :  divergent_i64_BinOp <xor, V_XOR_B32_e32>;
627
628let SubtargetPredicate = Has16BitInsts in {
629
630let FPDPRounding = 1 in {
631def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16, [], "">;
632defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>;
633} // End FPDPRounding = 1
634
635defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16, lshl_rev>;
636defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16, lshr_rev>;
637defm V_ASHRREV_I16 : VOP2Inst <"v_ashrrev_i16", VOP_I16_I16_I16, ashr_rev>;
638
639let isCommutable = 1 in {
640let FPDPRounding = 1 in {
641defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, any_fadd>;
642defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, any_fsub>;
643defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">;
644defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, any_fmul>;
645
646let mayRaiseFPException = 0 in {
647def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">;
648}
649
650} // End FPDPRounding = 1
651defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16_ARITH, add>;
652defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16_ARITH, sub>;
653defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16_ARITH, null_frag, "v_sub_u16">;
654defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16, mul>;
655defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum_like>;
656defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum_like>;
657defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16, umax>;
658defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16, smax>;
659defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16, umin>;
660defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16, smin>;
661
662let Constraints = "$vdst = $src2", DisableEncoding="$src2",
663    isConvertibleToThreeAddress = 1 in {
664defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>;
665}
666} // End isCommutable = 1
667
668} // End SubtargetPredicate = Has16BitInsts
669
670let SubtargetPredicate = HasDLInsts in {
671
672defm V_XNOR_B32 : VOP2Inst <"v_xnor_b32", VOP_I32_I32_I32>;
673
674let Constraints = "$vdst = $src2",
675    DisableEncoding = "$src2",
676    isConvertibleToThreeAddress = 1,
677    isCommutable = 1 in
678defm V_FMAC_F32 : VOP2Inst <"v_fmac_f32", VOP_MAC_F32>;
679
680} // End SubtargetPredicate = HasDLInsts
681
682let SubtargetPredicate = HasFmaLegacy32 in {
683
684let Constraints = "$vdst = $src2",
685    DisableEncoding = "$src2",
686    isConvertibleToThreeAddress = 1,
687    isCommutable = 1 in
688defm V_FMAC_LEGACY_F32 : VOP2Inst <"v_fmac_legacy_f32", VOP_MAC_LEGACY_F32>;
689
690} // End SubtargetPredicate = HasFmaLegacy32
691
692let Constraints = "$vdst = $src2",
693      DisableEncoding="$src2",
694      isConvertibleToThreeAddress = 1,
695      isCommutable = 1,
696      IsDOT = 1 in {
697  let SubtargetPredicate = HasDot5Insts in
698    defm V_DOT2C_F32_F16 : VOP2Inst<"v_dot2c_f32_f16", VOP_DOT_ACC_F32_V2F16>;
699  let SubtargetPredicate = HasDot6Insts in
700    defm V_DOT4C_I32_I8  : VOP2Inst<"v_dot4c_i32_i8",  VOP_DOT_ACC_I32_I32>;
701
702  let SubtargetPredicate = HasDot4Insts in
703    defm V_DOT2C_I32_I16 : VOP2Inst<"v_dot2c_i32_i16", VOP_DOT_ACC_I32_I32>;
704  let SubtargetPredicate = HasDot3Insts in
705    defm V_DOT8C_I32_I4  : VOP2Inst<"v_dot8c_i32_i4",  VOP_DOT_ACC_I32_I32>;
706}
707
708let AddedComplexity = 30 in {
709  def : GCNPat<
710    (f32 (AMDGPUfdot2 v2f16:$src0, v2f16:$src1, f32:$src2, (i1 DSTCLAMP.NONE))),
711    (f32 (V_DOT2C_F32_F16_e32 $src0, $src1, $src2))
712  > {
713    let SubtargetPredicate = HasDot5Insts;
714  }
715  def : GCNPat<
716    (i32 (int_amdgcn_sdot4 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
717    (i32 (V_DOT4C_I32_I8_e32 $src0, $src1, $src2))
718  > {
719    let SubtargetPredicate = HasDot6Insts;
720  }
721  def : GCNPat<
722    (i32 (int_amdgcn_sdot2 v2i16:$src0, v2i16:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
723    (i32 (V_DOT2C_I32_I16_e32 $src0, $src1, $src2))
724  > {
725    let SubtargetPredicate = HasDot4Insts;
726  }
727  def : GCNPat<
728    (i32 (int_amdgcn_sdot8 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
729    (i32 (V_DOT8C_I32_I4_e32 $src0, $src1, $src2))
730  > {
731    let SubtargetPredicate = HasDot3Insts;
732  }
733} // End AddedComplexity = 30
734
735let SubtargetPredicate = isGFX10Plus in {
736
737def V_FMAMK_F32 : VOP2_Pseudo<"v_fmamk_f32", VOP_MADMK_F32, [], "">;
738let FPDPRounding = 1 in
739def V_FMAMK_F16 : VOP2_Pseudo <"v_fmamk_f16", VOP_MADMK_F16, [], "">;
740
741let isCommutable = 1 in {
742def V_FMAAK_F32 : VOP2_Pseudo<"v_fmaak_f32", VOP_MADAK_F32, [], "">;
743let FPDPRounding = 1 in
744def V_FMAAK_F16 : VOP2_Pseudo <"v_fmaak_f16", VOP_MADAK_F16, [], "">;
745} // End isCommutable = 1
746
747let Constraints = "$vdst = $src2",
748    DisableEncoding="$src2",
749    isConvertibleToThreeAddress = 1,
750    isCommutable = 1 in {
751defm V_FMAC_F16 : VOP2Inst <"v_fmac_f16", VOP_MAC_F16>;
752}
753
754} // End SubtargetPredicate = isGFX10Plus
755
756let SubtargetPredicate = HasPkFmacF16Inst in {
757defm V_PK_FMAC_F16 : VOP2Inst<"v_pk_fmac_f16", VOP_V2F16_V2F16_V2F16>;
758} // End SubtargetPredicate = HasPkFmacF16Inst
759
760// Note: 16-bit instructions produce a 0 result in the high 16-bits
761// on GFX8 and GFX9 and preserve high 16 bits on GFX10+
762multiclass Arithmetic_i16_0Hi_Pats <SDPatternOperator op, Instruction inst> {
763
764def : GCNPat<
765  (i32 (zext (op i16:$src0, i16:$src1))),
766  (inst VSrc_b16:$src0, VSrc_b16:$src1)
767>;
768
769def : GCNPat<
770  (i64 (zext (op i16:$src0, i16:$src1))),
771   (REG_SEQUENCE VReg_64,
772     (inst $src0, $src1), sub0,
773     (V_MOV_B32_e32 (i32 0)), sub1)
774>;
775}
776
777class ZExt_i16_i1_Pat <SDNode ext> : GCNPat <
778  (i16 (ext i1:$src)),
779  (V_CNDMASK_B32_e64 (i32 0/*src0mod*/), (i32 0/*src0*/),
780                     (i32 0/*src1mod*/), (i32 1/*src1*/),
781                     $src)
782>;
783
784foreach vt = [i16, v2i16] in {
785def : GCNPat <
786  (and vt:$src0, vt:$src1),
787  (V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
788>;
789
790def : GCNPat <
791  (or vt:$src0, vt:$src1),
792  (V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
793>;
794
795def : GCNPat <
796  (xor vt:$src0, vt:$src1),
797  (V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
798>;
799}
800
801let Predicates = [Has16BitInsts] in {
802
803// Undo sub x, c -> add x, -c canonicalization since c is more likely
804// an inline immediate than -c.
805// TODO: Also do for 64-bit.
806def : GCNPat<
807  (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)),
808  (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)
809>;
810
811
812let Predicates = [Has16BitInsts, isGFX7GFX8GFX9] in {
813
814def : GCNPat<
815  (i32 (zext (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)))),
816  (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)
817>;
818
819defm : Arithmetic_i16_0Hi_Pats<add, V_ADD_U16_e64>;
820defm : Arithmetic_i16_0Hi_Pats<mul, V_MUL_LO_U16_e64>;
821defm : Arithmetic_i16_0Hi_Pats<sub, V_SUB_U16_e64>;
822defm : Arithmetic_i16_0Hi_Pats<smin, V_MIN_I16_e64>;
823defm : Arithmetic_i16_0Hi_Pats<smax, V_MAX_I16_e64>;
824defm : Arithmetic_i16_0Hi_Pats<umin, V_MIN_U16_e64>;
825defm : Arithmetic_i16_0Hi_Pats<umax, V_MAX_U16_e64>;
826defm : Arithmetic_i16_0Hi_Pats<lshl_rev, V_LSHLREV_B16_e64>;
827defm : Arithmetic_i16_0Hi_Pats<lshr_rev, V_LSHRREV_B16_e64>;
828defm : Arithmetic_i16_0Hi_Pats<ashr_rev, V_ASHRREV_I16_e64>;
829}  // End Predicates = [Has16BitInsts, isGFX7GFX8GFX9]
830
831def : ZExt_i16_i1_Pat<zext>;
832def : ZExt_i16_i1_Pat<anyext>;
833
834def : GCNPat <
835  (i16 (sext i1:$src)),
836  (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
837                     /*src1mod*/(i32 0), /*src1*/(i32 -1), $src)
838>;
839
840} // End Predicates = [Has16BitInsts]
841
842
843let SubtargetPredicate = HasIntClamp in {
844// Set clamp bit for saturation.
845def : VOPBinOpClampPat<uaddsat, V_ADD_CO_U32_e64, i32>;
846def : VOPBinOpClampPat<usubsat, V_SUB_CO_U32_e64, i32>;
847}
848
849let SubtargetPredicate = HasAddNoCarryInsts, OtherPredicates = [HasIntClamp] in {
850let AddedComplexity = 1 in { // Prefer over form with carry-out.
851def : VOPBinOpClampPat<uaddsat, V_ADD_U32_e64, i32>;
852def : VOPBinOpClampPat<usubsat, V_SUB_U32_e64, i32>;
853}
854}
855
856let SubtargetPredicate = Has16BitInsts, OtherPredicates = [HasIntClamp] in {
857def : VOPBinOpClampPat<uaddsat, V_ADD_U16_e64, i16>;
858def : VOPBinOpClampPat<usubsat, V_SUB_U16_e64, i16>;
859}
860
861//===----------------------------------------------------------------------===//
862// Target-specific instruction encodings.
863//===----------------------------------------------------------------------===//
864
865class VOP2_DPP<bits<6> op, VOP2_DPP_Pseudo ps,
866               string opName = ps.OpName, VOPProfile p = ps.Pfl,
867               bit IsDPP16 = 0> :
868    VOP_DPP<opName, p, IsDPP16> {
869  let hasSideEffects = ps.hasSideEffects;
870  let Defs = ps.Defs;
871  let SchedRW = ps.SchedRW;
872  let Uses = ps.Uses;
873
874  bits<8> vdst;
875  bits<8> src1;
876  let Inst{8-0}   = 0xfa;
877  let Inst{16-9}  = !if(p.HasSrc1, src1{7-0}, 0);
878  let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
879  let Inst{30-25} = op;
880  let Inst{31}    = 0x0;
881}
882
883class Base_VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps,
884                 string opName = ps.OpName, VOPProfile p = ps.Pfl> :
885    VOP2_DPP<op, ps, opName, p, 1> {
886  let AssemblerPredicate = HasDPP16;
887  let SubtargetPredicate = HasDPP16;
888  let OtherPredicates = ps.OtherPredicates;
889}
890
891class VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps,
892                 string opName = ps.OpName, VOPProfile p = ps.Pfl> :
893    Base_VOP2_DPP16<op, ps, opName, p>,
894    SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX10>;
895
896class VOP2_DPP8<bits<6> op, VOP2_Pseudo ps,
897                string opName = ps.OpName, VOPProfile p = ps.Pfl> :
898    VOP_DPP8<ps.OpName, p> {
899  let hasSideEffects = ps.hasSideEffects;
900  let Defs = ps.Defs;
901  let SchedRW = ps.SchedRW;
902  let Uses = ps.Uses;
903
904  bits<8> vdst;
905  bits<8> src1;
906
907  let Inst{8-0}   = fi;
908  let Inst{16-9}  = !if(p.HasSrc1, src1{7-0}, 0);
909  let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
910  let Inst{30-25} = op;
911  let Inst{31}    = 0x0;
912
913  let AssemblerPredicate = HasDPP8;
914  let SubtargetPredicate = HasDPP8;
915  let OtherPredicates = ps.OtherPredicates;
916}
917
918//===----------------------------------------------------------------------===//
919// GFX10.
920//===----------------------------------------------------------------------===//
921
922let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
923  //===------------------------------- VOP2 -------------------------------===//
924  multiclass VOP2Only_Real_MADK_gfx10<bits<6> op> {
925    def _gfx10 :
926      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX10>,
927      VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
928  }
929  multiclass VOP2Only_Real_MADK_gfx10_with_name<bits<6> op, string opName,
930                                                string asmName> {
931    def _gfx10 :
932        VOP2_Real<!cast<VOP2_Pseudo>(opName), SIEncodingFamily.GFX10>,
933        VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> {
934      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName);
935      let AsmString = asmName # ps.AsmOperands;
936    }
937  }
938  multiclass VOP2_Real_e32_gfx10<bits<6> op> {
939    def _e32_gfx10 :
940      VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,
941      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
942  }
943  multiclass VOP2_Real_e64_gfx10<bits<6> op> {
944    def _e64_gfx10 :
945      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
946      VOP3e_gfx10<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
947  }
948  multiclass VOP2_Real_sdwa_gfx10<bits<6> op> {
949    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
950    def _sdwa_gfx10 :
951      VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
952      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
953      let DecoderNamespace = "SDWA10";
954    }
955  }
956  multiclass VOP2_Real_dpp_gfx10<bits<6> op> {
957    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
958    def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
959      let DecoderNamespace = "SDWA10";
960    }
961  }
962  multiclass VOP2_Real_dpp8_gfx10<bits<6> op> {
963    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
964    def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(NAME#"_e32")> {
965      let DecoderNamespace = "DPP8";
966    }
967  }
968
969  //===------------------------- VOP2 (with name) -------------------------===//
970  multiclass VOP2_Real_e32_gfx10_with_name<bits<6> op, string opName,
971                                           string asmName> {
972    def _e32_gfx10 :
973      VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
974      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
975        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
976        let AsmString = asmName # ps.AsmOperands;
977      }
978  }
979  multiclass VOP2_Real_e64_gfx10_with_name<bits<6> op, string opName,
980                                           string asmName> {
981    def _e64_gfx10 :
982      VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
983      VOP3e_gfx10<{0, 1, 0, 0, op{5-0}},
984                  !cast<VOP3_Pseudo>(opName#"_e64").Pfl> {
985        VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64");
986        let AsmString = asmName # ps.AsmOperands;
987      }
988  }
989  let DecoderNamespace = "SDWA10" in {
990    multiclass VOP2_Real_sdwa_gfx10_with_name<bits<6> op, string opName,
991                                              string asmName> {
992      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
993      def _sdwa_gfx10 :
994        VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
995        VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
996          VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
997          let AsmString = asmName # ps.AsmOperands;
998        }
999    }
1000    multiclass VOP2_Real_dpp_gfx10_with_name<bits<6> op, string opName,
1001                                             string asmName> {
1002      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1003      def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp")> {
1004        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
1005        let AsmString = asmName # ps.Pfl.AsmDPP16;
1006      }
1007    }
1008    multiclass VOP2_Real_dpp8_gfx10_with_name<bits<6> op, string opName,
1009                                              string asmName> {
1010      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1011      def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
1012        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
1013        let AsmString = asmName # ps.Pfl.AsmDPP8;
1014        let DecoderNamespace = "DPP8";
1015      }
1016    }
1017  } // End DecoderNamespace = "SDWA10"
1018
1019  //===------------------------------ VOP2be ------------------------------===//
1020  multiclass VOP2be_Real_e32_gfx10<bits<6> op, string opName, string asmName> {
1021    def _e32_gfx10 :
1022      VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
1023      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
1024        VOP2_Pseudo Ps = !cast<VOP2_Pseudo>(opName#"_e32");
1025        let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
1026      }
1027  }
1028  multiclass VOP2be_Real_e64_gfx10<bits<6> op, string opName, string asmName> {
1029    def _e64_gfx10 :
1030      VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
1031      VOP3be_gfx10<{0, 1, 0, 0, op{5-0}},
1032                   !cast<VOP3_Pseudo>(opName#"_e64").Pfl> {
1033        VOP3_Pseudo Ps = !cast<VOP3_Pseudo>(opName#"_e64");
1034        let AsmString = asmName # Ps.AsmOperands;
1035      }
1036  }
1037  multiclass VOP2be_Real_sdwa_gfx10<bits<6> op, string opName, string asmName> {
1038    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1039    def _sdwa_gfx10 :
1040      VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1041      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1042        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1043        let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
1044        let DecoderNamespace = "SDWA10";
1045      }
1046    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1047    def _sdwa_w32_gfx10 :
1048      Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1049      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1050        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1051        let AsmString = asmName # !subst("vcc", "vcc_lo", Ps.AsmOperands);
1052        let isAsmParserOnly = 1;
1053        let DecoderNamespace = "SDWA10";
1054        let WaveSizePredicate = isWave32;
1055      }
1056    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1057    def _sdwa_w64_gfx10 :
1058      Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1059      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1060        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1061        let AsmString = asmName # Ps.AsmOperands;
1062        let isAsmParserOnly = 1;
1063        let DecoderNamespace = "SDWA10";
1064        let WaveSizePredicate = isWave64;
1065      }
1066  }
1067  multiclass VOP2be_Real_dpp_gfx10<bits<6> op, string opName, string asmName> {
1068    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1069    def _dpp_gfx10 :
1070      VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1071        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1072        let AsmString = asmName # !subst(", vcc", "", AsmDPP);
1073        let DecoderNamespace = "SDWA10";
1074      }
1075    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1076    def _dpp_w32_gfx10 :
1077      Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1078        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1079        let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP);
1080        let isAsmParserOnly = 1;
1081        let WaveSizePredicate = isWave32;
1082      }
1083    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1084    def _dpp_w64_gfx10 :
1085      Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1086        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1087        let AsmString = asmName # AsmDPP;
1088        let isAsmParserOnly = 1;
1089        let WaveSizePredicate = isWave64;
1090      }
1091  }
1092  multiclass VOP2be_Real_dpp8_gfx10<bits<6> op, string opName, string asmName> {
1093    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1094    def _dpp8_gfx10 :
1095      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1096        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1097        let AsmString = asmName # !subst(", vcc", "", AsmDPP8);
1098        let DecoderNamespace = "DPP8";
1099      }
1100    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1101    def _dpp8_w32_gfx10 :
1102      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1103        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1104        let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8);
1105        let isAsmParserOnly = 1;
1106        let WaveSizePredicate = isWave32;
1107      }
1108    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1109    def _dpp8_w64_gfx10 :
1110      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1111        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1112        let AsmString = asmName # AsmDPP8;
1113        let isAsmParserOnly = 1;
1114        let WaveSizePredicate = isWave64;
1115      }
1116  }
1117
1118  //===----------------------------- VOP3Only -----------------------------===//
1119  multiclass VOP3Only_Real_gfx10<bits<10> op> {
1120    def _e64_gfx10 :
1121      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1122      VOP3e_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1123  }
1124
1125  //===---------------------------- VOP3beOnly ----------------------------===//
1126  multiclass VOP3beOnly_Real_gfx10<bits<10> op> {
1127    def _e64_gfx10 :
1128      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1129      VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1130  }
1131} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
1132
1133multiclass VOP2be_Real_gfx10<bits<6> op, string opName, string asmName> :
1134  VOP2be_Real_e32_gfx10<op, opName, asmName>,
1135  VOP2be_Real_e64_gfx10<op, opName, asmName>,
1136  VOP2be_Real_sdwa_gfx10<op, opName, asmName>,
1137  VOP2be_Real_dpp_gfx10<op, opName, asmName>,
1138  VOP2be_Real_dpp8_gfx10<op, opName, asmName>;
1139
1140multiclass VOP2e_Real_gfx10<bits<6> op, string opName, string asmName> :
1141  VOP2_Real_e32_gfx10<op>,
1142  VOP2_Real_e64_gfx10<op>,
1143  VOP2be_Real_sdwa_gfx10<op, opName, asmName>,
1144  VOP2be_Real_dpp_gfx10<op, opName, asmName>,
1145  VOP2be_Real_dpp8_gfx10<op, opName, asmName>;
1146
1147multiclass VOP2_Real_gfx10<bits<6> op> :
1148  VOP2_Real_e32_gfx10<op>, VOP2_Real_e64_gfx10<op>,
1149  VOP2_Real_sdwa_gfx10<op>, VOP2_Real_dpp_gfx10<op>, VOP2_Real_dpp8_gfx10<op>;
1150
1151multiclass VOP2_Real_gfx10_with_name<bits<6> op, string opName,
1152                                     string asmName> :
1153  VOP2_Real_e32_gfx10_with_name<op, opName, asmName>,
1154  VOP2_Real_e64_gfx10_with_name<op, opName, asmName>,
1155  VOP2_Real_sdwa_gfx10_with_name<op, opName, asmName>,
1156  VOP2_Real_dpp_gfx10_with_name<op, opName, asmName>,
1157  VOP2_Real_dpp8_gfx10_with_name<op, opName, asmName>;
1158
1159// NB: Same opcode as v_mac_legacy_f32
1160let DecoderNamespace = "GFX10_B" in
1161defm V_FMAC_LEGACY_F32 : VOP2_Real_gfx10<0x006>;
1162
1163defm V_XNOR_B32        : VOP2_Real_gfx10<0x01e>;
1164defm V_FMAC_F32        : VOP2_Real_gfx10<0x02b>;
1165defm V_FMAMK_F32       : VOP2Only_Real_MADK_gfx10<0x02c>;
1166defm V_FMAAK_F32       : VOP2Only_Real_MADK_gfx10<0x02d>;
1167defm V_ADD_F16         : VOP2_Real_gfx10<0x032>;
1168defm V_SUB_F16         : VOP2_Real_gfx10<0x033>;
1169defm V_SUBREV_F16      : VOP2_Real_gfx10<0x034>;
1170defm V_MUL_F16         : VOP2_Real_gfx10<0x035>;
1171defm V_FMAC_F16        : VOP2_Real_gfx10<0x036>;
1172defm V_FMAMK_F16       : VOP2Only_Real_MADK_gfx10<0x037>;
1173defm V_FMAAK_F16       : VOP2Only_Real_MADK_gfx10<0x038>;
1174defm V_MAX_F16         : VOP2_Real_gfx10<0x039>;
1175defm V_MIN_F16         : VOP2_Real_gfx10<0x03a>;
1176defm V_LDEXP_F16       : VOP2_Real_gfx10<0x03b>;
1177defm V_PK_FMAC_F16     : VOP2_Real_e32_gfx10<0x03c>;
1178
1179// VOP2 no carry-in, carry-out.
1180defm V_ADD_NC_U32 :
1181  VOP2_Real_gfx10_with_name<0x025, "V_ADD_U32", "v_add_nc_u32">;
1182defm V_SUB_NC_U32 :
1183  VOP2_Real_gfx10_with_name<0x026, "V_SUB_U32", "v_sub_nc_u32">;
1184defm V_SUBREV_NC_U32 :
1185  VOP2_Real_gfx10_with_name<0x027, "V_SUBREV_U32", "v_subrev_nc_u32">;
1186
1187// VOP2 carry-in, carry-out.
1188defm V_ADD_CO_CI_U32 :
1189  VOP2be_Real_gfx10<0x028, "V_ADDC_U32", "v_add_co_ci_u32">;
1190defm V_SUB_CO_CI_U32 :
1191  VOP2be_Real_gfx10<0x029, "V_SUBB_U32", "v_sub_co_ci_u32">;
1192defm V_SUBREV_CO_CI_U32 :
1193  VOP2be_Real_gfx10<0x02a, "V_SUBBREV_U32", "v_subrev_co_ci_u32">;
1194
1195defm V_CNDMASK_B32 :
1196  VOP2e_Real_gfx10<0x001, "V_CNDMASK_B32", "v_cndmask_b32">;
1197
1198// VOP3 only.
1199defm V_BFM_B32            : VOP3Only_Real_gfx10<0x363>;
1200defm V_BCNT_U32_B32       : VOP3Only_Real_gfx10<0x364>;
1201defm V_MBCNT_LO_U32_B32   : VOP3Only_Real_gfx10<0x365>;
1202defm V_MBCNT_HI_U32_B32   : VOP3Only_Real_gfx10<0x366>;
1203defm V_LDEXP_F32          : VOP3Only_Real_gfx10<0x362>;
1204defm V_CVT_PKNORM_I16_F32 : VOP3Only_Real_gfx10<0x368>;
1205defm V_CVT_PKNORM_U16_F32 : VOP3Only_Real_gfx10<0x369>;
1206defm V_CVT_PK_U16_U32     : VOP3Only_Real_gfx10<0x36a>;
1207defm V_CVT_PK_I16_I32     : VOP3Only_Real_gfx10<0x36b>;
1208
1209// VOP3 carry-out.
1210defm V_ADD_CO_U32 : VOP3beOnly_Real_gfx10<0x30f>;
1211defm V_SUB_CO_U32 : VOP3beOnly_Real_gfx10<0x310>;
1212defm V_SUBREV_CO_U32 : VOP3beOnly_Real_gfx10<0x319>;
1213
1214let SubtargetPredicate = isGFX10Plus in {
1215  defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx10>;
1216
1217  defm : VOP2bInstAliases<
1218    V_ADDC_U32_e32, V_ADD_CO_CI_U32_e32_gfx10, "v_add_co_ci_u32">;
1219  defm : VOP2bInstAliases<
1220    V_SUBB_U32_e32, V_SUB_CO_CI_U32_e32_gfx10, "v_sub_co_ci_u32">;
1221  defm : VOP2bInstAliases<
1222    V_SUBBREV_U32_e32, V_SUBREV_CO_CI_U32_e32_gfx10, "v_subrev_co_ci_u32">;
1223} // End SubtargetPredicate = isGFX10Plus
1224
1225//===----------------------------------------------------------------------===//
1226// GFX6, GFX7, GFX10.
1227//===----------------------------------------------------------------------===//
1228
1229class VOP2_DPPe <bits<6> op, VOP2_DPP_Pseudo ps, VOPProfile P = ps.Pfl> :
1230  VOP_DPPe <P> {
1231  bits<8> vdst;
1232  bits<8> src1;
1233  let Inst{8-0}   = 0xfa; //dpp
1234  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
1235  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
1236  let Inst{30-25} = op;
1237  let Inst{31}    = 0x0; //encoding
1238}
1239
1240let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
1241  multiclass VOP2Only_Real_gfx6_gfx7<bits<6> op> {
1242    def _gfx6_gfx7 :
1243      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1244      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1245  }
1246  multiclass VOP2Only_Real_MADK_gfx6_gfx7<bits<6> op> {
1247    def _gfx6_gfx7 :
1248      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1249      VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1250  }
1251  multiclass VOP2_Real_e32_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1252    def _e32_gfx6_gfx7 :
1253      VOP2_Real<!cast<VOP2_Pseudo>(PseudoName#"_e32"), SIEncodingFamily.SI>,
1254      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(PseudoName#"_e32").Pfl>;
1255  }
1256  multiclass VOP2_Real_e64_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1257    def _e64_gfx6_gfx7 :
1258      VOP3_Real<!cast<VOP3_Pseudo>(PseudoName#"_e64"), SIEncodingFamily.SI>,
1259      VOP3e_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(PseudoName#"_e64").Pfl>;
1260  }
1261  multiclass VOP2be_Real_e64_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1262    def _e64_gfx6_gfx7 :
1263      VOP3_Real<!cast<VOP3_Pseudo>(PseudoName#"_e64"), SIEncodingFamily.SI>,
1264      VOP3be_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(PseudoName#"_e64").Pfl>;
1265  }
1266} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
1267
1268multiclass VOP2Only_Real_MADK_gfx6_gfx7_gfx10<bits<6> op> :
1269  VOP2Only_Real_MADK_gfx6_gfx7<op>, VOP2Only_Real_MADK_gfx10<op>;
1270
1271multiclass VOP2_Real_gfx6_gfx7<bits<6> op> :
1272  VOP2_Real_e32_gfx6_gfx7<op>, VOP2_Real_e64_gfx6_gfx7<op>;
1273
1274multiclass VOP2_Real_gfx6_gfx7_gfx10<bits<6> op> :
1275  VOP2_Real_gfx6_gfx7<op>, VOP2_Real_gfx10<op>;
1276
1277multiclass VOP2be_Real_gfx6_gfx7<bits<6> op> :
1278  VOP2_Real_e32_gfx6_gfx7<op>, VOP2be_Real_e64_gfx6_gfx7<op>;
1279
1280multiclass VOP2be_Real_gfx6_gfx7_with_name<bits<6> op,
1281  string PseudoName, string asmName>  {
1282  defvar ps32 = !cast<VOP2_Pseudo>(PseudoName#"_e32");
1283  defvar ps64 = !cast<VOP3_Pseudo>(PseudoName#"_e64");
1284
1285  let AsmString = asmName # ps32.AsmOperands in {
1286    defm "" : VOP2_Real_e32_gfx6_gfx7<op, PseudoName>;
1287  }
1288
1289   let AsmString = asmName # ps64.AsmOperands in {
1290    defm "" : VOP2be_Real_e64_gfx6_gfx7<op, PseudoName>;
1291  }
1292}
1293
1294defm V_CNDMASK_B32        : VOP2_Real_gfx6_gfx7<0x000>;
1295defm V_MIN_LEGACY_F32     : VOP2_Real_gfx6_gfx7<0x00d>;
1296defm V_MAX_LEGACY_F32     : VOP2_Real_gfx6_gfx7<0x00e>;
1297defm V_LSHR_B32           : VOP2_Real_gfx6_gfx7<0x015>;
1298defm V_ASHR_I32           : VOP2_Real_gfx6_gfx7<0x017>;
1299defm V_LSHL_B32           : VOP2_Real_gfx6_gfx7<0x019>;
1300defm V_BFM_B32            : VOP2_Real_gfx6_gfx7<0x01e>;
1301defm V_BCNT_U32_B32       : VOP2_Real_gfx6_gfx7<0x022>;
1302defm V_MBCNT_LO_U32_B32   : VOP2_Real_gfx6_gfx7<0x023>;
1303defm V_MBCNT_HI_U32_B32   : VOP2_Real_gfx6_gfx7<0x024>;
1304defm V_LDEXP_F32          : VOP2_Real_gfx6_gfx7<0x02b>;
1305defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_gfx6_gfx7<0x02c>;
1306defm V_CVT_PKNORM_I16_F32 : VOP2_Real_gfx6_gfx7<0x02d>;
1307defm V_CVT_PKNORM_U16_F32 : VOP2_Real_gfx6_gfx7<0x02e>;
1308defm V_CVT_PK_U16_U32     : VOP2_Real_gfx6_gfx7<0x030>;
1309defm V_CVT_PK_I16_I32     : VOP2_Real_gfx6_gfx7<0x031>;
1310
1311// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in
1312// VI, but the VI instructions behave the same as the SI versions.
1313defm V_ADD_I32            : VOP2be_Real_gfx6_gfx7_with_name<0x025, "V_ADD_CO_U32", "v_add_i32">;
1314defm V_SUB_I32            : VOP2be_Real_gfx6_gfx7_with_name<0x026, "V_SUB_CO_U32", "v_sub_i32">;
1315defm V_SUBREV_I32         : VOP2be_Real_gfx6_gfx7_with_name<0x027, "V_SUBREV_CO_U32", "v_subrev_i32">;
1316defm V_ADDC_U32           : VOP2be_Real_gfx6_gfx7<0x028>;
1317defm V_SUBB_U32           : VOP2be_Real_gfx6_gfx7<0x029>;
1318defm V_SUBBREV_U32        : VOP2be_Real_gfx6_gfx7<0x02a>;
1319
1320defm V_READLANE_B32 : VOP2Only_Real_gfx6_gfx7<0x001>;
1321
1322let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
1323  defm V_WRITELANE_B32 : VOP2Only_Real_gfx6_gfx7<0x002>;
1324} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)
1325
1326let SubtargetPredicate = isGFX6GFX7 in {
1327  defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx6_gfx7>;
1328  defm : VOP2eInstAliases<V_ADD_CO_U32_e32, V_ADD_I32_e32_gfx6_gfx7>;
1329  defm : VOP2eInstAliases<V_SUB_CO_U32_e32, V_SUB_I32_e32_gfx6_gfx7>;
1330  defm : VOP2eInstAliases<V_SUBREV_CO_U32_e32, V_SUBREV_I32_e32_gfx6_gfx7>;
1331
1332  def : VOP2e64InstAlias<V_ADD_CO_U32_e64, V_ADD_I32_e64_gfx6_gfx7>;
1333  def : VOP2e64InstAlias<V_SUB_CO_U32_e64, V_SUB_I32_e64_gfx6_gfx7>;
1334  def : VOP2e64InstAlias<V_SUBREV_CO_U32_e64, V_SUBREV_I32_e64_gfx6_gfx7>;
1335} // End SubtargetPredicate = isGFX6GFX7
1336
1337defm V_ADD_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x003>;
1338defm V_SUB_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x004>;
1339defm V_SUBREV_F32         : VOP2_Real_gfx6_gfx7_gfx10<0x005>;
1340defm V_MAC_LEGACY_F32     : VOP2_Real_gfx6_gfx7_gfx10<0x006>;
1341defm V_MUL_LEGACY_F32     : VOP2_Real_gfx6_gfx7_gfx10<0x007>;
1342defm V_MUL_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x008>;
1343defm V_MUL_I32_I24        : VOP2_Real_gfx6_gfx7_gfx10<0x009>;
1344defm V_MUL_HI_I32_I24     : VOP2_Real_gfx6_gfx7_gfx10<0x00a>;
1345defm V_MUL_U32_U24        : VOP2_Real_gfx6_gfx7_gfx10<0x00b>;
1346defm V_MUL_HI_U32_U24     : VOP2_Real_gfx6_gfx7_gfx10<0x00c>;
1347defm V_MIN_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x00f>;
1348defm V_MAX_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x010>;
1349defm V_MIN_I32            : VOP2_Real_gfx6_gfx7_gfx10<0x011>;
1350defm V_MAX_I32            : VOP2_Real_gfx6_gfx7_gfx10<0x012>;
1351defm V_MIN_U32            : VOP2_Real_gfx6_gfx7_gfx10<0x013>;
1352defm V_MAX_U32            : VOP2_Real_gfx6_gfx7_gfx10<0x014>;
1353defm V_LSHRREV_B32        : VOP2_Real_gfx6_gfx7_gfx10<0x016>;
1354defm V_ASHRREV_I32        : VOP2_Real_gfx6_gfx7_gfx10<0x018>;
1355defm V_LSHLREV_B32        : VOP2_Real_gfx6_gfx7_gfx10<0x01a>;
1356defm V_AND_B32            : VOP2_Real_gfx6_gfx7_gfx10<0x01b>;
1357defm V_OR_B32             : VOP2_Real_gfx6_gfx7_gfx10<0x01c>;
1358defm V_XOR_B32            : VOP2_Real_gfx6_gfx7_gfx10<0x01d>;
1359defm V_MAC_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x01f>;
1360defm V_CVT_PKRTZ_F16_F32  : VOP2_Real_gfx6_gfx7_gfx10<0x02f>;
1361defm V_MADMK_F32          : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x020>;
1362defm V_MADAK_F32          : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x021>;
1363
1364//===----------------------------------------------------------------------===//
1365// GFX8, GFX9 (VI).
1366//===----------------------------------------------------------------------===//
1367
1368let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {
1369
1370multiclass VOP2_Real_MADK_vi <bits<6> op> {
1371  def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,
1372            VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1373}
1374
1375multiclass VOP2_Real_e32_vi <bits<6> op> {
1376  def _e32_vi :
1377    VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
1378    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
1379}
1380
1381multiclass VOP2_Real_e64_vi <bits<10> op> {
1382  def _e64_vi :
1383    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
1384    VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1385}
1386
1387multiclass VOP2_Real_e64only_vi <bits<10> op> {
1388  def _e64_vi :
1389    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
1390    VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1391      // Hack to stop printing _e64
1392      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME#"_e64");
1393      let OutOperandList = (outs VGPR_32:$vdst);
1394      let AsmString = ps.Mnemonic # " " # ps.AsmOperands;
1395    }
1396}
1397
1398multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> :
1399  VOP2_Real_e32_vi<op>,
1400  VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>;
1401
1402} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8"
1403
1404multiclass VOP2_SDWA_Real <bits<6> op> {
1405  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA>.ret in
1406  def _sdwa_vi :
1407    VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1408    VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1409}
1410
1411multiclass VOP2_SDWA9_Real <bits<6> op> {
1412  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
1413  def _sdwa_gfx9 :
1414    VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1415    VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1416}
1417
1418let AssemblerPredicate = isGFX8Only in {
1419
1420multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName> {
1421  def _e32_vi :
1422    VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.VI>,
1423    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
1424      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32");
1425      let AsmString = AsmName # ps.AsmOperands;
1426      let DecoderNamespace = "GFX8";
1427    }
1428  def _e64_vi :
1429    VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.VI>,
1430    VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
1431      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64");
1432      let AsmString = AsmName # ps.AsmOperands;
1433      let DecoderNamespace = "GFX8";
1434    }
1435  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA>.ret in
1436    def _sdwa_vi :
1437      VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>,
1438      VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {
1439        VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa");
1440        let AsmString = AsmName # ps.AsmOperands;
1441      }
1442  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in
1443    def _dpp_vi :
1444      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.VI>,
1445      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> {
1446        VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp");
1447        let AsmString = AsmName # ps.AsmOperands;
1448      }
1449}
1450}
1451
1452let AssemblerPredicate = isGFX9Only in {
1453
1454multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> {
1455  def _e32_gfx9 :
1456    VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.GFX9>,
1457    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
1458      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32");
1459      let AsmString = AsmName # ps.AsmOperands;
1460      let DecoderNamespace = "GFX9";
1461    }
1462  def _e64_gfx9 :
1463    VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>,
1464    VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
1465      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64");
1466      let AsmString = AsmName # ps.AsmOperands;
1467      let DecoderNamespace = "GFX9";
1468    }
1469  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA9>.ret in
1470    def _sdwa_gfx9 :
1471      VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>,
1472      VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {
1473        VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa");
1474        let AsmString = AsmName # ps.AsmOperands;
1475      }
1476  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in
1477    def _dpp_gfx9 :
1478      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.GFX9>,
1479      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> {
1480        VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp");
1481        let AsmString = AsmName # ps.AsmOperands;
1482        let DecoderNamespace = "SDWA9";
1483      }
1484}
1485
1486multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> {
1487  def _e32_gfx9 :
1488    VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX9>,
1489    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>{
1490      let DecoderNamespace = "GFX9";
1491    }
1492  def _e64_gfx9 :
1493    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>,
1494    VOP3e_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1495      let DecoderNamespace = "GFX9";
1496    }
1497  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
1498    def _sdwa_gfx9 :
1499      VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1500      VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
1501      }
1502  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
1503    def _dpp_gfx9 :
1504      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,
1505      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
1506        let DecoderNamespace = "SDWA9";
1507      }
1508}
1509
1510} // AssemblerPredicate = isGFX9Only
1511
1512multiclass VOP2_Real_e32e64_vi <bits<6> op> :
1513  Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> {
1514
1515  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
1516    def _dpp_vi :
1517      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.VI>,
1518      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;
1519}
1520
1521defm V_CNDMASK_B32        : VOP2_Real_e32e64_vi <0x0>;
1522defm V_ADD_F32            : VOP2_Real_e32e64_vi <0x1>;
1523defm V_SUB_F32            : VOP2_Real_e32e64_vi <0x2>;
1524defm V_SUBREV_F32         : VOP2_Real_e32e64_vi <0x3>;
1525defm V_MUL_LEGACY_F32     : VOP2_Real_e32e64_vi <0x4>;
1526defm V_MUL_F32            : VOP2_Real_e32e64_vi <0x5>;
1527defm V_MUL_I32_I24        : VOP2_Real_e32e64_vi <0x6>;
1528defm V_MUL_HI_I32_I24     : VOP2_Real_e32e64_vi <0x7>;
1529defm V_MUL_U32_U24        : VOP2_Real_e32e64_vi <0x8>;
1530defm V_MUL_HI_U32_U24     : VOP2_Real_e32e64_vi <0x9>;
1531defm V_MIN_F32            : VOP2_Real_e32e64_vi <0xa>;
1532defm V_MAX_F32            : VOP2_Real_e32e64_vi <0xb>;
1533defm V_MIN_I32            : VOP2_Real_e32e64_vi <0xc>;
1534defm V_MAX_I32            : VOP2_Real_e32e64_vi <0xd>;
1535defm V_MIN_U32            : VOP2_Real_e32e64_vi <0xe>;
1536defm V_MAX_U32            : VOP2_Real_e32e64_vi <0xf>;
1537defm V_LSHRREV_B32        : VOP2_Real_e32e64_vi <0x10>;
1538defm V_ASHRREV_I32        : VOP2_Real_e32e64_vi <0x11>;
1539defm V_LSHLREV_B32        : VOP2_Real_e32e64_vi <0x12>;
1540defm V_AND_B32            : VOP2_Real_e32e64_vi <0x13>;
1541defm V_OR_B32             : VOP2_Real_e32e64_vi <0x14>;
1542defm V_XOR_B32            : VOP2_Real_e32e64_vi <0x15>;
1543defm V_MAC_F32            : VOP2_Real_e32e64_vi <0x16>;
1544defm V_MADMK_F32          : VOP2_Real_MADK_vi <0x17>;
1545defm V_MADAK_F32          : VOP2_Real_MADK_vi <0x18>;
1546
1547defm V_ADD_U32            : VOP2be_Real_e32e64_vi_only <0x19, "V_ADD_CO_U32",     "v_add_u32">;
1548defm V_SUB_U32            : VOP2be_Real_e32e64_vi_only <0x1a, "V_SUB_CO_U32",     "v_sub_u32">;
1549defm V_SUBREV_U32         : VOP2be_Real_e32e64_vi_only <0x1b, "V_SUBREV_CO_U32",  "v_subrev_u32">;
1550defm V_ADDC_U32           : VOP2be_Real_e32e64_vi_only <0x1c, "V_ADDC_U32",    "v_addc_u32">;
1551defm V_SUBB_U32           : VOP2be_Real_e32e64_vi_only <0x1d, "V_SUBB_U32",    "v_subb_u32">;
1552defm V_SUBBREV_U32        : VOP2be_Real_e32e64_vi_only <0x1e, "V_SUBBREV_U32", "v_subbrev_u32">;
1553
1554defm V_ADD_CO_U32         : VOP2be_Real_e32e64_gfx9 <0x19, "V_ADD_CO_U32",     "v_add_co_u32">;
1555defm V_SUB_CO_U32         : VOP2be_Real_e32e64_gfx9 <0x1a, "V_SUB_CO_U32",     "v_sub_co_u32">;
1556defm V_SUBREV_CO_U32      : VOP2be_Real_e32e64_gfx9 <0x1b, "V_SUBREV_CO_U32",  "v_subrev_co_u32">;
1557defm V_ADDC_CO_U32        : VOP2be_Real_e32e64_gfx9 <0x1c, "V_ADDC_U32",    "v_addc_co_u32">;
1558defm V_SUBB_CO_U32        : VOP2be_Real_e32e64_gfx9 <0x1d, "V_SUBB_U32",    "v_subb_co_u32">;
1559defm V_SUBBREV_CO_U32     : VOP2be_Real_e32e64_gfx9 <0x1e, "V_SUBBREV_U32", "v_subbrev_co_u32">;
1560
1561defm V_ADD_U32            : VOP2_Real_e32e64_gfx9 <0x34>;
1562defm V_SUB_U32            : VOP2_Real_e32e64_gfx9 <0x35>;
1563defm V_SUBREV_U32         : VOP2_Real_e32e64_gfx9 <0x36>;
1564
1565defm V_BFM_B32            : VOP2_Real_e64only_vi <0x293>;
1566defm V_BCNT_U32_B32       : VOP2_Real_e64only_vi <0x28b>;
1567defm V_MBCNT_LO_U32_B32   : VOP2_Real_e64only_vi <0x28c>;
1568defm V_MBCNT_HI_U32_B32   : VOP2_Real_e64only_vi <0x28d>;
1569defm V_LDEXP_F32          : VOP2_Real_e64only_vi <0x288>;
1570defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64only_vi <0x1f0>;
1571defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64only_vi <0x294>;
1572defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64only_vi <0x295>;
1573defm V_CVT_PKRTZ_F16_F32  : VOP2_Real_e64only_vi <0x296>;
1574defm V_CVT_PK_U16_U32     : VOP2_Real_e64only_vi <0x297>;
1575defm V_CVT_PK_I16_I32     : VOP2_Real_e64only_vi <0x298>;
1576
1577defm V_ADD_F16            : VOP2_Real_e32e64_vi <0x1f>;
1578defm V_SUB_F16            : VOP2_Real_e32e64_vi <0x20>;
1579defm V_SUBREV_F16         : VOP2_Real_e32e64_vi <0x21>;
1580defm V_MUL_F16            : VOP2_Real_e32e64_vi <0x22>;
1581defm V_MAC_F16            : VOP2_Real_e32e64_vi <0x23>;
1582defm V_MADMK_F16          : VOP2_Real_MADK_vi <0x24>;
1583defm V_MADAK_F16          : VOP2_Real_MADK_vi <0x25>;
1584defm V_ADD_U16            : VOP2_Real_e32e64_vi <0x26>;
1585defm V_SUB_U16            : VOP2_Real_e32e64_vi <0x27>;
1586defm V_SUBREV_U16         : VOP2_Real_e32e64_vi <0x28>;
1587defm V_MUL_LO_U16         : VOP2_Real_e32e64_vi <0x29>;
1588defm V_LSHLREV_B16        : VOP2_Real_e32e64_vi <0x2a>;
1589defm V_LSHRREV_B16        : VOP2_Real_e32e64_vi <0x2b>;
1590defm V_ASHRREV_I16        : VOP2_Real_e32e64_vi <0x2c>;
1591defm V_MAX_F16            : VOP2_Real_e32e64_vi <0x2d>;
1592defm V_MIN_F16            : VOP2_Real_e32e64_vi <0x2e>;
1593defm V_MAX_U16            : VOP2_Real_e32e64_vi <0x2f>;
1594defm V_MAX_I16            : VOP2_Real_e32e64_vi <0x30>;
1595defm V_MIN_U16            : VOP2_Real_e32e64_vi <0x31>;
1596defm V_MIN_I16            : VOP2_Real_e32e64_vi <0x32>;
1597defm V_LDEXP_F16          : VOP2_Real_e32e64_vi <0x33>;
1598
1599let SubtargetPredicate = isGFX8GFX9 in {
1600
1601// Aliases to simplify matching of floating-point instructions that
1602// are VOP2 on SI and VOP3 on VI.
1603class SI2_VI3Alias <string name, VOP3_Real inst> : InstAlias <
1604  name#" $dst, $src0, $src1",
1605  !if(inst.Pfl.HasOMod,
1606      (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0),
1607      (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0))
1608>, PredicateControl {
1609  let UseInstAsmMatchConverter = 0;
1610  let AsmVariantName = AMDGPUAsmVariants.VOP3;
1611}
1612
1613def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>;
1614def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>;
1615def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>;
1616def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;
1617def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;
1618
1619defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_vi>;
1620
1621} // End SubtargetPredicate = isGFX8GFX9
1622
1623let SubtargetPredicate = isGFX9Only in {
1624
1625defm : VOP2bInstAliases<V_ADD_U32_e32,     V_ADD_CO_U32_e32_gfx9,     "v_add_co_u32">;
1626defm : VOP2bInstAliases<V_ADDC_U32_e32,    V_ADDC_CO_U32_e32_gfx9,    "v_addc_co_u32">;
1627defm : VOP2bInstAliases<V_SUB_U32_e32,     V_SUB_CO_U32_e32_gfx9,     "v_sub_co_u32">;
1628defm : VOP2bInstAliases<V_SUBB_U32_e32,    V_SUBB_CO_U32_e32_gfx9,    "v_subb_co_u32">;
1629defm : VOP2bInstAliases<V_SUBREV_U32_e32,  V_SUBREV_CO_U32_e32_gfx9,  "v_subrev_co_u32">;
1630defm : VOP2bInstAliases<V_SUBBREV_U32_e32, V_SUBBREV_CO_U32_e32_gfx9, "v_subbrev_co_u32">;
1631
1632} // End SubtargetPredicate = isGFX9Only
1633
1634let SubtargetPredicate = HasDLInsts in {
1635
1636defm V_FMAC_F32 : VOP2_Real_e32e64_vi <0x3b>;
1637defm V_XNOR_B32 : VOP2_Real_e32e64_vi <0x3d>;
1638
1639} // End SubtargetPredicate = HasDLInsts
1640
1641multiclass VOP2_Real_DOT_ACC_gfx9<bits<6> op> : VOP2_Real_e32_vi<op> {
1642  def _dpp_vi : VOP2_DPP<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;
1643}
1644
1645multiclass VOP2_Real_DOT_ACC_gfx10<bits<6> op> :
1646  VOP2_Real_e32_gfx10<op>,
1647  VOP2_Real_dpp_gfx10<op>,
1648  VOP2_Real_dpp8_gfx10<op>;
1649
1650let SubtargetPredicate = HasDot5Insts in {
1651  defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx9<0x37>;
1652  // NB: Opcode conflicts with V_DOT8C_I32_I4
1653  // This opcode exists in gfx 10.1* only
1654  defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx10<0x02>;
1655}
1656
1657let SubtargetPredicate = HasDot6Insts in {
1658  defm V_DOT4C_I32_I8  : VOP2_Real_DOT_ACC_gfx9<0x39>;
1659  defm V_DOT4C_I32_I8  : VOP2_Real_DOT_ACC_gfx10<0x0d>;
1660}
1661
1662let SubtargetPredicate = HasDot4Insts in {
1663  defm V_DOT2C_I32_I16 : VOP2_Real_DOT_ACC_gfx9<0x38>;
1664}
1665let SubtargetPredicate = HasDot3Insts in {
1666  defm V_DOT8C_I32_I4  : VOP2_Real_DOT_ACC_gfx9<0x3a>;
1667}
1668
1669let SubtargetPredicate = HasPkFmacF16Inst in {
1670defm V_PK_FMAC_F16 : VOP2_Real_e32_vi<0x3c>;
1671} // End SubtargetPredicate = HasPkFmacF16Inst
1672
1673let SubtargetPredicate = HasDot3Insts in {
1674  // NB: Opcode conflicts with V_DOT2C_F32_F16
1675  let DecoderNamespace = "GFX10_B" in
1676  defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx10<0x02>;
1677}
1678