1//===-- VOP2Instructions.td - Vector Instruction Definitions --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// VOP2 Classes
11//===----------------------------------------------------------------------===//
12
13class VOP2e <bits<6> op, VOPProfile P> : Enc32 {
14  bits<8> vdst;
15  bits<9> src0;
16  bits<8> src1;
17
18  let Inst{8-0}   = !if(P.HasSrc0, src0, 0);
19  let Inst{16-9}  = !if(P.HasSrc1, src1, 0);
20  let Inst{24-17} = !if(P.EmitDst, vdst, 0);
21  let Inst{30-25} = op;
22  let Inst{31}    = 0x0; //encoding
23}
24
25class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 {
26  bits<8>  vdst;
27  bits<9>  src0;
28  bits<8>  src1;
29  bits<32> imm;
30
31  let Inst{8-0}   = !if(P.HasSrc0, src0, 0);
32  let Inst{16-9}  = !if(P.HasSrc1, src1, 0);
33  let Inst{24-17} = !if(P.EmitDst, vdst, 0);
34  let Inst{30-25} = op;
35  let Inst{31}    = 0x0; // encoding
36  let Inst{63-32} = imm;
37}
38
39class VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> {
40  bits<8> vdst;
41  bits<8> src1;
42
43  let Inst{8-0}   = 0xf9; // sdwa
44  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
45  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
46  let Inst{30-25} = op;
47  let Inst{31}    = 0x0; // encoding
48}
49
50class VOP2_SDWA9Ae <bits<6> op, VOPProfile P> : VOP_SDWA9Ae <P> {
51  bits<8> vdst;
52  bits<9> src1;
53
54  let Inst{8-0}   = 0xf9; // sdwa
55  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
56  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
57  let Inst{30-25} = op;
58  let Inst{31}    = 0x0; // encoding
59  let Inst{63}    = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr
60}
61
62class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> :
63  VOP_Pseudo <opName, suffix, P, P.Outs32, P.Ins32, "", pattern> {
64
65  let AsmOperands = P.Asm32;
66
67  let Size = 4;
68  let mayLoad = 0;
69  let mayStore = 0;
70  let hasSideEffects = 0;
71
72  let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
73
74  let mayRaiseFPException = ReadsModeReg;
75
76  let VOP2 = 1;
77  let VALU = 1;
78  let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
79
80  let AsmVariantName = AMDGPUAsmVariants.Default;
81}
82
83class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> :
84  InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
85  SIMCInstr <ps.PseudoInstr, EncodingFamily> {
86
87  let isPseudo = 0;
88  let isCodeGenOnly = 0;
89
90  let Constraints     = ps.Constraints;
91  let DisableEncoding = ps.DisableEncoding;
92
93  // copy relevant pseudo op flags
94  let SubtargetPredicate = ps.SubtargetPredicate;
95  let AsmMatchConverter  = ps.AsmMatchConverter;
96  let AsmVariantName     = ps.AsmVariantName;
97  let Constraints        = ps.Constraints;
98  let DisableEncoding    = ps.DisableEncoding;
99  let TSFlags            = ps.TSFlags;
100  let UseNamedOperandTable = ps.UseNamedOperandTable;
101  let Uses                 = ps.Uses;
102  let Defs                 = ps.Defs;
103}
104
105class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
106  VOP_SDWA_Pseudo <OpName, P, pattern> {
107  let AsmMatchConverter = "cvtSdwaVOP2";
108}
109
110class VOP2_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
111  VOP_DPP_Pseudo <OpName, P, pattern> {
112}
113
114
115class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies {
116  list<dag> ret = !if(P.HasModifiers,
117    [(set P.DstVT:$vdst,
118      (node (P.Src0VT
119              !if(P.HasOMod,
120                  (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
121                  (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
122            (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
123    [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
124}
125
126multiclass VOP2Inst_e32<string opName,
127                        VOPProfile P,
128                        SDPatternOperator node = null_frag,
129                        string revOp = opName,
130                        bit GFX9Renamed = 0> {
131  let renamedInGFX9 = GFX9Renamed in {
132    def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
133               Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
134  } // End renamedInGFX9 = GFX9Renamed
135}
136
137multiclass VOP2Inst_e64<string opName,
138                        VOPProfile P,
139                        SDPatternOperator node = null_frag,
140                        string revOp = opName,
141                        bit GFX9Renamed = 0> {
142  let renamedInGFX9 = GFX9Renamed in {
143    def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
144               Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
145  } // End renamedInGFX9 = GFX9Renamed
146}
147
148multiclass VOP2Inst_sdwa<string opName,
149                         VOPProfile P,
150                         SDPatternOperator node = null_frag,
151                         string revOp = opName,
152                         bit GFX9Renamed = 0> {
153  let renamedInGFX9 = GFX9Renamed in {
154    foreach _ = BoolToList<P.HasExtSDWA>.ret in
155      def _sdwa : VOP2_SDWA_Pseudo <opName, P>;
156  } // End renamedInGFX9 = GFX9Renamed
157}
158
159multiclass VOP2Inst<string opName,
160                    VOPProfile P,
161                    SDPatternOperator node = null_frag,
162                    string revOp = opName,
163                    bit GFX9Renamed = 0> :
164    VOP2Inst_e32<opName, P, node, revOp, GFX9Renamed>,
165    VOP2Inst_e64<opName, P, node, revOp, GFX9Renamed>,
166    VOP2Inst_sdwa<opName, P, node, revOp, GFX9Renamed> {
167  let renamedInGFX9 = GFX9Renamed in {
168    foreach _ = BoolToList<P.HasExtDPP>.ret in
169      def _dpp  : VOP2_DPP_Pseudo <opName, P>;
170  }
171}
172
173multiclass VOP2bInst <string opName,
174                      VOPProfile P,
175                      SDPatternOperator node = null_frag,
176                      string revOp = opName,
177                      bit GFX9Renamed = 0,
178                      bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
179  let renamedInGFX9 = GFX9Renamed in {
180    let SchedRW = [Write32Bit, WriteSALU] in {
181      let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
182        def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
183                   Commutable_REV<revOp#"_e32", !eq(revOp, opName)> {
184          let usesCustomInserter = !eq(P.NumSrcArgs, 2);
185        }
186
187        foreach _ = BoolToList<P.HasExtSDWA>.ret in
188          def _sdwa  : VOP2_SDWA_Pseudo <opName, P> {
189            let AsmMatchConverter = "cvtSdwaVOP2b";
190          }
191        foreach _ = BoolToList<P.HasExtDPP>.ret in
192          def _dpp  : VOP2_DPP_Pseudo <opName, P>;
193      }
194
195      def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
196                 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
197    }
198  }
199}
200
201class VOP2bInstAlias <VOP2_Pseudo ps, Instruction inst,
202                      string OpName, string opnd> :
203  InstAlias <OpName#" "#!subst("vcc", opnd, ps.Pfl.Asm32),
204             (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
205                   ps.Pfl.Src1RC32:$src1)>,
206  PredicateControl {
207}
208
209multiclass VOP2bInstAliases<VOP2_Pseudo ps, VOP2_Real inst, string OpName> {
210  let WaveSizePredicate = isWave32 in {
211    def : VOP2bInstAlias<ps, inst, OpName, "vcc_lo">;
212  }
213  let WaveSizePredicate = isWave64 in {
214    def : VOP2bInstAlias<ps, inst, OpName, "vcc">;
215  }
216}
217
218multiclass VOP2eInst <string opName,
219                      VOPProfile P,
220                      SDPatternOperator node = null_frag,
221                      string revOp = opName,
222                      bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
223
224  let SchedRW = [Write32Bit] in {
225    let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in {
226      def _e32 : VOP2_Pseudo <opName, P>,
227                 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
228
229      foreach _ = BoolToList<P.HasExtSDWA>.ret in
230        def _sdwa : VOP2_SDWA_Pseudo <opName, P> {
231          let AsmMatchConverter = "cvtSdwaVOP2e";
232        }
233
234      foreach _ = BoolToList<P.HasExtDPP>.ret in
235        def _dpp  : VOP2_DPP_Pseudo <opName, P>;
236    }
237
238    def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
239               Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
240  }
241}
242
243class VOP2eInstAlias <VOP2_Pseudo ps, Instruction inst, string opnd = ""> :
244  InstAlias <ps.OpName#" "#ps.Pfl.Asm32#", "#opnd,
245             (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
246                   ps.Pfl.Src1RC32:$src1)>, PredicateControl;
247
248class VOP2e64InstAlias <VOP3_Pseudo ps, Instruction inst> :
249  InstAlias <ps.OpName#" "#ps.Pfl.Asm64,
250             (inst ps.Pfl.DstRC:$vdst, VOPDstS64orS32:$sdst,
251                   ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, clampmod:$clamp)>,
252  PredicateControl;
253
254multiclass VOP2eInstAliases<VOP2_Pseudo ps, VOP2_Real inst> {
255  let WaveSizePredicate = isWave32 in {
256    def : VOP2eInstAlias<ps, inst, "vcc_lo">;
257  }
258  let WaveSizePredicate = isWave64 in {
259    def : VOP2eInstAlias<ps, inst, "vcc">;
260  }
261}
262
263class VOP_MADAK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
264  field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
265  field dag Ins32 = !if(!eq(vt.Size, 32),
266                        (ins VCSrc_f32:$src0, VGPR_32:$src1, ImmOpType:$imm),
267                        (ins VCSrc_f16:$src0, VGPR_32:$src1, ImmOpType:$imm));
268  field bit HasExt = 0;
269
270  // Hack to stop printing _e64
271  let DstRC = RegisterOperand<VGPR_32>;
272  field string Asm32 = " $vdst, $src0, $src1, $imm";
273}
274
275def VOP_MADAK_F16 : VOP_MADAK <f16>;
276def VOP_MADAK_F32 : VOP_MADAK <f32>;
277
278class VOP_MADMK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
279  field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
280  field dag Ins32 = (ins VCSrc_f32:$src0, ImmOpType:$imm, VGPR_32:$src1);
281  field bit HasExt = 0;
282
283  // Hack to stop printing _e64
284  let DstRC = RegisterOperand<VGPR_32>;
285  field string Asm32 = " $vdst, $src0, $imm, $src1";
286}
287
288def VOP_MADMK_F16 : VOP_MADMK <f16>;
289def VOP_MADMK_F32 : VOP_MADMK <f32>;
290
291// FIXME: Remove src2_modifiers. It isn't used, so is wasting memory
292// and processing time but it makes it easier to convert to mad.
293class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, vt0]> {
294  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
295  let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
296                       0, HasModifiers, HasModifiers, HasOMod,
297                       Src0Mod, Src1Mod, Src2Mod>.ret;
298  let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
299                    Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
300                    VGPR_32:$src2, // stub argument
301                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
302                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
303  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
304
305  let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
306                     Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
307                     VGPR_32:$src2, // stub argument
308                     dpp8:$dpp8, FI:$fi);
309
310  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
311                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
312                     VGPR_32:$src2, // stub argument
313                     clampmod:$clamp, omod:$omod,
314                     dst_sel:$dst_sel, dst_unused:$dst_unused,
315                     src0_sel:$src0_sel, src1_sel:$src1_sel);
316  let Asm32 = getAsm32<1, 2, vt0>.ret;
317  let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, vt0>.ret;
318  let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt0>.ret;
319  let AsmDPP16 = getAsmDPP16<1, 2, HasModifiers, vt0>.ret;
320  let AsmDPP8 = getAsmDPP8<1, 2, 0, vt0>.ret;
321  let AsmSDWA = getAsmSDWA<1, 2, vt0>.ret;
322  let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt0>.ret;
323  let HasSrc2 = 0;
324  let HasSrc2Mods = 0;
325
326  let HasExt = 1;
327  let HasExtDPP = 1;
328  let HasExtSDWA = 1;
329  let HasExtSDWA9 = 0;
330  let TieRegDPP = "$src2";
331}
332
333def VOP_MAC_F16 : VOP_MAC <f16>;
334def VOP_MAC_F32 : VOP_MAC <f32>;
335
336class VOP_DOT_ACC<ValueType vt0, ValueType vt1> : VOP_MAC<vt0, vt1> {
337  let HasClamp = 0;
338  let HasExtSDWA = 0;
339  let HasModifiers = 1;
340  let HasOpSel = 0;
341  let IsPacked = 0;
342}
343
344def VOP_DOT_ACC_F32_V2F16 : VOP_DOT_ACC<f32, v2f16> {
345  let Src0ModDPP = FPVRegInputMods;
346  let Src1ModDPP = FPVRegInputMods;
347}
348def VOP_DOT_ACC_I32_I32   : VOP_DOT_ACC<i32, i32>;
349
350// Write out to vcc or arbitrary SGPR.
351def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], 0, /*EnableClamp=*/1> {
352  let Asm32 = "$vdst, vcc, $src0, $src1";
353  let Asm64 = "$vdst, $sdst, $src0, $src1$clamp";
354  let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
355  let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
356  let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
357  let AsmDPP8 = "$vdst, vcc, $src0, $src1 $dpp8$fi";
358  let AsmDPP16 = AsmDPP#"$fi";
359  let Outs32 = (outs DstRC:$vdst);
360  let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
361}
362
363// Write out to vcc or arbitrary SGPR and read in from vcc or
364// arbitrary SGPR.
365def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], 0, /*EnableClamp=*/1> {
366  let Asm32 = "$vdst, vcc, $src0, $src1, vcc";
367  let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
368  let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel";
369  let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel";
370  let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
371  let AsmDPP8 = "$vdst, vcc, $src0, $src1, vcc $dpp8$fi";
372  let AsmDPP16 = AsmDPP#"$fi";
373  let Outs32 = (outs DstRC:$vdst);
374  let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
375
376  // Suppress src2 implied by type since the 32-bit encoding uses an
377  // implicit VCC use.
378  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
379
380  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
381                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
382                     clampmod:$clamp,
383                     dst_sel:$dst_sel, dst_unused:$dst_unused,
384                     src0_sel:$src0_sel, src1_sel:$src1_sel);
385
386  let InsDPP = (ins DstRCDPP:$old,
387                    Src0DPP:$src0,
388                    Src1DPP:$src1,
389                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
390                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
391  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
392
393  let HasExt = 1;
394  let HasExtDPP = 1;
395  let HasExtSDWA = 1;
396  let HasExtSDWA9 = 1;
397}
398
399// Read in from vcc or arbitrary SGPR.
400def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], /*EnableF32SrcMods=*/1> {
401  let Asm32 = "$vdst, $src0, $src1";
402  let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2";
403  let AsmSDWA = "$vdst, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel";
404  let AsmSDWA9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel";
405  let AsmDPP = "$vdst, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
406  let AsmDPP8 = "$vdst, $src0, $src1, vcc $dpp8$fi";
407  let AsmDPP16 = AsmDPP#"$fi";
408
409  let Outs32 = (outs DstRC:$vdst);
410  let Outs64 = (outs DstRC:$vdst);
411
412  // Suppress src2 implied by type since the 32-bit encoding uses an
413  // implicit VCC use.
414  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
415
416  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
417                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
418                     clampmod:$clamp,
419                     dst_sel:$dst_sel, dst_unused:$dst_unused,
420                     src0_sel:$src0_sel, src1_sel:$src1_sel);
421
422  let InsDPP = (ins DstRCDPP:$old,
423                    Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
424                    Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
425                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
426                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
427  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
428
429  let HasExt = 1;
430  let HasExtDPP = 1;
431  let HasExtSDWA = 1;
432  let HasExtSDWA9 = 1;
433}
434
435def VOP_READLANE : VOPProfile<[i32, i32, i32]> {
436  let Outs32 = (outs SReg_32:$vdst);
437  let Outs64 = Outs32;
438  let Ins32 = (ins VRegOrLds_32:$src0, SCSrc_b32:$src1);
439  let Ins64 = Ins32;
440  let Asm32 = " $vdst, $src0, $src1";
441  let Asm64 = Asm32;
442
443  let HasExt = 0;
444  let HasExtDPP = 0;
445  let HasExtSDWA = 0;
446  let HasExtSDWA9 = 0;
447}
448
449def VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> {
450  let Outs32 = (outs VGPR_32:$vdst);
451  let Outs64 = Outs32;
452  let Ins32 = (ins SCSrc_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in);
453  let Ins64 = Ins32;
454  let Asm32 = " $vdst, $src0, $src1";
455  let Asm64 = Asm32;
456  let HasSrc2 = 0;
457  let HasSrc2Mods = 0;
458
459  let HasExt = 0;
460  let HasExtDPP = 0;
461  let HasExtSDWA = 0;
462  let HasExtSDWA9 = 0;
463}
464
465//===----------------------------------------------------------------------===//
466// VOP2 Instructions
467//===----------------------------------------------------------------------===//
468
469defm V_CNDMASK_B32 : VOP2eInst <"v_cndmask_b32", VOP2e_I32_I32_I32_I1>;
470let SubtargetPredicate = HasMadMacF32Insts in
471def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, []>;
472
473let isCommutable = 1 in {
474defm V_ADD_F32 : VOP2Inst <"v_add_f32", VOP_F32_F32_F32, any_fadd>;
475defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, any_fsub>;
476defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">;
477defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>;
478defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, any_fmul>;
479defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32_ARITH, AMDGPUmul_i24>;
480defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_i24>;
481defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32_ARITH, AMDGPUmul_u24>;
482defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_u24>;
483defm V_MIN_F32 : VOP2Inst <"v_min_f32", VOP_F32_F32_F32, fminnum_like>;
484defm V_MAX_F32 : VOP2Inst <"v_max_f32", VOP_F32_F32_F32, fmaxnum_like>;
485defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smin>;
486defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smax>;
487defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umin>;
488defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umax>;
489defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, lshr_rev, "v_lshr_b32">;
490defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, ashr_rev, "v_ashr_i32">;
491defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, lshl_rev, "v_lshl_b32">;
492defm V_AND_B32 : VOP2Inst <"v_and_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, and>;
493defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, or>;
494defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, xor>;
495
496let mayRaiseFPException = 0 in {
497let SubtargetPredicate = HasMadMacF32Insts in {
498let Constraints = "$vdst = $src2", DisableEncoding="$src2",
499    isConvertibleToThreeAddress = 1 in {
500defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>;
501}
502
503def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32, []>;
504} // End SubtargetPredicate = HasMadMacF32Insts
505}
506
507// No patterns so that the scalar instructions are always selected.
508// The scalar versions will be replaced with vector when needed later.
509defm V_ADD_CO_U32 : VOP2bInst <"v_add_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_add_co_u32", 1>;
510defm V_SUB_CO_U32 : VOP2bInst <"v_sub_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>;
511defm V_SUBREV_CO_U32 : VOP2bInst <"v_subrev_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>;
512defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_addc_u32", 1>;
513defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>;
514defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>;
515
516
517let SubtargetPredicate = HasAddNoCarryInsts in {
518defm V_ADD_U32 : VOP2Inst <"v_add_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_add_u32", 1>;
519defm V_SUB_U32 : VOP2Inst <"v_sub_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>;
520defm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>;
521}
522
523} // End isCommutable = 1
524
525// These are special and do not read the exec mask.
526let isConvergent = 1, Uses = []<Register> in {
527def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE,
528  [(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))]>;
529
530let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in {
531def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE,
532  [(set i32:$vdst, (int_amdgcn_writelane i32:$src0, i32:$src1, i32:$vdst_in))]>;
533} // End $vdst = $vdst_in, DisableEncoding $vdst_in
534} // End isConvergent = 1
535
536defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_NO_EXT<VOP_I32_I32_I32>>;
537defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, add_ctpop>;
538defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_lo>;
539defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_hi>;
540defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_NO_EXT<VOP_F32_F32_I32>, AMDGPUldexp>;
541defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_NO_EXT<VOP_I32_F32_I32>>; // TODO: set "Uses = dst"
542
543let ReadsModeReg = 0, mayRaiseFPException = 0 in {
544defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_i16_f32>;
545defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_u16_f32>;
546}
547
548defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_NO_EXT<VOP_V2F16_F32_F32>, AMDGPUpkrtz_f16_f32>;
549defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_u16_u32>;
550defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_i16_i32>;
551
552
553let SubtargetPredicate = isGFX6GFX7 in {
554defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>;
555defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>;
556} // End SubtargetPredicate = isGFX6GFX7
557
558let isCommutable = 1 in {
559let SubtargetPredicate = isGFX6GFX7GFX10 in {
560let OtherPredicates = [HasMadMacF32Insts] in
561defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_F32_F32_F32>;
562} // End SubtargetPredicate = isGFX6GFX7GFX10
563let SubtargetPredicate = isGFX6GFX7 in {
564defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, srl>;
565defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, sra>;
566defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, shl>;
567} // End SubtargetPredicate = isGFX6GFX7
568} // End isCommutable = 1
569
570
571class DivergentBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :
572  GCNPat<
573      (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
574      !if(!cast<Commutable_REV>(Inst).IsOrig,
575        (Inst $src0, $src1),
576        (Inst $src1, $src0)
577      )
578  >;
579
580class DivergentClampingBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :
581  GCNPat<
582      (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
583      !if(!cast<Commutable_REV>(Inst).IsOrig,
584        (Inst $src0, $src1, 0),
585        (Inst $src1, $src0, 0)
586      )
587  >;
588
589def : DivergentBinOp<srl, V_LSHRREV_B32_e64>;
590def : DivergentBinOp<sra, V_ASHRREV_I32_e64>;
591def : DivergentBinOp<shl, V_LSHLREV_B32_e64>;
592
593let SubtargetPredicate = HasAddNoCarryInsts in {
594  def : DivergentClampingBinOp<add, V_ADD_U32_e64>;
595  def : DivergentClampingBinOp<sub, V_SUB_U32_e64>;
596}
597
598let SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] in {
599def : DivergentClampingBinOp<add, V_ADD_CO_U32_e64>;
600def : DivergentClampingBinOp<sub, V_SUB_CO_U32_e64>;
601}
602
603def : DivergentBinOp<adde, V_ADDC_U32_e32>;
604def : DivergentBinOp<sube, V_SUBB_U32_e32>;
605
606class divergent_i64_BinOp <SDPatternOperator Op, Instruction Inst> :
607  GCNPat<
608      (getDivergentFrag<Op>.ret i64:$src0, i64:$src1),
609      (REG_SEQUENCE VReg_64,
610        (Inst
611          (i32 (EXTRACT_SUBREG $src0, sub0)),
612          (i32 (EXTRACT_SUBREG $src1, sub0))
613        ), sub0,
614        (Inst
615          (i32 (EXTRACT_SUBREG $src0, sub1)),
616          (i32 (EXTRACT_SUBREG $src1, sub1))
617        ), sub1
618      )
619  >;
620
621def :  divergent_i64_BinOp <and, V_AND_B32_e32>;
622def :  divergent_i64_BinOp <or,  V_OR_B32_e32>;
623def :  divergent_i64_BinOp <xor, V_XOR_B32_e32>;
624
625let SubtargetPredicate = Has16BitInsts in {
626
627let FPDPRounding = 1 in {
628def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16, [], "">;
629defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>;
630} // End FPDPRounding = 1
631
632defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16, lshl_rev>;
633defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16, lshr_rev>;
634defm V_ASHRREV_I16 : VOP2Inst <"v_ashrrev_i16", VOP_I16_I16_I16, ashr_rev>;
635
636let isCommutable = 1 in {
637let FPDPRounding = 1 in {
638defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, any_fadd>;
639defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, any_fsub>;
640defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">;
641defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, any_fmul>;
642
643let mayRaiseFPException = 0 in {
644def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">;
645}
646
647} // End FPDPRounding = 1
648defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16_ARITH, add>;
649defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16_ARITH, sub>;
650defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16_ARITH, null_frag, "v_sub_u16">;
651defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16, mul>;
652defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum_like>;
653defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum_like>;
654defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16, umax>;
655defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16, smax>;
656defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16, umin>;
657defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16, smin>;
658
659let Constraints = "$vdst = $src2", DisableEncoding="$src2",
660    isConvertibleToThreeAddress = 1 in {
661defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>;
662}
663} // End isCommutable = 1
664
665} // End SubtargetPredicate = Has16BitInsts
666
667let SubtargetPredicate = HasDLInsts in {
668
669defm V_XNOR_B32 : VOP2Inst <"v_xnor_b32", VOP_I32_I32_I32>;
670
671let Constraints = "$vdst = $src2",
672    DisableEncoding="$src2",
673    isConvertibleToThreeAddress = 1,
674    isCommutable = 1 in {
675defm V_FMAC_F32 : VOP2Inst <"v_fmac_f32", VOP_MAC_F32>;
676}
677
678} // End SubtargetPredicate = HasDLInsts
679
680let Constraints = "$vdst = $src2",
681      DisableEncoding="$src2",
682      isConvertibleToThreeAddress = 1,
683      isCommutable = 1,
684      IsDOT = 1 in {
685  let SubtargetPredicate = HasDot5Insts in
686    defm V_DOT2C_F32_F16 : VOP2Inst<"v_dot2c_f32_f16", VOP_DOT_ACC_F32_V2F16>;
687  let SubtargetPredicate = HasDot6Insts in
688    defm V_DOT4C_I32_I8  : VOP2Inst<"v_dot4c_i32_i8",  VOP_DOT_ACC_I32_I32>;
689
690  let SubtargetPredicate = HasDot4Insts in
691    defm V_DOT2C_I32_I16 : VOP2Inst<"v_dot2c_i32_i16", VOP_DOT_ACC_I32_I32>;
692  let SubtargetPredicate = HasDot3Insts in
693    defm V_DOT8C_I32_I4  : VOP2Inst<"v_dot8c_i32_i4",  VOP_DOT_ACC_I32_I32>;
694}
695
696let AddedComplexity = 30 in {
697  def : GCNPat<
698    (f32 (AMDGPUfdot2 v2f16:$src0, v2f16:$src1, f32:$src2, (i1 DSTCLAMP.NONE))),
699    (f32 (V_DOT2C_F32_F16_e32 $src0, $src1, $src2))
700  > {
701    let SubtargetPredicate = HasDot5Insts;
702  }
703  def : GCNPat<
704    (i32 (int_amdgcn_sdot4 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
705    (i32 (V_DOT4C_I32_I8_e32 $src0, $src1, $src2))
706  > {
707    let SubtargetPredicate = HasDot6Insts;
708  }
709  def : GCNPat<
710    (i32 (int_amdgcn_sdot2 v2i16:$src0, v2i16:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
711    (i32 (V_DOT2C_I32_I16_e32 $src0, $src1, $src2))
712  > {
713    let SubtargetPredicate = HasDot4Insts;
714  }
715  def : GCNPat<
716    (i32 (int_amdgcn_sdot8 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
717    (i32 (V_DOT8C_I32_I4_e32 $src0, $src1, $src2))
718  > {
719    let SubtargetPredicate = HasDot3Insts;
720  }
721} // End AddedComplexity = 30
722
723let SubtargetPredicate = isGFX10Plus in {
724
725def V_FMAMK_F32 : VOP2_Pseudo<"v_fmamk_f32", VOP_MADMK_F32, [], "">;
726let FPDPRounding = 1 in
727def V_FMAMK_F16 : VOP2_Pseudo <"v_fmamk_f16", VOP_MADMK_F16, [], "">;
728
729let isCommutable = 1 in {
730def V_FMAAK_F32 : VOP2_Pseudo<"v_fmaak_f32", VOP_MADAK_F32, [], "">;
731let FPDPRounding = 1 in
732def V_FMAAK_F16 : VOP2_Pseudo <"v_fmaak_f16", VOP_MADAK_F16, [], "">;
733} // End isCommutable = 1
734
735let Constraints = "$vdst = $src2",
736    DisableEncoding="$src2",
737    isConvertibleToThreeAddress = 1,
738    isCommutable = 1 in {
739defm V_FMAC_F16 : VOP2Inst <"v_fmac_f16", VOP_MAC_F16>;
740}
741
742} // End SubtargetPredicate = isGFX10Plus
743
744let SubtargetPredicate = HasPkFmacF16Inst in {
745defm V_PK_FMAC_F16 : VOP2Inst<"v_pk_fmac_f16", VOP_V2F16_V2F16_V2F16>;
746} // End SubtargetPredicate = HasPkFmacF16Inst
747
748// Note: 16-bit instructions produce a 0 result in the high 16-bits
749// on GFX8 and GFX9 and preserve high 16 bits on GFX10+
750multiclass Arithmetic_i16_0Hi_Pats <SDPatternOperator op, Instruction inst> {
751
752def : GCNPat<
753  (i32 (zext (op i16:$src0, i16:$src1))),
754  (inst VSrc_b16:$src0, VSrc_b16:$src1)
755>;
756
757def : GCNPat<
758  (i64 (zext (op i16:$src0, i16:$src1))),
759   (REG_SEQUENCE VReg_64,
760     (inst $src0, $src1), sub0,
761     (V_MOV_B32_e32 (i32 0)), sub1)
762>;
763}
764
765class ZExt_i16_i1_Pat <SDNode ext> : GCNPat <
766  (i16 (ext i1:$src)),
767  (V_CNDMASK_B32_e64 (i32 0/*src0mod*/), (i32 0/*src0*/),
768                     (i32 0/*src1mod*/), (i32 1/*src1*/),
769                     $src)
770>;
771
772foreach vt = [i16, v2i16] in {
773def : GCNPat <
774  (and vt:$src0, vt:$src1),
775  (V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
776>;
777
778def : GCNPat <
779  (or vt:$src0, vt:$src1),
780  (V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
781>;
782
783def : GCNPat <
784  (xor vt:$src0, vt:$src1),
785  (V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
786>;
787}
788
789let Predicates = [Has16BitInsts] in {
790
791// Undo sub x, c -> add x, -c canonicalization since c is more likely
792// an inline immediate than -c.
793// TODO: Also do for 64-bit.
794def : GCNPat<
795  (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)),
796  (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)
797>;
798
799
800let Predicates = [Has16BitInsts, isGFX7GFX8GFX9] in {
801
802def : GCNPat<
803  (i32 (zext (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)))),
804  (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)
805>;
806
807defm : Arithmetic_i16_0Hi_Pats<add, V_ADD_U16_e64>;
808defm : Arithmetic_i16_0Hi_Pats<mul, V_MUL_LO_U16_e64>;
809defm : Arithmetic_i16_0Hi_Pats<sub, V_SUB_U16_e64>;
810defm : Arithmetic_i16_0Hi_Pats<smin, V_MIN_I16_e64>;
811defm : Arithmetic_i16_0Hi_Pats<smax, V_MAX_I16_e64>;
812defm : Arithmetic_i16_0Hi_Pats<umin, V_MIN_U16_e64>;
813defm : Arithmetic_i16_0Hi_Pats<umax, V_MAX_U16_e64>;
814defm : Arithmetic_i16_0Hi_Pats<lshl_rev, V_LSHLREV_B16_e64>;
815defm : Arithmetic_i16_0Hi_Pats<lshr_rev, V_LSHRREV_B16_e64>;
816defm : Arithmetic_i16_0Hi_Pats<ashr_rev, V_ASHRREV_I16_e64>;
817}  // End Predicates = [Has16BitInsts, isGFX7GFX8GFX9]
818
819def : ZExt_i16_i1_Pat<zext>;
820def : ZExt_i16_i1_Pat<anyext>;
821
822def : GCNPat <
823  (i16 (sext i1:$src)),
824  (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
825                     /*src1mod*/(i32 0), /*src1*/(i32 -1), $src)
826>;
827
828} // End Predicates = [Has16BitInsts]
829
830
831let SubtargetPredicate = HasIntClamp in {
832// Set clamp bit for saturation.
833def : VOPBinOpClampPat<uaddsat, V_ADD_CO_U32_e64, i32>;
834def : VOPBinOpClampPat<usubsat, V_SUB_CO_U32_e64, i32>;
835}
836
837let SubtargetPredicate = HasAddNoCarryInsts, OtherPredicates = [HasIntClamp] in {
838let AddedComplexity = 1 in { // Prefer over form with carry-out.
839def : VOPBinOpClampPat<uaddsat, V_ADD_U32_e64, i32>;
840def : VOPBinOpClampPat<usubsat, V_SUB_U32_e64, i32>;
841}
842}
843
844let SubtargetPredicate = Has16BitInsts, OtherPredicates = [HasIntClamp] in {
845def : VOPBinOpClampPat<uaddsat, V_ADD_U16_e64, i16>;
846def : VOPBinOpClampPat<usubsat, V_SUB_U16_e64, i16>;
847}
848
849//===----------------------------------------------------------------------===//
850// Target-specific instruction encodings.
851//===----------------------------------------------------------------------===//
852
853class VOP2_DPP<bits<6> op, VOP2_DPP_Pseudo ps,
854               string opName = ps.OpName, VOPProfile p = ps.Pfl,
855               bit IsDPP16 = 0> :
856    VOP_DPP<opName, p, IsDPP16> {
857  let hasSideEffects = ps.hasSideEffects;
858  let Defs = ps.Defs;
859  let SchedRW = ps.SchedRW;
860  let Uses = ps.Uses;
861
862  bits<8> vdst;
863  bits<8> src1;
864  let Inst{8-0}   = 0xfa;
865  let Inst{16-9}  = !if(p.HasSrc1, src1{7-0}, 0);
866  let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
867  let Inst{30-25} = op;
868  let Inst{31}    = 0x0;
869}
870
871class Base_VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps,
872                 string opName = ps.OpName, VOPProfile p = ps.Pfl> :
873    VOP2_DPP<op, ps, opName, p, 1> {
874  let AssemblerPredicate = HasDPP16;
875  let SubtargetPredicate = HasDPP16;
876}
877
878class VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps,
879                 string opName = ps.OpName, VOPProfile p = ps.Pfl> :
880    Base_VOP2_DPP16<op, ps, opName, p>,
881    SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX10>;
882
883class VOP2_DPP8<bits<6> op, VOP2_Pseudo ps,
884                string opName = ps.OpName, VOPProfile p = ps.Pfl> :
885    VOP_DPP8<ps.OpName, p> {
886  let hasSideEffects = ps.hasSideEffects;
887  let Defs = ps.Defs;
888  let SchedRW = ps.SchedRW;
889  let Uses = ps.Uses;
890
891  bits<8> vdst;
892  bits<8> src1;
893
894  let Inst{8-0}   = fi;
895  let Inst{16-9}  = !if(p.HasSrc1, src1{7-0}, 0);
896  let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
897  let Inst{30-25} = op;
898  let Inst{31}    = 0x0;
899
900  let AssemblerPredicate = HasDPP8;
901  let SubtargetPredicate = HasDPP8;
902}
903
904//===----------------------------------------------------------------------===//
905// GFX10.
906//===----------------------------------------------------------------------===//
907
908let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
909  //===------------------------------- VOP2 -------------------------------===//
910  multiclass VOP2Only_Real_MADK_gfx10<bits<6> op> {
911    def _gfx10 :
912      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX10>,
913      VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
914  }
915  multiclass VOP2Only_Real_MADK_gfx10_with_name<bits<6> op, string opName,
916                                                string asmName> {
917    def _gfx10 :
918        VOP2_Real<!cast<VOP2_Pseudo>(opName), SIEncodingFamily.GFX10>,
919        VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> {
920      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName);
921      let AsmString = asmName # ps.AsmOperands;
922    }
923  }
924  multiclass VOP2_Real_e32_gfx10<bits<6> op> {
925    def _e32_gfx10 :
926      VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,
927      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
928  }
929  multiclass VOP2_Real_e64_gfx10<bits<6> op> {
930    def _e64_gfx10 :
931      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
932      VOP3e_gfx10<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
933  }
934  multiclass VOP2_Real_sdwa_gfx10<bits<6> op> {
935    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
936    def _sdwa_gfx10 :
937      VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
938      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
939      let DecoderNamespace = "SDWA10";
940    }
941  }
942  multiclass VOP2_Real_dpp_gfx10<bits<6> op> {
943    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
944    def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
945      let DecoderNamespace = "SDWA10";
946    }
947  }
948  multiclass VOP2_Real_dpp8_gfx10<bits<6> op> {
949    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
950    def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(NAME#"_e32")> {
951      let DecoderNamespace = "DPP8";
952    }
953  }
954
955  //===------------------------- VOP2 (with name) -------------------------===//
956  multiclass VOP2_Real_e32_gfx10_with_name<bits<6> op, string opName,
957                                           string asmName> {
958    def _e32_gfx10 :
959      VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
960      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
961        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
962        let AsmString = asmName # ps.AsmOperands;
963      }
964  }
965  multiclass VOP2_Real_e64_gfx10_with_name<bits<6> op, string opName,
966                                           string asmName> {
967    def _e64_gfx10 :
968      VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
969      VOP3e_gfx10<{0, 1, 0, 0, op{5-0}},
970                  !cast<VOP3_Pseudo>(opName#"_e64").Pfl> {
971        VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64");
972        let AsmString = asmName # ps.AsmOperands;
973      }
974  }
975  let DecoderNamespace = "SDWA10" in {
976    multiclass VOP2_Real_sdwa_gfx10_with_name<bits<6> op, string opName,
977                                              string asmName> {
978      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
979      def _sdwa_gfx10 :
980        VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
981        VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
982          VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
983          let AsmString = asmName # ps.AsmOperands;
984        }
985    }
986    multiclass VOP2_Real_dpp_gfx10_with_name<bits<6> op, string opName,
987                                             string asmName> {
988      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
989      def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp")> {
990        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
991        let AsmString = asmName # ps.Pfl.AsmDPP16;
992      }
993    }
994    multiclass VOP2_Real_dpp8_gfx10_with_name<bits<6> op, string opName,
995                                              string asmName> {
996      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
997      def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
998        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
999        let AsmString = asmName # ps.Pfl.AsmDPP8;
1000        let DecoderNamespace = "DPP8";
1001      }
1002    }
1003  } // End DecoderNamespace = "SDWA10"
1004
1005  //===------------------------------ VOP2be ------------------------------===//
1006  multiclass VOP2be_Real_e32_gfx10<bits<6> op, string opName, string asmName> {
1007    def _e32_gfx10 :
1008      VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
1009      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
1010        VOP2_Pseudo Ps = !cast<VOP2_Pseudo>(opName#"_e32");
1011        let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
1012      }
1013  }
1014  multiclass VOP2be_Real_e64_gfx10<bits<6> op, string opName, string asmName> {
1015    def _e64_gfx10 :
1016      VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
1017      VOP3be_gfx10<{0, 1, 0, 0, op{5-0}},
1018                   !cast<VOP3_Pseudo>(opName#"_e64").Pfl> {
1019        VOP3_Pseudo Ps = !cast<VOP3_Pseudo>(opName#"_e64");
1020        let AsmString = asmName # Ps.AsmOperands;
1021      }
1022  }
1023  multiclass VOP2be_Real_sdwa_gfx10<bits<6> op, string opName, string asmName> {
1024    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1025    def _sdwa_gfx10 :
1026      VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1027      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1028        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1029        let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
1030        let DecoderNamespace = "SDWA10";
1031      }
1032    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1033    def _sdwa_w32_gfx10 :
1034      Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1035      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1036        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1037        let AsmString = asmName # !subst("vcc", "vcc_lo", Ps.AsmOperands);
1038        let isAsmParserOnly = 1;
1039        let DecoderNamespace = "SDWA10";
1040        let WaveSizePredicate = isWave32;
1041      }
1042    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1043    def _sdwa_w64_gfx10 :
1044      Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1045      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1046        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1047        let AsmString = asmName # Ps.AsmOperands;
1048        let isAsmParserOnly = 1;
1049        let DecoderNamespace = "SDWA10";
1050        let WaveSizePredicate = isWave64;
1051      }
1052  }
1053  multiclass VOP2be_Real_dpp_gfx10<bits<6> op, string opName, string asmName> {
1054    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1055    def _dpp_gfx10 :
1056      VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1057        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1058        let AsmString = asmName # !subst(", vcc", "", AsmDPP);
1059        let DecoderNamespace = "SDWA10";
1060      }
1061    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1062    def _dpp_w32_gfx10 :
1063      Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1064        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1065        let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP);
1066        let isAsmParserOnly = 1;
1067        let WaveSizePredicate = isWave32;
1068      }
1069    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1070    def _dpp_w64_gfx10 :
1071      Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1072        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1073        let AsmString = asmName # AsmDPP;
1074        let isAsmParserOnly = 1;
1075        let WaveSizePredicate = isWave64;
1076      }
1077  }
1078  multiclass VOP2be_Real_dpp8_gfx10<bits<6> op, string opName, string asmName> {
1079    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1080    def _dpp8_gfx10 :
1081      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1082        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1083        let AsmString = asmName # !subst(", vcc", "", AsmDPP8);
1084        let DecoderNamespace = "DPP8";
1085      }
1086    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1087    def _dpp8_w32_gfx10 :
1088      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1089        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1090        let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8);
1091        let isAsmParserOnly = 1;
1092        let WaveSizePredicate = isWave32;
1093      }
1094    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1095    def _dpp8_w64_gfx10 :
1096      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1097        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1098        let AsmString = asmName # AsmDPP8;
1099        let isAsmParserOnly = 1;
1100        let WaveSizePredicate = isWave64;
1101      }
1102  }
1103
1104  //===----------------------------- VOP3Only -----------------------------===//
1105  multiclass VOP3Only_Real_gfx10<bits<10> op> {
1106    def _e64_gfx10 :
1107      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1108      VOP3e_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1109  }
1110
1111  //===---------------------------- VOP3beOnly ----------------------------===//
1112  multiclass VOP3beOnly_Real_gfx10<bits<10> op> {
1113    def _e64_gfx10 :
1114      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1115      VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1116  }
1117} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
1118
1119multiclass VOP2be_Real_gfx10<bits<6> op, string opName, string asmName> :
1120  VOP2be_Real_e32_gfx10<op, opName, asmName>,
1121  VOP2be_Real_e64_gfx10<op, opName, asmName>,
1122  VOP2be_Real_sdwa_gfx10<op, opName, asmName>,
1123  VOP2be_Real_dpp_gfx10<op, opName, asmName>,
1124  VOP2be_Real_dpp8_gfx10<op, opName, asmName>;
1125
1126multiclass VOP2e_Real_gfx10<bits<6> op, string opName, string asmName> :
1127  VOP2_Real_e32_gfx10<op>,
1128  VOP2_Real_e64_gfx10<op>,
1129  VOP2be_Real_sdwa_gfx10<op, opName, asmName>,
1130  VOP2be_Real_dpp_gfx10<op, opName, asmName>,
1131  VOP2be_Real_dpp8_gfx10<op, opName, asmName>;
1132
1133multiclass VOP2_Real_gfx10<bits<6> op> :
1134  VOP2_Real_e32_gfx10<op>, VOP2_Real_e64_gfx10<op>,
1135  VOP2_Real_sdwa_gfx10<op>, VOP2_Real_dpp_gfx10<op>, VOP2_Real_dpp8_gfx10<op>;
1136
1137multiclass VOP2_Real_gfx10_with_name<bits<6> op, string opName,
1138                                     string asmName> :
1139  VOP2_Real_e32_gfx10_with_name<op, opName, asmName>,
1140  VOP2_Real_e64_gfx10_with_name<op, opName, asmName>,
1141  VOP2_Real_sdwa_gfx10_with_name<op, opName, asmName>,
1142  VOP2_Real_dpp_gfx10_with_name<op, opName, asmName>,
1143  VOP2_Real_dpp8_gfx10_with_name<op, opName, asmName>;
1144
1145defm V_XNOR_B32      : VOP2_Real_gfx10<0x01e>;
1146defm V_FMAC_F32      : VOP2_Real_gfx10<0x02b>;
1147defm V_FMAMK_F32     : VOP2Only_Real_MADK_gfx10<0x02c>;
1148defm V_FMAAK_F32     : VOP2Only_Real_MADK_gfx10<0x02d>;
1149defm V_ADD_F16       : VOP2_Real_gfx10<0x032>;
1150defm V_SUB_F16       : VOP2_Real_gfx10<0x033>;
1151defm V_SUBREV_F16    : VOP2_Real_gfx10<0x034>;
1152defm V_MUL_F16       : VOP2_Real_gfx10<0x035>;
1153defm V_FMAC_F16      : VOP2_Real_gfx10<0x036>;
1154defm V_FMAMK_F16     : VOP2Only_Real_MADK_gfx10<0x037>;
1155defm V_FMAAK_F16     : VOP2Only_Real_MADK_gfx10<0x038>;
1156defm V_MAX_F16       : VOP2_Real_gfx10<0x039>;
1157defm V_MIN_F16       : VOP2_Real_gfx10<0x03a>;
1158defm V_LDEXP_F16     : VOP2_Real_gfx10<0x03b>;
1159defm V_PK_FMAC_F16   : VOP2_Real_e32_gfx10<0x03c>;
1160
1161// VOP2 no carry-in, carry-out.
1162defm V_ADD_NC_U32 :
1163  VOP2_Real_gfx10_with_name<0x025, "V_ADD_U32", "v_add_nc_u32">;
1164defm V_SUB_NC_U32 :
1165  VOP2_Real_gfx10_with_name<0x026, "V_SUB_U32", "v_sub_nc_u32">;
1166defm V_SUBREV_NC_U32 :
1167  VOP2_Real_gfx10_with_name<0x027, "V_SUBREV_U32", "v_subrev_nc_u32">;
1168
1169// VOP2 carry-in, carry-out.
1170defm V_ADD_CO_CI_U32 :
1171  VOP2be_Real_gfx10<0x028, "V_ADDC_U32", "v_add_co_ci_u32">;
1172defm V_SUB_CO_CI_U32 :
1173  VOP2be_Real_gfx10<0x029, "V_SUBB_U32", "v_sub_co_ci_u32">;
1174defm V_SUBREV_CO_CI_U32 :
1175  VOP2be_Real_gfx10<0x02a, "V_SUBBREV_U32", "v_subrev_co_ci_u32">;
1176
1177defm V_CNDMASK_B32 :
1178  VOP2e_Real_gfx10<0x001, "V_CNDMASK_B32", "v_cndmask_b32">;
1179
1180// VOP3 only.
1181defm V_BFM_B32            : VOP3Only_Real_gfx10<0x363>;
1182defm V_BCNT_U32_B32       : VOP3Only_Real_gfx10<0x364>;
1183defm V_MBCNT_LO_U32_B32   : VOP3Only_Real_gfx10<0x365>;
1184defm V_MBCNT_HI_U32_B32   : VOP3Only_Real_gfx10<0x366>;
1185defm V_LDEXP_F32          : VOP3Only_Real_gfx10<0x362>;
1186defm V_CVT_PKNORM_I16_F32 : VOP3Only_Real_gfx10<0x368>;
1187defm V_CVT_PKNORM_U16_F32 : VOP3Only_Real_gfx10<0x369>;
1188defm V_CVT_PK_U16_U32     : VOP3Only_Real_gfx10<0x36a>;
1189defm V_CVT_PK_I16_I32     : VOP3Only_Real_gfx10<0x36b>;
1190
1191// VOP3 carry-out.
1192defm V_ADD_CO_U32 : VOP3beOnly_Real_gfx10<0x30f>;
1193defm V_SUB_CO_U32 : VOP3beOnly_Real_gfx10<0x310>;
1194defm V_SUBREV_CO_U32 : VOP3beOnly_Real_gfx10<0x319>;
1195
1196let SubtargetPredicate = isGFX10Plus in {
1197  defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx10>;
1198
1199  defm : VOP2bInstAliases<
1200    V_ADDC_U32_e32, V_ADD_CO_CI_U32_e32_gfx10, "v_add_co_ci_u32">;
1201  defm : VOP2bInstAliases<
1202    V_SUBB_U32_e32, V_SUB_CO_CI_U32_e32_gfx10, "v_sub_co_ci_u32">;
1203  defm : VOP2bInstAliases<
1204    V_SUBBREV_U32_e32, V_SUBREV_CO_CI_U32_e32_gfx10, "v_subrev_co_ci_u32">;
1205} // End SubtargetPredicate = isGFX10Plus
1206
1207//===----------------------------------------------------------------------===//
1208// GFX6, GFX7, GFX10.
1209//===----------------------------------------------------------------------===//
1210
1211class VOP2_DPPe <bits<6> op, VOP2_DPP_Pseudo ps, VOPProfile P = ps.Pfl> :
1212  VOP_DPPe <P> {
1213  bits<8> vdst;
1214  bits<8> src1;
1215  let Inst{8-0}   = 0xfa; //dpp
1216  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
1217  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
1218  let Inst{30-25} = op;
1219  let Inst{31}    = 0x0; //encoding
1220}
1221
1222let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
1223  multiclass VOP2Only_Real_gfx6_gfx7<bits<6> op> {
1224    def _gfx6_gfx7 :
1225      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1226      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1227  }
1228  multiclass VOP2Only_Real_MADK_gfx6_gfx7<bits<6> op> {
1229    def _gfx6_gfx7 :
1230      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1231      VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1232  }
1233  multiclass VOP2_Real_e32_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1234    def _e32_gfx6_gfx7 :
1235      VOP2_Real<!cast<VOP2_Pseudo>(PseudoName#"_e32"), SIEncodingFamily.SI>,
1236      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(PseudoName#"_e32").Pfl>;
1237  }
1238  multiclass VOP2_Real_e64_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1239    def _e64_gfx6_gfx7 :
1240      VOP3_Real<!cast<VOP3_Pseudo>(PseudoName#"_e64"), SIEncodingFamily.SI>,
1241      VOP3e_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(PseudoName#"_e64").Pfl>;
1242  }
1243  multiclass VOP2be_Real_e64_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1244    def _e64_gfx6_gfx7 :
1245      VOP3_Real<!cast<VOP3_Pseudo>(PseudoName#"_e64"), SIEncodingFamily.SI>,
1246      VOP3be_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(PseudoName#"_e64").Pfl>;
1247  }
1248} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
1249
1250multiclass VOP2Only_Real_MADK_gfx6_gfx7_gfx10<bits<6> op> :
1251  VOP2Only_Real_MADK_gfx6_gfx7<op>, VOP2Only_Real_MADK_gfx10<op>;
1252
1253multiclass VOP2_Real_gfx6_gfx7<bits<6> op> :
1254  VOP2_Real_e32_gfx6_gfx7<op>, VOP2_Real_e64_gfx6_gfx7<op>;
1255
1256multiclass VOP2_Real_gfx6_gfx7_gfx10<bits<6> op> :
1257  VOP2_Real_gfx6_gfx7<op>, VOP2_Real_gfx10<op>;
1258
1259multiclass VOP2be_Real_gfx6_gfx7<bits<6> op> :
1260  VOP2_Real_e32_gfx6_gfx7<op>, VOP2be_Real_e64_gfx6_gfx7<op>;
1261
1262multiclass VOP2be_Real_gfx6_gfx7_with_name<bits<6> op,
1263  string PseudoName, string asmName>  {
1264  defvar ps32 = !cast<VOP2_Pseudo>(PseudoName#"_e32");
1265  defvar ps64 = !cast<VOP3_Pseudo>(PseudoName#"_e64");
1266
1267  let AsmString = asmName # ps32.AsmOperands in {
1268    defm "" : VOP2_Real_e32_gfx6_gfx7<op, PseudoName>;
1269  }
1270
1271   let AsmString = asmName # ps64.AsmOperands in {
1272    defm "" : VOP2be_Real_e64_gfx6_gfx7<op, PseudoName>;
1273  }
1274}
1275
1276defm V_CNDMASK_B32        : VOP2_Real_gfx6_gfx7<0x000>;
1277defm V_MIN_LEGACY_F32     : VOP2_Real_gfx6_gfx7<0x00d>;
1278defm V_MAX_LEGACY_F32     : VOP2_Real_gfx6_gfx7<0x00e>;
1279defm V_LSHR_B32           : VOP2_Real_gfx6_gfx7<0x015>;
1280defm V_ASHR_I32           : VOP2_Real_gfx6_gfx7<0x017>;
1281defm V_LSHL_B32           : VOP2_Real_gfx6_gfx7<0x019>;
1282defm V_BFM_B32            : VOP2_Real_gfx6_gfx7<0x01e>;
1283defm V_BCNT_U32_B32       : VOP2_Real_gfx6_gfx7<0x022>;
1284defm V_MBCNT_LO_U32_B32   : VOP2_Real_gfx6_gfx7<0x023>;
1285defm V_MBCNT_HI_U32_B32   : VOP2_Real_gfx6_gfx7<0x024>;
1286defm V_LDEXP_F32          : VOP2_Real_gfx6_gfx7<0x02b>;
1287defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_gfx6_gfx7<0x02c>;
1288defm V_CVT_PKNORM_I16_F32 : VOP2_Real_gfx6_gfx7<0x02d>;
1289defm V_CVT_PKNORM_U16_F32 : VOP2_Real_gfx6_gfx7<0x02e>;
1290defm V_CVT_PK_U16_U32     : VOP2_Real_gfx6_gfx7<0x030>;
1291defm V_CVT_PK_I16_I32     : VOP2_Real_gfx6_gfx7<0x031>;
1292
1293// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in
1294// VI, but the VI instructions behave the same as the SI versions.
1295defm V_ADD_I32            : VOP2be_Real_gfx6_gfx7_with_name<0x025, "V_ADD_CO_U32", "v_add_i32">;
1296defm V_SUB_I32            : VOP2be_Real_gfx6_gfx7_with_name<0x026, "V_SUB_CO_U32", "v_sub_i32">;
1297defm V_SUBREV_I32         : VOP2be_Real_gfx6_gfx7_with_name<0x027, "V_SUBREV_CO_U32", "v_subrev_i32">;
1298defm V_ADDC_U32           : VOP2be_Real_gfx6_gfx7<0x028>;
1299defm V_SUBB_U32           : VOP2be_Real_gfx6_gfx7<0x029>;
1300defm V_SUBBREV_U32        : VOP2be_Real_gfx6_gfx7<0x02a>;
1301
1302defm V_READLANE_B32 : VOP2Only_Real_gfx6_gfx7<0x001>;
1303
1304let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
1305  defm V_WRITELANE_B32 : VOP2Only_Real_gfx6_gfx7<0x002>;
1306} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)
1307
1308let SubtargetPredicate = isGFX6GFX7 in {
1309  defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx6_gfx7>;
1310  defm : VOP2eInstAliases<V_ADD_CO_U32_e32, V_ADD_I32_e32_gfx6_gfx7>;
1311  defm : VOP2eInstAliases<V_SUB_CO_U32_e32, V_SUB_I32_e32_gfx6_gfx7>;
1312  defm : VOP2eInstAliases<V_SUBREV_CO_U32_e32, V_SUBREV_I32_e32_gfx6_gfx7>;
1313
1314  def : VOP2e64InstAlias<V_ADD_CO_U32_e64, V_ADD_I32_e64_gfx6_gfx7>;
1315  def : VOP2e64InstAlias<V_SUB_CO_U32_e64, V_SUB_I32_e64_gfx6_gfx7>;
1316  def : VOP2e64InstAlias<V_SUBREV_CO_U32_e64, V_SUBREV_I32_e64_gfx6_gfx7>;
1317} // End SubtargetPredicate = isGFX6GFX7
1318
1319defm V_ADD_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x003>;
1320defm V_SUB_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x004>;
1321defm V_SUBREV_F32         : VOP2_Real_gfx6_gfx7_gfx10<0x005>;
1322let OtherPredicates = [HasMadMacF32Insts] in
1323defm V_MAC_LEGACY_F32     : VOP2_Real_gfx6_gfx7_gfx10<0x006>;
1324defm V_MUL_LEGACY_F32     : VOP2_Real_gfx6_gfx7_gfx10<0x007>;
1325defm V_MUL_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x008>;
1326defm V_MUL_I32_I24        : VOP2_Real_gfx6_gfx7_gfx10<0x009>;
1327defm V_MUL_HI_I32_I24     : VOP2_Real_gfx6_gfx7_gfx10<0x00a>;
1328defm V_MUL_U32_U24        : VOP2_Real_gfx6_gfx7_gfx10<0x00b>;
1329defm V_MUL_HI_U32_U24     : VOP2_Real_gfx6_gfx7_gfx10<0x00c>;
1330defm V_MIN_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x00f>;
1331defm V_MAX_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x010>;
1332defm V_MIN_I32            : VOP2_Real_gfx6_gfx7_gfx10<0x011>;
1333defm V_MAX_I32            : VOP2_Real_gfx6_gfx7_gfx10<0x012>;
1334defm V_MIN_U32            : VOP2_Real_gfx6_gfx7_gfx10<0x013>;
1335defm V_MAX_U32            : VOP2_Real_gfx6_gfx7_gfx10<0x014>;
1336defm V_LSHRREV_B32        : VOP2_Real_gfx6_gfx7_gfx10<0x016>;
1337defm V_ASHRREV_I32        : VOP2_Real_gfx6_gfx7_gfx10<0x018>;
1338defm V_LSHLREV_B32        : VOP2_Real_gfx6_gfx7_gfx10<0x01a>;
1339defm V_AND_B32            : VOP2_Real_gfx6_gfx7_gfx10<0x01b>;
1340defm V_OR_B32             : VOP2_Real_gfx6_gfx7_gfx10<0x01c>;
1341defm V_XOR_B32            : VOP2_Real_gfx6_gfx7_gfx10<0x01d>;
1342defm V_MAC_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x01f>;
1343defm V_CVT_PKRTZ_F16_F32  : VOP2_Real_gfx6_gfx7_gfx10<0x02f>;
1344defm V_MADMK_F32          : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x020>;
1345defm V_MADAK_F32          : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x021>;
1346
1347//===----------------------------------------------------------------------===//
1348// GFX8, GFX9 (VI).
1349//===----------------------------------------------------------------------===//
1350
1351let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {
1352
1353multiclass VOP2_Real_MADK_vi <bits<6> op> {
1354  def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,
1355            VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1356}
1357
1358multiclass VOP2_Real_e32_vi <bits<6> op> {
1359  def _e32_vi :
1360    VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
1361    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
1362}
1363
1364multiclass VOP2_Real_e64_vi <bits<10> op> {
1365  def _e64_vi :
1366    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
1367    VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1368}
1369
1370multiclass VOP2_Real_e64only_vi <bits<10> op> {
1371  def _e64_vi :
1372    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
1373    VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1374      // Hack to stop printing _e64
1375      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME#"_e64");
1376      let OutOperandList = (outs VGPR_32:$vdst);
1377      let AsmString = ps.Mnemonic # " " # ps.AsmOperands;
1378    }
1379}
1380
1381multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> :
1382  VOP2_Real_e32_vi<op>,
1383  VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>;
1384
1385} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8"
1386
1387multiclass VOP2_SDWA_Real <bits<6> op> {
1388  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA>.ret in
1389  def _sdwa_vi :
1390    VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1391    VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1392}
1393
1394multiclass VOP2_SDWA9_Real <bits<6> op> {
1395  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
1396  def _sdwa_gfx9 :
1397    VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1398    VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1399}
1400
1401let AssemblerPredicate = isGFX8Only in {
1402
1403multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName> {
1404  def _e32_vi :
1405    VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.VI>,
1406    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
1407      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32");
1408      let AsmString = AsmName # ps.AsmOperands;
1409      let DecoderNamespace = "GFX8";
1410    }
1411  def _e64_vi :
1412    VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.VI>,
1413    VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
1414      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64");
1415      let AsmString = AsmName # ps.AsmOperands;
1416      let DecoderNamespace = "GFX8";
1417    }
1418  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA>.ret in
1419    def _sdwa_vi :
1420      VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>,
1421      VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {
1422        VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa");
1423        let AsmString = AsmName # ps.AsmOperands;
1424      }
1425  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in
1426    def _dpp_vi :
1427      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.VI>,
1428      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> {
1429        VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp");
1430        let AsmString = AsmName # ps.AsmOperands;
1431      }
1432}
1433}
1434
1435let AssemblerPredicate = isGFX9Only in {
1436
1437multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> {
1438  def _e32_gfx9 :
1439    VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.GFX9>,
1440    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
1441      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32");
1442      let AsmString = AsmName # ps.AsmOperands;
1443      let DecoderNamespace = "GFX9";
1444    }
1445  def _e64_gfx9 :
1446    VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>,
1447    VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
1448      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64");
1449      let AsmString = AsmName # ps.AsmOperands;
1450      let DecoderNamespace = "GFX9";
1451    }
1452  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA9>.ret in
1453    def _sdwa_gfx9 :
1454      VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>,
1455      VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {
1456        VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa");
1457        let AsmString = AsmName # ps.AsmOperands;
1458      }
1459  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in
1460    def _dpp_gfx9 :
1461      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.GFX9>,
1462      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> {
1463        VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp");
1464        let AsmString = AsmName # ps.AsmOperands;
1465        let DecoderNamespace = "SDWA9";
1466      }
1467}
1468
1469multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> {
1470  def _e32_gfx9 :
1471    VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX9>,
1472    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>{
1473      let DecoderNamespace = "GFX9";
1474    }
1475  def _e64_gfx9 :
1476    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>,
1477    VOP3e_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1478      let DecoderNamespace = "GFX9";
1479    }
1480  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
1481    def _sdwa_gfx9 :
1482      VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1483      VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
1484      }
1485  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
1486    def _dpp_gfx9 :
1487      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,
1488      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
1489        let DecoderNamespace = "SDWA9";
1490      }
1491}
1492
1493} // AssemblerPredicate = isGFX9Only
1494
1495multiclass VOP2_Real_e32e64_vi <bits<6> op> :
1496  Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> {
1497
1498  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
1499    def _dpp_vi :
1500      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.VI>,
1501      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;
1502}
1503
1504defm V_CNDMASK_B32        : VOP2_Real_e32e64_vi <0x0>;
1505defm V_ADD_F32            : VOP2_Real_e32e64_vi <0x1>;
1506defm V_SUB_F32            : VOP2_Real_e32e64_vi <0x2>;
1507defm V_SUBREV_F32         : VOP2_Real_e32e64_vi <0x3>;
1508defm V_MUL_LEGACY_F32     : VOP2_Real_e32e64_vi <0x4>;
1509defm V_MUL_F32            : VOP2_Real_e32e64_vi <0x5>;
1510defm V_MUL_I32_I24        : VOP2_Real_e32e64_vi <0x6>;
1511defm V_MUL_HI_I32_I24     : VOP2_Real_e32e64_vi <0x7>;
1512defm V_MUL_U32_U24        : VOP2_Real_e32e64_vi <0x8>;
1513defm V_MUL_HI_U32_U24     : VOP2_Real_e32e64_vi <0x9>;
1514defm V_MIN_F32            : VOP2_Real_e32e64_vi <0xa>;
1515defm V_MAX_F32            : VOP2_Real_e32e64_vi <0xb>;
1516defm V_MIN_I32            : VOP2_Real_e32e64_vi <0xc>;
1517defm V_MAX_I32            : VOP2_Real_e32e64_vi <0xd>;
1518defm V_MIN_U32            : VOP2_Real_e32e64_vi <0xe>;
1519defm V_MAX_U32            : VOP2_Real_e32e64_vi <0xf>;
1520defm V_LSHRREV_B32        : VOP2_Real_e32e64_vi <0x10>;
1521defm V_ASHRREV_I32        : VOP2_Real_e32e64_vi <0x11>;
1522defm V_LSHLREV_B32        : VOP2_Real_e32e64_vi <0x12>;
1523defm V_AND_B32            : VOP2_Real_e32e64_vi <0x13>;
1524defm V_OR_B32             : VOP2_Real_e32e64_vi <0x14>;
1525defm V_XOR_B32            : VOP2_Real_e32e64_vi <0x15>;
1526defm V_MAC_F32            : VOP2_Real_e32e64_vi <0x16>;
1527defm V_MADMK_F32          : VOP2_Real_MADK_vi <0x17>;
1528defm V_MADAK_F32          : VOP2_Real_MADK_vi <0x18>;
1529
1530defm V_ADD_U32            : VOP2be_Real_e32e64_vi_only <0x19, "V_ADD_CO_U32",     "v_add_u32">;
1531defm V_SUB_U32            : VOP2be_Real_e32e64_vi_only <0x1a, "V_SUB_CO_U32",     "v_sub_u32">;
1532defm V_SUBREV_U32         : VOP2be_Real_e32e64_vi_only <0x1b, "V_SUBREV_CO_U32",  "v_subrev_u32">;
1533defm V_ADDC_U32           : VOP2be_Real_e32e64_vi_only <0x1c, "V_ADDC_U32",    "v_addc_u32">;
1534defm V_SUBB_U32           : VOP2be_Real_e32e64_vi_only <0x1d, "V_SUBB_U32",    "v_subb_u32">;
1535defm V_SUBBREV_U32        : VOP2be_Real_e32e64_vi_only <0x1e, "V_SUBBREV_U32", "v_subbrev_u32">;
1536
1537defm V_ADD_CO_U32         : VOP2be_Real_e32e64_gfx9 <0x19, "V_ADD_CO_U32",     "v_add_co_u32">;
1538defm V_SUB_CO_U32         : VOP2be_Real_e32e64_gfx9 <0x1a, "V_SUB_CO_U32",     "v_sub_co_u32">;
1539defm V_SUBREV_CO_U32      : VOP2be_Real_e32e64_gfx9 <0x1b, "V_SUBREV_CO_U32",  "v_subrev_co_u32">;
1540defm V_ADDC_CO_U32        : VOP2be_Real_e32e64_gfx9 <0x1c, "V_ADDC_U32",    "v_addc_co_u32">;
1541defm V_SUBB_CO_U32        : VOP2be_Real_e32e64_gfx9 <0x1d, "V_SUBB_U32",    "v_subb_co_u32">;
1542defm V_SUBBREV_CO_U32     : VOP2be_Real_e32e64_gfx9 <0x1e, "V_SUBBREV_U32", "v_subbrev_co_u32">;
1543
1544defm V_ADD_U32            : VOP2_Real_e32e64_gfx9 <0x34>;
1545defm V_SUB_U32            : VOP2_Real_e32e64_gfx9 <0x35>;
1546defm V_SUBREV_U32         : VOP2_Real_e32e64_gfx9 <0x36>;
1547
1548defm V_BFM_B32            : VOP2_Real_e64only_vi <0x293>;
1549defm V_BCNT_U32_B32       : VOP2_Real_e64only_vi <0x28b>;
1550defm V_MBCNT_LO_U32_B32   : VOP2_Real_e64only_vi <0x28c>;
1551defm V_MBCNT_HI_U32_B32   : VOP2_Real_e64only_vi <0x28d>;
1552defm V_LDEXP_F32          : VOP2_Real_e64only_vi <0x288>;
1553defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64only_vi <0x1f0>;
1554defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64only_vi <0x294>;
1555defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64only_vi <0x295>;
1556defm V_CVT_PKRTZ_F16_F32  : VOP2_Real_e64only_vi <0x296>;
1557defm V_CVT_PK_U16_U32     : VOP2_Real_e64only_vi <0x297>;
1558defm V_CVT_PK_I16_I32     : VOP2_Real_e64only_vi <0x298>;
1559
1560defm V_ADD_F16            : VOP2_Real_e32e64_vi <0x1f>;
1561defm V_SUB_F16            : VOP2_Real_e32e64_vi <0x20>;
1562defm V_SUBREV_F16         : VOP2_Real_e32e64_vi <0x21>;
1563defm V_MUL_F16            : VOP2_Real_e32e64_vi <0x22>;
1564defm V_MAC_F16            : VOP2_Real_e32e64_vi <0x23>;
1565defm V_MADMK_F16          : VOP2_Real_MADK_vi <0x24>;
1566defm V_MADAK_F16          : VOP2_Real_MADK_vi <0x25>;
1567defm V_ADD_U16            : VOP2_Real_e32e64_vi <0x26>;
1568defm V_SUB_U16            : VOP2_Real_e32e64_vi <0x27>;
1569defm V_SUBREV_U16         : VOP2_Real_e32e64_vi <0x28>;
1570defm V_MUL_LO_U16         : VOP2_Real_e32e64_vi <0x29>;
1571defm V_LSHLREV_B16        : VOP2_Real_e32e64_vi <0x2a>;
1572defm V_LSHRREV_B16        : VOP2_Real_e32e64_vi <0x2b>;
1573defm V_ASHRREV_I16        : VOP2_Real_e32e64_vi <0x2c>;
1574defm V_MAX_F16            : VOP2_Real_e32e64_vi <0x2d>;
1575defm V_MIN_F16            : VOP2_Real_e32e64_vi <0x2e>;
1576defm V_MAX_U16            : VOP2_Real_e32e64_vi <0x2f>;
1577defm V_MAX_I16            : VOP2_Real_e32e64_vi <0x30>;
1578defm V_MIN_U16            : VOP2_Real_e32e64_vi <0x31>;
1579defm V_MIN_I16            : VOP2_Real_e32e64_vi <0x32>;
1580defm V_LDEXP_F16          : VOP2_Real_e32e64_vi <0x33>;
1581
1582let SubtargetPredicate = isGFX8GFX9 in {
1583
1584// Aliases to simplify matching of floating-point instructions that
1585// are VOP2 on SI and VOP3 on VI.
1586class SI2_VI3Alias <string name, VOP3_Real inst> : InstAlias <
1587  name#" $dst, $src0, $src1",
1588  !if(inst.Pfl.HasOMod,
1589      (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0),
1590      (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0))
1591>, PredicateControl {
1592  let UseInstAsmMatchConverter = 0;
1593  let AsmVariantName = AMDGPUAsmVariants.VOP3;
1594}
1595
1596def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>;
1597def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>;
1598def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>;
1599def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;
1600def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;
1601
1602defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_vi>;
1603
1604} // End SubtargetPredicate = isGFX8GFX9
1605
1606let SubtargetPredicate = isGFX9Only in {
1607
1608defm : VOP2bInstAliases<V_ADD_U32_e32,     V_ADD_CO_U32_e32_gfx9,     "v_add_co_u32">;
1609defm : VOP2bInstAliases<V_ADDC_U32_e32,    V_ADDC_CO_U32_e32_gfx9,    "v_addc_co_u32">;
1610defm : VOP2bInstAliases<V_SUB_U32_e32,     V_SUB_CO_U32_e32_gfx9,     "v_sub_co_u32">;
1611defm : VOP2bInstAliases<V_SUBB_U32_e32,    V_SUBB_CO_U32_e32_gfx9,    "v_subb_co_u32">;
1612defm : VOP2bInstAliases<V_SUBREV_U32_e32,  V_SUBREV_CO_U32_e32_gfx9,  "v_subrev_co_u32">;
1613defm : VOP2bInstAliases<V_SUBBREV_U32_e32, V_SUBBREV_CO_U32_e32_gfx9, "v_subbrev_co_u32">;
1614
1615} // End SubtargetPredicate = isGFX9Only
1616
1617let SubtargetPredicate = HasDLInsts in {
1618
1619defm V_FMAC_F32 : VOP2_Real_e32e64_vi <0x3b>;
1620defm V_XNOR_B32 : VOP2_Real_e32e64_vi <0x3d>;
1621
1622} // End SubtargetPredicate = HasDLInsts
1623
1624multiclass VOP2_Real_DOT_ACC_gfx9<bits<6> op> : VOP2_Real_e32_vi<op> {
1625  def _dpp_vi : VOP2_DPP<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;
1626}
1627
1628multiclass VOP2_Real_DOT_ACC_gfx10<bits<6> op> :
1629  VOP2_Real_e32_gfx10<op>,
1630  VOP2_Real_dpp_gfx10<op>,
1631  VOP2_Real_dpp8_gfx10<op>;
1632
1633let SubtargetPredicate = HasDot5Insts in {
1634  defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx9<0x37>;
1635  // NB: Opcode conflicts with V_DOT8C_I32_I4
1636  // This opcode exists in gfx 10.1* only
1637  defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx10<0x02>;
1638}
1639
1640let SubtargetPredicate = HasDot6Insts in {
1641  defm V_DOT4C_I32_I8  : VOP2_Real_DOT_ACC_gfx9<0x39>;
1642  defm V_DOT4C_I32_I8  : VOP2_Real_DOT_ACC_gfx10<0x0d>;
1643}
1644
1645let SubtargetPredicate = HasDot4Insts in {
1646  defm V_DOT2C_I32_I16 : VOP2_Real_DOT_ACC_gfx9<0x38>;
1647}
1648let SubtargetPredicate = HasDot3Insts in {
1649  defm V_DOT8C_I32_I4  : VOP2_Real_DOT_ACC_gfx9<0x3a>;
1650}
1651
1652let SubtargetPredicate = HasPkFmacF16Inst in {
1653defm V_PK_FMAC_F16 : VOP2_Real_e32_vi<0x3c>;
1654} // End SubtargetPredicate = HasPkFmacF16Inst
1655
1656let SubtargetPredicate = HasDot3Insts in {
1657  // NB: Opcode conflicts with V_DOT2C_F32_F16
1658  let DecoderNamespace = "GFX10_B" in
1659  defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx10<0x02>;
1660}
1661