1//===-- VOP2Instructions.td - Vector Instruction Definitions --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// VOP2 Classes
11//===----------------------------------------------------------------------===//
12
13class VOP2e <bits<6> op, VOPProfile P> : Enc32 {
14  bits<8> vdst;
15  bits<9> src0;
16  bits<8> src1;
17
18  let Inst{8-0}   = !if(P.HasSrc0, src0, 0);
19  let Inst{16-9}  = !if(P.HasSrc1, src1, 0);
20  let Inst{24-17} = !if(P.EmitDst, vdst, 0);
21  let Inst{30-25} = op;
22  let Inst{31}    = 0x0; //encoding
23}
24
25class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 {
26  bits<8>  vdst;
27  bits<9>  src0;
28  bits<8>  src1;
29  bits<32> imm;
30
31  let Inst{8-0}   = !if(P.HasSrc0, src0, 0);
32  let Inst{16-9}  = !if(P.HasSrc1, src1, 0);
33  let Inst{24-17} = !if(P.EmitDst, vdst, 0);
34  let Inst{30-25} = op;
35  let Inst{31}    = 0x0; // encoding
36  let Inst{63-32} = imm;
37}
38
39class VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> {
40  bits<8> vdst;
41  bits<8> src1;
42
43  let Inst{8-0}   = 0xf9; // sdwa
44  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
45  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
46  let Inst{30-25} = op;
47  let Inst{31}    = 0x0; // encoding
48}
49
50class VOP2_SDWA9Ae <bits<6> op, VOPProfile P> : VOP_SDWA9Ae <P> {
51  bits<8> vdst;
52  bits<9> src1;
53
54  let Inst{8-0}   = 0xf9; // sdwa
55  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
56  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
57  let Inst{30-25} = op;
58  let Inst{31}    = 0x0; // encoding
59  let Inst{63}    = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr
60}
61
62class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> :
63  VOP_Pseudo <opName, suffix, P, P.Outs32, P.Ins32, "", pattern> {
64
65  let AsmOperands = P.Asm32;
66
67  let Size = 4;
68  let mayLoad = 0;
69  let mayStore = 0;
70  let hasSideEffects = 0;
71
72  let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
73
74  let mayRaiseFPException = ReadsModeReg;
75
76  let VOP2 = 1;
77  let VALU = 1;
78  let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
79
80  let AsmVariantName = AMDGPUAsmVariants.Default;
81}
82
83class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> :
84  VOP_Real <ps>,
85  InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
86  SIMCInstr <ps.PseudoInstr, EncodingFamily> {
87
88  let isPseudo = 0;
89  let isCodeGenOnly = 0;
90
91  let Constraints     = ps.Constraints;
92  let DisableEncoding = ps.DisableEncoding;
93
94  // copy relevant pseudo op flags
95  let SubtargetPredicate = ps.SubtargetPredicate;
96  let OtherPredicates    = ps.OtherPredicates;
97  let AsmMatchConverter  = ps.AsmMatchConverter;
98  let AsmVariantName     = ps.AsmVariantName;
99  let Constraints        = ps.Constraints;
100  let DisableEncoding    = ps.DisableEncoding;
101  let TSFlags            = ps.TSFlags;
102  let UseNamedOperandTable = ps.UseNamedOperandTable;
103  let Uses                 = ps.Uses;
104  let Defs                 = ps.Defs;
105  let SchedRW              = ps.SchedRW;
106}
107
108class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
109  VOP_SDWA_Pseudo <OpName, P, pattern> {
110  let AsmMatchConverter = "cvtSdwaVOP2";
111}
112
113class VOP2_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
114  VOP_DPP_Pseudo <OpName, P, pattern> {
115}
116
117
118class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies {
119  list<dag> ret = !if(P.HasModifiers,
120    [(set P.DstVT:$vdst,
121      (node (P.Src0VT
122              !if(P.HasOMod,
123                  (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
124                  (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
125            (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
126    [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
127}
128
129multiclass VOP2Inst_e32<string opName,
130                        VOPProfile P,
131                        SDPatternOperator node = null_frag,
132                        string revOp = opName,
133                        bit GFX9Renamed = 0> {
134  let renamedInGFX9 = GFX9Renamed in {
135    def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
136               Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
137  } // End renamedInGFX9 = GFX9Renamed
138}
139
140multiclass VOP2Inst_e64<string opName,
141                        VOPProfile P,
142                        SDPatternOperator node = null_frag,
143                        string revOp = opName,
144                        bit GFX9Renamed = 0> {
145  let renamedInGFX9 = GFX9Renamed in {
146    def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
147               Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
148  } // End renamedInGFX9 = GFX9Renamed
149}
150
151multiclass VOP2Inst_sdwa<string opName,
152                         VOPProfile P,
153                         SDPatternOperator node = null_frag,
154                         string revOp = opName,
155                         bit GFX9Renamed = 0> {
156  let renamedInGFX9 = GFX9Renamed in {
157    foreach _ = BoolToList<P.HasExtSDWA>.ret in
158      def _sdwa : VOP2_SDWA_Pseudo <opName, P>;
159  } // End renamedInGFX9 = GFX9Renamed
160}
161
162multiclass VOP2Inst<string opName,
163                    VOPProfile P,
164                    SDPatternOperator node = null_frag,
165                    string revOp = opName,
166                    bit GFX9Renamed = 0> :
167    VOP2Inst_e32<opName, P, node, revOp, GFX9Renamed>,
168    VOP2Inst_e64<opName, P, node, revOp, GFX9Renamed>,
169    VOP2Inst_sdwa<opName, P, node, revOp, GFX9Renamed> {
170  let renamedInGFX9 = GFX9Renamed in {
171    foreach _ = BoolToList<P.HasExtDPP>.ret in
172      def _dpp  : VOP2_DPP_Pseudo <opName, P>;
173  }
174}
175
176multiclass VOP2bInst <string opName,
177                      VOPProfile P,
178                      SDPatternOperator node = null_frag,
179                      string revOp = opName,
180                      bit GFX9Renamed = 0,
181                      bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
182  let renamedInGFX9 = GFX9Renamed in {
183    let SchedRW = [Write32Bit, WriteSALU] in {
184      let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
185        def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
186                   Commutable_REV<revOp#"_e32", !eq(revOp, opName)> {
187          let usesCustomInserter = !eq(P.NumSrcArgs, 2);
188        }
189
190        foreach _ = BoolToList<P.HasExtSDWA>.ret in
191          def _sdwa  : VOP2_SDWA_Pseudo <opName, P> {
192            let AsmMatchConverter = "cvtSdwaVOP2b";
193          }
194        foreach _ = BoolToList<P.HasExtDPP>.ret in
195          def _dpp  : VOP2_DPP_Pseudo <opName, P>;
196      }
197
198      def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
199                 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
200    }
201  }
202}
203
204class VOP2bInstAlias <VOP2_Pseudo ps, Instruction inst,
205                      string OpName, string opnd> :
206  InstAlias <OpName#" "#!subst("vcc", opnd, ps.Pfl.Asm32),
207             (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
208                   ps.Pfl.Src1RC32:$src1)>,
209  PredicateControl {
210}
211
212multiclass VOP2bInstAliases<VOP2_Pseudo ps, VOP2_Real inst, string OpName> {
213  let WaveSizePredicate = isWave32 in {
214    def : VOP2bInstAlias<ps, inst, OpName, "vcc_lo">;
215  }
216  let WaveSizePredicate = isWave64 in {
217    def : VOP2bInstAlias<ps, inst, OpName, "vcc">;
218  }
219}
220
221multiclass VOP2eInst <string opName,
222                      VOPProfile P,
223                      SDPatternOperator node = null_frag,
224                      string revOp = opName,
225                      bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
226
227  let SchedRW = [Write32Bit] in {
228    let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in {
229      def _e32 : VOP2_Pseudo <opName, P>,
230                 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
231
232      foreach _ = BoolToList<P.HasExtSDWA>.ret in
233        def _sdwa : VOP2_SDWA_Pseudo <opName, P> {
234          let AsmMatchConverter = "cvtSdwaVOP2e";
235        }
236
237      foreach _ = BoolToList<P.HasExtDPP>.ret in
238        def _dpp  : VOP2_DPP_Pseudo <opName, P>;
239    }
240
241    def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
242               Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
243  }
244}
245
246class VOP2eInstAlias <VOP2_Pseudo ps, Instruction inst, string opnd = ""> :
247  InstAlias <ps.OpName#" "#ps.Pfl.Asm32#", "#opnd,
248             (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
249                   ps.Pfl.Src1RC32:$src1)>, PredicateControl;
250
251class VOP2e64InstAlias <VOP3_Pseudo ps, Instruction inst> :
252  InstAlias <ps.OpName#" "#ps.Pfl.Asm64,
253             (inst ps.Pfl.DstRC:$vdst, VOPDstS64orS32:$sdst,
254                   ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, clampmod:$clamp)>,
255  PredicateControl;
256
257multiclass VOP2eInstAliases<VOP2_Pseudo ps, VOP2_Real inst> {
258  let WaveSizePredicate = isWave32 in {
259    def : VOP2eInstAlias<ps, inst, "vcc_lo">;
260  }
261  let WaveSizePredicate = isWave64 in {
262    def : VOP2eInstAlias<ps, inst, "vcc">;
263  }
264}
265
266class VOP_MADAK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
267  field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
268  field dag Ins32 = !if(!eq(vt.Size, 32),
269                        (ins VCSrc_f32:$src0, VGPR_32:$src1, ImmOpType:$imm),
270                        (ins VCSrc_f16:$src0, VGPR_32:$src1, ImmOpType:$imm));
271  field bit HasExt = 0;
272  let IsSingle = 1;
273
274  field string Asm32 = "$vdst, $src0, $src1, $imm";
275}
276
277def VOP_MADAK_F16 : VOP_MADAK <f16>;
278def VOP_MADAK_F32 : VOP_MADAK <f32>;
279
280class VOP_MADMK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
281  field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
282  field dag Ins32 = (ins VCSrc_f32:$src0, ImmOpType:$imm, VGPR_32:$src1);
283  field bit HasExt = 0;
284  let IsSingle = 1;
285
286  field string Asm32 = "$vdst, $src0, $imm, $src1";
287}
288
289def VOP_MADMK_F16 : VOP_MADMK <f16>;
290def VOP_MADMK_F32 : VOP_MADMK <f32>;
291
292class getRegisterOperandForVT<ValueType VT> {
293  RegisterOperand ret = RegisterOperand<getVregSrcForVT<VT>.ret>;
294}
295
296// FIXME: Remove src2_modifiers. It isn't used, so is wasting memory
297// and processing time but it makes it easier to convert to mad.
298class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, vt0]> {
299  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, getVregSrcForVT<Src2VT>.ret:$src2);
300  let Ins64 = getIns64<Src0RC64, Src1RC64, getRegisterOperandForVT<Src2VT>.ret, 3,
301                       0, HasModifiers, HasModifiers, HasOMod,
302                       Src0Mod, Src1Mod, Src2Mod>.ret;
303  let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
304                    Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
305                    getVregSrcForVT<Src2VT>.ret:$src2, // stub argument
306                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
307                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
308  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
309  let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
310                     Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
311                     getVregSrcForVT<Src2VT>.ret:$src2, // stub argument
312                     dpp8:$dpp8, FI:$fi);
313  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
314                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
315                     getVregSrcForVT<Src2VT>.ret:$src2, // stub argument
316                     clampmod:$clamp, omod:$omod,
317                     dst_sel:$dst_sel, dst_unused:$dst_unused,
318                     src0_sel:$src0_sel, src1_sel:$src1_sel);
319  let Asm32 = getAsm32<1, 2, vt0>.ret;
320  let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, vt0>.ret;
321  let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt0>.ret;
322  let AsmDPP16 = getAsmDPP16<1, 2, HasModifiers, vt0>.ret;
323  let AsmDPP8 = getAsmDPP8<1, 2, 0, vt0>.ret;
324  let AsmSDWA = getAsmSDWA<1, 2, vt0>.ret;
325  let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt0>.ret;
326  let HasSrc2 = 0;
327  let HasSrc2Mods = 0;
328
329  let HasExt = 1;
330  let HasExtDPP = 1;
331  let HasExtSDWA = 1;
332  let HasExtSDWA9 = 0;
333  let TieRegDPP = "$src2";
334}
335
336def VOP_MAC_F16 : VOP_MAC <f16>;
337def VOP_MAC_F32 : VOP_MAC <f32>;
338let HasExtDPP = 0 in
339def VOP_MAC_LEGACY_F32 : VOP_MAC <f32>;
340let HasExtSDWA = 0, HasExt64BitDPP = 1 in
341def VOP_MAC_F64 : VOP_MAC <f64>;
342
343class VOP_DOT_ACC<ValueType vt0, ValueType vt1> : VOP_MAC<vt0, vt1> {
344  let HasClamp = 0;
345  let HasExtSDWA = 0;
346  let HasOpSel = 0;
347  let IsPacked = 0;
348}
349
350def VOP_DOT_ACC_F32_V2F16 : VOP_DOT_ACC<f32, v2f16> {
351  let Src0ModDPP = FPVRegInputMods;
352  let Src1ModDPP = FPVRegInputMods;
353}
354
355def VOP_DOT_ACC_I32_I32   : VOP_DOT_ACC<i32, i32> {
356  let HasSrc0Mods = 1;
357  let HasSrc1Mods = 1;
358}
359
360// Write out to vcc or arbitrary SGPR.
361def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], 0, /*EnableClamp=*/1> {
362  let Asm32 = "$vdst, vcc, $src0, $src1";
363  let Asm64 = "$vdst, $sdst, $src0, $src1$clamp";
364  let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
365  let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
366  let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
367  let AsmDPP8 = "$vdst, vcc, $src0, $src1 $dpp8$fi";
368  let AsmDPP16 = AsmDPP#"$fi";
369  let Outs32 = (outs DstRC:$vdst);
370  let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
371}
372
373// Write out to vcc or arbitrary SGPR and read in from vcc or
374// arbitrary SGPR.
375def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], 0, /*EnableClamp=*/1> {
376  let Asm32 = "$vdst, vcc, $src0, $src1, vcc";
377  let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
378  let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
379  let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
380  let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
381  let AsmDPP8 = "$vdst, vcc, $src0, $src1, vcc $dpp8$fi";
382  let AsmDPP16 = AsmDPP#"$fi";
383  let Outs32 = (outs DstRC:$vdst);
384  let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
385
386  // Suppress src2 implied by type since the 32-bit encoding uses an
387  // implicit VCC use.
388  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
389
390  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
391                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
392                     clampmod:$clamp,
393                     dst_sel:$dst_sel, dst_unused:$dst_unused,
394                     src0_sel:$src0_sel, src1_sel:$src1_sel);
395
396  let InsDPP = (ins DstRCDPP:$old,
397                    Src0DPP:$src0,
398                    Src1DPP:$src1,
399                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
400                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
401  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
402
403  let HasExt = 1;
404  let HasExtDPP = 1;
405  let HasExtSDWA = 1;
406  let HasExtSDWA9 = 1;
407}
408
409// Read in from vcc or arbitrary SGPR.
410def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], /*EnableF32SrcMods=*/1> {
411  let Asm32 = "$vdst, $src0, $src1";
412  let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2";
413  let AsmSDWA = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
414  let AsmSDWA9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
415  let AsmDPP = "$vdst, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
416  let AsmDPP8 = "$vdst, $src0, $src1, vcc $dpp8$fi";
417  let AsmDPP16 = AsmDPP#"$fi";
418
419  let Outs32 = (outs DstRC:$vdst);
420  let Outs64 = (outs DstRC:$vdst);
421
422  // Suppress src2 implied by type since the 32-bit encoding uses an
423  // implicit VCC use.
424  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
425
426  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
427                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
428                     clampmod:$clamp,
429                     dst_sel:$dst_sel, dst_unused:$dst_unused,
430                     src0_sel:$src0_sel, src1_sel:$src1_sel);
431
432  let InsDPP = (ins DstRCDPP:$old,
433                    Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
434                    Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
435                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
436                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
437  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
438
439  let HasExt = 1;
440  let HasExtDPP = 1;
441  let HasExtSDWA = 1;
442  let HasExtSDWA9 = 1;
443}
444
445def VOP_READLANE : VOPProfile<[i32, i32, i32]> {
446  let Outs32 = (outs SReg_32:$vdst);
447  let Outs64 = Outs32;
448  let Ins32 = (ins VRegOrLds_32:$src0, SCSrc_b32:$src1);
449  let Ins64 = Ins32;
450  let Asm32 = " $vdst, $src0, $src1";
451  let Asm64 = Asm32;
452
453  let HasExt = 0;
454  let HasExtDPP = 0;
455  let HasExt64BitDPP = 0;
456  let HasExtSDWA = 0;
457  let HasExtSDWA9 = 0;
458}
459
460def VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> {
461  let Outs32 = (outs VGPR_32:$vdst);
462  let Outs64 = Outs32;
463  let Ins32 = (ins SCSrc_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in);
464  let Ins64 = Ins32;
465  let Asm32 = " $vdst, $src0, $src1";
466  let Asm64 = Asm32;
467  let HasSrc2 = 0;
468  let HasSrc2Mods = 0;
469
470  let HasExt = 0;
471  let HasExtDPP = 0;
472  let HasExt64BitDPP = 0;
473  let HasExtSDWA = 0;
474  let HasExtSDWA9 = 0;
475}
476
477//===----------------------------------------------------------------------===//
478// VOP2 Instructions
479//===----------------------------------------------------------------------===//
480
481defm V_CNDMASK_B32 : VOP2eInst <"v_cndmask_b32", VOP2e_I32_I32_I32_I1>;
482let SubtargetPredicate = HasMadMacF32Insts in
483def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, []>;
484
485let isCommutable = 1 in {
486defm V_ADD_F32 : VOP2Inst <"v_add_f32", VOP_F32_F32_F32, any_fadd>;
487defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, any_fsub>;
488defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">;
489defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>;
490defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, any_fmul>;
491defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32_ARITH, AMDGPUmul_i24>;
492defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_i24>;
493defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32_ARITH, AMDGPUmul_u24>;
494defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_u24>;
495defm V_MIN_F32 : VOP2Inst <"v_min_f32", VOP_F32_F32_F32, fminnum_like>;
496defm V_MAX_F32 : VOP2Inst <"v_max_f32", VOP_F32_F32_F32, fmaxnum_like>;
497defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smin>;
498defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smax>;
499defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umin>;
500defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umax>;
501defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, lshr_rev, "v_lshr_b32">;
502defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, ashr_rev, "v_ashr_i32">;
503defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, lshl_rev, "v_lshl_b32">;
504defm V_AND_B32 : VOP2Inst <"v_and_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, and>;
505defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, or>;
506defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, xor>;
507
508let mayRaiseFPException = 0 in {
509let OtherPredicates = [HasMadMacF32Insts] in {
510let Constraints = "$vdst = $src2", DisableEncoding="$src2",
511    isConvertibleToThreeAddress = 1 in {
512defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>;
513
514let SubtargetPredicate = isGFX6GFX7GFX10 in
515defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_MAC_LEGACY_F32>;
516} // End Constraints = "$vdst = $src2", DisableEncoding="$src2",
517  //     isConvertibleToThreeAddress = 1
518
519def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32, []>;
520} // End OtherPredicates = [HasMadMacF32Insts]
521} // End mayRaiseFPException = 0
522
523// No patterns so that the scalar instructions are always selected.
524// The scalar versions will be replaced with vector when needed later.
525defm V_ADD_CO_U32 : VOP2bInst <"v_add_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_add_co_u32", 1>;
526defm V_SUB_CO_U32 : VOP2bInst <"v_sub_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>;
527defm V_SUBREV_CO_U32 : VOP2bInst <"v_subrev_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>;
528defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_addc_u32", 1>;
529defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>;
530defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>;
531
532
533let SubtargetPredicate = HasAddNoCarryInsts in {
534defm V_ADD_U32 : VOP2Inst <"v_add_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_add_u32", 1>;
535defm V_SUB_U32 : VOP2Inst <"v_sub_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>;
536defm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>;
537}
538
539} // End isCommutable = 1
540
541// These are special and do not read the exec mask.
542let isConvergent = 1, Uses = []<Register> in {
543def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE,
544  [(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))]>;
545
546let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in {
547def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE,
548  [(set i32:$vdst, (int_amdgcn_writelane i32:$src0, i32:$src1, i32:$vdst_in))]>;
549} // End $vdst = $vdst_in, DisableEncoding $vdst_in
550} // End isConvergent = 1
551
552defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_NO_EXT<VOP_I32_I32_I32>>;
553defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, add_ctpop>;
554defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_lo>;
555defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_hi>;
556defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_NO_EXT<VOP_F32_F32_I32>, AMDGPUldexp>;
557defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_NO_EXT<VOP_I32_F32_I32>>; // TODO: set "Uses = dst"
558
559let ReadsModeReg = 0, mayRaiseFPException = 0 in {
560defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_i16_f32>;
561defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_u16_f32>;
562}
563
564defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_NO_EXT<VOP_V2F16_F32_F32>, AMDGPUpkrtz_f16_f32>;
565defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_u16_u32>;
566defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_i16_i32>;
567
568
569let SubtargetPredicate = isGFX6GFX7 in {
570defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>;
571defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>;
572} // End SubtargetPredicate = isGFX6GFX7
573
574let isCommutable = 1 in {
575let SubtargetPredicate = isGFX6GFX7 in {
576defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, srl>;
577defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, sra>;
578defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, shl>;
579} // End SubtargetPredicate = isGFX6GFX7
580} // End isCommutable = 1
581
582
583class DivergentBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :
584  GCNPat<
585      (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
586      !if(!cast<Commutable_REV>(Inst).IsOrig,
587        (Inst $src0, $src1),
588        (Inst $src1, $src0)
589      )
590  >;
591
592class DivergentClampingBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :
593  GCNPat<
594      (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
595      !if(!cast<Commutable_REV>(Inst).IsOrig,
596        (Inst $src0, $src1, 0),
597        (Inst $src1, $src0, 0)
598      )
599  >;
600
601def : DivergentBinOp<srl, V_LSHRREV_B32_e64>;
602def : DivergentBinOp<sra, V_ASHRREV_I32_e64>;
603def : DivergentBinOp<shl, V_LSHLREV_B32_e64>;
604
605let SubtargetPredicate = HasAddNoCarryInsts in {
606  def : DivergentClampingBinOp<add, V_ADD_U32_e64>;
607  def : DivergentClampingBinOp<sub, V_SUB_U32_e64>;
608}
609
610let SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] in {
611def : DivergentClampingBinOp<add, V_ADD_CO_U32_e64>;
612def : DivergentClampingBinOp<sub, V_SUB_CO_U32_e64>;
613}
614
615def : DivergentBinOp<adde, V_ADDC_U32_e32>;
616def : DivergentBinOp<sube, V_SUBB_U32_e32>;
617
618class divergent_i64_BinOp <SDPatternOperator Op, Instruction Inst> :
619  GCNPat<
620      (getDivergentFrag<Op>.ret i64:$src0, i64:$src1),
621      (REG_SEQUENCE VReg_64,
622        (Inst
623          (i32 (EXTRACT_SUBREG $src0, sub0)),
624          (i32 (EXTRACT_SUBREG $src1, sub0))
625        ), sub0,
626        (Inst
627          (i32 (EXTRACT_SUBREG $src0, sub1)),
628          (i32 (EXTRACT_SUBREG $src1, sub1))
629        ), sub1
630      )
631  >;
632
633def :  divergent_i64_BinOp <and, V_AND_B32_e32>;
634def :  divergent_i64_BinOp <or,  V_OR_B32_e32>;
635def :  divergent_i64_BinOp <xor, V_XOR_B32_e32>;
636
637let SubtargetPredicate = Has16BitInsts in {
638
639let FPDPRounding = 1 in {
640def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16, [], "">;
641defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>;
642} // End FPDPRounding = 1
643
644defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16, lshl_rev>;
645defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16, lshr_rev>;
646defm V_ASHRREV_I16 : VOP2Inst <"v_ashrrev_i16", VOP_I16_I16_I16, ashr_rev>;
647
648let isCommutable = 1 in {
649let FPDPRounding = 1 in {
650defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, any_fadd>;
651defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, any_fsub>;
652defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">;
653defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, any_fmul>;
654
655let mayRaiseFPException = 0 in {
656def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">;
657}
658
659} // End FPDPRounding = 1
660defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16_ARITH, add>;
661defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16_ARITH, sub>;
662defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16_ARITH, null_frag, "v_sub_u16">;
663defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16, mul>;
664defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum_like>;
665defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum_like>;
666defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16, umax>;
667defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16, smax>;
668defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16, umin>;
669defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16, smin>;
670
671let Constraints = "$vdst = $src2", DisableEncoding="$src2",
672    isConvertibleToThreeAddress = 1 in {
673defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>;
674}
675} // End isCommutable = 1
676
677} // End SubtargetPredicate = Has16BitInsts
678
679let SubtargetPredicate = HasDLInsts in {
680
681defm V_XNOR_B32 : VOP2Inst <"v_xnor_b32", VOP_I32_I32_I32, xnor>;
682
683let Constraints = "$vdst = $src2",
684    DisableEncoding = "$src2",
685    isConvertibleToThreeAddress = 1,
686    isCommutable = 1 in
687defm V_FMAC_F32 : VOP2Inst <"v_fmac_f32", VOP_MAC_F32>;
688
689} // End SubtargetPredicate = HasDLInsts
690
691let SubtargetPredicate = HasFmaLegacy32 in {
692
693let Constraints = "$vdst = $src2",
694    DisableEncoding = "$src2",
695    isConvertibleToThreeAddress = 1,
696    isCommutable = 1 in
697defm V_FMAC_LEGACY_F32 : VOP2Inst <"v_fmac_legacy_f32", VOP_MAC_LEGACY_F32>;
698
699} // End SubtargetPredicate = HasFmaLegacy32
700
701let SubtargetPredicate = isGFX90APlus,
702    Constraints = "$vdst = $src2",
703    DisableEncoding="$src2",
704    isConvertibleToThreeAddress = 1,
705    isCommutable = 1,
706    SchedRW = [WriteDoubleAdd] in
707defm V_FMAC_F64 : VOP2Inst <"v_fmac_f64", VOP_MAC_F64>;
708
709let Constraints = "$vdst = $src2",
710      DisableEncoding="$src2",
711      isConvertibleToThreeAddress = 1,
712      isCommutable = 1,
713      IsDOT = 1 in {
714  let SubtargetPredicate = HasDot5Insts in
715    defm V_DOT2C_F32_F16 : VOP2Inst<"v_dot2c_f32_f16", VOP_DOT_ACC_F32_V2F16>;
716  let SubtargetPredicate = HasDot6Insts in
717    defm V_DOT4C_I32_I8  : VOP2Inst<"v_dot4c_i32_i8",  VOP_DOT_ACC_I32_I32>;
718
719  let SubtargetPredicate = HasDot4Insts in
720    defm V_DOT2C_I32_I16 : VOP2Inst<"v_dot2c_i32_i16", VOP_DOT_ACC_I32_I32>;
721  let SubtargetPredicate = HasDot3Insts in
722    defm V_DOT8C_I32_I4  : VOP2Inst<"v_dot8c_i32_i4",  VOP_DOT_ACC_I32_I32>;
723}
724
725let AddedComplexity = 30 in {
726  def : GCNPat<
727    (f32 (AMDGPUfdot2 v2f16:$src0, v2f16:$src1, f32:$src2, (i1 DSTCLAMP.NONE))),
728    (f32 (V_DOT2C_F32_F16_e32 $src0, $src1, $src2))
729  > {
730    let SubtargetPredicate = HasDot5Insts;
731  }
732  def : GCNPat<
733    (i32 (int_amdgcn_sdot4 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
734    (i32 (V_DOT4C_I32_I8_e32 $src0, $src1, $src2))
735  > {
736    let SubtargetPredicate = HasDot6Insts;
737  }
738  def : GCNPat<
739    (i32 (int_amdgcn_sdot2 v2i16:$src0, v2i16:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
740    (i32 (V_DOT2C_I32_I16_e32 $src0, $src1, $src2))
741  > {
742    let SubtargetPredicate = HasDot4Insts;
743  }
744  def : GCNPat<
745    (i32 (int_amdgcn_sdot8 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
746    (i32 (V_DOT8C_I32_I4_e32 $src0, $src1, $src2))
747  > {
748    let SubtargetPredicate = HasDot3Insts;
749  }
750} // End AddedComplexity = 30
751
752let SubtargetPredicate = HasFmaakFmamkF32Insts in {
753def V_FMAMK_F32 : VOP2_Pseudo<"v_fmamk_f32", VOP_MADMK_F32, [], "">;
754
755let isCommutable = 1 in
756def V_FMAAK_F32 : VOP2_Pseudo<"v_fmaak_f32", VOP_MADAK_F32, [], "">;
757}
758
759let SubtargetPredicate = isGFX10Plus in {
760
761let FPDPRounding = 1 in {
762def V_FMAMK_F16 : VOP2_Pseudo <"v_fmamk_f16", VOP_MADMK_F16, [], "">;
763
764let isCommutable = 1 in
765def V_FMAAK_F16 : VOP2_Pseudo <"v_fmaak_f16", VOP_MADAK_F16, [], "">;
766} // End FPDPRounding  = 1
767
768let Constraints = "$vdst = $src2",
769    DisableEncoding="$src2",
770    isConvertibleToThreeAddress = 1,
771    isCommutable = 1 in {
772defm V_FMAC_F16 : VOP2Inst <"v_fmac_f16", VOP_MAC_F16>;
773}
774
775} // End SubtargetPredicate = isGFX10Plus
776
777let SubtargetPredicate = HasPkFmacF16Inst in {
778defm V_PK_FMAC_F16 : VOP2Inst<"v_pk_fmac_f16", VOP_V2F16_V2F16_V2F16>;
779} // End SubtargetPredicate = HasPkFmacF16Inst
780
781// Note: 16-bit instructions produce a 0 result in the high 16-bits
782// on GFX8 and GFX9 and preserve high 16 bits on GFX10+
783multiclass Arithmetic_i16_0Hi_Pats <SDPatternOperator op, Instruction inst> {
784
785def : GCNPat<
786  (i32 (zext (op i16:$src0, i16:$src1))),
787  (inst VSrc_b16:$src0, VSrc_b16:$src1)
788>;
789
790def : GCNPat<
791  (i64 (zext (op i16:$src0, i16:$src1))),
792   (REG_SEQUENCE VReg_64,
793     (inst $src0, $src1), sub0,
794     (V_MOV_B32_e32 (i32 0)), sub1)
795>;
796}
797
798class ZExt_i16_i1_Pat <SDNode ext> : GCNPat <
799  (i16 (ext i1:$src)),
800  (V_CNDMASK_B32_e64 (i32 0/*src0mod*/), (i32 0/*src0*/),
801                     (i32 0/*src1mod*/), (i32 1/*src1*/),
802                     $src)
803>;
804
805foreach vt = [i16, v2i16] in {
806def : GCNPat <
807  (and vt:$src0, vt:$src1),
808  (V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
809>;
810
811def : GCNPat <
812  (or vt:$src0, vt:$src1),
813  (V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
814>;
815
816def : GCNPat <
817  (xor vt:$src0, vt:$src1),
818  (V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
819>;
820}
821
822let Predicates = [Has16BitInsts] in {
823
824// Undo sub x, c -> add x, -c canonicalization since c is more likely
825// an inline immediate than -c.
826// TODO: Also do for 64-bit.
827def : GCNPat<
828  (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)),
829  (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)
830>;
831
832
833let Predicates = [Has16BitInsts, isGFX7GFX8GFX9] in {
834
835def : GCNPat<
836  (i32 (zext (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)))),
837  (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)
838>;
839
840defm : Arithmetic_i16_0Hi_Pats<add, V_ADD_U16_e64>;
841defm : Arithmetic_i16_0Hi_Pats<mul, V_MUL_LO_U16_e64>;
842defm : Arithmetic_i16_0Hi_Pats<sub, V_SUB_U16_e64>;
843defm : Arithmetic_i16_0Hi_Pats<smin, V_MIN_I16_e64>;
844defm : Arithmetic_i16_0Hi_Pats<smax, V_MAX_I16_e64>;
845defm : Arithmetic_i16_0Hi_Pats<umin, V_MIN_U16_e64>;
846defm : Arithmetic_i16_0Hi_Pats<umax, V_MAX_U16_e64>;
847defm : Arithmetic_i16_0Hi_Pats<lshl_rev, V_LSHLREV_B16_e64>;
848defm : Arithmetic_i16_0Hi_Pats<lshr_rev, V_LSHRREV_B16_e64>;
849defm : Arithmetic_i16_0Hi_Pats<ashr_rev, V_ASHRREV_I16_e64>;
850}  // End Predicates = [Has16BitInsts, isGFX7GFX8GFX9]
851
852def : ZExt_i16_i1_Pat<zext>;
853def : ZExt_i16_i1_Pat<anyext>;
854
855def : GCNPat <
856  (i16 (sext i1:$src)),
857  (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
858                     /*src1mod*/(i32 0), /*src1*/(i32 -1), $src)
859>;
860
861} // End Predicates = [Has16BitInsts]
862
863
864let SubtargetPredicate = HasIntClamp in {
865// Set clamp bit for saturation.
866def : VOPBinOpClampPat<uaddsat, V_ADD_CO_U32_e64, i32>;
867def : VOPBinOpClampPat<usubsat, V_SUB_CO_U32_e64, i32>;
868}
869
870let SubtargetPredicate = HasAddNoCarryInsts, OtherPredicates = [HasIntClamp] in {
871let AddedComplexity = 1 in { // Prefer over form with carry-out.
872def : VOPBinOpClampPat<uaddsat, V_ADD_U32_e64, i32>;
873def : VOPBinOpClampPat<usubsat, V_SUB_U32_e64, i32>;
874}
875}
876
877let SubtargetPredicate = Has16BitInsts, OtherPredicates = [HasIntClamp] in {
878def : VOPBinOpClampPat<uaddsat, V_ADD_U16_e64, i16>;
879def : VOPBinOpClampPat<usubsat, V_SUB_U16_e64, i16>;
880}
881
882//===----------------------------------------------------------------------===//
883// Target-specific instruction encodings.
884//===----------------------------------------------------------------------===//
885
886class VOP2_DPP<bits<6> op, VOP2_DPP_Pseudo ps,
887               string opName = ps.OpName, VOPProfile p = ps.Pfl,
888               bit IsDPP16 = 0> :
889    VOP_DPP<opName, p, IsDPP16> {
890  let hasSideEffects = ps.hasSideEffects;
891  let Defs = ps.Defs;
892  let SchedRW = ps.SchedRW;
893  let Uses = ps.Uses;
894
895  bits<8> vdst;
896  bits<8> src1;
897  let Inst{8-0}   = 0xfa;
898  let Inst{16-9}  = !if(p.HasSrc1, src1{7-0}, 0);
899  let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
900  let Inst{30-25} = op;
901  let Inst{31}    = 0x0;
902}
903
904class Base_VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps,
905                 string opName = ps.OpName, VOPProfile p = ps.Pfl> :
906    VOP2_DPP<op, ps, opName, p, 1> {
907  let AssemblerPredicate = HasDPP16;
908  let SubtargetPredicate = HasDPP16;
909  let OtherPredicates = ps.OtherPredicates;
910}
911
912class VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps,
913                 string opName = ps.OpName, VOPProfile p = ps.Pfl> :
914    Base_VOP2_DPP16<op, ps, opName, p>,
915    SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX10>;
916
917class VOP2_DPP8<bits<6> op, VOP2_Pseudo ps,
918                string opName = ps.OpName, VOPProfile p = ps.Pfl> :
919    VOP_DPP8<ps.OpName, p> {
920  let hasSideEffects = ps.hasSideEffects;
921  let Defs = ps.Defs;
922  let SchedRW = ps.SchedRW;
923  let Uses = ps.Uses;
924
925  bits<8> vdst;
926  bits<8> src1;
927
928  let Inst{8-0}   = fi;
929  let Inst{16-9}  = !if(p.HasSrc1, src1{7-0}, 0);
930  let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
931  let Inst{30-25} = op;
932  let Inst{31}    = 0x0;
933
934  let AssemblerPredicate = HasDPP8;
935  let SubtargetPredicate = HasDPP8;
936  let OtherPredicates = ps.OtherPredicates;
937}
938
939//===----------------------------------------------------------------------===//
940// GFX10.
941//===----------------------------------------------------------------------===//
942
943let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
944  //===------------------------------- VOP2 -------------------------------===//
945  multiclass VOP2Only_Real_MADK_gfx10<bits<6> op> {
946    def _gfx10 :
947      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX10>,
948      VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
949  }
950  multiclass VOP2Only_Real_MADK_gfx10_with_name<bits<6> op, string opName,
951                                                string asmName> {
952    def _gfx10 :
953        VOP2_Real<!cast<VOP2_Pseudo>(opName), SIEncodingFamily.GFX10>,
954        VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> {
955      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName);
956      let AsmString = asmName # ps.AsmOperands;
957    }
958  }
959  multiclass VOP2_Real_e32_gfx10<bits<6> op> {
960    def _e32_gfx10 :
961      VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,
962      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
963  }
964  multiclass VOP2_Real_e64_gfx10<bits<6> op> {
965    def _e64_gfx10 :
966      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
967      VOP3e_gfx10<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
968  }
969  multiclass VOP2_Real_sdwa_gfx10<bits<6> op> {
970    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
971    def _sdwa_gfx10 :
972      VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
973      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
974      let DecoderNamespace = "SDWA10";
975    }
976  }
977  multiclass VOP2_Real_dpp_gfx10<bits<6> op> {
978    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
979    def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
980      let DecoderNamespace = "SDWA10";
981    }
982  }
983  multiclass VOP2_Real_dpp8_gfx10<bits<6> op> {
984    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
985    def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(NAME#"_e32")> {
986      let DecoderNamespace = "DPP8";
987    }
988  }
989
990  //===------------------------- VOP2 (with name) -------------------------===//
991  multiclass VOP2_Real_e32_gfx10_with_name<bits<6> op, string opName,
992                                           string asmName> {
993    def _e32_gfx10 :
994      VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
995      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
996        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
997        let AsmString = asmName # ps.AsmOperands;
998      }
999  }
1000  multiclass VOP2_Real_e64_gfx10_with_name<bits<6> op, string opName,
1001                                           string asmName> {
1002    def _e64_gfx10 :
1003      VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
1004      VOP3e_gfx10<{0, 1, 0, 0, op{5-0}},
1005                  !cast<VOP3_Pseudo>(opName#"_e64").Pfl> {
1006        VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64");
1007        let AsmString = asmName # ps.AsmOperands;
1008      }
1009  }
1010  let DecoderNamespace = "SDWA10" in {
1011    multiclass VOP2_Real_sdwa_gfx10_with_name<bits<6> op, string opName,
1012                                              string asmName> {
1013      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1014      def _sdwa_gfx10 :
1015        VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1016        VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1017          VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1018          let AsmString = asmName # ps.AsmOperands;
1019        }
1020    }
1021    multiclass VOP2_Real_dpp_gfx10_with_name<bits<6> op, string opName,
1022                                             string asmName> {
1023      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1024      def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp")> {
1025        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
1026        let AsmString = asmName # ps.Pfl.AsmDPP16;
1027      }
1028    }
1029    multiclass VOP2_Real_dpp8_gfx10_with_name<bits<6> op, string opName,
1030                                              string asmName> {
1031      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1032      def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
1033        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
1034        let AsmString = asmName # ps.Pfl.AsmDPP8;
1035        let DecoderNamespace = "DPP8";
1036      }
1037    }
1038  } // End DecoderNamespace = "SDWA10"
1039
1040  //===------------------------------ VOP2be ------------------------------===//
1041  multiclass VOP2be_Real_e32_gfx10<bits<6> op, string opName, string asmName> {
1042    def _e32_gfx10 :
1043      VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
1044      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
1045        VOP2_Pseudo Ps = !cast<VOP2_Pseudo>(opName#"_e32");
1046        let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
1047      }
1048  }
1049  multiclass VOP2be_Real_e64_gfx10<bits<6> op, string opName, string asmName> {
1050    def _e64_gfx10 :
1051      VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
1052      VOP3be_gfx10<{0, 1, 0, 0, op{5-0}},
1053                   !cast<VOP3_Pseudo>(opName#"_e64").Pfl> {
1054        VOP3_Pseudo Ps = !cast<VOP3_Pseudo>(opName#"_e64");
1055        let AsmString = asmName # Ps.AsmOperands;
1056      }
1057  }
1058  multiclass VOP2be_Real_sdwa_gfx10<bits<6> op, string opName, string asmName> {
1059    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1060    def _sdwa_gfx10 :
1061      VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1062      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1063        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1064        let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
1065        let DecoderNamespace = "SDWA10";
1066      }
1067    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1068    def _sdwa_w32_gfx10 :
1069      Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1070      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1071        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1072        let AsmString = asmName # !subst("vcc", "vcc_lo", Ps.AsmOperands);
1073        let isAsmParserOnly = 1;
1074        let DecoderNamespace = "SDWA10";
1075        let WaveSizePredicate = isWave32;
1076      }
1077    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1078    def _sdwa_w64_gfx10 :
1079      Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1080      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1081        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1082        let AsmString = asmName # Ps.AsmOperands;
1083        let isAsmParserOnly = 1;
1084        let DecoderNamespace = "SDWA10";
1085        let WaveSizePredicate = isWave64;
1086      }
1087  }
1088  multiclass VOP2be_Real_dpp_gfx10<bits<6> op, string opName, string asmName> {
1089    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1090    def _dpp_gfx10 :
1091      VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1092        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1093        let AsmString = asmName # !subst(", vcc", "", AsmDPP);
1094        let DecoderNamespace = "SDWA10";
1095      }
1096    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1097    def _dpp_w32_gfx10 :
1098      Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1099        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1100        let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP);
1101        let isAsmParserOnly = 1;
1102        let WaveSizePredicate = isWave32;
1103      }
1104    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1105    def _dpp_w64_gfx10 :
1106      Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1107        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1108        let AsmString = asmName # AsmDPP;
1109        let isAsmParserOnly = 1;
1110        let WaveSizePredicate = isWave64;
1111      }
1112  }
1113  multiclass VOP2be_Real_dpp8_gfx10<bits<6> op, string opName, string asmName> {
1114    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1115    def _dpp8_gfx10 :
1116      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1117        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1118        let AsmString = asmName # !subst(", vcc", "", AsmDPP8);
1119        let DecoderNamespace = "DPP8";
1120      }
1121    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1122    def _dpp8_w32_gfx10 :
1123      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1124        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1125        let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8);
1126        let isAsmParserOnly = 1;
1127        let WaveSizePredicate = isWave32;
1128      }
1129    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1130    def _dpp8_w64_gfx10 :
1131      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1132        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1133        let AsmString = asmName # AsmDPP8;
1134        let isAsmParserOnly = 1;
1135        let WaveSizePredicate = isWave64;
1136      }
1137  }
1138
1139  //===----------------------------- VOP3Only -----------------------------===//
1140  multiclass VOP3Only_Real_gfx10<bits<10> op> {
1141    def _e64_gfx10 :
1142      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1143      VOP3e_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1144        let IsSingle = 1;
1145      }
1146  }
1147
1148  //===---------------------------- VOP3beOnly ----------------------------===//
1149  multiclass VOP3beOnly_Real_gfx10<bits<10> op> {
1150    def _e64_gfx10 :
1151      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1152      VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1153        let IsSingle = 1;
1154      }
1155  }
1156} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
1157
1158multiclass VOP2be_Real_gfx10<bits<6> op, string opName, string asmName> :
1159  VOP2be_Real_e32_gfx10<op, opName, asmName>,
1160  VOP2be_Real_e64_gfx10<op, opName, asmName>,
1161  VOP2be_Real_sdwa_gfx10<op, opName, asmName>,
1162  VOP2be_Real_dpp_gfx10<op, opName, asmName>,
1163  VOP2be_Real_dpp8_gfx10<op, opName, asmName>;
1164
1165multiclass VOP2e_Real_gfx10<bits<6> op, string opName, string asmName> :
1166  VOP2_Real_e32_gfx10<op>,
1167  VOP2_Real_e64_gfx10<op>,
1168  VOP2be_Real_sdwa_gfx10<op, opName, asmName>,
1169  VOP2be_Real_dpp_gfx10<op, opName, asmName>,
1170  VOP2be_Real_dpp8_gfx10<op, opName, asmName>;
1171
1172multiclass VOP2_Real_gfx10<bits<6> op> :
1173  VOP2_Real_e32_gfx10<op>, VOP2_Real_e64_gfx10<op>,
1174  VOP2_Real_sdwa_gfx10<op>, VOP2_Real_dpp_gfx10<op>, VOP2_Real_dpp8_gfx10<op>;
1175
1176multiclass VOP2_Real_gfx10_with_name<bits<6> op, string opName,
1177                                     string asmName> :
1178  VOP2_Real_e32_gfx10_with_name<op, opName, asmName>,
1179  VOP2_Real_e64_gfx10_with_name<op, opName, asmName>,
1180  VOP2_Real_sdwa_gfx10_with_name<op, opName, asmName>,
1181  VOP2_Real_dpp_gfx10_with_name<op, opName, asmName>,
1182  VOP2_Real_dpp8_gfx10_with_name<op, opName, asmName>;
1183
1184// NB: Same opcode as v_mac_legacy_f32
1185let DecoderNamespace = "GFX10_B" in
1186defm V_FMAC_LEGACY_F32 : VOP2_Real_gfx10<0x006>;
1187
1188defm V_XNOR_B32        : VOP2_Real_gfx10<0x01e>;
1189defm V_FMAC_F32        : VOP2_Real_gfx10<0x02b>;
1190defm V_FMAMK_F32       : VOP2Only_Real_MADK_gfx10<0x02c>;
1191defm V_FMAAK_F32       : VOP2Only_Real_MADK_gfx10<0x02d>;
1192defm V_ADD_F16         : VOP2_Real_gfx10<0x032>;
1193defm V_SUB_F16         : VOP2_Real_gfx10<0x033>;
1194defm V_SUBREV_F16      : VOP2_Real_gfx10<0x034>;
1195defm V_MUL_F16         : VOP2_Real_gfx10<0x035>;
1196defm V_FMAC_F16        : VOP2_Real_gfx10<0x036>;
1197defm V_FMAMK_F16       : VOP2Only_Real_MADK_gfx10<0x037>;
1198defm V_FMAAK_F16       : VOP2Only_Real_MADK_gfx10<0x038>;
1199defm V_MAX_F16         : VOP2_Real_gfx10<0x039>;
1200defm V_MIN_F16         : VOP2_Real_gfx10<0x03a>;
1201defm V_LDEXP_F16       : VOP2_Real_gfx10<0x03b>;
1202
1203let IsSingle = 1 in {
1204defm V_PK_FMAC_F16     : VOP2_Real_e32_gfx10<0x03c>;
1205}
1206
1207// VOP2 no carry-in, carry-out.
1208defm V_ADD_NC_U32 :
1209  VOP2_Real_gfx10_with_name<0x025, "V_ADD_U32", "v_add_nc_u32">;
1210defm V_SUB_NC_U32 :
1211  VOP2_Real_gfx10_with_name<0x026, "V_SUB_U32", "v_sub_nc_u32">;
1212defm V_SUBREV_NC_U32 :
1213  VOP2_Real_gfx10_with_name<0x027, "V_SUBREV_U32", "v_subrev_nc_u32">;
1214
1215// VOP2 carry-in, carry-out.
1216defm V_ADD_CO_CI_U32 :
1217  VOP2be_Real_gfx10<0x028, "V_ADDC_U32", "v_add_co_ci_u32">;
1218defm V_SUB_CO_CI_U32 :
1219  VOP2be_Real_gfx10<0x029, "V_SUBB_U32", "v_sub_co_ci_u32">;
1220defm V_SUBREV_CO_CI_U32 :
1221  VOP2be_Real_gfx10<0x02a, "V_SUBBREV_U32", "v_subrev_co_ci_u32">;
1222
1223defm V_CNDMASK_B32 :
1224  VOP2e_Real_gfx10<0x001, "V_CNDMASK_B32", "v_cndmask_b32">;
1225
1226// VOP3 only.
1227defm V_BFM_B32            : VOP3Only_Real_gfx10<0x363>;
1228defm V_BCNT_U32_B32       : VOP3Only_Real_gfx10<0x364>;
1229defm V_MBCNT_LO_U32_B32   : VOP3Only_Real_gfx10<0x365>;
1230defm V_MBCNT_HI_U32_B32   : VOP3Only_Real_gfx10<0x366>;
1231defm V_LDEXP_F32          : VOP3Only_Real_gfx10<0x362>;
1232defm V_CVT_PKNORM_I16_F32 : VOP3Only_Real_gfx10<0x368>;
1233defm V_CVT_PKNORM_U16_F32 : VOP3Only_Real_gfx10<0x369>;
1234defm V_CVT_PK_U16_U32     : VOP3Only_Real_gfx10<0x36a>;
1235defm V_CVT_PK_I16_I32     : VOP3Only_Real_gfx10<0x36b>;
1236
1237// VOP3 carry-out.
1238defm V_ADD_CO_U32 : VOP3beOnly_Real_gfx10<0x30f>;
1239defm V_SUB_CO_U32 : VOP3beOnly_Real_gfx10<0x310>;
1240defm V_SUBREV_CO_U32 : VOP3beOnly_Real_gfx10<0x319>;
1241
1242let SubtargetPredicate = isGFX10Plus in {
1243  defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx10>;
1244
1245  defm : VOP2bInstAliases<
1246    V_ADDC_U32_e32, V_ADD_CO_CI_U32_e32_gfx10, "v_add_co_ci_u32">;
1247  defm : VOP2bInstAliases<
1248    V_SUBB_U32_e32, V_SUB_CO_CI_U32_e32_gfx10, "v_sub_co_ci_u32">;
1249  defm : VOP2bInstAliases<
1250    V_SUBBREV_U32_e32, V_SUBREV_CO_CI_U32_e32_gfx10, "v_subrev_co_ci_u32">;
1251} // End SubtargetPredicate = isGFX10Plus
1252
1253//===----------------------------------------------------------------------===//
1254// GFX6, GFX7, GFX10.
1255//===----------------------------------------------------------------------===//
1256
1257class VOP2_DPPe <bits<6> op, VOP2_DPP_Pseudo ps, VOPProfile P = ps.Pfl> :
1258  VOP_DPPe <P> {
1259  bits<8> vdst;
1260  bits<8> src1;
1261  let Inst{8-0}   = 0xfa; //dpp
1262  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
1263  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
1264  let Inst{30-25} = op;
1265  let Inst{31}    = 0x0; //encoding
1266}
1267
1268let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
1269  multiclass VOP2_Lane_Real_gfx6_gfx7<bits<6> op> {
1270    def _gfx6_gfx7 :
1271      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1272      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1273  }
1274  multiclass VOP2Only_Real_MADK_gfx6_gfx7<bits<6> op> {
1275    def _gfx6_gfx7 :
1276      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1277      VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1278  }
1279  multiclass VOP2_Real_e32_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1280    def _e32_gfx6_gfx7 :
1281      VOP2_Real<!cast<VOP2_Pseudo>(PseudoName#"_e32"), SIEncodingFamily.SI>,
1282      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(PseudoName#"_e32").Pfl>;
1283  }
1284  multiclass VOP2_Real_e64_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1285    def _e64_gfx6_gfx7 :
1286      VOP3_Real<!cast<VOP3_Pseudo>(PseudoName#"_e64"), SIEncodingFamily.SI>,
1287      VOP3e_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(PseudoName#"_e64").Pfl>;
1288  }
1289  multiclass VOP2be_Real_e64_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1290    def _e64_gfx6_gfx7 :
1291      VOP3_Real<!cast<VOP3_Pseudo>(PseudoName#"_e64"), SIEncodingFamily.SI>,
1292      VOP3be_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(PseudoName#"_e64").Pfl>;
1293  }
1294} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
1295
1296multiclass VOP2Only_Real_MADK_gfx6_gfx7_gfx10<bits<6> op> :
1297  VOP2Only_Real_MADK_gfx6_gfx7<op>, VOP2Only_Real_MADK_gfx10<op>;
1298
1299multiclass VOP2_Real_gfx6_gfx7<bits<6> op> :
1300  VOP2_Real_e32_gfx6_gfx7<op>, VOP2_Real_e64_gfx6_gfx7<op>;
1301
1302multiclass VOP2_Real_gfx6_gfx7_gfx10<bits<6> op> :
1303  VOP2_Real_gfx6_gfx7<op>, VOP2_Real_gfx10<op>;
1304
1305multiclass VOP2be_Real_gfx6_gfx7<bits<6> op> :
1306  VOP2_Real_e32_gfx6_gfx7<op>, VOP2be_Real_e64_gfx6_gfx7<op>;
1307
1308multiclass VOP2be_Real_gfx6_gfx7_with_name<bits<6> op,
1309  string PseudoName, string asmName>  {
1310  defvar ps32 = !cast<VOP2_Pseudo>(PseudoName#"_e32");
1311  defvar ps64 = !cast<VOP3_Pseudo>(PseudoName#"_e64");
1312
1313  let AsmString = asmName # ps32.AsmOperands in {
1314    defm "" : VOP2_Real_e32_gfx6_gfx7<op, PseudoName>;
1315  }
1316
1317   let AsmString = asmName # ps64.AsmOperands in {
1318    defm "" : VOP2be_Real_e64_gfx6_gfx7<op, PseudoName>;
1319  }
1320}
1321
1322defm V_CNDMASK_B32        : VOP2_Real_gfx6_gfx7<0x000>;
1323defm V_MIN_LEGACY_F32     : VOP2_Real_gfx6_gfx7<0x00d>;
1324defm V_MAX_LEGACY_F32     : VOP2_Real_gfx6_gfx7<0x00e>;
1325defm V_LSHR_B32           : VOP2_Real_gfx6_gfx7<0x015>;
1326defm V_ASHR_I32           : VOP2_Real_gfx6_gfx7<0x017>;
1327defm V_LSHL_B32           : VOP2_Real_gfx6_gfx7<0x019>;
1328defm V_BFM_B32            : VOP2_Real_gfx6_gfx7<0x01e>;
1329defm V_BCNT_U32_B32       : VOP2_Real_gfx6_gfx7<0x022>;
1330defm V_MBCNT_LO_U32_B32   : VOP2_Real_gfx6_gfx7<0x023>;
1331defm V_MBCNT_HI_U32_B32   : VOP2_Real_gfx6_gfx7<0x024>;
1332defm V_LDEXP_F32          : VOP2_Real_gfx6_gfx7<0x02b>;
1333defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_gfx6_gfx7<0x02c>;
1334defm V_CVT_PKNORM_I16_F32 : VOP2_Real_gfx6_gfx7<0x02d>;
1335defm V_CVT_PKNORM_U16_F32 : VOP2_Real_gfx6_gfx7<0x02e>;
1336defm V_CVT_PK_U16_U32     : VOP2_Real_gfx6_gfx7<0x030>;
1337defm V_CVT_PK_I16_I32     : VOP2_Real_gfx6_gfx7<0x031>;
1338
1339// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in
1340// VI, but the VI instructions behave the same as the SI versions.
1341defm V_ADD_I32            : VOP2be_Real_gfx6_gfx7_with_name<0x025, "V_ADD_CO_U32", "v_add_i32">;
1342defm V_SUB_I32            : VOP2be_Real_gfx6_gfx7_with_name<0x026, "V_SUB_CO_U32", "v_sub_i32">;
1343defm V_SUBREV_I32         : VOP2be_Real_gfx6_gfx7_with_name<0x027, "V_SUBREV_CO_U32", "v_subrev_i32">;
1344defm V_ADDC_U32           : VOP2be_Real_gfx6_gfx7<0x028>;
1345defm V_SUBB_U32           : VOP2be_Real_gfx6_gfx7<0x029>;
1346defm V_SUBBREV_U32        : VOP2be_Real_gfx6_gfx7<0x02a>;
1347
1348defm V_READLANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x001>;
1349
1350let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
1351  defm V_WRITELANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x002>;
1352} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)
1353
1354let SubtargetPredicate = isGFX6GFX7 in {
1355  defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx6_gfx7>;
1356  defm : VOP2eInstAliases<V_ADD_CO_U32_e32, V_ADD_I32_e32_gfx6_gfx7>;
1357  defm : VOP2eInstAliases<V_SUB_CO_U32_e32, V_SUB_I32_e32_gfx6_gfx7>;
1358  defm : VOP2eInstAliases<V_SUBREV_CO_U32_e32, V_SUBREV_I32_e32_gfx6_gfx7>;
1359
1360  def : VOP2e64InstAlias<V_ADD_CO_U32_e64, V_ADD_I32_e64_gfx6_gfx7>;
1361  def : VOP2e64InstAlias<V_SUB_CO_U32_e64, V_SUB_I32_e64_gfx6_gfx7>;
1362  def : VOP2e64InstAlias<V_SUBREV_CO_U32_e64, V_SUBREV_I32_e64_gfx6_gfx7>;
1363} // End SubtargetPredicate = isGFX6GFX7
1364
1365defm V_ADD_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x003>;
1366defm V_SUB_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x004>;
1367defm V_SUBREV_F32         : VOP2_Real_gfx6_gfx7_gfx10<0x005>;
1368defm V_MAC_LEGACY_F32     : VOP2_Real_gfx6_gfx7_gfx10<0x006>;
1369defm V_MUL_LEGACY_F32     : VOP2_Real_gfx6_gfx7_gfx10<0x007>;
1370defm V_MUL_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x008>;
1371defm V_MUL_I32_I24        : VOP2_Real_gfx6_gfx7_gfx10<0x009>;
1372defm V_MUL_HI_I32_I24     : VOP2_Real_gfx6_gfx7_gfx10<0x00a>;
1373defm V_MUL_U32_U24        : VOP2_Real_gfx6_gfx7_gfx10<0x00b>;
1374defm V_MUL_HI_U32_U24     : VOP2_Real_gfx6_gfx7_gfx10<0x00c>;
1375defm V_MIN_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x00f>;
1376defm V_MAX_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x010>;
1377defm V_MIN_I32            : VOP2_Real_gfx6_gfx7_gfx10<0x011>;
1378defm V_MAX_I32            : VOP2_Real_gfx6_gfx7_gfx10<0x012>;
1379defm V_MIN_U32            : VOP2_Real_gfx6_gfx7_gfx10<0x013>;
1380defm V_MAX_U32            : VOP2_Real_gfx6_gfx7_gfx10<0x014>;
1381defm V_LSHRREV_B32        : VOP2_Real_gfx6_gfx7_gfx10<0x016>;
1382defm V_ASHRREV_I32        : VOP2_Real_gfx6_gfx7_gfx10<0x018>;
1383defm V_LSHLREV_B32        : VOP2_Real_gfx6_gfx7_gfx10<0x01a>;
1384defm V_AND_B32            : VOP2_Real_gfx6_gfx7_gfx10<0x01b>;
1385defm V_OR_B32             : VOP2_Real_gfx6_gfx7_gfx10<0x01c>;
1386defm V_XOR_B32            : VOP2_Real_gfx6_gfx7_gfx10<0x01d>;
1387defm V_MAC_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x01f>;
1388defm V_CVT_PKRTZ_F16_F32  : VOP2_Real_gfx6_gfx7_gfx10<0x02f>;
1389defm V_MADMK_F32          : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x020>;
1390defm V_MADAK_F32          : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x021>;
1391
1392//===----------------------------------------------------------------------===//
1393// GFX8, GFX9 (VI).
1394//===----------------------------------------------------------------------===//
1395
1396let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {
1397
1398multiclass VOP2_Real_MADK_vi <bits<6> op> {
1399  def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,
1400            VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1401}
1402
1403multiclass VOP2_Real_e32_vi <bits<6> op> {
1404  def _e32_vi :
1405    VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
1406    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
1407}
1408
1409multiclass VOP2_Real_e64_vi <bits<10> op> {
1410  def _e64_vi :
1411    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
1412    VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1413}
1414
1415multiclass VOP2_Real_e64only_vi <bits<10> op> {
1416  def _e64_vi :
1417    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
1418    VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1419      let IsSingle = 1;
1420    }
1421}
1422
1423multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> :
1424  VOP2_Real_e32_vi<op>,
1425  VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>;
1426
1427} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8"
1428
1429multiclass VOP2_SDWA_Real <bits<6> op> {
1430  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA>.ret in
1431  def _sdwa_vi :
1432    VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1433    VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1434}
1435
1436multiclass VOP2_SDWA9_Real <bits<6> op> {
1437  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
1438  def _sdwa_gfx9 :
1439    VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1440    VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1441}
1442
1443let AssemblerPredicate = isGFX8Only in {
1444
1445multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName> {
1446  def _e32_vi :
1447    VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.VI>,
1448    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
1449      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32");
1450      let AsmString = AsmName # ps.AsmOperands;
1451      let DecoderNamespace = "GFX8";
1452    }
1453  def _e64_vi :
1454    VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.VI>,
1455    VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
1456      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64");
1457      let AsmString = AsmName # ps.AsmOperands;
1458      let DecoderNamespace = "GFX8";
1459    }
1460  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA>.ret in
1461    def _sdwa_vi :
1462      VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>,
1463      VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {
1464        VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa");
1465        let AsmString = AsmName # ps.AsmOperands;
1466      }
1467  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in
1468    def _dpp_vi :
1469      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.VI>,
1470      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> {
1471        VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp");
1472        let AsmString = AsmName # ps.AsmOperands;
1473      }
1474}
1475}
1476
1477let AssemblerPredicate = isGFX9Only in {
1478
1479multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> {
1480  def _e32_gfx9 :
1481    VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.GFX9>,
1482    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
1483      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32");
1484      let AsmString = AsmName # ps.AsmOperands;
1485      let DecoderNamespace = "GFX9";
1486    }
1487  def _e64_gfx9 :
1488    VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>,
1489    VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
1490      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64");
1491      let AsmString = AsmName # ps.AsmOperands;
1492      let DecoderNamespace = "GFX9";
1493    }
1494  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA9>.ret in
1495    def _sdwa_gfx9 :
1496      VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>,
1497      VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {
1498        VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa");
1499        let AsmString = AsmName # ps.AsmOperands;
1500      }
1501  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in
1502    def _dpp_gfx9 :
1503      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.GFX9>,
1504      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> {
1505        VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp");
1506        let AsmString = AsmName # ps.AsmOperands;
1507        let DecoderNamespace = "SDWA9";
1508      }
1509}
1510
1511multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> {
1512  def _e32_gfx9 :
1513    VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX9>,
1514    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>{
1515      let DecoderNamespace = "GFX9";
1516    }
1517  def _e64_gfx9 :
1518    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>,
1519    VOP3e_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1520      let DecoderNamespace = "GFX9";
1521    }
1522  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
1523    def _sdwa_gfx9 :
1524      VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1525      VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
1526      }
1527  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
1528    def _dpp_gfx9 :
1529      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,
1530      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
1531        let DecoderNamespace = "SDWA9";
1532      }
1533}
1534
1535} // AssemblerPredicate = isGFX9Only
1536
1537multiclass VOP2_Real_e32e64_vi <bits<6> op> :
1538  Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> {
1539
1540  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
1541    def _dpp_vi :
1542      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.VI>,
1543      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;
1544}
1545
1546defm V_CNDMASK_B32        : VOP2_Real_e32e64_vi <0x0>;
1547defm V_ADD_F32            : VOP2_Real_e32e64_vi <0x1>;
1548defm V_SUB_F32            : VOP2_Real_e32e64_vi <0x2>;
1549defm V_SUBREV_F32         : VOP2_Real_e32e64_vi <0x3>;
1550let AssemblerPredicate = isGCN3ExcludingGFX90A in
1551defm V_MUL_LEGACY_F32     : VOP2_Real_e32e64_vi <0x4>;
1552defm V_MUL_F32            : VOP2_Real_e32e64_vi <0x5>;
1553defm V_MUL_I32_I24        : VOP2_Real_e32e64_vi <0x6>;
1554defm V_MUL_HI_I32_I24     : VOP2_Real_e32e64_vi <0x7>;
1555defm V_MUL_U32_U24        : VOP2_Real_e32e64_vi <0x8>;
1556defm V_MUL_HI_U32_U24     : VOP2_Real_e32e64_vi <0x9>;
1557defm V_MIN_F32            : VOP2_Real_e32e64_vi <0xa>;
1558defm V_MAX_F32            : VOP2_Real_e32e64_vi <0xb>;
1559defm V_MIN_I32            : VOP2_Real_e32e64_vi <0xc>;
1560defm V_MAX_I32            : VOP2_Real_e32e64_vi <0xd>;
1561defm V_MIN_U32            : VOP2_Real_e32e64_vi <0xe>;
1562defm V_MAX_U32            : VOP2_Real_e32e64_vi <0xf>;
1563defm V_LSHRREV_B32        : VOP2_Real_e32e64_vi <0x10>;
1564defm V_ASHRREV_I32        : VOP2_Real_e32e64_vi <0x11>;
1565defm V_LSHLREV_B32        : VOP2_Real_e32e64_vi <0x12>;
1566defm V_AND_B32            : VOP2_Real_e32e64_vi <0x13>;
1567defm V_OR_B32             : VOP2_Real_e32e64_vi <0x14>;
1568defm V_XOR_B32            : VOP2_Real_e32e64_vi <0x15>;
1569defm V_MAC_F32            : VOP2_Real_e32e64_vi <0x16>;
1570defm V_MADMK_F32          : VOP2_Real_MADK_vi <0x17>;
1571defm V_MADAK_F32          : VOP2_Real_MADK_vi <0x18>;
1572
1573defm V_ADD_U32            : VOP2be_Real_e32e64_vi_only <0x19, "V_ADD_CO_U32",     "v_add_u32">;
1574defm V_SUB_U32            : VOP2be_Real_e32e64_vi_only <0x1a, "V_SUB_CO_U32",     "v_sub_u32">;
1575defm V_SUBREV_U32         : VOP2be_Real_e32e64_vi_only <0x1b, "V_SUBREV_CO_U32",  "v_subrev_u32">;
1576defm V_ADDC_U32           : VOP2be_Real_e32e64_vi_only <0x1c, "V_ADDC_U32",    "v_addc_u32">;
1577defm V_SUBB_U32           : VOP2be_Real_e32e64_vi_only <0x1d, "V_SUBB_U32",    "v_subb_u32">;
1578defm V_SUBBREV_U32        : VOP2be_Real_e32e64_vi_only <0x1e, "V_SUBBREV_U32", "v_subbrev_u32">;
1579
1580defm V_ADD_CO_U32         : VOP2be_Real_e32e64_gfx9 <0x19, "V_ADD_CO_U32",     "v_add_co_u32">;
1581defm V_SUB_CO_U32         : VOP2be_Real_e32e64_gfx9 <0x1a, "V_SUB_CO_U32",     "v_sub_co_u32">;
1582defm V_SUBREV_CO_U32      : VOP2be_Real_e32e64_gfx9 <0x1b, "V_SUBREV_CO_U32",  "v_subrev_co_u32">;
1583defm V_ADDC_CO_U32        : VOP2be_Real_e32e64_gfx9 <0x1c, "V_ADDC_U32",    "v_addc_co_u32">;
1584defm V_SUBB_CO_U32        : VOP2be_Real_e32e64_gfx9 <0x1d, "V_SUBB_U32",    "v_subb_co_u32">;
1585defm V_SUBBREV_CO_U32     : VOP2be_Real_e32e64_gfx9 <0x1e, "V_SUBBREV_U32", "v_subbrev_co_u32">;
1586
1587defm V_ADD_U32            : VOP2_Real_e32e64_gfx9 <0x34>;
1588defm V_SUB_U32            : VOP2_Real_e32e64_gfx9 <0x35>;
1589defm V_SUBREV_U32         : VOP2_Real_e32e64_gfx9 <0x36>;
1590
1591defm V_BFM_B32            : VOP2_Real_e64only_vi <0x293>;
1592defm V_BCNT_U32_B32       : VOP2_Real_e64only_vi <0x28b>;
1593defm V_MBCNT_LO_U32_B32   : VOP2_Real_e64only_vi <0x28c>;
1594defm V_MBCNT_HI_U32_B32   : VOP2_Real_e64only_vi <0x28d>;
1595defm V_LDEXP_F32          : VOP2_Real_e64only_vi <0x288>;
1596defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64only_vi <0x1f0>;
1597defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64only_vi <0x294>;
1598defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64only_vi <0x295>;
1599defm V_CVT_PKRTZ_F16_F32  : VOP2_Real_e64only_vi <0x296>;
1600defm V_CVT_PK_U16_U32     : VOP2_Real_e64only_vi <0x297>;
1601defm V_CVT_PK_I16_I32     : VOP2_Real_e64only_vi <0x298>;
1602
1603defm V_ADD_F16            : VOP2_Real_e32e64_vi <0x1f>;
1604defm V_SUB_F16            : VOP2_Real_e32e64_vi <0x20>;
1605defm V_SUBREV_F16         : VOP2_Real_e32e64_vi <0x21>;
1606defm V_MUL_F16            : VOP2_Real_e32e64_vi <0x22>;
1607defm V_MAC_F16            : VOP2_Real_e32e64_vi <0x23>;
1608defm V_MADMK_F16          : VOP2_Real_MADK_vi <0x24>;
1609defm V_MADAK_F16          : VOP2_Real_MADK_vi <0x25>;
1610defm V_ADD_U16            : VOP2_Real_e32e64_vi <0x26>;
1611defm V_SUB_U16            : VOP2_Real_e32e64_vi <0x27>;
1612defm V_SUBREV_U16         : VOP2_Real_e32e64_vi <0x28>;
1613defm V_MUL_LO_U16         : VOP2_Real_e32e64_vi <0x29>;
1614defm V_LSHLREV_B16        : VOP2_Real_e32e64_vi <0x2a>;
1615defm V_LSHRREV_B16        : VOP2_Real_e32e64_vi <0x2b>;
1616defm V_ASHRREV_I16        : VOP2_Real_e32e64_vi <0x2c>;
1617defm V_MAX_F16            : VOP2_Real_e32e64_vi <0x2d>;
1618defm V_MIN_F16            : VOP2_Real_e32e64_vi <0x2e>;
1619defm V_MAX_U16            : VOP2_Real_e32e64_vi <0x2f>;
1620defm V_MAX_I16            : VOP2_Real_e32e64_vi <0x30>;
1621defm V_MIN_U16            : VOP2_Real_e32e64_vi <0x31>;
1622defm V_MIN_I16            : VOP2_Real_e32e64_vi <0x32>;
1623defm V_LDEXP_F16          : VOP2_Real_e32e64_vi <0x33>;
1624
1625let SubtargetPredicate = isGFX8GFX9 in {
1626
1627// Aliases to simplify matching of floating-point instructions that
1628// are VOP2 on SI and VOP3 on VI.
1629class SI2_VI3Alias <string name, VOP3_Real inst> : InstAlias <
1630  name#" $dst, $src0, $src1",
1631  !if(inst.Pfl.HasOMod,
1632      (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0),
1633      (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0))
1634>, PredicateControl {
1635  let UseInstAsmMatchConverter = 0;
1636  let AsmVariantName = AMDGPUAsmVariants.VOP3;
1637}
1638
1639def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>;
1640def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>;
1641def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>;
1642def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;
1643def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;
1644
1645defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_vi>;
1646
1647} // End SubtargetPredicate = isGFX8GFX9
1648
1649let SubtargetPredicate = isGFX9Only in {
1650
1651defm : VOP2bInstAliases<V_ADD_U32_e32,     V_ADD_CO_U32_e32_gfx9,     "v_add_co_u32">;
1652defm : VOP2bInstAliases<V_ADDC_U32_e32,    V_ADDC_CO_U32_e32_gfx9,    "v_addc_co_u32">;
1653defm : VOP2bInstAliases<V_SUB_U32_e32,     V_SUB_CO_U32_e32_gfx9,     "v_sub_co_u32">;
1654defm : VOP2bInstAliases<V_SUBB_U32_e32,    V_SUBB_CO_U32_e32_gfx9,    "v_subb_co_u32">;
1655defm : VOP2bInstAliases<V_SUBREV_U32_e32,  V_SUBREV_CO_U32_e32_gfx9,  "v_subrev_co_u32">;
1656defm : VOP2bInstAliases<V_SUBBREV_U32_e32, V_SUBBREV_CO_U32_e32_gfx9, "v_subbrev_co_u32">;
1657
1658} // End SubtargetPredicate = isGFX9Only
1659
1660let SubtargetPredicate = HasDLInsts in {
1661
1662defm V_FMAC_F32 : VOP2_Real_e32e64_vi <0x3b>;
1663defm V_XNOR_B32 : VOP2_Real_e32e64_vi <0x3d>;
1664
1665} // End SubtargetPredicate = HasDLInsts
1666
1667let AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A" in {
1668  multiclass VOP2_Real_e32_gfx90a <bits<6> op> {
1669    def _e32_gfx90a :
1670      VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX90A>,
1671      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
1672  }
1673
1674  multiclass VOP2_Real_e64_gfx90a <bits<10> op> {
1675    def _e64_gfx90a :
1676      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX90A>,
1677      VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1678  }
1679
1680  multiclass Base_VOP2_Real_e32e64_gfx90a <bits<6> op> :
1681    VOP2_Real_e32_gfx90a<op>,
1682    VOP2_Real_e64_gfx90a<{0, 1, 0, 0, op{5-0}}>;
1683
1684  multiclass VOP2_Real_e32e64_gfx90a <bits<6> op> :
1685    Base_VOP2_Real_e32e64_gfx90a<op> {
1686
1687    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
1688      def _dpp_gfx90a :
1689        VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX90A>,
1690        VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
1691          let DecoderNamespace = "SDWA9";
1692        }
1693  }
1694} // End AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A"
1695
1696let SubtargetPredicate = isGFX90APlus in {
1697  defm V_FMAC_F64       : VOP2_Real_e32e64_gfx90a <0x4>;
1698  let IsSingle = 1 in {
1699    defm V_MUL_LEGACY_F32 : VOP2_Real_e64_gfx90a <0x2a1>;
1700  }
1701} // End SubtargetPredicate = isGFX90APlus
1702
1703multiclass VOP2_Real_DOT_ACC_gfx9<bits<6> op> : VOP2_Real_e32_vi<op> {
1704  def _dpp_vi : VOP2_DPP<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;
1705}
1706
1707multiclass VOP2_Real_DOT_ACC_gfx10<bits<6> op> :
1708  VOP2_Real_e32_gfx10<op>,
1709  VOP2_Real_dpp_gfx10<op>,
1710  VOP2_Real_dpp8_gfx10<op>;
1711
1712let SubtargetPredicate = HasDot5Insts in {
1713  defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx9<0x37>;
1714  // NB: Opcode conflicts with V_DOT8C_I32_I4
1715  // This opcode exists in gfx 10.1* only
1716  defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx10<0x02>;
1717}
1718
1719let SubtargetPredicate = HasDot6Insts in {
1720  defm V_DOT4C_I32_I8  : VOP2_Real_DOT_ACC_gfx9<0x39>;
1721  defm V_DOT4C_I32_I8  : VOP2_Real_DOT_ACC_gfx10<0x0d>;
1722}
1723
1724let SubtargetPredicate = HasDot4Insts in {
1725  defm V_DOT2C_I32_I16 : VOP2_Real_DOT_ACC_gfx9<0x38>;
1726}
1727let SubtargetPredicate = HasDot3Insts in {
1728  defm V_DOT8C_I32_I4  : VOP2_Real_DOT_ACC_gfx9<0x3a>;
1729}
1730
1731let SubtargetPredicate = HasPkFmacF16Inst in {
1732defm V_PK_FMAC_F16 : VOP2_Real_e32_vi<0x3c>;
1733} // End SubtargetPredicate = HasPkFmacF16Inst
1734
1735let SubtargetPredicate = HasDot3Insts in {
1736  // NB: Opcode conflicts with V_DOT2C_F32_F16
1737  let DecoderNamespace = "GFX10_B" in
1738  defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx10<0x02>;
1739}
1740