1//===-- VOP2Instructions.td - Vector Instruction Definitions --------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// VOP2 Classes 11//===----------------------------------------------------------------------===// 12 13class VOP2e <bits<6> op, VOPProfile P> : Enc32 { 14 bits<8> vdst; 15 bits<9> src0; 16 bits<8> src1; 17 18 let Inst{8-0} = !if(P.HasSrc0, src0, 0); 19 let Inst{16-9} = !if(P.HasSrc1, src1, 0); 20 let Inst{24-17} = !if(P.EmitDst, vdst, 0); 21 let Inst{30-25} = op; 22 let Inst{31} = 0x0; //encoding 23} 24 25class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 { 26 bits<8> vdst; 27 bits<9> src0; 28 bits<8> src1; 29 bits<32> imm; 30 31 let Inst{8-0} = !if(P.HasSrc0, src0, 0); 32 let Inst{16-9} = !if(P.HasSrc1, src1, 0); 33 let Inst{24-17} = !if(P.EmitDst, vdst, 0); 34 let Inst{30-25} = op; 35 let Inst{31} = 0x0; // encoding 36 let Inst{63-32} = imm; 37} 38 39class VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> { 40 bits<8> vdst; 41 bits<8> src1; 42 43 let Inst{8-0} = 0xf9; // sdwa 44 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 45 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 46 let Inst{30-25} = op; 47 let Inst{31} = 0x0; // encoding 48} 49 50class VOP2_SDWA9Ae <bits<6> op, VOPProfile P> : VOP_SDWA9Ae <P> { 51 bits<8> vdst; 52 bits<9> src1; 53 54 let Inst{8-0} = 0xf9; // sdwa 55 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 56 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 57 let Inst{30-25} = op; 58 let Inst{31} = 0x0; // encoding 59 let Inst{63} = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr 60} 61 62class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> : 63 VOP_Pseudo <opName, suffix, P, P.Outs32, P.Ins32, "", pattern> { 64 65 let AsmOperands = P.Asm32; 66 67 let Size = 4; 68 let mayLoad = 0; 69 let mayStore = 0; 70 let hasSideEffects = 0; 71 72 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 73 74 let mayRaiseFPException = ReadsModeReg; 75 76 let VOP2 = 1; 77 let VALU = 1; 78 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 79 80 let AsmVariantName = AMDGPUAsmVariants.Default; 81} 82 83class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> : 84 VOP_Real <ps>, 85 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 86 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 87 88 let VALU = 1; 89 let VOP2 = 1; 90 let isPseudo = 0; 91 let isCodeGenOnly = 0; 92 93 let Constraints = ps.Constraints; 94 let DisableEncoding = ps.DisableEncoding; 95 96 // copy relevant pseudo op flags 97 let SubtargetPredicate = ps.SubtargetPredicate; 98 let OtherPredicates = ps.OtherPredicates; 99 let AsmMatchConverter = ps.AsmMatchConverter; 100 let AsmVariantName = ps.AsmVariantName; 101 let Constraints = ps.Constraints; 102 let DisableEncoding = ps.DisableEncoding; 103 let TSFlags = ps.TSFlags; 104 let UseNamedOperandTable = ps.UseNamedOperandTable; 105 let Uses = ps.Uses; 106 let Defs = ps.Defs; 107 let SchedRW = ps.SchedRW; 108 let mayLoad = ps.mayLoad; 109 let mayStore = ps.mayStore; 110} 111 112class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : 113 VOP_SDWA_Pseudo <OpName, P, pattern> { 114 let AsmMatchConverter = "cvtSdwaVOP2"; 115} 116 117class VOP2_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : 118 VOP_DPP_Pseudo <OpName, P, pattern> { 119} 120 121 122class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies { 123 list<dag> ret = !if(P.HasModifiers, 124 [(set P.DstVT:$vdst, 125 (node (P.Src0VT 126 !if(P.HasOMod, 127 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 128 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))), 129 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], 130 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]); 131} 132 133multiclass VOP2Inst_e32<string opName, 134 VOPProfile P, 135 SDPatternOperator node = null_frag, 136 string revOp = opName, 137 bit GFX9Renamed = 0> { 138 let renamedInGFX9 = GFX9Renamed in { 139 def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>, 140 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>; 141 } // End renamedInGFX9 = GFX9Renamed 142} 143 144multiclass VOP2Inst_e64<string opName, 145 VOPProfile P, 146 SDPatternOperator node = null_frag, 147 string revOp = opName, 148 bit GFX9Renamed = 0> { 149 let renamedInGFX9 = GFX9Renamed in { 150 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>, 151 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>; 152 } // End renamedInGFX9 = GFX9Renamed 153} 154 155multiclass VOP2Inst_sdwa<string opName, 156 VOPProfile P, 157 bit GFX9Renamed = 0> { 158 let renamedInGFX9 = GFX9Renamed in { 159 foreach _ = BoolToList<P.HasExtSDWA>.ret in 160 def _sdwa : VOP2_SDWA_Pseudo <opName, P>; 161 } // End renamedInGFX9 = GFX9Renamed 162} 163 164multiclass VOP2Inst<string opName, 165 VOPProfile P, 166 SDPatternOperator node = null_frag, 167 string revOp = opName, 168 bit GFX9Renamed = 0> : 169 VOP2Inst_e32<opName, P, node, revOp, GFX9Renamed>, 170 VOP2Inst_e64<opName, P, node, revOp, GFX9Renamed>, 171 VOP2Inst_sdwa<opName, P, GFX9Renamed> { 172 let renamedInGFX9 = GFX9Renamed in { 173 foreach _ = BoolToList<P.HasExtDPP>.ret in 174 def _dpp : VOP2_DPP_Pseudo <opName, P>; 175 } 176} 177 178multiclass VOP2bInst <string opName, 179 VOPProfile P, 180 SDPatternOperator node = null_frag, 181 string revOp = opName, 182 bit GFX9Renamed = 0, 183 bit useSGPRInput = !eq(P.NumSrcArgs, 3)> { 184 let renamedInGFX9 = GFX9Renamed in { 185 let SchedRW = [Write32Bit, WriteSALU] in { 186 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in { 187 def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>, 188 Commutable_REV<revOp#"_e32", !eq(revOp, opName)> { 189 let usesCustomInserter = true; 190 } 191 192 foreach _ = BoolToList<P.HasExtSDWA>.ret in 193 def _sdwa : VOP2_SDWA_Pseudo <opName, P> { 194 let AsmMatchConverter = "cvtSdwaVOP2b"; 195 } 196 foreach _ = BoolToList<P.HasExtDPP>.ret in 197 def _dpp : VOP2_DPP_Pseudo <opName, P>; 198 } 199 200 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>, 201 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>; 202 } 203 } 204} 205 206class VOP2bInstAlias <VOP2_Pseudo ps, Instruction inst, 207 string OpName, string opnd> : 208 InstAlias <OpName#" "#!subst("vcc", opnd, ps.Pfl.Asm32), 209 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0, 210 ps.Pfl.Src1RC32:$src1)>, 211 PredicateControl { 212} 213 214multiclass VOP2bInstAliases<VOP2_Pseudo ps, VOP2_Real inst, string OpName> { 215 let WaveSizePredicate = isWave32 in { 216 def : VOP2bInstAlias<ps, inst, OpName, "vcc_lo">; 217 } 218 let WaveSizePredicate = isWave64 in { 219 def : VOP2bInstAlias<ps, inst, OpName, "vcc">; 220 } 221} 222 223multiclass VOP2eInst <string opName, 224 VOPProfile P, 225 SDPatternOperator node = null_frag, 226 string revOp = opName, 227 bit useSGPRInput = !eq(P.NumSrcArgs, 3)> { 228 229 let SchedRW = [Write32Bit] in { 230 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in { 231 def _e32 : VOP2_Pseudo <opName, P>, 232 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>; 233 234 foreach _ = BoolToList<P.HasExtSDWA>.ret in 235 def _sdwa : VOP2_SDWA_Pseudo <opName, P> { 236 let AsmMatchConverter = "cvtSdwaVOP2e"; 237 } 238 239 foreach _ = BoolToList<P.HasExtDPP>.ret in 240 def _dpp : VOP2_DPP_Pseudo <opName, P>; 241 } 242 243 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>, 244 Commutable_REV<revOp#"_e64", !eq(revOp, opName)> { 245 let isReMaterializable = 1; 246 } 247 } 248} 249 250class VOP2eInstAlias <VOP2_Pseudo ps, Instruction inst, string opnd = ""> : 251 InstAlias <ps.OpName#" "#ps.Pfl.Asm32#", "#opnd, 252 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0, 253 ps.Pfl.Src1RC32:$src1)>, PredicateControl; 254 255class VOP2e64InstAlias <VOP3_Pseudo ps, Instruction inst> : 256 InstAlias <ps.OpName#" "#ps.Pfl.Asm64, 257 (inst ps.Pfl.DstRC:$vdst, VOPDstS64orS32:$sdst, 258 ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, clampmod:$clamp)>, 259 PredicateControl; 260 261multiclass VOP2eInstAliases<VOP2_Pseudo ps, VOP2_Real inst> { 262 let WaveSizePredicate = isWave32 in { 263 def : VOP2eInstAlias<ps, inst, "vcc_lo">; 264 } 265 let WaveSizePredicate = isWave64 in { 266 def : VOP2eInstAlias<ps, inst, "vcc">; 267 } 268} 269 270class VOP_MADAK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> { 271 field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm); 272 field dag Ins32 = !if(!eq(vt.Size, 32), 273 (ins VCSrc_f32:$src0, VGPR_32:$src1, ImmOpType:$imm), 274 (ins VCSrc_f16:$src0, VGPR_32:$src1, ImmOpType:$imm)); 275 field bit HasExt = 0; 276 let IsSingle = 1; 277 278 field string Asm32 = "$vdst, $src0, $src1, $imm"; 279} 280 281def VOP_MADAK_F16 : VOP_MADAK <f16>; 282def VOP_MADAK_F32 : VOP_MADAK <f32>; 283 284class VOP_MADMK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> { 285 field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm); 286 field dag Ins32 = (ins VCSrc_f32:$src0, ImmOpType:$imm, VGPR_32:$src1); 287 field bit HasExt = 0; 288 let IsSingle = 1; 289 290 field string Asm32 = "$vdst, $src0, $imm, $src1"; 291} 292 293def VOP_MADMK_F16 : VOP_MADMK <f16>; 294def VOP_MADMK_F32 : VOP_MADMK <f32>; 295 296class getRegisterOperandForVT<ValueType VT> { 297 RegisterOperand ret = RegisterOperand<getVregSrcForVT<VT>.ret>; 298} 299 300// FIXME: Remove src2_modifiers. It isn't used, so is wasting memory 301// and processing time but it makes it easier to convert to mad. 302class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, vt0]> { 303 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, getVregSrcForVT<Src2VT>.ret:$src2); 304 let Ins64 = getIns64<Src0RC64, Src1RC64, getRegisterOperandForVT<Src2VT>.ret, 3, 305 0, HasModifiers, HasModifiers, HasOMod, 306 Src0Mod, Src1Mod, Src2Mod>.ret; 307 let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, 308 Src1ModDPP:$src1_modifiers, Src1DPP:$src1, 309 getVregSrcForVT<Src2VT>.ret:$src2, // stub argument 310 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 311 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 312 let InsDPP16 = !con(InsDPP, (ins FI:$fi)); 313 let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, 314 Src1ModDPP:$src1_modifiers, Src1DPP:$src1, 315 getVregSrcForVT<Src2VT>.ret:$src2, // stub argument 316 dpp8:$dpp8, FI:$fi); 317 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 318 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 319 getVregSrcForVT<Src2VT>.ret:$src2, // stub argument 320 clampmod:$clamp, omod:$omod, 321 dst_sel:$dst_sel, dst_unused:$dst_unused, 322 src0_sel:$src0_sel, src1_sel:$src1_sel); 323 let Asm32 = getAsm32<1, 2, vt0>.ret; 324 let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, vt0>.ret; 325 let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt0>.ret; 326 let AsmDPP16 = getAsmDPP16<1, 2, HasModifiers, vt0>.ret; 327 let AsmDPP8 = getAsmDPP8<1, 2, 0, vt0>.ret; 328 let AsmSDWA = getAsmSDWA<1, 2, vt0>.ret; 329 let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt0>.ret; 330 let HasSrc2 = 0; 331 let HasSrc2Mods = 0; 332 333 let HasExt = 1; 334 let HasExtDPP = 1; 335 let HasExtSDWA = 1; 336 let HasExtSDWA9 = 0; 337 let TieRegDPP = "$src2"; 338} 339 340def VOP_MAC_F16 : VOP_MAC <f16>; 341def VOP_MAC_F32 : VOP_MAC <f32>; 342let HasExtDPP = 0 in 343def VOP_MAC_LEGACY_F32 : VOP_MAC <f32>; 344let HasExtSDWA = 0, HasExt64BitDPP = 1 in 345def VOP_MAC_F64 : VOP_MAC <f64>; 346 347class VOP_DOT_ACC<ValueType vt0, ValueType vt1> : VOP_MAC<vt0, vt1> { 348 let HasClamp = 0; 349 let HasExtSDWA = 0; 350 let HasOpSel = 0; 351 let IsPacked = 0; 352} 353 354def VOP_DOT_ACC_F32_V2F16 : VOP_DOT_ACC<f32, v2f16> { 355 let Src0ModDPP = FPVRegInputMods; 356 let Src1ModDPP = FPVRegInputMods; 357} 358 359def VOP_DOT_ACC_I32_I32 : VOP_DOT_ACC<i32, i32> { 360 let HasSrc0Mods = 1; 361 let HasSrc1Mods = 1; 362} 363 364// Write out to vcc or arbitrary SGPR. 365def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], 0, /*EnableClamp=*/1> { 366 let Asm32 = "$vdst, vcc, $src0, $src1"; 367 let Asm64 = "$vdst, $sdst, $src0, $src1$clamp"; 368 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 369 let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 370 let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 371 let AsmDPP8 = "$vdst, vcc, $src0, $src1 $dpp8$fi"; 372 let AsmDPP16 = AsmDPP#"$fi"; 373 let Outs32 = (outs DstRC:$vdst); 374 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 375} 376 377// Write out to vcc or arbitrary SGPR and read in from vcc or 378// arbitrary SGPR. 379def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], 0, /*EnableClamp=*/1> { 380 let Asm32 = "$vdst, vcc, $src0, $src1, vcc"; 381 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp"; 382 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 383 let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 384 let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 385 let AsmDPP8 = "$vdst, vcc, $src0, $src1, vcc $dpp8$fi"; 386 let AsmDPP16 = AsmDPP#"$fi"; 387 let Outs32 = (outs DstRC:$vdst); 388 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 389 390 // Suppress src2 implied by type since the 32-bit encoding uses an 391 // implicit VCC use. 392 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1); 393 394 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 395 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 396 clampmod:$clamp, 397 dst_sel:$dst_sel, dst_unused:$dst_unused, 398 src0_sel:$src0_sel, src1_sel:$src1_sel); 399 400 let InsDPP = (ins DstRCDPP:$old, 401 Src0DPP:$src0, 402 Src1DPP:$src1, 403 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 404 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 405 let InsDPP16 = !con(InsDPP, (ins FI:$fi)); 406 407 let HasExt = 1; 408 let HasExtDPP = 1; 409 let HasExtSDWA = 1; 410 let HasExtSDWA9 = 1; 411} 412 413// Read in from vcc or arbitrary SGPR. 414def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], /*EnableF32SrcMods=*/1> { 415 let Asm32 = "$vdst, $src0, $src1"; 416 let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2"; 417 let AsmSDWA = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 418 let AsmSDWA9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 419 let AsmDPP = "$vdst, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 420 let AsmDPP8 = "$vdst, $src0, $src1, vcc $dpp8$fi"; 421 let AsmDPP16 = AsmDPP#"$fi"; 422 423 let Outs32 = (outs DstRC:$vdst); 424 let Outs64 = (outs DstRC:$vdst); 425 426 // Suppress src2 implied by type since the 32-bit encoding uses an 427 // implicit VCC use. 428 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1); 429 430 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 431 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 432 clampmod:$clamp, 433 dst_sel:$dst_sel, dst_unused:$dst_unused, 434 src0_sel:$src0_sel, src1_sel:$src1_sel); 435 436 let InsDPP = (ins DstRCDPP:$old, 437 Src0ModDPP:$src0_modifiers, Src0DPP:$src0, 438 Src1ModDPP:$src1_modifiers, Src1DPP:$src1, 439 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 440 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 441 let InsDPP16 = !con(InsDPP, (ins FI:$fi)); 442 443 let HasExt = 1; 444 let HasExtDPP = 1; 445 let HasExtSDWA = 1; 446 let HasExtSDWA9 = 1; 447} 448 449def VOP_READLANE : VOPProfile<[i32, i32, i32]> { 450 let Outs32 = (outs SReg_32:$vdst); 451 let Outs64 = Outs32; 452 let Ins32 = (ins VRegOrLds_32:$src0, SCSrc_b32:$src1); 453 let Ins64 = Ins32; 454 let Asm32 = " $vdst, $src0, $src1"; 455 let Asm64 = Asm32; 456 457 let HasExt = 0; 458 let HasExtDPP = 0; 459 let HasExt64BitDPP = 0; 460 let HasExtSDWA = 0; 461 let HasExtSDWA9 = 0; 462} 463 464def VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> { 465 let Outs32 = (outs VGPR_32:$vdst); 466 let Outs64 = Outs32; 467 let Ins32 = (ins SCSrc_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in); 468 let Ins64 = Ins32; 469 let Asm32 = " $vdst, $src0, $src1"; 470 let Asm64 = Asm32; 471 let HasSrc2 = 0; 472 let HasSrc2Mods = 0; 473 474 let HasExt = 0; 475 let HasExtDPP = 0; 476 let HasExt64BitDPP = 0; 477 let HasExtSDWA = 0; 478 let HasExtSDWA9 = 0; 479} 480 481//===----------------------------------------------------------------------===// 482// VOP2 Instructions 483//===----------------------------------------------------------------------===// 484 485defm V_CNDMASK_B32 : VOP2eInst <"v_cndmask_b32", VOP2e_I32_I32_I32_I1>; 486let SubtargetPredicate = HasMadMacF32Insts, isReMaterializable = 1 in 487def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, []>; 488 489let isCommutable = 1 in { 490let isReMaterializable = 1 in { 491defm V_ADD_F32 : VOP2Inst <"v_add_f32", VOP_F32_F32_F32, any_fadd>; 492defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, any_fsub>; 493defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">; 494defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>; 495defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, any_fmul>; 496defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32_ARITH, AMDGPUmul_i24>; 497defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_i24>; 498defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32_ARITH, AMDGPUmul_u24>; 499defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_u24>; 500defm V_MIN_F32 : VOP2Inst <"v_min_f32", VOP_F32_F32_F32, fminnum_like>; 501defm V_MAX_F32 : VOP2Inst <"v_max_f32", VOP_F32_F32_F32, fmaxnum_like>; 502defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smin>; 503defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smax>; 504defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umin>; 505defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umax>; 506defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, lshr_rev, "v_lshr_b32">; 507defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, ashr_rev, "v_ashr_i32">; 508defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, lshl_rev, "v_lshl_b32">; 509defm V_AND_B32 : VOP2Inst <"v_and_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, and>; 510defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, or>; 511defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, xor>; 512} // End isReMaterializable = 1 513 514let mayRaiseFPException = 0 in { 515let OtherPredicates = [HasMadMacF32Insts] in { 516let Constraints = "$vdst = $src2", DisableEncoding="$src2", 517 isConvertibleToThreeAddress = 1 in { 518defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>; 519 520let SubtargetPredicate = isGFX6GFX7GFX10 in 521defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_MAC_LEGACY_F32>; 522} // End Constraints = "$vdst = $src2", DisableEncoding="$src2", 523 // isConvertibleToThreeAddress = 1 524 525let isReMaterializable = 1 in 526def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32, []>; 527} // End OtherPredicates = [HasMadMacF32Insts] 528} // End mayRaiseFPException = 0 529 530// No patterns so that the scalar instructions are always selected. 531// The scalar versions will be replaced with vector when needed later. 532defm V_ADD_CO_U32 : VOP2bInst <"v_add_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_add_co_u32", 1>; 533defm V_SUB_CO_U32 : VOP2bInst <"v_sub_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>; 534defm V_SUBREV_CO_U32 : VOP2bInst <"v_subrev_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>; 535defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_addc_u32", 1>; 536defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>; 537defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>; 538 539 540let SubtargetPredicate = HasAddNoCarryInsts, isReMaterializable = 1 in { 541defm V_ADD_U32 : VOP2Inst <"v_add_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_add_u32", 1>; 542defm V_SUB_U32 : VOP2Inst <"v_sub_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>; 543defm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>; 544} 545 546} // End isCommutable = 1 547 548// These are special and do not read the exec mask. 549let isConvergent = 1, Uses = []<Register> in { 550def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE, 551 [(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))]>; 552 553let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in { 554def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE, 555 [(set i32:$vdst, (int_amdgcn_writelane i32:$src0, i32:$src1, i32:$vdst_in))]>; 556} // End $vdst = $vdst_in, DisableEncoding $vdst_in 557} // End isConvergent = 1 558 559let isReMaterializable = 1 in { 560defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_NO_EXT<VOP_I32_I32_I32>>; 561defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, add_ctpop>; 562defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_lo>; 563defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_hi>; 564defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_NO_EXT<VOP_F32_F32_I32>, AMDGPUldexp>; 565 566let ReadsModeReg = 0, mayRaiseFPException = 0 in { 567defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_i16_f32>; 568defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_u16_f32>; 569} 570 571defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_NO_EXT<VOP_V2F16_F32_F32>, AMDGPUpkrtz_f16_f32>; 572defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_u16_u32>; 573defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_i16_i32>; 574 575 576let SubtargetPredicate = isGFX6GFX7 in { 577defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>; 578defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>; 579} // End SubtargetPredicate = isGFX6GFX7 580 581let isCommutable = 1 in { 582let SubtargetPredicate = isGFX6GFX7 in { 583defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, srl>; 584defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, sra>; 585defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, shl>; 586} // End SubtargetPredicate = isGFX6GFX7 587} // End isCommutable = 1 588} // End isReMaterializable = 1 589 590defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_NO_EXT<VOP_I32_F32_I32>>; // TODO: set "Uses = dst" 591 592class DivergentBinOp<SDPatternOperator Op, VOP_Pseudo Inst> : 593 GCNPat< 594 (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1), 595 !if(!cast<Commutable_REV>(Inst).IsOrig, 596 (Inst $src0, $src1), 597 (Inst $src1, $src0) 598 ) 599 >; 600 601class DivergentClampingBinOp<SDPatternOperator Op, VOP_Pseudo Inst> : 602 GCNPat< 603 (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1), 604 !if(!cast<Commutable_REV>(Inst).IsOrig, 605 (Inst $src0, $src1, 0), 606 (Inst $src1, $src0, 0) 607 ) 608 >; 609 610def : DivergentBinOp<srl, V_LSHRREV_B32_e64>; 611def : DivergentBinOp<sra, V_ASHRREV_I32_e64>; 612def : DivergentBinOp<shl, V_LSHLREV_B32_e64>; 613 614let SubtargetPredicate = HasAddNoCarryInsts in { 615 def : DivergentClampingBinOp<add, V_ADD_U32_e64>; 616 def : DivergentClampingBinOp<sub, V_SUB_U32_e64>; 617} 618 619let SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] in { 620def : DivergentClampingBinOp<add, V_ADD_CO_U32_e64>; 621def : DivergentClampingBinOp<sub, V_SUB_CO_U32_e64>; 622} 623 624def : DivergentBinOp<adde, V_ADDC_U32_e32>; 625def : DivergentBinOp<sube, V_SUBB_U32_e32>; 626 627class divergent_i64_BinOp <SDPatternOperator Op, Instruction Inst> : 628 GCNPat< 629 (getDivergentFrag<Op>.ret i64:$src0, i64:$src1), 630 (REG_SEQUENCE VReg_64, 631 (Inst 632 (i32 (EXTRACT_SUBREG $src0, sub0)), 633 (i32 (EXTRACT_SUBREG $src1, sub0)) 634 ), sub0, 635 (Inst 636 (i32 (EXTRACT_SUBREG $src0, sub1)), 637 (i32 (EXTRACT_SUBREG $src1, sub1)) 638 ), sub1 639 ) 640 >; 641 642def : divergent_i64_BinOp <and, V_AND_B32_e32>; 643def : divergent_i64_BinOp <or, V_OR_B32_e32>; 644def : divergent_i64_BinOp <xor, V_XOR_B32_e32>; 645 646let SubtargetPredicate = Has16BitInsts in { 647 648let FPDPRounding = 1 in { 649def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16, [], "">; 650defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>; 651} // End FPDPRounding = 1 652 653defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16, lshl_rev>; 654defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16, lshr_rev>; 655defm V_ASHRREV_I16 : VOP2Inst <"v_ashrrev_i16", VOP_I16_I16_I16, ashr_rev>; 656 657let isCommutable = 1 in { 658let FPDPRounding = 1 in { 659defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, any_fadd>; 660defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, any_fsub>; 661defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">; 662defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, any_fmul>; 663 664let mayRaiseFPException = 0 in { 665def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">; 666} 667 668} // End FPDPRounding = 1 669defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16_ARITH, add>; 670defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16_ARITH, sub>; 671defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16_ARITH, null_frag, "v_sub_u16">; 672defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16, mul>; 673defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum_like>; 674defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum_like>; 675defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16, umax>; 676defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16, smax>; 677defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16, umin>; 678defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16, smin>; 679 680let Constraints = "$vdst = $src2", DisableEncoding="$src2", 681 isConvertibleToThreeAddress = 1 in { 682defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>; 683} 684} // End isCommutable = 1 685 686} // End SubtargetPredicate = Has16BitInsts 687 688let SubtargetPredicate = HasDLInsts in { 689 690let isReMaterializable = 1 in 691defm V_XNOR_B32 : VOP2Inst <"v_xnor_b32", VOP_I32_I32_I32, xnor>; 692 693let Constraints = "$vdst = $src2", 694 DisableEncoding = "$src2", 695 isConvertibleToThreeAddress = 1, 696 isCommutable = 1 in 697defm V_FMAC_F32 : VOP2Inst <"v_fmac_f32", VOP_MAC_F32>; 698 699} // End SubtargetPredicate = HasDLInsts 700 701let SubtargetPredicate = HasFmaLegacy32 in { 702 703let Constraints = "$vdst = $src2", 704 DisableEncoding = "$src2", 705 isConvertibleToThreeAddress = 1, 706 isCommutable = 1 in 707defm V_FMAC_LEGACY_F32 : VOP2Inst <"v_fmac_legacy_f32", VOP_MAC_LEGACY_F32>; 708 709} // End SubtargetPredicate = HasFmaLegacy32 710 711let SubtargetPredicate = isGFX90APlus, 712 Constraints = "$vdst = $src2", 713 DisableEncoding="$src2", 714 isConvertibleToThreeAddress = 1, 715 isCommutable = 1, 716 SchedRW = [WriteDoubleAdd] in 717defm V_FMAC_F64 : VOP2Inst <"v_fmac_f64", VOP_MAC_F64>; 718 719let Constraints = "$vdst = $src2", 720 DisableEncoding="$src2", 721 isConvertibleToThreeAddress = 1, 722 isCommutable = 1, 723 IsDOT = 1 in { 724 let SubtargetPredicate = HasDot5Insts in 725 defm V_DOT2C_F32_F16 : VOP2Inst<"v_dot2c_f32_f16", VOP_DOT_ACC_F32_V2F16>; 726 let SubtargetPredicate = HasDot6Insts in 727 defm V_DOT4C_I32_I8 : VOP2Inst<"v_dot4c_i32_i8", VOP_DOT_ACC_I32_I32>; 728 729 let SubtargetPredicate = HasDot4Insts in 730 defm V_DOT2C_I32_I16 : VOP2Inst<"v_dot2c_i32_i16", VOP_DOT_ACC_I32_I32>; 731 let SubtargetPredicate = HasDot3Insts in 732 defm V_DOT8C_I32_I4 : VOP2Inst<"v_dot8c_i32_i4", VOP_DOT_ACC_I32_I32>; 733} 734 735let AddedComplexity = 30 in { 736 def : GCNPat< 737 (f32 (AMDGPUfdot2 v2f16:$src0, v2f16:$src1, f32:$src2, (i1 DSTCLAMP.NONE))), 738 (f32 (V_DOT2C_F32_F16_e32 $src0, $src1, $src2)) 739 > { 740 let SubtargetPredicate = HasDot5Insts; 741 } 742 def : GCNPat< 743 (i32 (int_amdgcn_sdot4 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))), 744 (i32 (V_DOT4C_I32_I8_e32 $src0, $src1, $src2)) 745 > { 746 let SubtargetPredicate = HasDot6Insts; 747 } 748 def : GCNPat< 749 (i32 (int_amdgcn_sdot2 v2i16:$src0, v2i16:$src1, i32:$src2, (i1 DSTCLAMP.NONE))), 750 (i32 (V_DOT2C_I32_I16_e32 $src0, $src1, $src2)) 751 > { 752 let SubtargetPredicate = HasDot4Insts; 753 } 754 def : GCNPat< 755 (i32 (int_amdgcn_sdot8 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))), 756 (i32 (V_DOT8C_I32_I4_e32 $src0, $src1, $src2)) 757 > { 758 let SubtargetPredicate = HasDot3Insts; 759 } 760} // End AddedComplexity = 30 761 762let SubtargetPredicate = HasFmaakFmamkF32Insts, isReMaterializable = 1 in { 763def V_FMAMK_F32 : VOP2_Pseudo<"v_fmamk_f32", VOP_MADMK_F32, [], "">; 764 765let isCommutable = 1 in 766def V_FMAAK_F32 : VOP2_Pseudo<"v_fmaak_f32", VOP_MADAK_F32, [], "">; 767} 768 769let SubtargetPredicate = isGFX10Plus in { 770 771let FPDPRounding = 1 in { 772def V_FMAMK_F16 : VOP2_Pseudo <"v_fmamk_f16", VOP_MADMK_F16, [], "">; 773 774let isCommutable = 1 in 775def V_FMAAK_F16 : VOP2_Pseudo <"v_fmaak_f16", VOP_MADAK_F16, [], "">; 776} // End FPDPRounding = 1 777 778let Constraints = "$vdst = $src2", 779 DisableEncoding="$src2", 780 isConvertibleToThreeAddress = 1, 781 isCommutable = 1 in { 782defm V_FMAC_F16 : VOP2Inst <"v_fmac_f16", VOP_MAC_F16>; 783} 784 785} // End SubtargetPredicate = isGFX10Plus 786 787let SubtargetPredicate = HasPkFmacF16Inst in { 788defm V_PK_FMAC_F16 : VOP2Inst<"v_pk_fmac_f16", VOP_V2F16_V2F16_V2F16>; 789} // End SubtargetPredicate = HasPkFmacF16Inst 790 791// Note: 16-bit instructions produce a 0 result in the high 16-bits 792// on GFX8 and GFX9 and preserve high 16 bits on GFX10+ 793multiclass Arithmetic_i16_0Hi_Pats <SDPatternOperator op, Instruction inst> { 794 795def : GCNPat< 796 (i32 (zext (op i16:$src0, i16:$src1))), 797 (inst VSrc_b16:$src0, VSrc_b16:$src1) 798>; 799 800def : GCNPat< 801 (i64 (zext (op i16:$src0, i16:$src1))), 802 (REG_SEQUENCE VReg_64, 803 (inst $src0, $src1), sub0, 804 (V_MOV_B32_e32 (i32 0)), sub1) 805>; 806} 807 808class ZExt_i16_i1_Pat <SDNode ext> : GCNPat < 809 (i16 (ext i1:$src)), 810 (V_CNDMASK_B32_e64 (i32 0/*src0mod*/), (i32 0/*src0*/), 811 (i32 0/*src1mod*/), (i32 1/*src1*/), 812 $src) 813>; 814 815foreach vt = [i16, v2i16] in { 816def : GCNPat < 817 (and vt:$src0, vt:$src1), 818 (V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1) 819>; 820 821def : GCNPat < 822 (or vt:$src0, vt:$src1), 823 (V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1) 824>; 825 826def : GCNPat < 827 (xor vt:$src0, vt:$src1), 828 (V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1) 829>; 830} 831 832let Predicates = [Has16BitInsts] in { 833 834// Undo sub x, c -> add x, -c canonicalization since c is more likely 835// an inline immediate than -c. 836// TODO: Also do for 64-bit. 837def : GCNPat< 838 (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)), 839 (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1) 840>; 841 842 843let Predicates = [Has16BitInsts, isGFX7GFX8GFX9] in { 844 845def : GCNPat< 846 (i32 (zext (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)))), 847 (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1) 848>; 849 850defm : Arithmetic_i16_0Hi_Pats<add, V_ADD_U16_e64>; 851defm : Arithmetic_i16_0Hi_Pats<mul, V_MUL_LO_U16_e64>; 852defm : Arithmetic_i16_0Hi_Pats<sub, V_SUB_U16_e64>; 853defm : Arithmetic_i16_0Hi_Pats<smin, V_MIN_I16_e64>; 854defm : Arithmetic_i16_0Hi_Pats<smax, V_MAX_I16_e64>; 855defm : Arithmetic_i16_0Hi_Pats<umin, V_MIN_U16_e64>; 856defm : Arithmetic_i16_0Hi_Pats<umax, V_MAX_U16_e64>; 857defm : Arithmetic_i16_0Hi_Pats<lshl_rev, V_LSHLREV_B16_e64>; 858defm : Arithmetic_i16_0Hi_Pats<lshr_rev, V_LSHRREV_B16_e64>; 859defm : Arithmetic_i16_0Hi_Pats<ashr_rev, V_ASHRREV_I16_e64>; 860} // End Predicates = [Has16BitInsts, isGFX7GFX8GFX9] 861 862def : ZExt_i16_i1_Pat<zext>; 863def : ZExt_i16_i1_Pat<anyext>; 864 865def : GCNPat < 866 (i16 (sext i1:$src)), 867 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0), 868 /*src1mod*/(i32 0), /*src1*/(i32 -1), $src) 869>; 870 871} // End Predicates = [Has16BitInsts] 872 873 874let SubtargetPredicate = HasIntClamp in { 875// Set clamp bit for saturation. 876def : VOPBinOpClampPat<uaddsat, V_ADD_CO_U32_e64, i32>; 877def : VOPBinOpClampPat<usubsat, V_SUB_CO_U32_e64, i32>; 878} 879 880let SubtargetPredicate = HasAddNoCarryInsts, OtherPredicates = [HasIntClamp] in { 881let AddedComplexity = 1 in { // Prefer over form with carry-out. 882def : VOPBinOpClampPat<uaddsat, V_ADD_U32_e64, i32>; 883def : VOPBinOpClampPat<usubsat, V_SUB_U32_e64, i32>; 884} 885} 886 887let SubtargetPredicate = Has16BitInsts, OtherPredicates = [HasIntClamp] in { 888def : VOPBinOpClampPat<uaddsat, V_ADD_U16_e64, i16>; 889def : VOPBinOpClampPat<usubsat, V_SUB_U16_e64, i16>; 890} 891 892//===----------------------------------------------------------------------===// 893// Target-specific instruction encodings. 894//===----------------------------------------------------------------------===// 895 896class VOP2_DPP<bits<6> op, VOP2_DPP_Pseudo ps, 897 string opName = ps.OpName, VOPProfile p = ps.Pfl, 898 bit IsDPP16 = 0> : 899 VOP_DPP<opName, p, IsDPP16> { 900 let hasSideEffects = ps.hasSideEffects; 901 let Defs = ps.Defs; 902 let SchedRW = ps.SchedRW; 903 let Uses = ps.Uses; 904 905 bits<8> vdst; 906 bits<8> src1; 907 let Inst{8-0} = 0xfa; 908 let Inst{16-9} = !if(p.HasSrc1, src1{7-0}, 0); 909 let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0); 910 let Inst{30-25} = op; 911 let Inst{31} = 0x0; 912} 913 914class Base_VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps, 915 string opName = ps.OpName, VOPProfile p = ps.Pfl> : 916 VOP2_DPP<op, ps, opName, p, 1> { 917 let AssemblerPredicate = HasDPP16; 918 let SubtargetPredicate = HasDPP16; 919 let OtherPredicates = ps.OtherPredicates; 920} 921 922class VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps, 923 string opName = ps.OpName, VOPProfile p = ps.Pfl> : 924 Base_VOP2_DPP16<op, ps, opName, p>, 925 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX10>; 926 927class VOP2_DPP8<bits<6> op, VOP2_Pseudo ps, 928 VOPProfile p = ps.Pfl> : 929 VOP_DPP8<ps.OpName, p> { 930 let hasSideEffects = ps.hasSideEffects; 931 let Defs = ps.Defs; 932 let SchedRW = ps.SchedRW; 933 let Uses = ps.Uses; 934 935 bits<8> vdst; 936 bits<8> src1; 937 938 let Inst{8-0} = fi; 939 let Inst{16-9} = !if(p.HasSrc1, src1{7-0}, 0); 940 let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0); 941 let Inst{30-25} = op; 942 let Inst{31} = 0x0; 943 944 let OtherPredicates = ps.OtherPredicates; 945} 946 947//===----------------------------------------------------------------------===// 948// GFX10. 949//===----------------------------------------------------------------------===// 950 951let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in { 952 //===------------------------------- VOP2 -------------------------------===// 953 multiclass VOP2Only_Real_MADK_gfx10<bits<6> op> { 954 def _gfx10 : 955 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX10>, 956 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 957 } 958 multiclass VOP2Only_Real_MADK_gfx10_with_name<bits<6> op, string opName, 959 string asmName> { 960 def _gfx10 : 961 VOP2_Real<!cast<VOP2_Pseudo>(opName), SIEncodingFamily.GFX10>, 962 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> { 963 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName); 964 let AsmString = asmName # ps.AsmOperands; 965 } 966 } 967 multiclass VOP2_Real_e32_gfx10<bits<6> op> { 968 def _e32_gfx10 : 969 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>, 970 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 971 } 972 multiclass VOP2_Real_e64_gfx10<bits<6> op> { 973 def _e64_gfx10 : 974 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 975 VOP3e_gfx10<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 976 } 977 multiclass VOP2_Real_sdwa_gfx10<bits<6> op> { 978 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in 979 def _sdwa_gfx10 : 980 VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 981 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> { 982 let DecoderNamespace = "SDWA10"; 983 } 984 } 985 multiclass VOP2_Real_dpp_gfx10<bits<6> op> { 986 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in 987 def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> { 988 let DecoderNamespace = "SDWA10"; 989 } 990 } 991 multiclass VOP2_Real_dpp8_gfx10<bits<6> op> { 992 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in 993 def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(NAME#"_e32")> { 994 let DecoderNamespace = "DPP8"; 995 } 996 } 997 998 //===------------------------- VOP2 (with name) -------------------------===// 999 multiclass VOP2_Real_e32_gfx10_with_name<bits<6> op, string opName, 1000 string asmName> { 1001 def _e32_gfx10 : 1002 VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>, 1003 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> { 1004 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32"); 1005 let AsmString = asmName # ps.AsmOperands; 1006 } 1007 } 1008 multiclass VOP2_Real_e64_gfx10_with_name<bits<6> op, string opName, 1009 string asmName> { 1010 def _e64_gfx10 : 1011 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>, 1012 VOP3e_gfx10<{0, 1, 0, 0, op{5-0}}, 1013 !cast<VOP3_Pseudo>(opName#"_e64").Pfl> { 1014 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1015 let AsmString = asmName # ps.AsmOperands; 1016 } 1017 } 1018 let DecoderNamespace = "SDWA10" in { 1019 multiclass VOP2_Real_sdwa_gfx10_with_name<bits<6> op, string opName, 1020 string asmName> { 1021 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in 1022 def _sdwa_gfx10 : 1023 VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>, 1024 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> { 1025 VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa"); 1026 let AsmString = asmName # ps.AsmOperands; 1027 } 1028 } 1029 multiclass VOP2_Real_dpp_gfx10_with_name<bits<6> op, string opName, 1030 string asmName> { 1031 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1032 def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp")> { 1033 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32"); 1034 let AsmString = asmName # ps.Pfl.AsmDPP16; 1035 } 1036 } 1037 multiclass VOP2_Real_dpp8_gfx10_with_name<bits<6> op, string opName, 1038 string asmName> { 1039 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1040 def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> { 1041 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32"); 1042 let AsmString = asmName # ps.Pfl.AsmDPP8; 1043 let DecoderNamespace = "DPP8"; 1044 } 1045 } 1046 } // End DecoderNamespace = "SDWA10" 1047 1048 //===------------------------------ VOP2be ------------------------------===// 1049 multiclass VOP2be_Real_e32_gfx10<bits<6> op, string opName, string asmName> { 1050 def _e32_gfx10 : 1051 VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>, 1052 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> { 1053 VOP2_Pseudo Ps = !cast<VOP2_Pseudo>(opName#"_e32"); 1054 let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands); 1055 } 1056 } 1057 multiclass VOP2be_Real_e64_gfx10<bits<6> op, string opName, string asmName> { 1058 def _e64_gfx10 : 1059 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>, 1060 VOP3be_gfx10<{0, 1, 0, 0, op{5-0}}, 1061 !cast<VOP3_Pseudo>(opName#"_e64").Pfl> { 1062 VOP3_Pseudo Ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1063 let AsmString = asmName # Ps.AsmOperands; 1064 } 1065 } 1066 multiclass VOP2be_Real_sdwa_gfx10<bits<6> op, string opName, string asmName> { 1067 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in 1068 def _sdwa_gfx10 : 1069 VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>, 1070 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> { 1071 VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa"); 1072 let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands); 1073 let DecoderNamespace = "SDWA10"; 1074 } 1075 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in 1076 def _sdwa_w32_gfx10 : 1077 Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>, 1078 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> { 1079 VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa"); 1080 let AsmString = asmName # !subst("vcc", "vcc_lo", Ps.AsmOperands); 1081 let isAsmParserOnly = 1; 1082 let DecoderNamespace = "SDWA10"; 1083 let WaveSizePredicate = isWave32; 1084 } 1085 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in 1086 def _sdwa_w64_gfx10 : 1087 Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>, 1088 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> { 1089 VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa"); 1090 let AsmString = asmName # Ps.AsmOperands; 1091 let isAsmParserOnly = 1; 1092 let DecoderNamespace = "SDWA10"; 1093 let WaveSizePredicate = isWave64; 1094 } 1095 } 1096 multiclass VOP2be_Real_dpp_gfx10<bits<6> op, string opName, string asmName> { 1097 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1098 def _dpp_gfx10 : 1099 VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> { 1100 string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16; 1101 let AsmString = asmName # !subst(", vcc", "", AsmDPP); 1102 let DecoderNamespace = "SDWA10"; 1103 } 1104 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1105 def _dpp_w32_gfx10 : 1106 Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> { 1107 string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16; 1108 let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP); 1109 let isAsmParserOnly = 1; 1110 let WaveSizePredicate = isWave32; 1111 } 1112 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1113 def _dpp_w64_gfx10 : 1114 Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> { 1115 string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16; 1116 let AsmString = asmName # AsmDPP; 1117 let isAsmParserOnly = 1; 1118 let WaveSizePredicate = isWave64; 1119 } 1120 } 1121 multiclass VOP2be_Real_dpp8_gfx10<bits<6> op, string opName, string asmName> { 1122 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1123 def _dpp8_gfx10 : 1124 VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> { 1125 string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8; 1126 let AsmString = asmName # !subst(", vcc", "", AsmDPP8); 1127 let DecoderNamespace = "DPP8"; 1128 } 1129 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1130 def _dpp8_w32_gfx10 : 1131 VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> { 1132 string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8; 1133 let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8); 1134 let isAsmParserOnly = 1; 1135 let WaveSizePredicate = isWave32; 1136 } 1137 foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in 1138 def _dpp8_w64_gfx10 : 1139 VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> { 1140 string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8; 1141 let AsmString = asmName # AsmDPP8; 1142 let isAsmParserOnly = 1; 1143 let WaveSizePredicate = isWave64; 1144 } 1145 } 1146 1147 //===----------------------------- VOP3Only -----------------------------===// 1148 multiclass VOP3Only_Real_gfx10<bits<10> op> { 1149 def _e64_gfx10 : 1150 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 1151 VOP3e_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1152 let IsSingle = 1; 1153 } 1154 } 1155 1156 //===---------------------------- VOP3beOnly ----------------------------===// 1157 multiclass VOP3beOnly_Real_gfx10<bits<10> op> { 1158 def _e64_gfx10 : 1159 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 1160 VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1161 let IsSingle = 1; 1162 } 1163 } 1164} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" 1165 1166multiclass VOP2be_Real_gfx10<bits<6> op, string opName, string asmName> : 1167 VOP2be_Real_e32_gfx10<op, opName, asmName>, 1168 VOP2be_Real_e64_gfx10<op, opName, asmName>, 1169 VOP2be_Real_sdwa_gfx10<op, opName, asmName>, 1170 VOP2be_Real_dpp_gfx10<op, opName, asmName>, 1171 VOP2be_Real_dpp8_gfx10<op, opName, asmName>; 1172 1173multiclass VOP2e_Real_gfx10<bits<6> op, string opName, string asmName> : 1174 VOP2_Real_e32_gfx10<op>, 1175 VOP2_Real_e64_gfx10<op>, 1176 VOP2be_Real_sdwa_gfx10<op, opName, asmName>, 1177 VOP2be_Real_dpp_gfx10<op, opName, asmName>, 1178 VOP2be_Real_dpp8_gfx10<op, opName, asmName>; 1179 1180multiclass VOP2_Real_gfx10<bits<6> op> : 1181 VOP2_Real_e32_gfx10<op>, VOP2_Real_e64_gfx10<op>, 1182 VOP2_Real_sdwa_gfx10<op>, VOP2_Real_dpp_gfx10<op>, VOP2_Real_dpp8_gfx10<op>; 1183 1184multiclass VOP2_Real_gfx10_with_name<bits<6> op, string opName, 1185 string asmName> : 1186 VOP2_Real_e32_gfx10_with_name<op, opName, asmName>, 1187 VOP2_Real_e64_gfx10_with_name<op, opName, asmName>, 1188 VOP2_Real_sdwa_gfx10_with_name<op, opName, asmName>, 1189 VOP2_Real_dpp_gfx10_with_name<op, opName, asmName>, 1190 VOP2_Real_dpp8_gfx10_with_name<op, opName, asmName>; 1191 1192// NB: Same opcode as v_mac_legacy_f32 1193let DecoderNamespace = "GFX10_B" in 1194defm V_FMAC_LEGACY_F32 : VOP2_Real_gfx10<0x006>; 1195 1196defm V_XNOR_B32 : VOP2_Real_gfx10<0x01e>; 1197defm V_FMAC_F32 : VOP2_Real_gfx10<0x02b>; 1198defm V_FMAMK_F32 : VOP2Only_Real_MADK_gfx10<0x02c>; 1199defm V_FMAAK_F32 : VOP2Only_Real_MADK_gfx10<0x02d>; 1200defm V_ADD_F16 : VOP2_Real_gfx10<0x032>; 1201defm V_SUB_F16 : VOP2_Real_gfx10<0x033>; 1202defm V_SUBREV_F16 : VOP2_Real_gfx10<0x034>; 1203defm V_MUL_F16 : VOP2_Real_gfx10<0x035>; 1204defm V_FMAC_F16 : VOP2_Real_gfx10<0x036>; 1205defm V_FMAMK_F16 : VOP2Only_Real_MADK_gfx10<0x037>; 1206defm V_FMAAK_F16 : VOP2Only_Real_MADK_gfx10<0x038>; 1207defm V_MAX_F16 : VOP2_Real_gfx10<0x039>; 1208defm V_MIN_F16 : VOP2_Real_gfx10<0x03a>; 1209defm V_LDEXP_F16 : VOP2_Real_gfx10<0x03b>; 1210 1211let IsSingle = 1 in { 1212defm V_PK_FMAC_F16 : VOP2_Real_e32_gfx10<0x03c>; 1213} 1214 1215// VOP2 no carry-in, carry-out. 1216defm V_ADD_NC_U32 : 1217 VOP2_Real_gfx10_with_name<0x025, "V_ADD_U32", "v_add_nc_u32">; 1218defm V_SUB_NC_U32 : 1219 VOP2_Real_gfx10_with_name<0x026, "V_SUB_U32", "v_sub_nc_u32">; 1220defm V_SUBREV_NC_U32 : 1221 VOP2_Real_gfx10_with_name<0x027, "V_SUBREV_U32", "v_subrev_nc_u32">; 1222 1223// VOP2 carry-in, carry-out. 1224defm V_ADD_CO_CI_U32 : 1225 VOP2be_Real_gfx10<0x028, "V_ADDC_U32", "v_add_co_ci_u32">; 1226defm V_SUB_CO_CI_U32 : 1227 VOP2be_Real_gfx10<0x029, "V_SUBB_U32", "v_sub_co_ci_u32">; 1228defm V_SUBREV_CO_CI_U32 : 1229 VOP2be_Real_gfx10<0x02a, "V_SUBBREV_U32", "v_subrev_co_ci_u32">; 1230 1231defm V_CNDMASK_B32 : 1232 VOP2e_Real_gfx10<0x001, "V_CNDMASK_B32", "v_cndmask_b32">; 1233 1234// VOP3 only. 1235defm V_BFM_B32 : VOP3Only_Real_gfx10<0x363>; 1236defm V_BCNT_U32_B32 : VOP3Only_Real_gfx10<0x364>; 1237defm V_MBCNT_LO_U32_B32 : VOP3Only_Real_gfx10<0x365>; 1238defm V_MBCNT_HI_U32_B32 : VOP3Only_Real_gfx10<0x366>; 1239defm V_LDEXP_F32 : VOP3Only_Real_gfx10<0x362>; 1240defm V_CVT_PKNORM_I16_F32 : VOP3Only_Real_gfx10<0x368>; 1241defm V_CVT_PKNORM_U16_F32 : VOP3Only_Real_gfx10<0x369>; 1242defm V_CVT_PK_U16_U32 : VOP3Only_Real_gfx10<0x36a>; 1243defm V_CVT_PK_I16_I32 : VOP3Only_Real_gfx10<0x36b>; 1244 1245// VOP3 carry-out. 1246defm V_ADD_CO_U32 : VOP3beOnly_Real_gfx10<0x30f>; 1247defm V_SUB_CO_U32 : VOP3beOnly_Real_gfx10<0x310>; 1248defm V_SUBREV_CO_U32 : VOP3beOnly_Real_gfx10<0x319>; 1249 1250let SubtargetPredicate = isGFX10Plus in { 1251 defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx10>; 1252 1253 defm : VOP2bInstAliases< 1254 V_ADDC_U32_e32, V_ADD_CO_CI_U32_e32_gfx10, "v_add_co_ci_u32">; 1255 defm : VOP2bInstAliases< 1256 V_SUBB_U32_e32, V_SUB_CO_CI_U32_e32_gfx10, "v_sub_co_ci_u32">; 1257 defm : VOP2bInstAliases< 1258 V_SUBBREV_U32_e32, V_SUBREV_CO_CI_U32_e32_gfx10, "v_subrev_co_ci_u32">; 1259} // End SubtargetPredicate = isGFX10Plus 1260 1261//===----------------------------------------------------------------------===// 1262// GFX6, GFX7, GFX10. 1263//===----------------------------------------------------------------------===// 1264 1265class VOP2_DPPe <bits<6> op, VOP2_DPP_Pseudo ps, VOPProfile P = ps.Pfl> : 1266 VOP_DPPe <P> { 1267 bits<8> vdst; 1268 bits<8> src1; 1269 let Inst{8-0} = 0xfa; //dpp 1270 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 1271 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 1272 let Inst{30-25} = op; 1273 let Inst{31} = 0x0; //encoding 1274} 1275 1276let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in { 1277 multiclass VOP2_Lane_Real_gfx6_gfx7<bits<6> op> { 1278 def _gfx6_gfx7 : 1279 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>, 1280 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 1281 } 1282 multiclass VOP2Only_Real_MADK_gfx6_gfx7<bits<6> op> { 1283 def _gfx6_gfx7 : 1284 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>, 1285 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 1286 } 1287 multiclass VOP2_Real_e32_gfx6_gfx7<bits<6> op, string opName = NAME> { 1288 def _e32_gfx6_gfx7 : 1289 VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.SI>, 1290 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl>; 1291 } 1292 multiclass VOP2_Real_e64_gfx6_gfx7<bits<6> op, string opName = NAME> { 1293 def _e64_gfx6_gfx7 : 1294 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.SI>, 1295 VOP3e_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(opName#"_e64").Pfl>; 1296 } 1297 multiclass VOP2be_Real_e64_gfx6_gfx7<bits<6> op, string opName = NAME> { 1298 def _e64_gfx6_gfx7 : 1299 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.SI>, 1300 VOP3be_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(opName#"_e64").Pfl>; 1301 } 1302} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" 1303 1304multiclass VOP2Only_Real_MADK_gfx6_gfx7_gfx10<bits<6> op> : 1305 VOP2Only_Real_MADK_gfx6_gfx7<op>, VOP2Only_Real_MADK_gfx10<op>; 1306 1307multiclass VOP2_Real_gfx6_gfx7<bits<6> op> : 1308 VOP2_Real_e32_gfx6_gfx7<op>, VOP2_Real_e64_gfx6_gfx7<op>; 1309 1310multiclass VOP2_Real_gfx6_gfx7_gfx10<bits<6> op> : 1311 VOP2_Real_gfx6_gfx7<op>, VOP2_Real_gfx10<op>; 1312 1313multiclass VOP2be_Real_gfx6_gfx7<bits<6> op> : 1314 VOP2_Real_e32_gfx6_gfx7<op>, VOP2be_Real_e64_gfx6_gfx7<op>; 1315 1316multiclass VOP2be_Real_gfx6_gfx7_with_name<bits<6> op, 1317 string opName, string asmName> { 1318 defvar ps32 = !cast<VOP2_Pseudo>(opName#"_e32"); 1319 defvar ps64 = !cast<VOP3_Pseudo>(opName#"_e64"); 1320 1321 let AsmString = asmName # ps32.AsmOperands in { 1322 defm "" : VOP2_Real_e32_gfx6_gfx7<op, opName>; 1323 } 1324 1325 let AsmString = asmName # ps64.AsmOperands in { 1326 defm "" : VOP2be_Real_e64_gfx6_gfx7<op, opName>; 1327 } 1328} 1329 1330defm V_CNDMASK_B32 : VOP2_Real_gfx6_gfx7<0x000>; 1331defm V_MIN_LEGACY_F32 : VOP2_Real_gfx6_gfx7<0x00d>; 1332defm V_MAX_LEGACY_F32 : VOP2_Real_gfx6_gfx7<0x00e>; 1333defm V_LSHR_B32 : VOP2_Real_gfx6_gfx7<0x015>; 1334defm V_ASHR_I32 : VOP2_Real_gfx6_gfx7<0x017>; 1335defm V_LSHL_B32 : VOP2_Real_gfx6_gfx7<0x019>; 1336defm V_BFM_B32 : VOP2_Real_gfx6_gfx7<0x01e>; 1337defm V_BCNT_U32_B32 : VOP2_Real_gfx6_gfx7<0x022>; 1338defm V_MBCNT_LO_U32_B32 : VOP2_Real_gfx6_gfx7<0x023>; 1339defm V_MBCNT_HI_U32_B32 : VOP2_Real_gfx6_gfx7<0x024>; 1340defm V_LDEXP_F32 : VOP2_Real_gfx6_gfx7<0x02b>; 1341defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_gfx6_gfx7<0x02c>; 1342defm V_CVT_PKNORM_I16_F32 : VOP2_Real_gfx6_gfx7<0x02d>; 1343defm V_CVT_PKNORM_U16_F32 : VOP2_Real_gfx6_gfx7<0x02e>; 1344defm V_CVT_PK_U16_U32 : VOP2_Real_gfx6_gfx7<0x030>; 1345defm V_CVT_PK_I16_I32 : VOP2_Real_gfx6_gfx7<0x031>; 1346 1347// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in 1348// VI, but the VI instructions behave the same as the SI versions. 1349defm V_ADD_I32 : VOP2be_Real_gfx6_gfx7_with_name<0x025, "V_ADD_CO_U32", "v_add_i32">; 1350defm V_SUB_I32 : VOP2be_Real_gfx6_gfx7_with_name<0x026, "V_SUB_CO_U32", "v_sub_i32">; 1351defm V_SUBREV_I32 : VOP2be_Real_gfx6_gfx7_with_name<0x027, "V_SUBREV_CO_U32", "v_subrev_i32">; 1352defm V_ADDC_U32 : VOP2be_Real_gfx6_gfx7<0x028>; 1353defm V_SUBB_U32 : VOP2be_Real_gfx6_gfx7<0x029>; 1354defm V_SUBBREV_U32 : VOP2be_Real_gfx6_gfx7<0x02a>; 1355 1356defm V_READLANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x001>; 1357 1358let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in { 1359 defm V_WRITELANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x002>; 1360} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) 1361 1362let SubtargetPredicate = isGFX6GFX7 in { 1363 defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx6_gfx7>; 1364 defm : VOP2eInstAliases<V_ADD_CO_U32_e32, V_ADD_I32_e32_gfx6_gfx7>; 1365 defm : VOP2eInstAliases<V_SUB_CO_U32_e32, V_SUB_I32_e32_gfx6_gfx7>; 1366 defm : VOP2eInstAliases<V_SUBREV_CO_U32_e32, V_SUBREV_I32_e32_gfx6_gfx7>; 1367 1368 def : VOP2e64InstAlias<V_ADD_CO_U32_e64, V_ADD_I32_e64_gfx6_gfx7>; 1369 def : VOP2e64InstAlias<V_SUB_CO_U32_e64, V_SUB_I32_e64_gfx6_gfx7>; 1370 def : VOP2e64InstAlias<V_SUBREV_CO_U32_e64, V_SUBREV_I32_e64_gfx6_gfx7>; 1371} // End SubtargetPredicate = isGFX6GFX7 1372 1373defm V_ADD_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x003>; 1374defm V_SUB_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x004>; 1375defm V_SUBREV_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x005>; 1376defm V_MAC_LEGACY_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x006>; 1377defm V_MUL_LEGACY_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x007>; 1378defm V_MUL_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x008>; 1379defm V_MUL_I32_I24 : VOP2_Real_gfx6_gfx7_gfx10<0x009>; 1380defm V_MUL_HI_I32_I24 : VOP2_Real_gfx6_gfx7_gfx10<0x00a>; 1381defm V_MUL_U32_U24 : VOP2_Real_gfx6_gfx7_gfx10<0x00b>; 1382defm V_MUL_HI_U32_U24 : VOP2_Real_gfx6_gfx7_gfx10<0x00c>; 1383defm V_MIN_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x00f>; 1384defm V_MAX_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x010>; 1385defm V_MIN_I32 : VOP2_Real_gfx6_gfx7_gfx10<0x011>; 1386defm V_MAX_I32 : VOP2_Real_gfx6_gfx7_gfx10<0x012>; 1387defm V_MIN_U32 : VOP2_Real_gfx6_gfx7_gfx10<0x013>; 1388defm V_MAX_U32 : VOP2_Real_gfx6_gfx7_gfx10<0x014>; 1389defm V_LSHRREV_B32 : VOP2_Real_gfx6_gfx7_gfx10<0x016>; 1390defm V_ASHRREV_I32 : VOP2_Real_gfx6_gfx7_gfx10<0x018>; 1391defm V_LSHLREV_B32 : VOP2_Real_gfx6_gfx7_gfx10<0x01a>; 1392defm V_AND_B32 : VOP2_Real_gfx6_gfx7_gfx10<0x01b>; 1393defm V_OR_B32 : VOP2_Real_gfx6_gfx7_gfx10<0x01c>; 1394defm V_XOR_B32 : VOP2_Real_gfx6_gfx7_gfx10<0x01d>; 1395defm V_MAC_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x01f>; 1396defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x02f>; 1397defm V_MADMK_F32 : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x020>; 1398defm V_MADAK_F32 : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x021>; 1399 1400//===----------------------------------------------------------------------===// 1401// GFX8, GFX9 (VI). 1402//===----------------------------------------------------------------------===// 1403 1404let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in { 1405 1406multiclass VOP2_Real_MADK_vi <bits<6> op> { 1407 def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>, 1408 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 1409} 1410 1411multiclass VOP2_Real_e32_vi <bits<6> op> { 1412 def _e32_vi : 1413 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>, 1414 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 1415} 1416 1417multiclass VOP2_Real_e64_vi <bits<10> op> { 1418 def _e64_vi : 1419 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1420 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1421} 1422 1423multiclass VOP2_Real_e64only_vi <bits<10> op> { 1424 def _e64_vi : 1425 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1426 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1427 let IsSingle = 1; 1428 } 1429} 1430 1431multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> : 1432 VOP2_Real_e32_vi<op>, 1433 VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>; 1434 1435} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" 1436 1437multiclass VOP2_SDWA_Real <bits<6> op> { 1438 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA>.ret in 1439 def _sdwa_vi : 1440 VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 1441 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 1442} 1443 1444multiclass VOP2_SDWA9_Real <bits<6> op> { 1445 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in 1446 def _sdwa_gfx9 : 1447 VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 1448 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 1449} 1450 1451let AssemblerPredicate = isGFX8Only in { 1452 1453multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName> { 1454 def _e32_vi : 1455 VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.VI>, 1456 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> { 1457 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32"); 1458 let AsmString = AsmName # ps.AsmOperands; 1459 let DecoderNamespace = "GFX8"; 1460 } 1461 def _e64_vi : 1462 VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.VI>, 1463 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> { 1464 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64"); 1465 let AsmString = AsmName # ps.AsmOperands; 1466 let DecoderNamespace = "GFX8"; 1467 } 1468 foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA>.ret in 1469 def _sdwa_vi : 1470 VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>, 1471 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> { 1472 VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa"); 1473 let AsmString = AsmName # ps.AsmOperands; 1474 } 1475 foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in 1476 def _dpp_vi : 1477 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.VI>, 1478 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> { 1479 VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp"); 1480 let AsmString = AsmName # ps.AsmOperands; 1481 } 1482} 1483} 1484 1485let AssemblerPredicate = isGFX9Only in { 1486 1487multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> { 1488 def _e32_gfx9 : 1489 VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.GFX9>, 1490 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> { 1491 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32"); 1492 let AsmString = AsmName # ps.AsmOperands; 1493 let DecoderNamespace = "GFX9"; 1494 } 1495 def _e64_gfx9 : 1496 VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>, 1497 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> { 1498 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64"); 1499 let AsmString = AsmName # ps.AsmOperands; 1500 let DecoderNamespace = "GFX9"; 1501 } 1502 foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA9>.ret in 1503 def _sdwa_gfx9 : 1504 VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>, 1505 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> { 1506 VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa"); 1507 let AsmString = AsmName # ps.AsmOperands; 1508 } 1509 foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in 1510 def _dpp_gfx9 : 1511 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.GFX9>, 1512 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> { 1513 VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp"); 1514 let AsmString = AsmName # ps.AsmOperands; 1515 let DecoderNamespace = "SDWA9"; 1516 } 1517} 1518 1519multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> { 1520 def _e32_gfx9 : 1521 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX9>, 1522 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>{ 1523 let DecoderNamespace = "GFX9"; 1524 } 1525 def _e64_gfx9 : 1526 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>, 1527 VOP3e_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1528 let DecoderNamespace = "GFX9"; 1529 } 1530 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in 1531 def _sdwa_gfx9 : 1532 VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 1533 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> { 1534 } 1535 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in 1536 def _dpp_gfx9 : 1537 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>, 1538 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> { 1539 let DecoderNamespace = "SDWA9"; 1540 } 1541} 1542 1543} // AssemblerPredicate = isGFX9Only 1544 1545multiclass VOP2_Real_e32e64_vi <bits<6> op> : 1546 Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> { 1547 1548 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in 1549 def _dpp_vi : 1550 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.VI>, 1551 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>; 1552} 1553 1554defm V_CNDMASK_B32 : VOP2_Real_e32e64_vi <0x0>; 1555defm V_ADD_F32 : VOP2_Real_e32e64_vi <0x1>; 1556defm V_SUB_F32 : VOP2_Real_e32e64_vi <0x2>; 1557defm V_SUBREV_F32 : VOP2_Real_e32e64_vi <0x3>; 1558let AssemblerPredicate = isGCN3ExcludingGFX90A in 1559defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_vi <0x4>; 1560defm V_MUL_F32 : VOP2_Real_e32e64_vi <0x5>; 1561defm V_MUL_I32_I24 : VOP2_Real_e32e64_vi <0x6>; 1562defm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_vi <0x7>; 1563defm V_MUL_U32_U24 : VOP2_Real_e32e64_vi <0x8>; 1564defm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_vi <0x9>; 1565defm V_MIN_F32 : VOP2_Real_e32e64_vi <0xa>; 1566defm V_MAX_F32 : VOP2_Real_e32e64_vi <0xb>; 1567defm V_MIN_I32 : VOP2_Real_e32e64_vi <0xc>; 1568defm V_MAX_I32 : VOP2_Real_e32e64_vi <0xd>; 1569defm V_MIN_U32 : VOP2_Real_e32e64_vi <0xe>; 1570defm V_MAX_U32 : VOP2_Real_e32e64_vi <0xf>; 1571defm V_LSHRREV_B32 : VOP2_Real_e32e64_vi <0x10>; 1572defm V_ASHRREV_I32 : VOP2_Real_e32e64_vi <0x11>; 1573defm V_LSHLREV_B32 : VOP2_Real_e32e64_vi <0x12>; 1574defm V_AND_B32 : VOP2_Real_e32e64_vi <0x13>; 1575defm V_OR_B32 : VOP2_Real_e32e64_vi <0x14>; 1576defm V_XOR_B32 : VOP2_Real_e32e64_vi <0x15>; 1577defm V_MAC_F32 : VOP2_Real_e32e64_vi <0x16>; 1578defm V_MADMK_F32 : VOP2_Real_MADK_vi <0x17>; 1579defm V_MADAK_F32 : VOP2_Real_MADK_vi <0x18>; 1580 1581defm V_ADD_U32 : VOP2be_Real_e32e64_vi_only <0x19, "V_ADD_CO_U32", "v_add_u32">; 1582defm V_SUB_U32 : VOP2be_Real_e32e64_vi_only <0x1a, "V_SUB_CO_U32", "v_sub_u32">; 1583defm V_SUBREV_U32 : VOP2be_Real_e32e64_vi_only <0x1b, "V_SUBREV_CO_U32", "v_subrev_u32">; 1584defm V_ADDC_U32 : VOP2be_Real_e32e64_vi_only <0x1c, "V_ADDC_U32", "v_addc_u32">; 1585defm V_SUBB_U32 : VOP2be_Real_e32e64_vi_only <0x1d, "V_SUBB_U32", "v_subb_u32">; 1586defm V_SUBBREV_U32 : VOP2be_Real_e32e64_vi_only <0x1e, "V_SUBBREV_U32", "v_subbrev_u32">; 1587 1588defm V_ADD_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x19, "V_ADD_CO_U32", "v_add_co_u32">; 1589defm V_SUB_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1a, "V_SUB_CO_U32", "v_sub_co_u32">; 1590defm V_SUBREV_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1b, "V_SUBREV_CO_U32", "v_subrev_co_u32">; 1591defm V_ADDC_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1c, "V_ADDC_U32", "v_addc_co_u32">; 1592defm V_SUBB_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1d, "V_SUBB_U32", "v_subb_co_u32">; 1593defm V_SUBBREV_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1e, "V_SUBBREV_U32", "v_subbrev_co_u32">; 1594 1595defm V_ADD_U32 : VOP2_Real_e32e64_gfx9 <0x34>; 1596defm V_SUB_U32 : VOP2_Real_e32e64_gfx9 <0x35>; 1597defm V_SUBREV_U32 : VOP2_Real_e32e64_gfx9 <0x36>; 1598 1599defm V_BFM_B32 : VOP2_Real_e64only_vi <0x293>; 1600defm V_BCNT_U32_B32 : VOP2_Real_e64only_vi <0x28b>; 1601defm V_MBCNT_LO_U32_B32 : VOP2_Real_e64only_vi <0x28c>; 1602defm V_MBCNT_HI_U32_B32 : VOP2_Real_e64only_vi <0x28d>; 1603defm V_LDEXP_F32 : VOP2_Real_e64only_vi <0x288>; 1604defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64only_vi <0x1f0>; 1605defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64only_vi <0x294>; 1606defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64only_vi <0x295>; 1607defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e64only_vi <0x296>; 1608defm V_CVT_PK_U16_U32 : VOP2_Real_e64only_vi <0x297>; 1609defm V_CVT_PK_I16_I32 : VOP2_Real_e64only_vi <0x298>; 1610 1611defm V_ADD_F16 : VOP2_Real_e32e64_vi <0x1f>; 1612defm V_SUB_F16 : VOP2_Real_e32e64_vi <0x20>; 1613defm V_SUBREV_F16 : VOP2_Real_e32e64_vi <0x21>; 1614defm V_MUL_F16 : VOP2_Real_e32e64_vi <0x22>; 1615defm V_MAC_F16 : VOP2_Real_e32e64_vi <0x23>; 1616defm V_MADMK_F16 : VOP2_Real_MADK_vi <0x24>; 1617defm V_MADAK_F16 : VOP2_Real_MADK_vi <0x25>; 1618defm V_ADD_U16 : VOP2_Real_e32e64_vi <0x26>; 1619defm V_SUB_U16 : VOP2_Real_e32e64_vi <0x27>; 1620defm V_SUBREV_U16 : VOP2_Real_e32e64_vi <0x28>; 1621defm V_MUL_LO_U16 : VOP2_Real_e32e64_vi <0x29>; 1622defm V_LSHLREV_B16 : VOP2_Real_e32e64_vi <0x2a>; 1623defm V_LSHRREV_B16 : VOP2_Real_e32e64_vi <0x2b>; 1624defm V_ASHRREV_I16 : VOP2_Real_e32e64_vi <0x2c>; 1625defm V_MAX_F16 : VOP2_Real_e32e64_vi <0x2d>; 1626defm V_MIN_F16 : VOP2_Real_e32e64_vi <0x2e>; 1627defm V_MAX_U16 : VOP2_Real_e32e64_vi <0x2f>; 1628defm V_MAX_I16 : VOP2_Real_e32e64_vi <0x30>; 1629defm V_MIN_U16 : VOP2_Real_e32e64_vi <0x31>; 1630defm V_MIN_I16 : VOP2_Real_e32e64_vi <0x32>; 1631defm V_LDEXP_F16 : VOP2_Real_e32e64_vi <0x33>; 1632 1633let SubtargetPredicate = isGFX8GFX9 in { 1634 1635// Aliases to simplify matching of floating-point instructions that 1636// are VOP2 on SI and VOP3 on VI. 1637class SI2_VI3Alias <string name, VOP3_Real inst> : InstAlias < 1638 name#" $dst, $src0, $src1", 1639 !if(inst.Pfl.HasOMod, 1640 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0), 1641 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0)) 1642>, PredicateControl { 1643 let UseInstAsmMatchConverter = 0; 1644 let AsmVariantName = AMDGPUAsmVariants.VOP3; 1645} 1646 1647def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>; 1648def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>; 1649def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>; 1650def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>; 1651def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>; 1652 1653defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_vi>; 1654 1655} // End SubtargetPredicate = isGFX8GFX9 1656 1657let SubtargetPredicate = isGFX9Only in { 1658 1659defm : VOP2bInstAliases<V_ADD_U32_e32, V_ADD_CO_U32_e32_gfx9, "v_add_co_u32">; 1660defm : VOP2bInstAliases<V_ADDC_U32_e32, V_ADDC_CO_U32_e32_gfx9, "v_addc_co_u32">; 1661defm : VOP2bInstAliases<V_SUB_U32_e32, V_SUB_CO_U32_e32_gfx9, "v_sub_co_u32">; 1662defm : VOP2bInstAliases<V_SUBB_U32_e32, V_SUBB_CO_U32_e32_gfx9, "v_subb_co_u32">; 1663defm : VOP2bInstAliases<V_SUBREV_U32_e32, V_SUBREV_CO_U32_e32_gfx9, "v_subrev_co_u32">; 1664defm : VOP2bInstAliases<V_SUBBREV_U32_e32, V_SUBBREV_CO_U32_e32_gfx9, "v_subbrev_co_u32">; 1665 1666} // End SubtargetPredicate = isGFX9Only 1667 1668let SubtargetPredicate = HasDLInsts in { 1669 1670defm V_FMAC_F32 : VOP2_Real_e32e64_vi <0x3b>; 1671defm V_XNOR_B32 : VOP2_Real_e32e64_vi <0x3d>; 1672 1673} // End SubtargetPredicate = HasDLInsts 1674 1675let AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A" in { 1676 multiclass VOP2_Real_e32_gfx90a <bits<6> op> { 1677 def _e32_gfx90a : 1678 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX90A>, 1679 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 1680 } 1681 1682 multiclass VOP2_Real_e64_gfx90a <bits<10> op> { 1683 def _e64_gfx90a : 1684 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX90A>, 1685 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1686 } 1687 1688 multiclass Base_VOP2_Real_e32e64_gfx90a <bits<6> op> : 1689 VOP2_Real_e32_gfx90a<op>, 1690 VOP2_Real_e64_gfx90a<{0, 1, 0, 0, op{5-0}}>; 1691 1692 multiclass VOP2_Real_e32e64_gfx90a <bits<6> op> : 1693 Base_VOP2_Real_e32e64_gfx90a<op> { 1694 1695 foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in 1696 def _dpp_gfx90a : 1697 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX90A>, 1698 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> { 1699 let DecoderNamespace = "SDWA9"; 1700 } 1701 } 1702} // End AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A" 1703 1704let SubtargetPredicate = isGFX90APlus in { 1705 defm V_FMAC_F64 : VOP2_Real_e32e64_gfx90a <0x4>; 1706 let IsSingle = 1 in { 1707 defm V_MUL_LEGACY_F32 : VOP2_Real_e64_gfx90a <0x2a1>; 1708 } 1709} // End SubtargetPredicate = isGFX90APlus 1710 1711multiclass VOP2_Real_DOT_ACC_gfx9<bits<6> op> : VOP2_Real_e32_vi<op> { 1712 def _dpp_vi : VOP2_DPP<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>; 1713} 1714 1715multiclass VOP2_Real_DOT_ACC_gfx10<bits<6> op> : 1716 VOP2_Real_e32_gfx10<op>, 1717 VOP2_Real_dpp_gfx10<op>, 1718 VOP2_Real_dpp8_gfx10<op>; 1719 1720let SubtargetPredicate = HasDot5Insts in { 1721 defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx9<0x37>; 1722 // NB: Opcode conflicts with V_DOT8C_I32_I4 1723 // This opcode exists in gfx 10.1* only 1724 defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx10<0x02>; 1725} 1726 1727let SubtargetPredicate = HasDot6Insts in { 1728 defm V_DOT4C_I32_I8 : VOP2_Real_DOT_ACC_gfx9<0x39>; 1729 defm V_DOT4C_I32_I8 : VOP2_Real_DOT_ACC_gfx10<0x0d>; 1730} 1731 1732let SubtargetPredicate = HasDot4Insts in { 1733 defm V_DOT2C_I32_I16 : VOP2_Real_DOT_ACC_gfx9<0x38>; 1734} 1735let SubtargetPredicate = HasDot3Insts in { 1736 defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx9<0x3a>; 1737} 1738 1739let SubtargetPredicate = HasPkFmacF16Inst in { 1740defm V_PK_FMAC_F16 : VOP2_Real_e32_vi<0x3c>; 1741} // End SubtargetPredicate = HasPkFmacF16Inst 1742 1743let SubtargetPredicate = HasDot3Insts in { 1744 // NB: Opcode conflicts with V_DOT2C_F32_F16 1745 let DecoderNamespace = "GFX10_B" in 1746 defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx10<0x02>; 1747} 1748