1//===-- VOP2Instructions.td - Vector Instruction Definitions --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// VOP2 Classes
11//===----------------------------------------------------------------------===//
12
13class VOP2e <bits<6> op, VOPProfile P> : Enc32 {
14  bits<8> vdst;
15  bits<9> src0;
16  bits<8> src1;
17
18  let Inst{8-0}   = !if(P.HasSrc0, src0, 0);
19  let Inst{16-9}  = !if(P.HasSrc1, src1, 0);
20  let Inst{24-17} = !if(P.EmitDst, vdst, 0);
21  let Inst{30-25} = op;
22  let Inst{31}    = 0x0; //encoding
23}
24
25class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 {
26  bits<8>  vdst;
27  bits<9>  src0;
28  bits<8>  src1;
29  bits<32> imm;
30
31  let Inst{8-0}   = !if(P.HasSrc0, src0, 0);
32  let Inst{16-9}  = !if(P.HasSrc1, src1, 0);
33  let Inst{24-17} = !if(P.EmitDst, vdst, 0);
34  let Inst{30-25} = op;
35  let Inst{31}    = 0x0; // encoding
36  let Inst{63-32} = imm;
37}
38
39class VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> {
40  bits<8> vdst;
41  bits<8> src1;
42
43  let Inst{8-0}   = 0xf9; // sdwa
44  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
45  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
46  let Inst{30-25} = op;
47  let Inst{31}    = 0x0; // encoding
48}
49
50class VOP2_SDWA9Ae <bits<6> op, VOPProfile P> : VOP_SDWA9Ae <P> {
51  bits<8> vdst;
52  bits<9> src1;
53
54  let Inst{8-0}   = 0xf9; // sdwa
55  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
56  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
57  let Inst{30-25} = op;
58  let Inst{31}    = 0x0; // encoding
59  let Inst{63}    = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr
60}
61
62class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> :
63  VOP_Pseudo <opName, suffix, P, P.Outs32, P.Ins32, "", pattern> {
64
65  let AsmOperands = P.Asm32;
66
67  let Size = 4;
68  let mayLoad = 0;
69  let mayStore = 0;
70  let hasSideEffects = 0;
71
72  let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
73
74  let mayRaiseFPException = ReadsModeReg;
75
76  let VOP2 = 1;
77  let VALU = 1;
78  let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
79
80  let AsmVariantName = AMDGPUAsmVariants.Default;
81}
82
83class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> :
84  VOP_Real <ps>,
85  InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
86  SIMCInstr <ps.PseudoInstr, EncodingFamily> {
87
88  let isPseudo = 0;
89  let isCodeGenOnly = 0;
90
91  let Constraints     = ps.Constraints;
92  let DisableEncoding = ps.DisableEncoding;
93
94  // copy relevant pseudo op flags
95  let SubtargetPredicate = ps.SubtargetPredicate;
96  let OtherPredicates    = ps.OtherPredicates;
97  let AsmMatchConverter  = ps.AsmMatchConverter;
98  let AsmVariantName     = ps.AsmVariantName;
99  let Constraints        = ps.Constraints;
100  let DisableEncoding    = ps.DisableEncoding;
101  let TSFlags            = ps.TSFlags;
102  let UseNamedOperandTable = ps.UseNamedOperandTable;
103  let Uses                 = ps.Uses;
104  let Defs                 = ps.Defs;
105  let SchedRW              = ps.SchedRW;
106}
107
108class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
109  VOP_SDWA_Pseudo <OpName, P, pattern> {
110  let AsmMatchConverter = "cvtSdwaVOP2";
111}
112
113class VOP2_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
114  VOP_DPP_Pseudo <OpName, P, pattern> {
115}
116
117
118class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies {
119  list<dag> ret = !if(P.HasModifiers,
120    [(set P.DstVT:$vdst,
121      (node (P.Src0VT
122              !if(P.HasOMod,
123                  (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
124                  (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
125            (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
126    [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
127}
128
129multiclass VOP2Inst_e32<string opName,
130                        VOPProfile P,
131                        SDPatternOperator node = null_frag,
132                        string revOp = opName,
133                        bit GFX9Renamed = 0> {
134  let renamedInGFX9 = GFX9Renamed in {
135    def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
136               Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
137  } // End renamedInGFX9 = GFX9Renamed
138}
139
140multiclass VOP2Inst_e64<string opName,
141                        VOPProfile P,
142                        SDPatternOperator node = null_frag,
143                        string revOp = opName,
144                        bit GFX9Renamed = 0> {
145  let renamedInGFX9 = GFX9Renamed in {
146    def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
147               Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
148  } // End renamedInGFX9 = GFX9Renamed
149}
150
151multiclass VOP2Inst_sdwa<string opName,
152                         VOPProfile P,
153                         SDPatternOperator node = null_frag,
154                         string revOp = opName,
155                         bit GFX9Renamed = 0> {
156  let renamedInGFX9 = GFX9Renamed in {
157    foreach _ = BoolToList<P.HasExtSDWA>.ret in
158      def _sdwa : VOP2_SDWA_Pseudo <opName, P>;
159  } // End renamedInGFX9 = GFX9Renamed
160}
161
162multiclass VOP2Inst<string opName,
163                    VOPProfile P,
164                    SDPatternOperator node = null_frag,
165                    string revOp = opName,
166                    bit GFX9Renamed = 0> :
167    VOP2Inst_e32<opName, P, node, revOp, GFX9Renamed>,
168    VOP2Inst_e64<opName, P, node, revOp, GFX9Renamed>,
169    VOP2Inst_sdwa<opName, P, node, revOp, GFX9Renamed> {
170  let renamedInGFX9 = GFX9Renamed in {
171    foreach _ = BoolToList<P.HasExtDPP>.ret in
172      def _dpp  : VOP2_DPP_Pseudo <opName, P>;
173  }
174}
175
176multiclass VOP2bInst <string opName,
177                      VOPProfile P,
178                      SDPatternOperator node = null_frag,
179                      string revOp = opName,
180                      bit GFX9Renamed = 0,
181                      bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
182  let renamedInGFX9 = GFX9Renamed in {
183    let SchedRW = [Write32Bit, WriteSALU] in {
184      let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
185        def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
186                   Commutable_REV<revOp#"_e32", !eq(revOp, opName)> {
187          let usesCustomInserter = !eq(P.NumSrcArgs, 2);
188        }
189
190        foreach _ = BoolToList<P.HasExtSDWA>.ret in
191          def _sdwa  : VOP2_SDWA_Pseudo <opName, P> {
192            let AsmMatchConverter = "cvtSdwaVOP2b";
193          }
194        foreach _ = BoolToList<P.HasExtDPP>.ret in
195          def _dpp  : VOP2_DPP_Pseudo <opName, P>;
196      }
197
198      def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
199                 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
200    }
201  }
202}
203
204class VOP2bInstAlias <VOP2_Pseudo ps, Instruction inst,
205                      string OpName, string opnd> :
206  InstAlias <OpName#" "#!subst("vcc", opnd, ps.Pfl.Asm32),
207             (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
208                   ps.Pfl.Src1RC32:$src1)>,
209  PredicateControl {
210}
211
212multiclass VOP2bInstAliases<VOP2_Pseudo ps, VOP2_Real inst, string OpName> {
213  let WaveSizePredicate = isWave32 in {
214    def : VOP2bInstAlias<ps, inst, OpName, "vcc_lo">;
215  }
216  let WaveSizePredicate = isWave64 in {
217    def : VOP2bInstAlias<ps, inst, OpName, "vcc">;
218  }
219}
220
221multiclass VOP2eInst <string opName,
222                      VOPProfile P,
223                      SDPatternOperator node = null_frag,
224                      string revOp = opName,
225                      bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
226
227  let SchedRW = [Write32Bit] in {
228    let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in {
229      def _e32 : VOP2_Pseudo <opName, P>,
230                 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
231
232      foreach _ = BoolToList<P.HasExtSDWA>.ret in
233        def _sdwa : VOP2_SDWA_Pseudo <opName, P> {
234          let AsmMatchConverter = "cvtSdwaVOP2e";
235        }
236
237      foreach _ = BoolToList<P.HasExtDPP>.ret in
238        def _dpp  : VOP2_DPP_Pseudo <opName, P>;
239    }
240
241    def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
242               Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
243  }
244}
245
246class VOP2eInstAlias <VOP2_Pseudo ps, Instruction inst, string opnd = ""> :
247  InstAlias <ps.OpName#" "#ps.Pfl.Asm32#", "#opnd,
248             (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
249                   ps.Pfl.Src1RC32:$src1)>, PredicateControl;
250
251class VOP2e64InstAlias <VOP3_Pseudo ps, Instruction inst> :
252  InstAlias <ps.OpName#" "#ps.Pfl.Asm64,
253             (inst ps.Pfl.DstRC:$vdst, VOPDstS64orS32:$sdst,
254                   ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, clampmod:$clamp)>,
255  PredicateControl;
256
257multiclass VOP2eInstAliases<VOP2_Pseudo ps, VOP2_Real inst> {
258  let WaveSizePredicate = isWave32 in {
259    def : VOP2eInstAlias<ps, inst, "vcc_lo">;
260  }
261  let WaveSizePredicate = isWave64 in {
262    def : VOP2eInstAlias<ps, inst, "vcc">;
263  }
264}
265
266class VOP_MADAK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
267  field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
268  field dag Ins32 = !if(!eq(vt.Size, 32),
269                        (ins VCSrc_f32:$src0, VGPR_32:$src1, ImmOpType:$imm),
270                        (ins VCSrc_f16:$src0, VGPR_32:$src1, ImmOpType:$imm));
271  field bit HasExt = 0;
272  let IsSingle = 1;
273
274  field string Asm32 = "$vdst, $src0, $src1, $imm";
275}
276
277def VOP_MADAK_F16 : VOP_MADAK <f16>;
278def VOP_MADAK_F32 : VOP_MADAK <f32>;
279
280class VOP_MADMK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
281  field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
282  field dag Ins32 = (ins VCSrc_f32:$src0, ImmOpType:$imm, VGPR_32:$src1);
283  field bit HasExt = 0;
284  let IsSingle = 1;
285
286  field string Asm32 = "$vdst, $src0, $imm, $src1";
287}
288
289def VOP_MADMK_F16 : VOP_MADMK <f16>;
290def VOP_MADMK_F32 : VOP_MADMK <f32>;
291
292class getRegisterOperandForVT<ValueType VT> {
293  RegisterOperand ret = RegisterOperand<getVregSrcForVT<VT>.ret>;
294}
295
296// FIXME: Remove src2_modifiers. It isn't used, so is wasting memory
297// and processing time but it makes it easier to convert to mad.
298class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, vt0]> {
299  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, getVregSrcForVT<Src2VT>.ret:$src2);
300  let Ins64 = getIns64<Src0RC64, Src1RC64, getRegisterOperandForVT<Src2VT>.ret, 3,
301                       0, HasModifiers, HasModifiers, HasOMod,
302                       Src0Mod, Src1Mod, Src2Mod>.ret;
303  let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
304                    Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
305                    getVregSrcForVT<Src2VT>.ret:$src2, // stub argument
306                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
307                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
308  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
309  let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
310                     Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
311                     getVregSrcForVT<Src2VT>.ret:$src2, // stub argument
312                     dpp8:$dpp8, FI:$fi);
313  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
314                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
315                     getVregSrcForVT<Src2VT>.ret:$src2, // stub argument
316                     clampmod:$clamp, omod:$omod,
317                     dst_sel:$dst_sel, dst_unused:$dst_unused,
318                     src0_sel:$src0_sel, src1_sel:$src1_sel);
319  let Asm32 = getAsm32<1, 2, vt0>.ret;
320  let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, vt0>.ret;
321  let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt0>.ret;
322  let AsmDPP16 = getAsmDPP16<1, 2, HasModifiers, vt0>.ret;
323  let AsmDPP8 = getAsmDPP8<1, 2, 0, vt0>.ret;
324  let AsmSDWA = getAsmSDWA<1, 2, vt0>.ret;
325  let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt0>.ret;
326  let HasSrc2 = 0;
327  let HasSrc2Mods = 0;
328
329  let HasExt = 1;
330  let HasExtDPP = 1;
331  let HasExtSDWA = 1;
332  let HasExtSDWA9 = 0;
333  let TieRegDPP = "$src2";
334}
335
336def VOP_MAC_F16 : VOP_MAC <f16>;
337def VOP_MAC_F32 : VOP_MAC <f32>;
338let HasExtDPP = 0 in
339def VOP_MAC_LEGACY_F32 : VOP_MAC <f32>;
340let HasExtSDWA = 0, HasExt64BitDPP = 1 in
341def VOP_MAC_F64 : VOP_MAC <f64>;
342
343class VOP_DOT_ACC<ValueType vt0, ValueType vt1> : VOP_MAC<vt0, vt1> {
344  let HasClamp = 0;
345  let HasExtSDWA = 0;
346  let HasOpSel = 0;
347  let IsPacked = 0;
348}
349
350def VOP_DOT_ACC_F32_V2F16 : VOP_DOT_ACC<f32, v2f16> {
351  let Src0ModDPP = FPVRegInputMods;
352  let Src1ModDPP = FPVRegInputMods;
353}
354
355def VOP_DOT_ACC_I32_I32   : VOP_DOT_ACC<i32, i32> {
356  let HasSrc0Mods = 1;
357  let HasSrc1Mods = 1;
358}
359
360// Write out to vcc or arbitrary SGPR.
361def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], 0, /*EnableClamp=*/1> {
362  let Asm32 = "$vdst, vcc, $src0, $src1";
363  let Asm64 = "$vdst, $sdst, $src0, $src1$clamp";
364  let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
365  let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
366  let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
367  let AsmDPP8 = "$vdst, vcc, $src0, $src1 $dpp8$fi";
368  let AsmDPP16 = AsmDPP#"$fi";
369  let Outs32 = (outs DstRC:$vdst);
370  let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
371}
372
373// Write out to vcc or arbitrary SGPR and read in from vcc or
374// arbitrary SGPR.
375def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], 0, /*EnableClamp=*/1> {
376  let Asm32 = "$vdst, vcc, $src0, $src1, vcc";
377  let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
378  let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
379  let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
380  let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
381  let AsmDPP8 = "$vdst, vcc, $src0, $src1, vcc $dpp8$fi";
382  let AsmDPP16 = AsmDPP#"$fi";
383  let Outs32 = (outs DstRC:$vdst);
384  let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
385
386  // Suppress src2 implied by type since the 32-bit encoding uses an
387  // implicit VCC use.
388  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
389
390  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
391                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
392                     clampmod:$clamp,
393                     dst_sel:$dst_sel, dst_unused:$dst_unused,
394                     src0_sel:$src0_sel, src1_sel:$src1_sel);
395
396  let InsDPP = (ins DstRCDPP:$old,
397                    Src0DPP:$src0,
398                    Src1DPP:$src1,
399                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
400                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
401  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
402
403  let HasExt = 1;
404  let HasExtDPP = 1;
405  let HasExtSDWA = 1;
406  let HasExtSDWA9 = 1;
407}
408
409// Read in from vcc or arbitrary SGPR.
410def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], /*EnableF32SrcMods=*/1> {
411  let Asm32 = "$vdst, $src0, $src1";
412  let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2";
413  let AsmSDWA = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
414  let AsmSDWA9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
415  let AsmDPP = "$vdst, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
416  let AsmDPP8 = "$vdst, $src0, $src1, vcc $dpp8$fi";
417  let AsmDPP16 = AsmDPP#"$fi";
418
419  let Outs32 = (outs DstRC:$vdst);
420  let Outs64 = (outs DstRC:$vdst);
421
422  // Suppress src2 implied by type since the 32-bit encoding uses an
423  // implicit VCC use.
424  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
425
426  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
427                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
428                     clampmod:$clamp,
429                     dst_sel:$dst_sel, dst_unused:$dst_unused,
430                     src0_sel:$src0_sel, src1_sel:$src1_sel);
431
432  let InsDPP = (ins DstRCDPP:$old,
433                    Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
434                    Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
435                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
436                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
437  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
438
439  let HasExt = 1;
440  let HasExtDPP = 1;
441  let HasExtSDWA = 1;
442  let HasExtSDWA9 = 1;
443}
444
445def VOP_READLANE : VOPProfile<[i32, i32, i32]> {
446  let Outs32 = (outs SReg_32:$vdst);
447  let Outs64 = Outs32;
448  let Ins32 = (ins VRegOrLds_32:$src0, SCSrc_b32:$src1);
449  let Ins64 = Ins32;
450  let Asm32 = " $vdst, $src0, $src1";
451  let Asm64 = Asm32;
452
453  let HasExt = 0;
454  let HasExtDPP = 0;
455  let HasExt64BitDPP = 0;
456  let HasExtSDWA = 0;
457  let HasExtSDWA9 = 0;
458}
459
460def VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> {
461  let Outs32 = (outs VGPR_32:$vdst);
462  let Outs64 = Outs32;
463  let Ins32 = (ins SCSrc_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in);
464  let Ins64 = Ins32;
465  let Asm32 = " $vdst, $src0, $src1";
466  let Asm64 = Asm32;
467  let HasSrc2 = 0;
468  let HasSrc2Mods = 0;
469
470  let HasExt = 0;
471  let HasExtDPP = 0;
472  let HasExt64BitDPP = 0;
473  let HasExtSDWA = 0;
474  let HasExtSDWA9 = 0;
475}
476
477//===----------------------------------------------------------------------===//
478// VOP2 Instructions
479//===----------------------------------------------------------------------===//
480
481defm V_CNDMASK_B32 : VOP2eInst <"v_cndmask_b32", VOP2e_I32_I32_I32_I1>;
482let SubtargetPredicate = HasMadMacF32Insts in
483def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, []>;
484
485let isCommutable = 1 in {
486defm V_ADD_F32 : VOP2Inst <"v_add_f32", VOP_F32_F32_F32, any_fadd>;
487defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, any_fsub>;
488defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">;
489defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>;
490defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, any_fmul>;
491defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32_ARITH, AMDGPUmul_i24>;
492defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_i24>;
493defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32_ARITH, AMDGPUmul_u24>;
494defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_u24>;
495defm V_MIN_F32 : VOP2Inst <"v_min_f32", VOP_F32_F32_F32, fminnum_like>;
496defm V_MAX_F32 : VOP2Inst <"v_max_f32", VOP_F32_F32_F32, fmaxnum_like>;
497defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smin>;
498defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smax>;
499defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umin>;
500defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umax>;
501defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, lshr_rev, "v_lshr_b32">;
502defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, ashr_rev, "v_ashr_i32">;
503defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, lshl_rev, "v_lshl_b32">;
504defm V_AND_B32 : VOP2Inst <"v_and_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, and>;
505defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, or>;
506defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, xor>;
507
508let mayRaiseFPException = 0 in {
509let OtherPredicates = [HasMadMacF32Insts] in {
510let Constraints = "$vdst = $src2", DisableEncoding="$src2",
511    isConvertibleToThreeAddress = 1 in {
512defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>;
513
514let SubtargetPredicate = isGFX6GFX7GFX10 in
515defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_MAC_LEGACY_F32>;
516} // End Constraints = "$vdst = $src2", DisableEncoding="$src2",
517  //     isConvertibleToThreeAddress = 1
518
519def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32, []>;
520} // End OtherPredicates = [HasMadMacF32Insts]
521} // End mayRaiseFPException = 0
522
523// No patterns so that the scalar instructions are always selected.
524// The scalar versions will be replaced with vector when needed later.
525defm V_ADD_CO_U32 : VOP2bInst <"v_add_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_add_co_u32", 1>;
526defm V_SUB_CO_U32 : VOP2bInst <"v_sub_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>;
527defm V_SUBREV_CO_U32 : VOP2bInst <"v_subrev_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>;
528defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_addc_u32", 1>;
529defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>;
530defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>;
531
532
533let SubtargetPredicate = HasAddNoCarryInsts in {
534defm V_ADD_U32 : VOP2Inst <"v_add_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_add_u32", 1>;
535defm V_SUB_U32 : VOP2Inst <"v_sub_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>;
536defm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>;
537}
538
539} // End isCommutable = 1
540
541// These are special and do not read the exec mask.
542let isConvergent = 1, Uses = []<Register> in {
543def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE,
544  [(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))]>;
545
546let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in {
547def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE,
548  [(set i32:$vdst, (int_amdgcn_writelane i32:$src0, i32:$src1, i32:$vdst_in))]>;
549} // End $vdst = $vdst_in, DisableEncoding $vdst_in
550} // End isConvergent = 1
551
552defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_NO_EXT<VOP_I32_I32_I32>>;
553defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, add_ctpop>;
554defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_lo>;
555defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_hi>;
556defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_NO_EXT<VOP_F32_F32_I32>, AMDGPUldexp>;
557defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_NO_EXT<VOP_I32_F32_I32>>; // TODO: set "Uses = dst"
558
559let ReadsModeReg = 0, mayRaiseFPException = 0 in {
560defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_i16_f32>;
561defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_u16_f32>;
562}
563
564defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_NO_EXT<VOP_V2F16_F32_F32>, AMDGPUpkrtz_f16_f32>;
565defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_u16_u32>;
566defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_i16_i32>;
567
568
569let SubtargetPredicate = isGFX6GFX7 in {
570defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>;
571defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>;
572} // End SubtargetPredicate = isGFX6GFX7
573
574let isCommutable = 1 in {
575let SubtargetPredicate = isGFX6GFX7 in {
576defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, srl>;
577defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, sra>;
578defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, shl>;
579} // End SubtargetPredicate = isGFX6GFX7
580} // End isCommutable = 1
581
582
583class DivergentBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :
584  GCNPat<
585      (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
586      !if(!cast<Commutable_REV>(Inst).IsOrig,
587        (Inst $src0, $src1),
588        (Inst $src1, $src0)
589      )
590  >;
591
592class DivergentClampingBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :
593  GCNPat<
594      (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
595      !if(!cast<Commutable_REV>(Inst).IsOrig,
596        (Inst $src0, $src1, 0),
597        (Inst $src1, $src0, 0)
598      )
599  >;
600
601def : DivergentBinOp<srl, V_LSHRREV_B32_e64>;
602def : DivergentBinOp<sra, V_ASHRREV_I32_e64>;
603def : DivergentBinOp<shl, V_LSHLREV_B32_e64>;
604
605let SubtargetPredicate = HasAddNoCarryInsts in {
606  def : DivergentClampingBinOp<add, V_ADD_U32_e64>;
607  def : DivergentClampingBinOp<sub, V_SUB_U32_e64>;
608}
609
610let SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] in {
611def : DivergentClampingBinOp<add, V_ADD_CO_U32_e64>;
612def : DivergentClampingBinOp<sub, V_SUB_CO_U32_e64>;
613}
614
615def : DivergentBinOp<adde, V_ADDC_U32_e32>;
616def : DivergentBinOp<sube, V_SUBB_U32_e32>;
617
618class divergent_i64_BinOp <SDPatternOperator Op, Instruction Inst> :
619  GCNPat<
620      (getDivergentFrag<Op>.ret i64:$src0, i64:$src1),
621      (REG_SEQUENCE VReg_64,
622        (Inst
623          (i32 (EXTRACT_SUBREG $src0, sub0)),
624          (i32 (EXTRACT_SUBREG $src1, sub0))
625        ), sub0,
626        (Inst
627          (i32 (EXTRACT_SUBREG $src0, sub1)),
628          (i32 (EXTRACT_SUBREG $src1, sub1))
629        ), sub1
630      )
631  >;
632
633def :  divergent_i64_BinOp <and, V_AND_B32_e32>;
634def :  divergent_i64_BinOp <or,  V_OR_B32_e32>;
635def :  divergent_i64_BinOp <xor, V_XOR_B32_e32>;
636
637let SubtargetPredicate = Has16BitInsts in {
638
639let FPDPRounding = 1 in {
640def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16, [], "">;
641defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>;
642} // End FPDPRounding = 1
643
644defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16, lshl_rev>;
645defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16, lshr_rev>;
646defm V_ASHRREV_I16 : VOP2Inst <"v_ashrrev_i16", VOP_I16_I16_I16, ashr_rev>;
647
648let isCommutable = 1 in {
649let FPDPRounding = 1 in {
650defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, any_fadd>;
651defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, any_fsub>;
652defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">;
653defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, any_fmul>;
654
655let mayRaiseFPException = 0 in {
656def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">;
657}
658
659} // End FPDPRounding = 1
660defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16_ARITH, add>;
661defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16_ARITH, sub>;
662defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16_ARITH, null_frag, "v_sub_u16">;
663defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16, mul>;
664defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum_like>;
665defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum_like>;
666defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16, umax>;
667defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16, smax>;
668defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16, umin>;
669defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16, smin>;
670
671let Constraints = "$vdst = $src2", DisableEncoding="$src2",
672    isConvertibleToThreeAddress = 1 in {
673defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>;
674}
675} // End isCommutable = 1
676
677} // End SubtargetPredicate = Has16BitInsts
678
679let SubtargetPredicate = HasDLInsts in {
680
681defm V_XNOR_B32 : VOP2Inst <"v_xnor_b32", VOP_I32_I32_I32, xnor>;
682
683let Constraints = "$vdst = $src2",
684    DisableEncoding = "$src2",
685    isConvertibleToThreeAddress = 1,
686    isCommutable = 1 in
687defm V_FMAC_F32 : VOP2Inst <"v_fmac_f32", VOP_MAC_F32>;
688
689} // End SubtargetPredicate = HasDLInsts
690
691let SubtargetPredicate = HasFmaLegacy32 in {
692
693let Constraints = "$vdst = $src2",
694    DisableEncoding = "$src2",
695    isConvertibleToThreeAddress = 1,
696    isCommutable = 1 in
697defm V_FMAC_LEGACY_F32 : VOP2Inst <"v_fmac_legacy_f32", VOP_MAC_LEGACY_F32>;
698
699} // End SubtargetPredicate = HasFmaLegacy32
700
701let SubtargetPredicate = isGFX90APlus,
702    Constraints = "$vdst = $src2",
703    DisableEncoding="$src2",
704    isConvertibleToThreeAddress = 1,
705    isCommutable = 1,
706    SchedRW = [WriteDoubleAdd] in
707defm V_FMAC_F64 : VOP2Inst <"v_fmac_f64", VOP_MAC_F64>;
708
709let Constraints = "$vdst = $src2",
710      DisableEncoding="$src2",
711      isConvertibleToThreeAddress = 1,
712      isCommutable = 1,
713      IsDOT = 1 in {
714  let SubtargetPredicate = HasDot5Insts in
715    defm V_DOT2C_F32_F16 : VOP2Inst<"v_dot2c_f32_f16", VOP_DOT_ACC_F32_V2F16>;
716  let SubtargetPredicate = HasDot6Insts in
717    defm V_DOT4C_I32_I8  : VOP2Inst<"v_dot4c_i32_i8",  VOP_DOT_ACC_I32_I32>;
718
719  let SubtargetPredicate = HasDot4Insts in
720    defm V_DOT2C_I32_I16 : VOP2Inst<"v_dot2c_i32_i16", VOP_DOT_ACC_I32_I32>;
721  let SubtargetPredicate = HasDot3Insts in
722    defm V_DOT8C_I32_I4  : VOP2Inst<"v_dot8c_i32_i4",  VOP_DOT_ACC_I32_I32>;
723}
724
725let AddedComplexity = 30 in {
726  def : GCNPat<
727    (f32 (AMDGPUfdot2 v2f16:$src0, v2f16:$src1, f32:$src2, (i1 DSTCLAMP.NONE))),
728    (f32 (V_DOT2C_F32_F16_e32 $src0, $src1, $src2))
729  > {
730    let SubtargetPredicate = HasDot5Insts;
731  }
732  def : GCNPat<
733    (i32 (int_amdgcn_sdot4 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
734    (i32 (V_DOT4C_I32_I8_e32 $src0, $src1, $src2))
735  > {
736    let SubtargetPredicate = HasDot6Insts;
737  }
738  def : GCNPat<
739    (i32 (int_amdgcn_sdot2 v2i16:$src0, v2i16:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
740    (i32 (V_DOT2C_I32_I16_e32 $src0, $src1, $src2))
741  > {
742    let SubtargetPredicate = HasDot4Insts;
743  }
744  def : GCNPat<
745    (i32 (int_amdgcn_sdot8 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
746    (i32 (V_DOT8C_I32_I4_e32 $src0, $src1, $src2))
747  > {
748    let SubtargetPredicate = HasDot3Insts;
749  }
750} // End AddedComplexity = 30
751
752let SubtargetPredicate = HasFmaakFmamkF32Insts in {
753def V_FMAMK_F32 : VOP2_Pseudo<"v_fmamk_f32", VOP_MADMK_F32, [], "">;
754
755let isCommutable = 1 in
756def V_FMAAK_F32 : VOP2_Pseudo<"v_fmaak_f32", VOP_MADAK_F32, [], "">;
757}
758
759let SubtargetPredicate = isGFX10Plus in {
760
761let FPDPRounding = 1 in {
762def V_FMAMK_F16 : VOP2_Pseudo <"v_fmamk_f16", VOP_MADMK_F16, [], "">;
763
764let isCommutable = 1 in
765def V_FMAAK_F16 : VOP2_Pseudo <"v_fmaak_f16", VOP_MADAK_F16, [], "">;
766} // End FPDPRounding  = 1
767
768let Constraints = "$vdst = $src2",
769    DisableEncoding="$src2",
770    isConvertibleToThreeAddress = 1,
771    isCommutable = 1 in {
772defm V_FMAC_F16 : VOP2Inst <"v_fmac_f16", VOP_MAC_F16>;
773}
774
775} // End SubtargetPredicate = isGFX10Plus
776
777let SubtargetPredicate = HasPkFmacF16Inst in {
778defm V_PK_FMAC_F16 : VOP2Inst<"v_pk_fmac_f16", VOP_V2F16_V2F16_V2F16>;
779} // End SubtargetPredicate = HasPkFmacF16Inst
780
781// Note: 16-bit instructions produce a 0 result in the high 16-bits
782// on GFX8 and GFX9 and preserve high 16 bits on GFX10+
783multiclass Arithmetic_i16_0Hi_Pats <SDPatternOperator op, Instruction inst> {
784
785def : GCNPat<
786  (i32 (zext (op i16:$src0, i16:$src1))),
787  (inst VSrc_b16:$src0, VSrc_b16:$src1)
788>;
789
790def : GCNPat<
791  (i64 (zext (op i16:$src0, i16:$src1))),
792   (REG_SEQUENCE VReg_64,
793     (inst $src0, $src1), sub0,
794     (V_MOV_B32_e32 (i32 0)), sub1)
795>;
796}
797
798class ZExt_i16_i1_Pat <SDNode ext> : GCNPat <
799  (i16 (ext i1:$src)),
800  (V_CNDMASK_B32_e64 (i32 0/*src0mod*/), (i32 0/*src0*/),
801                     (i32 0/*src1mod*/), (i32 1/*src1*/),
802                     $src)
803>;
804
805foreach vt = [i16, v2i16] in {
806def : GCNPat <
807  (and vt:$src0, vt:$src1),
808  (V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
809>;
810
811def : GCNPat <
812  (or vt:$src0, vt:$src1),
813  (V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
814>;
815
816def : GCNPat <
817  (xor vt:$src0, vt:$src1),
818  (V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
819>;
820}
821
822let Predicates = [Has16BitInsts] in {
823
824// Undo sub x, c -> add x, -c canonicalization since c is more likely
825// an inline immediate than -c.
826// TODO: Also do for 64-bit.
827def : GCNPat<
828  (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)),
829  (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)
830>;
831
832
833let Predicates = [Has16BitInsts, isGFX7GFX8GFX9] in {
834
835def : GCNPat<
836  (i32 (zext (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)))),
837  (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)
838>;
839
840defm : Arithmetic_i16_0Hi_Pats<add, V_ADD_U16_e64>;
841defm : Arithmetic_i16_0Hi_Pats<mul, V_MUL_LO_U16_e64>;
842defm : Arithmetic_i16_0Hi_Pats<sub, V_SUB_U16_e64>;
843defm : Arithmetic_i16_0Hi_Pats<smin, V_MIN_I16_e64>;
844defm : Arithmetic_i16_0Hi_Pats<smax, V_MAX_I16_e64>;
845defm : Arithmetic_i16_0Hi_Pats<umin, V_MIN_U16_e64>;
846defm : Arithmetic_i16_0Hi_Pats<umax, V_MAX_U16_e64>;
847defm : Arithmetic_i16_0Hi_Pats<lshl_rev, V_LSHLREV_B16_e64>;
848defm : Arithmetic_i16_0Hi_Pats<lshr_rev, V_LSHRREV_B16_e64>;
849defm : Arithmetic_i16_0Hi_Pats<ashr_rev, V_ASHRREV_I16_e64>;
850}  // End Predicates = [Has16BitInsts, isGFX7GFX8GFX9]
851
852def : ZExt_i16_i1_Pat<zext>;
853def : ZExt_i16_i1_Pat<anyext>;
854
855def : GCNPat <
856  (i16 (sext i1:$src)),
857  (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
858                     /*src1mod*/(i32 0), /*src1*/(i32 -1), $src)
859>;
860
861} // End Predicates = [Has16BitInsts]
862
863
864let SubtargetPredicate = HasIntClamp in {
865// Set clamp bit for saturation.
866def : VOPBinOpClampPat<uaddsat, V_ADD_CO_U32_e64, i32>;
867def : VOPBinOpClampPat<usubsat, V_SUB_CO_U32_e64, i32>;
868}
869
870let SubtargetPredicate = HasAddNoCarryInsts, OtherPredicates = [HasIntClamp] in {
871let AddedComplexity = 1 in { // Prefer over form with carry-out.
872def : VOPBinOpClampPat<uaddsat, V_ADD_U32_e64, i32>;
873def : VOPBinOpClampPat<usubsat, V_SUB_U32_e64, i32>;
874}
875}
876
877let SubtargetPredicate = Has16BitInsts, OtherPredicates = [HasIntClamp] in {
878def : VOPBinOpClampPat<uaddsat, V_ADD_U16_e64, i16>;
879def : VOPBinOpClampPat<usubsat, V_SUB_U16_e64, i16>;
880}
881
882//===----------------------------------------------------------------------===//
883// Target-specific instruction encodings.
884//===----------------------------------------------------------------------===//
885
886class VOP2_DPP<bits<6> op, VOP2_DPP_Pseudo ps,
887               string opName = ps.OpName, VOPProfile p = ps.Pfl,
888               bit IsDPP16 = 0> :
889    VOP_DPP<opName, p, IsDPP16> {
890  let hasSideEffects = ps.hasSideEffects;
891  let Defs = ps.Defs;
892  let SchedRW = ps.SchedRW;
893  let Uses = ps.Uses;
894
895  bits<8> vdst;
896  bits<8> src1;
897  let Inst{8-0}   = 0xfa;
898  let Inst{16-9}  = !if(p.HasSrc1, src1{7-0}, 0);
899  let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
900  let Inst{30-25} = op;
901  let Inst{31}    = 0x0;
902}
903
904class Base_VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps,
905                 string opName = ps.OpName, VOPProfile p = ps.Pfl> :
906    VOP2_DPP<op, ps, opName, p, 1> {
907  let AssemblerPredicate = HasDPP16;
908  let SubtargetPredicate = HasDPP16;
909  let OtherPredicates = ps.OtherPredicates;
910}
911
912class VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps,
913                 string opName = ps.OpName, VOPProfile p = ps.Pfl> :
914    Base_VOP2_DPP16<op, ps, opName, p>,
915    SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX10>;
916
917class VOP2_DPP8<bits<6> op, VOP2_Pseudo ps,
918                string opName = ps.OpName, VOPProfile p = ps.Pfl> :
919    VOP_DPP8<ps.OpName, p> {
920  let hasSideEffects = ps.hasSideEffects;
921  let Defs = ps.Defs;
922  let SchedRW = ps.SchedRW;
923  let Uses = ps.Uses;
924
925  bits<8> vdst;
926  bits<8> src1;
927
928  let Inst{8-0}   = fi;
929  let Inst{16-9}  = !if(p.HasSrc1, src1{7-0}, 0);
930  let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
931  let Inst{30-25} = op;
932  let Inst{31}    = 0x0;
933
934  let OtherPredicates = ps.OtherPredicates;
935}
936
937//===----------------------------------------------------------------------===//
938// GFX10.
939//===----------------------------------------------------------------------===//
940
941let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
942  //===------------------------------- VOP2 -------------------------------===//
943  multiclass VOP2Only_Real_MADK_gfx10<bits<6> op> {
944    def _gfx10 :
945      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX10>,
946      VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
947  }
948  multiclass VOP2Only_Real_MADK_gfx10_with_name<bits<6> op, string opName,
949                                                string asmName> {
950    def _gfx10 :
951        VOP2_Real<!cast<VOP2_Pseudo>(opName), SIEncodingFamily.GFX10>,
952        VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> {
953      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName);
954      let AsmString = asmName # ps.AsmOperands;
955    }
956  }
957  multiclass VOP2_Real_e32_gfx10<bits<6> op> {
958    def _e32_gfx10 :
959      VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,
960      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
961  }
962  multiclass VOP2_Real_e64_gfx10<bits<6> op> {
963    def _e64_gfx10 :
964      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
965      VOP3e_gfx10<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
966  }
967  multiclass VOP2_Real_sdwa_gfx10<bits<6> op> {
968    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
969    def _sdwa_gfx10 :
970      VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
971      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
972      let DecoderNamespace = "SDWA10";
973    }
974  }
975  multiclass VOP2_Real_dpp_gfx10<bits<6> op> {
976    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
977    def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
978      let DecoderNamespace = "SDWA10";
979    }
980  }
981  multiclass VOP2_Real_dpp8_gfx10<bits<6> op> {
982    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
983    def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(NAME#"_e32")> {
984      let DecoderNamespace = "DPP8";
985    }
986  }
987
988  //===------------------------- VOP2 (with name) -------------------------===//
989  multiclass VOP2_Real_e32_gfx10_with_name<bits<6> op, string opName,
990                                           string asmName> {
991    def _e32_gfx10 :
992      VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
993      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
994        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
995        let AsmString = asmName # ps.AsmOperands;
996      }
997  }
998  multiclass VOP2_Real_e64_gfx10_with_name<bits<6> op, string opName,
999                                           string asmName> {
1000    def _e64_gfx10 :
1001      VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
1002      VOP3e_gfx10<{0, 1, 0, 0, op{5-0}},
1003                  !cast<VOP3_Pseudo>(opName#"_e64").Pfl> {
1004        VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64");
1005        let AsmString = asmName # ps.AsmOperands;
1006      }
1007  }
1008  let DecoderNamespace = "SDWA10" in {
1009    multiclass VOP2_Real_sdwa_gfx10_with_name<bits<6> op, string opName,
1010                                              string asmName> {
1011      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1012      def _sdwa_gfx10 :
1013        VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1014        VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1015          VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1016          let AsmString = asmName # ps.AsmOperands;
1017        }
1018    }
1019    multiclass VOP2_Real_dpp_gfx10_with_name<bits<6> op, string opName,
1020                                             string asmName> {
1021      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1022      def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp")> {
1023        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
1024        let AsmString = asmName # ps.Pfl.AsmDPP16;
1025      }
1026    }
1027    multiclass VOP2_Real_dpp8_gfx10_with_name<bits<6> op, string opName,
1028                                              string asmName> {
1029      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1030      def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
1031        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
1032        let AsmString = asmName # ps.Pfl.AsmDPP8;
1033        let DecoderNamespace = "DPP8";
1034      }
1035    }
1036  } // End DecoderNamespace = "SDWA10"
1037
1038  //===------------------------------ VOP2be ------------------------------===//
1039  multiclass VOP2be_Real_e32_gfx10<bits<6> op, string opName, string asmName> {
1040    def _e32_gfx10 :
1041      VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
1042      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
1043        VOP2_Pseudo Ps = !cast<VOP2_Pseudo>(opName#"_e32");
1044        let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
1045      }
1046  }
1047  multiclass VOP2be_Real_e64_gfx10<bits<6> op, string opName, string asmName> {
1048    def _e64_gfx10 :
1049      VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
1050      VOP3be_gfx10<{0, 1, 0, 0, op{5-0}},
1051                   !cast<VOP3_Pseudo>(opName#"_e64").Pfl> {
1052        VOP3_Pseudo Ps = !cast<VOP3_Pseudo>(opName#"_e64");
1053        let AsmString = asmName # Ps.AsmOperands;
1054      }
1055  }
1056  multiclass VOP2be_Real_sdwa_gfx10<bits<6> op, string opName, string asmName> {
1057    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1058    def _sdwa_gfx10 :
1059      VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1060      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1061        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1062        let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
1063        let DecoderNamespace = "SDWA10";
1064      }
1065    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1066    def _sdwa_w32_gfx10 :
1067      Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1068      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1069        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1070        let AsmString = asmName # !subst("vcc", "vcc_lo", Ps.AsmOperands);
1071        let isAsmParserOnly = 1;
1072        let DecoderNamespace = "SDWA10";
1073        let WaveSizePredicate = isWave32;
1074      }
1075    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1076    def _sdwa_w64_gfx10 :
1077      Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1078      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1079        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1080        let AsmString = asmName # Ps.AsmOperands;
1081        let isAsmParserOnly = 1;
1082        let DecoderNamespace = "SDWA10";
1083        let WaveSizePredicate = isWave64;
1084      }
1085  }
1086  multiclass VOP2be_Real_dpp_gfx10<bits<6> op, string opName, string asmName> {
1087    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1088    def _dpp_gfx10 :
1089      VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1090        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1091        let AsmString = asmName # !subst(", vcc", "", AsmDPP);
1092        let DecoderNamespace = "SDWA10";
1093      }
1094    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1095    def _dpp_w32_gfx10 :
1096      Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1097        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1098        let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP);
1099        let isAsmParserOnly = 1;
1100        let WaveSizePredicate = isWave32;
1101      }
1102    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1103    def _dpp_w64_gfx10 :
1104      Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1105        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1106        let AsmString = asmName # AsmDPP;
1107        let isAsmParserOnly = 1;
1108        let WaveSizePredicate = isWave64;
1109      }
1110  }
1111  multiclass VOP2be_Real_dpp8_gfx10<bits<6> op, string opName, string asmName> {
1112    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1113    def _dpp8_gfx10 :
1114      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1115        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1116        let AsmString = asmName # !subst(", vcc", "", AsmDPP8);
1117        let DecoderNamespace = "DPP8";
1118      }
1119    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1120    def _dpp8_w32_gfx10 :
1121      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1122        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1123        let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8);
1124        let isAsmParserOnly = 1;
1125        let WaveSizePredicate = isWave32;
1126      }
1127    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1128    def _dpp8_w64_gfx10 :
1129      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1130        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1131        let AsmString = asmName # AsmDPP8;
1132        let isAsmParserOnly = 1;
1133        let WaveSizePredicate = isWave64;
1134      }
1135  }
1136
1137  //===----------------------------- VOP3Only -----------------------------===//
1138  multiclass VOP3Only_Real_gfx10<bits<10> op> {
1139    def _e64_gfx10 :
1140      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1141      VOP3e_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1142        let IsSingle = 1;
1143      }
1144  }
1145
1146  //===---------------------------- VOP3beOnly ----------------------------===//
1147  multiclass VOP3beOnly_Real_gfx10<bits<10> op> {
1148    def _e64_gfx10 :
1149      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1150      VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1151        let IsSingle = 1;
1152      }
1153  }
1154} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
1155
1156multiclass VOP2be_Real_gfx10<bits<6> op, string opName, string asmName> :
1157  VOP2be_Real_e32_gfx10<op, opName, asmName>,
1158  VOP2be_Real_e64_gfx10<op, opName, asmName>,
1159  VOP2be_Real_sdwa_gfx10<op, opName, asmName>,
1160  VOP2be_Real_dpp_gfx10<op, opName, asmName>,
1161  VOP2be_Real_dpp8_gfx10<op, opName, asmName>;
1162
1163multiclass VOP2e_Real_gfx10<bits<6> op, string opName, string asmName> :
1164  VOP2_Real_e32_gfx10<op>,
1165  VOP2_Real_e64_gfx10<op>,
1166  VOP2be_Real_sdwa_gfx10<op, opName, asmName>,
1167  VOP2be_Real_dpp_gfx10<op, opName, asmName>,
1168  VOP2be_Real_dpp8_gfx10<op, opName, asmName>;
1169
1170multiclass VOP2_Real_gfx10<bits<6> op> :
1171  VOP2_Real_e32_gfx10<op>, VOP2_Real_e64_gfx10<op>,
1172  VOP2_Real_sdwa_gfx10<op>, VOP2_Real_dpp_gfx10<op>, VOP2_Real_dpp8_gfx10<op>;
1173
1174multiclass VOP2_Real_gfx10_with_name<bits<6> op, string opName,
1175                                     string asmName> :
1176  VOP2_Real_e32_gfx10_with_name<op, opName, asmName>,
1177  VOP2_Real_e64_gfx10_with_name<op, opName, asmName>,
1178  VOP2_Real_sdwa_gfx10_with_name<op, opName, asmName>,
1179  VOP2_Real_dpp_gfx10_with_name<op, opName, asmName>,
1180  VOP2_Real_dpp8_gfx10_with_name<op, opName, asmName>;
1181
1182// NB: Same opcode as v_mac_legacy_f32
1183let DecoderNamespace = "GFX10_B" in
1184defm V_FMAC_LEGACY_F32 : VOP2_Real_gfx10<0x006>;
1185
1186defm V_XNOR_B32        : VOP2_Real_gfx10<0x01e>;
1187defm V_FMAC_F32        : VOP2_Real_gfx10<0x02b>;
1188defm V_FMAMK_F32       : VOP2Only_Real_MADK_gfx10<0x02c>;
1189defm V_FMAAK_F32       : VOP2Only_Real_MADK_gfx10<0x02d>;
1190defm V_ADD_F16         : VOP2_Real_gfx10<0x032>;
1191defm V_SUB_F16         : VOP2_Real_gfx10<0x033>;
1192defm V_SUBREV_F16      : VOP2_Real_gfx10<0x034>;
1193defm V_MUL_F16         : VOP2_Real_gfx10<0x035>;
1194defm V_FMAC_F16        : VOP2_Real_gfx10<0x036>;
1195defm V_FMAMK_F16       : VOP2Only_Real_MADK_gfx10<0x037>;
1196defm V_FMAAK_F16       : VOP2Only_Real_MADK_gfx10<0x038>;
1197defm V_MAX_F16         : VOP2_Real_gfx10<0x039>;
1198defm V_MIN_F16         : VOP2_Real_gfx10<0x03a>;
1199defm V_LDEXP_F16       : VOP2_Real_gfx10<0x03b>;
1200
1201let IsSingle = 1 in {
1202defm V_PK_FMAC_F16     : VOP2_Real_e32_gfx10<0x03c>;
1203}
1204
1205// VOP2 no carry-in, carry-out.
1206defm V_ADD_NC_U32 :
1207  VOP2_Real_gfx10_with_name<0x025, "V_ADD_U32", "v_add_nc_u32">;
1208defm V_SUB_NC_U32 :
1209  VOP2_Real_gfx10_with_name<0x026, "V_SUB_U32", "v_sub_nc_u32">;
1210defm V_SUBREV_NC_U32 :
1211  VOP2_Real_gfx10_with_name<0x027, "V_SUBREV_U32", "v_subrev_nc_u32">;
1212
1213// VOP2 carry-in, carry-out.
1214defm V_ADD_CO_CI_U32 :
1215  VOP2be_Real_gfx10<0x028, "V_ADDC_U32", "v_add_co_ci_u32">;
1216defm V_SUB_CO_CI_U32 :
1217  VOP2be_Real_gfx10<0x029, "V_SUBB_U32", "v_sub_co_ci_u32">;
1218defm V_SUBREV_CO_CI_U32 :
1219  VOP2be_Real_gfx10<0x02a, "V_SUBBREV_U32", "v_subrev_co_ci_u32">;
1220
1221defm V_CNDMASK_B32 :
1222  VOP2e_Real_gfx10<0x001, "V_CNDMASK_B32", "v_cndmask_b32">;
1223
1224// VOP3 only.
1225defm V_BFM_B32            : VOP3Only_Real_gfx10<0x363>;
1226defm V_BCNT_U32_B32       : VOP3Only_Real_gfx10<0x364>;
1227defm V_MBCNT_LO_U32_B32   : VOP3Only_Real_gfx10<0x365>;
1228defm V_MBCNT_HI_U32_B32   : VOP3Only_Real_gfx10<0x366>;
1229defm V_LDEXP_F32          : VOP3Only_Real_gfx10<0x362>;
1230defm V_CVT_PKNORM_I16_F32 : VOP3Only_Real_gfx10<0x368>;
1231defm V_CVT_PKNORM_U16_F32 : VOP3Only_Real_gfx10<0x369>;
1232defm V_CVT_PK_U16_U32     : VOP3Only_Real_gfx10<0x36a>;
1233defm V_CVT_PK_I16_I32     : VOP3Only_Real_gfx10<0x36b>;
1234
1235// VOP3 carry-out.
1236defm V_ADD_CO_U32 : VOP3beOnly_Real_gfx10<0x30f>;
1237defm V_SUB_CO_U32 : VOP3beOnly_Real_gfx10<0x310>;
1238defm V_SUBREV_CO_U32 : VOP3beOnly_Real_gfx10<0x319>;
1239
1240let SubtargetPredicate = isGFX10Plus in {
1241  defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx10>;
1242
1243  defm : VOP2bInstAliases<
1244    V_ADDC_U32_e32, V_ADD_CO_CI_U32_e32_gfx10, "v_add_co_ci_u32">;
1245  defm : VOP2bInstAliases<
1246    V_SUBB_U32_e32, V_SUB_CO_CI_U32_e32_gfx10, "v_sub_co_ci_u32">;
1247  defm : VOP2bInstAliases<
1248    V_SUBBREV_U32_e32, V_SUBREV_CO_CI_U32_e32_gfx10, "v_subrev_co_ci_u32">;
1249} // End SubtargetPredicate = isGFX10Plus
1250
1251//===----------------------------------------------------------------------===//
1252// GFX6, GFX7, GFX10.
1253//===----------------------------------------------------------------------===//
1254
1255class VOP2_DPPe <bits<6> op, VOP2_DPP_Pseudo ps, VOPProfile P = ps.Pfl> :
1256  VOP_DPPe <P> {
1257  bits<8> vdst;
1258  bits<8> src1;
1259  let Inst{8-0}   = 0xfa; //dpp
1260  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
1261  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
1262  let Inst{30-25} = op;
1263  let Inst{31}    = 0x0; //encoding
1264}
1265
1266let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
1267  multiclass VOP2_Lane_Real_gfx6_gfx7<bits<6> op> {
1268    def _gfx6_gfx7 :
1269      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1270      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1271  }
1272  multiclass VOP2Only_Real_MADK_gfx6_gfx7<bits<6> op> {
1273    def _gfx6_gfx7 :
1274      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1275      VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1276  }
1277  multiclass VOP2_Real_e32_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1278    def _e32_gfx6_gfx7 :
1279      VOP2_Real<!cast<VOP2_Pseudo>(PseudoName#"_e32"), SIEncodingFamily.SI>,
1280      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(PseudoName#"_e32").Pfl>;
1281  }
1282  multiclass VOP2_Real_e64_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1283    def _e64_gfx6_gfx7 :
1284      VOP3_Real<!cast<VOP3_Pseudo>(PseudoName#"_e64"), SIEncodingFamily.SI>,
1285      VOP3e_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(PseudoName#"_e64").Pfl>;
1286  }
1287  multiclass VOP2be_Real_e64_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1288    def _e64_gfx6_gfx7 :
1289      VOP3_Real<!cast<VOP3_Pseudo>(PseudoName#"_e64"), SIEncodingFamily.SI>,
1290      VOP3be_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(PseudoName#"_e64").Pfl>;
1291  }
1292} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
1293
1294multiclass VOP2Only_Real_MADK_gfx6_gfx7_gfx10<bits<6> op> :
1295  VOP2Only_Real_MADK_gfx6_gfx7<op>, VOP2Only_Real_MADK_gfx10<op>;
1296
1297multiclass VOP2_Real_gfx6_gfx7<bits<6> op> :
1298  VOP2_Real_e32_gfx6_gfx7<op>, VOP2_Real_e64_gfx6_gfx7<op>;
1299
1300multiclass VOP2_Real_gfx6_gfx7_gfx10<bits<6> op> :
1301  VOP2_Real_gfx6_gfx7<op>, VOP2_Real_gfx10<op>;
1302
1303multiclass VOP2be_Real_gfx6_gfx7<bits<6> op> :
1304  VOP2_Real_e32_gfx6_gfx7<op>, VOP2be_Real_e64_gfx6_gfx7<op>;
1305
1306multiclass VOP2be_Real_gfx6_gfx7_with_name<bits<6> op,
1307  string PseudoName, string asmName>  {
1308  defvar ps32 = !cast<VOP2_Pseudo>(PseudoName#"_e32");
1309  defvar ps64 = !cast<VOP3_Pseudo>(PseudoName#"_e64");
1310
1311  let AsmString = asmName # ps32.AsmOperands in {
1312    defm "" : VOP2_Real_e32_gfx6_gfx7<op, PseudoName>;
1313  }
1314
1315   let AsmString = asmName # ps64.AsmOperands in {
1316    defm "" : VOP2be_Real_e64_gfx6_gfx7<op, PseudoName>;
1317  }
1318}
1319
1320defm V_CNDMASK_B32        : VOP2_Real_gfx6_gfx7<0x000>;
1321defm V_MIN_LEGACY_F32     : VOP2_Real_gfx6_gfx7<0x00d>;
1322defm V_MAX_LEGACY_F32     : VOP2_Real_gfx6_gfx7<0x00e>;
1323defm V_LSHR_B32           : VOP2_Real_gfx6_gfx7<0x015>;
1324defm V_ASHR_I32           : VOP2_Real_gfx6_gfx7<0x017>;
1325defm V_LSHL_B32           : VOP2_Real_gfx6_gfx7<0x019>;
1326defm V_BFM_B32            : VOP2_Real_gfx6_gfx7<0x01e>;
1327defm V_BCNT_U32_B32       : VOP2_Real_gfx6_gfx7<0x022>;
1328defm V_MBCNT_LO_U32_B32   : VOP2_Real_gfx6_gfx7<0x023>;
1329defm V_MBCNT_HI_U32_B32   : VOP2_Real_gfx6_gfx7<0x024>;
1330defm V_LDEXP_F32          : VOP2_Real_gfx6_gfx7<0x02b>;
1331defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_gfx6_gfx7<0x02c>;
1332defm V_CVT_PKNORM_I16_F32 : VOP2_Real_gfx6_gfx7<0x02d>;
1333defm V_CVT_PKNORM_U16_F32 : VOP2_Real_gfx6_gfx7<0x02e>;
1334defm V_CVT_PK_U16_U32     : VOP2_Real_gfx6_gfx7<0x030>;
1335defm V_CVT_PK_I16_I32     : VOP2_Real_gfx6_gfx7<0x031>;
1336
1337// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in
1338// VI, but the VI instructions behave the same as the SI versions.
1339defm V_ADD_I32            : VOP2be_Real_gfx6_gfx7_with_name<0x025, "V_ADD_CO_U32", "v_add_i32">;
1340defm V_SUB_I32            : VOP2be_Real_gfx6_gfx7_with_name<0x026, "V_SUB_CO_U32", "v_sub_i32">;
1341defm V_SUBREV_I32         : VOP2be_Real_gfx6_gfx7_with_name<0x027, "V_SUBREV_CO_U32", "v_subrev_i32">;
1342defm V_ADDC_U32           : VOP2be_Real_gfx6_gfx7<0x028>;
1343defm V_SUBB_U32           : VOP2be_Real_gfx6_gfx7<0x029>;
1344defm V_SUBBREV_U32        : VOP2be_Real_gfx6_gfx7<0x02a>;
1345
1346defm V_READLANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x001>;
1347
1348let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
1349  defm V_WRITELANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x002>;
1350} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)
1351
1352let SubtargetPredicate = isGFX6GFX7 in {
1353  defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx6_gfx7>;
1354  defm : VOP2eInstAliases<V_ADD_CO_U32_e32, V_ADD_I32_e32_gfx6_gfx7>;
1355  defm : VOP2eInstAliases<V_SUB_CO_U32_e32, V_SUB_I32_e32_gfx6_gfx7>;
1356  defm : VOP2eInstAliases<V_SUBREV_CO_U32_e32, V_SUBREV_I32_e32_gfx6_gfx7>;
1357
1358  def : VOP2e64InstAlias<V_ADD_CO_U32_e64, V_ADD_I32_e64_gfx6_gfx7>;
1359  def : VOP2e64InstAlias<V_SUB_CO_U32_e64, V_SUB_I32_e64_gfx6_gfx7>;
1360  def : VOP2e64InstAlias<V_SUBREV_CO_U32_e64, V_SUBREV_I32_e64_gfx6_gfx7>;
1361} // End SubtargetPredicate = isGFX6GFX7
1362
1363defm V_ADD_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x003>;
1364defm V_SUB_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x004>;
1365defm V_SUBREV_F32         : VOP2_Real_gfx6_gfx7_gfx10<0x005>;
1366defm V_MAC_LEGACY_F32     : VOP2_Real_gfx6_gfx7_gfx10<0x006>;
1367defm V_MUL_LEGACY_F32     : VOP2_Real_gfx6_gfx7_gfx10<0x007>;
1368defm V_MUL_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x008>;
1369defm V_MUL_I32_I24        : VOP2_Real_gfx6_gfx7_gfx10<0x009>;
1370defm V_MUL_HI_I32_I24     : VOP2_Real_gfx6_gfx7_gfx10<0x00a>;
1371defm V_MUL_U32_U24        : VOP2_Real_gfx6_gfx7_gfx10<0x00b>;
1372defm V_MUL_HI_U32_U24     : VOP2_Real_gfx6_gfx7_gfx10<0x00c>;
1373defm V_MIN_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x00f>;
1374defm V_MAX_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x010>;
1375defm V_MIN_I32            : VOP2_Real_gfx6_gfx7_gfx10<0x011>;
1376defm V_MAX_I32            : VOP2_Real_gfx6_gfx7_gfx10<0x012>;
1377defm V_MIN_U32            : VOP2_Real_gfx6_gfx7_gfx10<0x013>;
1378defm V_MAX_U32            : VOP2_Real_gfx6_gfx7_gfx10<0x014>;
1379defm V_LSHRREV_B32        : VOP2_Real_gfx6_gfx7_gfx10<0x016>;
1380defm V_ASHRREV_I32        : VOP2_Real_gfx6_gfx7_gfx10<0x018>;
1381defm V_LSHLREV_B32        : VOP2_Real_gfx6_gfx7_gfx10<0x01a>;
1382defm V_AND_B32            : VOP2_Real_gfx6_gfx7_gfx10<0x01b>;
1383defm V_OR_B32             : VOP2_Real_gfx6_gfx7_gfx10<0x01c>;
1384defm V_XOR_B32            : VOP2_Real_gfx6_gfx7_gfx10<0x01d>;
1385defm V_MAC_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x01f>;
1386defm V_CVT_PKRTZ_F16_F32  : VOP2_Real_gfx6_gfx7_gfx10<0x02f>;
1387defm V_MADMK_F32          : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x020>;
1388defm V_MADAK_F32          : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x021>;
1389
1390//===----------------------------------------------------------------------===//
1391// GFX8, GFX9 (VI).
1392//===----------------------------------------------------------------------===//
1393
1394let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {
1395
1396multiclass VOP2_Real_MADK_vi <bits<6> op> {
1397  def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,
1398            VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1399}
1400
1401multiclass VOP2_Real_e32_vi <bits<6> op> {
1402  def _e32_vi :
1403    VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
1404    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
1405}
1406
1407multiclass VOP2_Real_e64_vi <bits<10> op> {
1408  def _e64_vi :
1409    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
1410    VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1411}
1412
1413multiclass VOP2_Real_e64only_vi <bits<10> op> {
1414  def _e64_vi :
1415    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
1416    VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1417      let IsSingle = 1;
1418    }
1419}
1420
1421multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> :
1422  VOP2_Real_e32_vi<op>,
1423  VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>;
1424
1425} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8"
1426
1427multiclass VOP2_SDWA_Real <bits<6> op> {
1428  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA>.ret in
1429  def _sdwa_vi :
1430    VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1431    VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1432}
1433
1434multiclass VOP2_SDWA9_Real <bits<6> op> {
1435  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
1436  def _sdwa_gfx9 :
1437    VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1438    VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1439}
1440
1441let AssemblerPredicate = isGFX8Only in {
1442
1443multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName> {
1444  def _e32_vi :
1445    VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.VI>,
1446    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
1447      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32");
1448      let AsmString = AsmName # ps.AsmOperands;
1449      let DecoderNamespace = "GFX8";
1450    }
1451  def _e64_vi :
1452    VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.VI>,
1453    VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
1454      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64");
1455      let AsmString = AsmName # ps.AsmOperands;
1456      let DecoderNamespace = "GFX8";
1457    }
1458  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA>.ret in
1459    def _sdwa_vi :
1460      VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>,
1461      VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {
1462        VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa");
1463        let AsmString = AsmName # ps.AsmOperands;
1464      }
1465  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in
1466    def _dpp_vi :
1467      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.VI>,
1468      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> {
1469        VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp");
1470        let AsmString = AsmName # ps.AsmOperands;
1471      }
1472}
1473}
1474
1475let AssemblerPredicate = isGFX9Only in {
1476
1477multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> {
1478  def _e32_gfx9 :
1479    VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.GFX9>,
1480    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
1481      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32");
1482      let AsmString = AsmName # ps.AsmOperands;
1483      let DecoderNamespace = "GFX9";
1484    }
1485  def _e64_gfx9 :
1486    VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>,
1487    VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
1488      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64");
1489      let AsmString = AsmName # ps.AsmOperands;
1490      let DecoderNamespace = "GFX9";
1491    }
1492  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA9>.ret in
1493    def _sdwa_gfx9 :
1494      VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>,
1495      VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {
1496        VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa");
1497        let AsmString = AsmName # ps.AsmOperands;
1498      }
1499  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in
1500    def _dpp_gfx9 :
1501      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.GFX9>,
1502      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> {
1503        VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp");
1504        let AsmString = AsmName # ps.AsmOperands;
1505        let DecoderNamespace = "SDWA9";
1506      }
1507}
1508
1509multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> {
1510  def _e32_gfx9 :
1511    VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX9>,
1512    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>{
1513      let DecoderNamespace = "GFX9";
1514    }
1515  def _e64_gfx9 :
1516    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>,
1517    VOP3e_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1518      let DecoderNamespace = "GFX9";
1519    }
1520  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
1521    def _sdwa_gfx9 :
1522      VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1523      VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
1524      }
1525  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
1526    def _dpp_gfx9 :
1527      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,
1528      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
1529        let DecoderNamespace = "SDWA9";
1530      }
1531}
1532
1533} // AssemblerPredicate = isGFX9Only
1534
1535multiclass VOP2_Real_e32e64_vi <bits<6> op> :
1536  Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> {
1537
1538  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
1539    def _dpp_vi :
1540      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.VI>,
1541      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;
1542}
1543
1544defm V_CNDMASK_B32        : VOP2_Real_e32e64_vi <0x0>;
1545defm V_ADD_F32            : VOP2_Real_e32e64_vi <0x1>;
1546defm V_SUB_F32            : VOP2_Real_e32e64_vi <0x2>;
1547defm V_SUBREV_F32         : VOP2_Real_e32e64_vi <0x3>;
1548let AssemblerPredicate = isGCN3ExcludingGFX90A in
1549defm V_MUL_LEGACY_F32     : VOP2_Real_e32e64_vi <0x4>;
1550defm V_MUL_F32            : VOP2_Real_e32e64_vi <0x5>;
1551defm V_MUL_I32_I24        : VOP2_Real_e32e64_vi <0x6>;
1552defm V_MUL_HI_I32_I24     : VOP2_Real_e32e64_vi <0x7>;
1553defm V_MUL_U32_U24        : VOP2_Real_e32e64_vi <0x8>;
1554defm V_MUL_HI_U32_U24     : VOP2_Real_e32e64_vi <0x9>;
1555defm V_MIN_F32            : VOP2_Real_e32e64_vi <0xa>;
1556defm V_MAX_F32            : VOP2_Real_e32e64_vi <0xb>;
1557defm V_MIN_I32            : VOP2_Real_e32e64_vi <0xc>;
1558defm V_MAX_I32            : VOP2_Real_e32e64_vi <0xd>;
1559defm V_MIN_U32            : VOP2_Real_e32e64_vi <0xe>;
1560defm V_MAX_U32            : VOP2_Real_e32e64_vi <0xf>;
1561defm V_LSHRREV_B32        : VOP2_Real_e32e64_vi <0x10>;
1562defm V_ASHRREV_I32        : VOP2_Real_e32e64_vi <0x11>;
1563defm V_LSHLREV_B32        : VOP2_Real_e32e64_vi <0x12>;
1564defm V_AND_B32            : VOP2_Real_e32e64_vi <0x13>;
1565defm V_OR_B32             : VOP2_Real_e32e64_vi <0x14>;
1566defm V_XOR_B32            : VOP2_Real_e32e64_vi <0x15>;
1567defm V_MAC_F32            : VOP2_Real_e32e64_vi <0x16>;
1568defm V_MADMK_F32          : VOP2_Real_MADK_vi <0x17>;
1569defm V_MADAK_F32          : VOP2_Real_MADK_vi <0x18>;
1570
1571defm V_ADD_U32            : VOP2be_Real_e32e64_vi_only <0x19, "V_ADD_CO_U32",     "v_add_u32">;
1572defm V_SUB_U32            : VOP2be_Real_e32e64_vi_only <0x1a, "V_SUB_CO_U32",     "v_sub_u32">;
1573defm V_SUBREV_U32         : VOP2be_Real_e32e64_vi_only <0x1b, "V_SUBREV_CO_U32",  "v_subrev_u32">;
1574defm V_ADDC_U32           : VOP2be_Real_e32e64_vi_only <0x1c, "V_ADDC_U32",    "v_addc_u32">;
1575defm V_SUBB_U32           : VOP2be_Real_e32e64_vi_only <0x1d, "V_SUBB_U32",    "v_subb_u32">;
1576defm V_SUBBREV_U32        : VOP2be_Real_e32e64_vi_only <0x1e, "V_SUBBREV_U32", "v_subbrev_u32">;
1577
1578defm V_ADD_CO_U32         : VOP2be_Real_e32e64_gfx9 <0x19, "V_ADD_CO_U32",     "v_add_co_u32">;
1579defm V_SUB_CO_U32         : VOP2be_Real_e32e64_gfx9 <0x1a, "V_SUB_CO_U32",     "v_sub_co_u32">;
1580defm V_SUBREV_CO_U32      : VOP2be_Real_e32e64_gfx9 <0x1b, "V_SUBREV_CO_U32",  "v_subrev_co_u32">;
1581defm V_ADDC_CO_U32        : VOP2be_Real_e32e64_gfx9 <0x1c, "V_ADDC_U32",    "v_addc_co_u32">;
1582defm V_SUBB_CO_U32        : VOP2be_Real_e32e64_gfx9 <0x1d, "V_SUBB_U32",    "v_subb_co_u32">;
1583defm V_SUBBREV_CO_U32     : VOP2be_Real_e32e64_gfx9 <0x1e, "V_SUBBREV_U32", "v_subbrev_co_u32">;
1584
1585defm V_ADD_U32            : VOP2_Real_e32e64_gfx9 <0x34>;
1586defm V_SUB_U32            : VOP2_Real_e32e64_gfx9 <0x35>;
1587defm V_SUBREV_U32         : VOP2_Real_e32e64_gfx9 <0x36>;
1588
1589defm V_BFM_B32            : VOP2_Real_e64only_vi <0x293>;
1590defm V_BCNT_U32_B32       : VOP2_Real_e64only_vi <0x28b>;
1591defm V_MBCNT_LO_U32_B32   : VOP2_Real_e64only_vi <0x28c>;
1592defm V_MBCNT_HI_U32_B32   : VOP2_Real_e64only_vi <0x28d>;
1593defm V_LDEXP_F32          : VOP2_Real_e64only_vi <0x288>;
1594defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64only_vi <0x1f0>;
1595defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64only_vi <0x294>;
1596defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64only_vi <0x295>;
1597defm V_CVT_PKRTZ_F16_F32  : VOP2_Real_e64only_vi <0x296>;
1598defm V_CVT_PK_U16_U32     : VOP2_Real_e64only_vi <0x297>;
1599defm V_CVT_PK_I16_I32     : VOP2_Real_e64only_vi <0x298>;
1600
1601defm V_ADD_F16            : VOP2_Real_e32e64_vi <0x1f>;
1602defm V_SUB_F16            : VOP2_Real_e32e64_vi <0x20>;
1603defm V_SUBREV_F16         : VOP2_Real_e32e64_vi <0x21>;
1604defm V_MUL_F16            : VOP2_Real_e32e64_vi <0x22>;
1605defm V_MAC_F16            : VOP2_Real_e32e64_vi <0x23>;
1606defm V_MADMK_F16          : VOP2_Real_MADK_vi <0x24>;
1607defm V_MADAK_F16          : VOP2_Real_MADK_vi <0x25>;
1608defm V_ADD_U16            : VOP2_Real_e32e64_vi <0x26>;
1609defm V_SUB_U16            : VOP2_Real_e32e64_vi <0x27>;
1610defm V_SUBREV_U16         : VOP2_Real_e32e64_vi <0x28>;
1611defm V_MUL_LO_U16         : VOP2_Real_e32e64_vi <0x29>;
1612defm V_LSHLREV_B16        : VOP2_Real_e32e64_vi <0x2a>;
1613defm V_LSHRREV_B16        : VOP2_Real_e32e64_vi <0x2b>;
1614defm V_ASHRREV_I16        : VOP2_Real_e32e64_vi <0x2c>;
1615defm V_MAX_F16            : VOP2_Real_e32e64_vi <0x2d>;
1616defm V_MIN_F16            : VOP2_Real_e32e64_vi <0x2e>;
1617defm V_MAX_U16            : VOP2_Real_e32e64_vi <0x2f>;
1618defm V_MAX_I16            : VOP2_Real_e32e64_vi <0x30>;
1619defm V_MIN_U16            : VOP2_Real_e32e64_vi <0x31>;
1620defm V_MIN_I16            : VOP2_Real_e32e64_vi <0x32>;
1621defm V_LDEXP_F16          : VOP2_Real_e32e64_vi <0x33>;
1622
1623let SubtargetPredicate = isGFX8GFX9 in {
1624
1625// Aliases to simplify matching of floating-point instructions that
1626// are VOP2 on SI and VOP3 on VI.
1627class SI2_VI3Alias <string name, VOP3_Real inst> : InstAlias <
1628  name#" $dst, $src0, $src1",
1629  !if(inst.Pfl.HasOMod,
1630      (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0),
1631      (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0))
1632>, PredicateControl {
1633  let UseInstAsmMatchConverter = 0;
1634  let AsmVariantName = AMDGPUAsmVariants.VOP3;
1635}
1636
1637def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>;
1638def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>;
1639def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>;
1640def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;
1641def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;
1642
1643defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_vi>;
1644
1645} // End SubtargetPredicate = isGFX8GFX9
1646
1647let SubtargetPredicate = isGFX9Only in {
1648
1649defm : VOP2bInstAliases<V_ADD_U32_e32,     V_ADD_CO_U32_e32_gfx9,     "v_add_co_u32">;
1650defm : VOP2bInstAliases<V_ADDC_U32_e32,    V_ADDC_CO_U32_e32_gfx9,    "v_addc_co_u32">;
1651defm : VOP2bInstAliases<V_SUB_U32_e32,     V_SUB_CO_U32_e32_gfx9,     "v_sub_co_u32">;
1652defm : VOP2bInstAliases<V_SUBB_U32_e32,    V_SUBB_CO_U32_e32_gfx9,    "v_subb_co_u32">;
1653defm : VOP2bInstAliases<V_SUBREV_U32_e32,  V_SUBREV_CO_U32_e32_gfx9,  "v_subrev_co_u32">;
1654defm : VOP2bInstAliases<V_SUBBREV_U32_e32, V_SUBBREV_CO_U32_e32_gfx9, "v_subbrev_co_u32">;
1655
1656} // End SubtargetPredicate = isGFX9Only
1657
1658let SubtargetPredicate = HasDLInsts in {
1659
1660defm V_FMAC_F32 : VOP2_Real_e32e64_vi <0x3b>;
1661defm V_XNOR_B32 : VOP2_Real_e32e64_vi <0x3d>;
1662
1663} // End SubtargetPredicate = HasDLInsts
1664
1665let AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A" in {
1666  multiclass VOP2_Real_e32_gfx90a <bits<6> op> {
1667    def _e32_gfx90a :
1668      VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX90A>,
1669      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
1670  }
1671
1672  multiclass VOP2_Real_e64_gfx90a <bits<10> op> {
1673    def _e64_gfx90a :
1674      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX90A>,
1675      VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1676  }
1677
1678  multiclass Base_VOP2_Real_e32e64_gfx90a <bits<6> op> :
1679    VOP2_Real_e32_gfx90a<op>,
1680    VOP2_Real_e64_gfx90a<{0, 1, 0, 0, op{5-0}}>;
1681
1682  multiclass VOP2_Real_e32e64_gfx90a <bits<6> op> :
1683    Base_VOP2_Real_e32e64_gfx90a<op> {
1684
1685    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
1686      def _dpp_gfx90a :
1687        VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX90A>,
1688        VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
1689          let DecoderNamespace = "SDWA9";
1690        }
1691  }
1692} // End AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A"
1693
1694let SubtargetPredicate = isGFX90APlus in {
1695  defm V_FMAC_F64       : VOP2_Real_e32e64_gfx90a <0x4>;
1696  let IsSingle = 1 in {
1697    defm V_MUL_LEGACY_F32 : VOP2_Real_e64_gfx90a <0x2a1>;
1698  }
1699} // End SubtargetPredicate = isGFX90APlus
1700
1701multiclass VOP2_Real_DOT_ACC_gfx9<bits<6> op> : VOP2_Real_e32_vi<op> {
1702  def _dpp_vi : VOP2_DPP<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;
1703}
1704
1705multiclass VOP2_Real_DOT_ACC_gfx10<bits<6> op> :
1706  VOP2_Real_e32_gfx10<op>,
1707  VOP2_Real_dpp_gfx10<op>,
1708  VOP2_Real_dpp8_gfx10<op>;
1709
1710let SubtargetPredicate = HasDot5Insts in {
1711  defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx9<0x37>;
1712  // NB: Opcode conflicts with V_DOT8C_I32_I4
1713  // This opcode exists in gfx 10.1* only
1714  defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx10<0x02>;
1715}
1716
1717let SubtargetPredicate = HasDot6Insts in {
1718  defm V_DOT4C_I32_I8  : VOP2_Real_DOT_ACC_gfx9<0x39>;
1719  defm V_DOT4C_I32_I8  : VOP2_Real_DOT_ACC_gfx10<0x0d>;
1720}
1721
1722let SubtargetPredicate = HasDot4Insts in {
1723  defm V_DOT2C_I32_I16 : VOP2_Real_DOT_ACC_gfx9<0x38>;
1724}
1725let SubtargetPredicate = HasDot3Insts in {
1726  defm V_DOT8C_I32_I4  : VOP2_Real_DOT_ACC_gfx9<0x3a>;
1727}
1728
1729let SubtargetPredicate = HasPkFmacF16Inst in {
1730defm V_PK_FMAC_F16 : VOP2_Real_e32_vi<0x3c>;
1731} // End SubtargetPredicate = HasPkFmacF16Inst
1732
1733let SubtargetPredicate = HasDot3Insts in {
1734  // NB: Opcode conflicts with V_DOT2C_F32_F16
1735  let DecoderNamespace = "GFX10_B" in
1736  defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx10<0x02>;
1737}
1738