1//===-- VOP1Instructions.td - Vector Instruction Defintions ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// VOP1 Classes 12//===----------------------------------------------------------------------===// 13 14class VOP1e <bits<8> op, VOPProfile P> : Enc32 { 15 bits<8> vdst; 16 bits<9> src0; 17 18 let Inst{8-0} = !if(P.HasSrc0, src0{8-0}, 0); 19 let Inst{16-9} = op; 20 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 21 let Inst{31-25} = 0x3f; //encoding 22} 23 24class VOP1_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> : 25 InstSI <P.Outs32, P.Ins32, "", pattern>, 26 VOP <opName>, 27 SIMCInstr <opName#"_e32", SIEncodingFamily.NONE>, 28 MnemonicAlias<opName#"_e32", opName> { 29 30 let isPseudo = 1; 31 let isCodeGenOnly = 1; 32 let UseNamedOperandTable = 1; 33 34 string Mnemonic = opName; 35 string AsmOperands = P.Asm32; 36 37 let Size = 4; 38 let mayLoad = 0; 39 let mayStore = 0; 40 let hasSideEffects = 0; 41 let SubtargetPredicate = isGCN; 42 43 let VOP1 = 1; 44 let VALU = 1; 45 let Uses = [EXEC]; 46 47 let AsmVariantName = AMDGPUAsmVariants.Default; 48 49 VOPProfile Pfl = P; 50} 51 52class VOP1_Real <VOP1_Pseudo ps, int EncodingFamily> : 53 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 54 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 55 56 let isPseudo = 0; 57 let isCodeGenOnly = 0; 58 59 // copy relevant pseudo op flags 60 let SubtargetPredicate = ps.SubtargetPredicate; 61 let AsmMatchConverter = ps.AsmMatchConverter; 62 let AsmVariantName = ps.AsmVariantName; 63 let Constraints = ps.Constraints; 64 let DisableEncoding = ps.DisableEncoding; 65 let TSFlags = ps.TSFlags; 66} 67 68class getVOP1Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies { 69 list<dag> ret = !if(P.HasModifiers, 70 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, 71 i32:$src0_modifiers, i1:$clamp, i32:$omod))))], 72 [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]); 73} 74 75multiclass VOP1Inst <string opName, VOPProfile P, 76 SDPatternOperator node = null_frag> { 77 def _e32 : VOP1_Pseudo <opName, P>; 78 def _e64 : VOP3_Pseudo <opName, P, getVOP1Pat64<node, P>.ret>; 79} 80 81//===----------------------------------------------------------------------===// 82// VOP1 Instructions 83//===----------------------------------------------------------------------===// 84 85let VOPAsmPrefer32Bit = 1 in { 86defm V_NOP : VOP1Inst <"v_nop", VOP_NONE>; 87} 88 89let isMoveImm = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in { 90defm V_MOV_B32 : VOP1Inst <"v_mov_b32", VOP_I32_I32>; 91} // End isMoveImm = 1 92 93// FIXME: Specify SchedRW for READFIRSTLANE_B32 94// TODO: Make profile for this, there is VOP3 encoding also 95def V_READFIRSTLANE_B32 : 96 InstSI <(outs SReg_32:$vdst), 97 (ins VGPR_32:$src0), 98 "v_readfirstlane_b32 $vdst, $src0", 99 [(set i32:$vdst, (int_amdgcn_readfirstlane i32:$src0))]>, 100 Enc32 { 101 102 let isCodeGenOnly = 0; 103 let UseNamedOperandTable = 1; 104 105 let Size = 4; 106 let mayLoad = 0; 107 let mayStore = 0; 108 let hasSideEffects = 0; 109 let SubtargetPredicate = isGCN; 110 111 let VOP1 = 1; 112 let VALU = 1; 113 let Uses = [EXEC]; 114 let isConvergent = 1; 115 116 bits<8> vdst; 117 bits<9> src0; 118 119 let Inst{8-0} = src0; 120 let Inst{16-9} = 0x2; 121 let Inst{24-17} = vdst; 122 let Inst{31-25} = 0x3f; //encoding 123} 124 125let SchedRW = [WriteQuarterRate32] in { 126defm V_CVT_I32_F64 : VOP1Inst <"v_cvt_i32_f64", VOP_I32_F64, fp_to_sint>; 127defm V_CVT_F64_I32 : VOP1Inst <"v_cvt_f64_i32", VOP_F64_I32, sint_to_fp>; 128defm V_CVT_F32_I32 : VOP1Inst <"v_cvt_f32_i32", VOP_F32_I32, sint_to_fp>; 129defm V_CVT_F32_U32 : VOP1Inst <"v_cvt_f32_u32", VOP_F32_I32, uint_to_fp>; 130defm V_CVT_U32_F32 : VOP1Inst <"v_cvt_u32_f32", VOP_I32_F32, fp_to_uint>; 131defm V_CVT_I32_F32 : VOP1Inst <"v_cvt_i32_f32", VOP_I32_F32, fp_to_sint>; 132defm V_CVT_F16_F32 : VOP1Inst <"v_cvt_f16_f32", VOP_I32_F32, fp_to_f16>; 133defm V_CVT_F32_F16 : VOP1Inst <"v_cvt_f32_f16", VOP_F32_I32, f16_to_fp>; 134defm V_CVT_RPI_I32_F32 : VOP1Inst <"v_cvt_rpi_i32_f32", VOP_I32_F32, cvt_rpi_i32_f32>; 135defm V_CVT_FLR_I32_F32 : VOP1Inst <"v_cvt_flr_i32_f32", VOP_I32_F32, cvt_flr_i32_f32>; 136defm V_CVT_OFF_F32_I4 : VOP1Inst <"v_cvt_off_f32_i4", VOP_F32_I32>; 137defm V_CVT_F32_F64 : VOP1Inst <"v_cvt_f32_f64", VOP_F32_F64, fpround>; 138defm V_CVT_F64_F32 : VOP1Inst <"v_cvt_f64_f32", VOP_F64_F32, fpextend>; 139defm V_CVT_F32_UBYTE0 : VOP1Inst <"v_cvt_f32_ubyte0", VOP_F32_I32, AMDGPUcvt_f32_ubyte0>; 140defm V_CVT_F32_UBYTE1 : VOP1Inst <"v_cvt_f32_ubyte1", VOP_F32_I32, AMDGPUcvt_f32_ubyte1>; 141defm V_CVT_F32_UBYTE2 : VOP1Inst <"v_cvt_f32_ubyte2", VOP_F32_I32, AMDGPUcvt_f32_ubyte2>; 142defm V_CVT_F32_UBYTE3 : VOP1Inst <"v_cvt_f32_ubyte3", VOP_F32_I32, AMDGPUcvt_f32_ubyte3>; 143defm V_CVT_U32_F64 : VOP1Inst <"v_cvt_u32_f64", VOP_I32_F64, fp_to_uint>; 144defm V_CVT_F64_U32 : VOP1Inst <"v_cvt_f64_u32", VOP_F64_I32, uint_to_fp>; 145} // End SchedRW = [WriteQuarterRate32] 146 147defm V_FRACT_F32 : VOP1Inst <"v_fract_f32", VOP_F32_F32, AMDGPUfract>; 148defm V_TRUNC_F32 : VOP1Inst <"v_trunc_f32", VOP_F32_F32, ftrunc>; 149defm V_CEIL_F32 : VOP1Inst <"v_ceil_f32", VOP_F32_F32, fceil>; 150defm V_RNDNE_F32 : VOP1Inst <"v_rndne_f32", VOP_F32_F32, frint>; 151defm V_FLOOR_F32 : VOP1Inst <"v_floor_f32", VOP_F32_F32, ffloor>; 152defm V_EXP_F32 : VOP1Inst <"v_exp_f32", VOP_F32_F32, fexp2>; 153 154let SchedRW = [WriteQuarterRate32] in { 155defm V_LOG_F32 : VOP1Inst <"v_log_f32", VOP_F32_F32, flog2>; 156defm V_RCP_F32 : VOP1Inst <"v_rcp_f32", VOP_F32_F32, AMDGPUrcp>; 157defm V_RCP_IFLAG_F32 : VOP1Inst <"v_rcp_iflag_f32", VOP_F32_F32>; 158defm V_RSQ_F32 : VOP1Inst <"v_rsq_f32", VOP_F32_F32, AMDGPUrsq>; 159} // End SchedRW = [WriteQuarterRate32] 160 161let SchedRW = [WriteDouble] in { 162defm V_RCP_F64 : VOP1Inst <"v_rcp_f64", VOP_F64_F64, AMDGPUrcp>; 163defm V_RSQ_F64 : VOP1Inst <"v_rsq_f64", VOP_F64_F64, AMDGPUrsq>; 164} // End SchedRW = [WriteDouble]; 165 166defm V_SQRT_F32 : VOP1Inst <"v_sqrt_f32", VOP_F32_F32, fsqrt>; 167 168let SchedRW = [WriteDouble] in { 169defm V_SQRT_F64 : VOP1Inst <"v_sqrt_f64", VOP_F64_F64, fsqrt>; 170} // End SchedRW = [WriteDouble] 171 172let SchedRW = [WriteQuarterRate32] in { 173defm V_SIN_F32 : VOP1Inst <"v_sin_f32", VOP_F32_F32, AMDGPUsin>; 174defm V_COS_F32 : VOP1Inst <"v_cos_f32", VOP_F32_F32, AMDGPUcos>; 175} // End SchedRW = [WriteQuarterRate32] 176 177defm V_NOT_B32 : VOP1Inst <"v_not_b32", VOP_I32_I32>; 178defm V_BFREV_B32 : VOP1Inst <"v_bfrev_b32", VOP_I32_I32>; 179defm V_FFBH_U32 : VOP1Inst <"v_ffbh_u32", VOP_I32_I32>; 180defm V_FFBL_B32 : VOP1Inst <"v_ffbl_b32", VOP_I32_I32>; 181defm V_FFBH_I32 : VOP1Inst <"v_ffbh_i32", VOP_I32_I32>; 182defm V_FREXP_EXP_I32_F64 : VOP1Inst <"v_frexp_exp_i32_f64", VOP_I32_F64, int_amdgcn_frexp_exp>; 183 184let SchedRW = [WriteDoubleAdd] in { 185defm V_FREXP_MANT_F64 : VOP1Inst <"v_frexp_mant_f64", VOP_F64_F64, int_amdgcn_frexp_mant>; 186defm V_FRACT_F64 : VOP1Inst <"v_fract_f64", VOP_F64_F64, AMDGPUfract>; 187} // End SchedRW = [WriteDoubleAdd] 188 189defm V_FREXP_EXP_I32_F32 : VOP1Inst <"v_frexp_exp_i32_f32", VOP_I32_F32, int_amdgcn_frexp_exp>; 190defm V_FREXP_MANT_F32 : VOP1Inst <"v_frexp_mant_f32", VOP_F32_F32, int_amdgcn_frexp_mant>; 191 192let VOPAsmPrefer32Bit = 1 in { 193defm V_CLREXCP : VOP1Inst <"v_clrexcp", VOP_NO_EXT<VOP_NONE>>; 194} 195 196// Restrict src0 to be VGPR 197def VOP_I32_VI32_NO_EXT : VOPProfile<[i32, i32, untyped, untyped]> { 198 let Src0RC32 = VRegSrc_32; 199 let Src0RC64 = VRegSrc_32; 200 201 let HasExt = 0; 202} 203 204// Special case because there are no true output operands. Hack vdst 205// to be a src operand. The custom inserter must add a tied implicit 206// def and use of the super register since there seems to be no way to 207// add an implicit def of a virtual register in tablegen. 208def VOP_MOVRELD : VOPProfile<[untyped, i32, untyped, untyped]> { 209 let Src0RC32 = VOPDstOperand<VGPR_32>; 210 let Src0RC64 = VOPDstOperand<VGPR_32>; 211 212 let Outs = (outs); 213 let Ins32 = (ins Src0RC32:$vdst, VSrc_b32:$src0); 214 let Ins64 = (ins Src0RC64:$vdst, VSrc_b32:$src0); 215 216 let InsDPP = (ins Src0RC32:$vdst, Src0RC32:$src0, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 217 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 218 let InsSDWA = (ins Src0RC32:$vdst, Int32InputMods:$src0_modifiers, VCSrc_b32:$src0, 219 clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused, 220 src0_sel:$src0_sel); 221 222 let Asm32 = getAsm32<1, 1>.ret; 223 let Asm64 = getAsm64<1, 1, 0>.ret; 224 let AsmDPP = getAsmDPP<1, 1, 0>.ret; 225 let AsmSDWA = getAsmSDWA<1, 1, 0>.ret; 226 227 let HasExt = 0; 228 let HasDst = 0; 229 let EmitDst = 1; // force vdst emission 230} 231 232let SubtargetPredicate = HasMovrel, Uses = [M0, EXEC] in { 233// v_movreld_b32 is a special case because the destination output 234 // register is really a source. It isn't actually read (but may be 235 // written), and is only to provide the base register to start 236 // indexing from. Tablegen seems to not let you define an implicit 237 // virtual register output for the super register being written into, 238 // so this must have an implicit def of the register added to it. 239defm V_MOVRELD_B32 : VOP1Inst <"v_movreld_b32", VOP_MOVRELD>; 240defm V_MOVRELS_B32 : VOP1Inst <"v_movrels_b32", VOP_I32_VI32_NO_EXT>; 241defm V_MOVRELSD_B32 : VOP1Inst <"v_movrelsd_b32", VOP_NO_EXT<VOP_I32_I32>>; 242} // End Uses = [M0, EXEC] 243 244// These instruction only exist on SI and CI 245let SubtargetPredicate = isSICI in { 246 247let SchedRW = [WriteQuarterRate32] in { 248defm V_MOV_FED_B32 : VOP1Inst <"v_mov_fed_b32", VOP_I32_I32>; 249defm V_LOG_CLAMP_F32 : VOP1Inst <"v_log_clamp_f32", VOP_F32_F32, int_amdgcn_log_clamp>; 250defm V_RCP_CLAMP_F32 : VOP1Inst <"v_rcp_clamp_f32", VOP_F32_F32>; 251defm V_RCP_LEGACY_F32 : VOP1Inst <"v_rcp_legacy_f32", VOP_F32_F32, AMDGPUrcp_legacy>; 252defm V_RSQ_CLAMP_F32 : VOP1Inst <"v_rsq_clamp_f32", VOP_F32_F32, AMDGPUrsq_clamp>; 253defm V_RSQ_LEGACY_F32 : VOP1Inst <"v_rsq_legacy_f32", VOP_F32_F32, AMDGPUrsq_legacy>; 254} // End SchedRW = [WriteQuarterRate32] 255 256let SchedRW = [WriteDouble] in { 257defm V_RCP_CLAMP_F64 : VOP1Inst <"v_rcp_clamp_f64", VOP_F64_F64>; 258defm V_RSQ_CLAMP_F64 : VOP1Inst <"v_rsq_clamp_f64", VOP_F64_F64, AMDGPUrsq_clamp>; 259} // End SchedRW = [WriteDouble] 260 261} // End SubtargetPredicate = isSICI 262 263 264let SubtargetPredicate = isCIVI in { 265 266let SchedRW = [WriteDoubleAdd] in { 267defm V_TRUNC_F64 : VOP1Inst <"v_trunc_f64", VOP_F64_F64, ftrunc>; 268defm V_CEIL_F64 : VOP1Inst <"v_ceil_f64", VOP_F64_F64, fceil>; 269defm V_FLOOR_F64 : VOP1Inst <"v_floor_f64", VOP_F64_F64, ffloor>; 270defm V_RNDNE_F64 : VOP1Inst <"v_rndne_f64", VOP_F64_F64, frint>; 271} // End SchedRW = [WriteDoubleAdd] 272 273let SchedRW = [WriteQuarterRate32] in { 274defm V_LOG_LEGACY_F32 : VOP1Inst <"v_log_legacy_f32", VOP_F32_F32>; 275defm V_EXP_LEGACY_F32 : VOP1Inst <"v_exp_legacy_f32", VOP_F32_F32>; 276} // End SchedRW = [WriteQuarterRate32] 277 278} // End SubtargetPredicate = isCIVI 279 280 281let SubtargetPredicate = isVI in { 282 283defm V_CVT_F16_U16 : VOP1Inst <"v_cvt_f16_u16", VOP_F16_I16, uint_to_fp>; 284defm V_CVT_F16_I16 : VOP1Inst <"v_cvt_f16_i16", VOP_F16_I16, sint_to_fp>; 285defm V_CVT_U16_F16 : VOP1Inst <"v_cvt_u16_f16", VOP_I16_F16, fp_to_uint>; 286defm V_CVT_I16_F16 : VOP1Inst <"v_cvt_i16_f16", VOP_I16_F16, fp_to_sint>; 287defm V_RCP_F16 : VOP1Inst <"v_rcp_f16", VOP_F16_F16, AMDGPUrcp>; 288defm V_SQRT_F16 : VOP1Inst <"v_sqrt_f16", VOP_F16_F16, fsqrt>; 289defm V_RSQ_F16 : VOP1Inst <"v_rsq_f16", VOP_F16_F16, AMDGPUrsq>; 290defm V_LOG_F16 : VOP1Inst <"v_log_f16", VOP_F16_F16, flog2>; 291defm V_EXP_F16 : VOP1Inst <"v_exp_f16", VOP_F16_F16, fexp2>; 292defm V_FREXP_MANT_F16 : VOP1Inst <"v_frexp_mant_f16", VOP_F16_F16, int_amdgcn_frexp_mant>; 293defm V_FREXP_EXP_I16_F16 : VOP1Inst <"v_frexp_exp_i16_f16", VOP_I16_F16, int_amdgcn_frexp_exp>; 294defm V_FLOOR_F16 : VOP1Inst <"v_floor_f16", VOP_F16_F16, ffloor>; 295defm V_CEIL_F16 : VOP1Inst <"v_ceil_f16", VOP_F16_F16, fceil>; 296defm V_TRUNC_F16 : VOP1Inst <"v_trunc_f16", VOP_F16_F16, ftrunc>; 297defm V_RNDNE_F16 : VOP1Inst <"v_rndne_f16", VOP_F16_F16, frint>; 298defm V_FRACT_F16 : VOP1Inst <"v_fract_f16", VOP_F16_F16, AMDGPUfract>; 299defm V_SIN_F16 : VOP1Inst <"v_sin_f16", VOP_F16_F16, AMDGPUsin>; 300defm V_COS_F16 : VOP1Inst <"v_cos_f16", VOP_F16_F16, AMDGPUcos>; 301 302} 303 304let Predicates = [isVI] in { 305 306def : Pat< 307 (f32 (f16_to_fp i16:$src)), 308 (V_CVT_F32_F16_e32 $src) 309>; 310 311def : Pat< 312 (i16 (fp_to_f16 f32:$src)), 313 (V_CVT_F16_F32_e32 $src) 314>; 315 316} 317 318//===----------------------------------------------------------------------===// 319// Target 320//===----------------------------------------------------------------------===// 321 322//===----------------------------------------------------------------------===// 323// SI 324//===----------------------------------------------------------------------===// 325 326multiclass VOP1_Real_si <bits<9> op> { 327 let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in { 328 def _e32_si : 329 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>, 330 VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>; 331 def _e64_si : 332 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 333 VOP3e_si <{1, 1, op{6-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 334 } 335} 336 337defm V_NOP : VOP1_Real_si <0x0>; 338defm V_MOV_B32 : VOP1_Real_si <0x1>; 339defm V_CVT_I32_F64 : VOP1_Real_si <0x3>; 340defm V_CVT_F64_I32 : VOP1_Real_si <0x4>; 341defm V_CVT_F32_I32 : VOP1_Real_si <0x5>; 342defm V_CVT_F32_U32 : VOP1_Real_si <0x6>; 343defm V_CVT_U32_F32 : VOP1_Real_si <0x7>; 344defm V_CVT_I32_F32 : VOP1_Real_si <0x8>; 345defm V_MOV_FED_B32 : VOP1_Real_si <0x9>; 346defm V_CVT_F16_F32 : VOP1_Real_si <0xa>; 347defm V_CVT_F32_F16 : VOP1_Real_si <0xb>; 348defm V_CVT_RPI_I32_F32 : VOP1_Real_si <0xc>; 349defm V_CVT_FLR_I32_F32 : VOP1_Real_si <0xd>; 350defm V_CVT_OFF_F32_I4 : VOP1_Real_si <0xe>; 351defm V_CVT_F32_F64 : VOP1_Real_si <0xf>; 352defm V_CVT_F64_F32 : VOP1_Real_si <0x10>; 353defm V_CVT_F32_UBYTE0 : VOP1_Real_si <0x11>; 354defm V_CVT_F32_UBYTE1 : VOP1_Real_si <0x12>; 355defm V_CVT_F32_UBYTE2 : VOP1_Real_si <0x13>; 356defm V_CVT_F32_UBYTE3 : VOP1_Real_si <0x14>; 357defm V_CVT_U32_F64 : VOP1_Real_si <0x15>; 358defm V_CVT_F64_U32 : VOP1_Real_si <0x16>; 359defm V_FRACT_F32 : VOP1_Real_si <0x20>; 360defm V_TRUNC_F32 : VOP1_Real_si <0x21>; 361defm V_CEIL_F32 : VOP1_Real_si <0x22>; 362defm V_RNDNE_F32 : VOP1_Real_si <0x23>; 363defm V_FLOOR_F32 : VOP1_Real_si <0x24>; 364defm V_EXP_F32 : VOP1_Real_si <0x25>; 365defm V_LOG_CLAMP_F32 : VOP1_Real_si <0x26>; 366defm V_LOG_F32 : VOP1_Real_si <0x27>; 367defm V_RCP_CLAMP_F32 : VOP1_Real_si <0x28>; 368defm V_RCP_LEGACY_F32 : VOP1_Real_si <0x29>; 369defm V_RCP_F32 : VOP1_Real_si <0x2a>; 370defm V_RCP_IFLAG_F32 : VOP1_Real_si <0x2b>; 371defm V_RSQ_CLAMP_F32 : VOP1_Real_si <0x2c>; 372defm V_RSQ_LEGACY_F32 : VOP1_Real_si <0x2d>; 373defm V_RSQ_F32 : VOP1_Real_si <0x2e>; 374defm V_RCP_F64 : VOP1_Real_si <0x2f>; 375defm V_RCP_CLAMP_F64 : VOP1_Real_si <0x30>; 376defm V_RSQ_F64 : VOP1_Real_si <0x31>; 377defm V_RSQ_CLAMP_F64 : VOP1_Real_si <0x32>; 378defm V_SQRT_F32 : VOP1_Real_si <0x33>; 379defm V_SQRT_F64 : VOP1_Real_si <0x34>; 380defm V_SIN_F32 : VOP1_Real_si <0x35>; 381defm V_COS_F32 : VOP1_Real_si <0x36>; 382defm V_NOT_B32 : VOP1_Real_si <0x37>; 383defm V_BFREV_B32 : VOP1_Real_si <0x38>; 384defm V_FFBH_U32 : VOP1_Real_si <0x39>; 385defm V_FFBL_B32 : VOP1_Real_si <0x3a>; 386defm V_FFBH_I32 : VOP1_Real_si <0x3b>; 387defm V_FREXP_EXP_I32_F64 : VOP1_Real_si <0x3c>; 388defm V_FREXP_MANT_F64 : VOP1_Real_si <0x3d>; 389defm V_FRACT_F64 : VOP1_Real_si <0x3e>; 390defm V_FREXP_EXP_I32_F32 : VOP1_Real_si <0x3f>; 391defm V_FREXP_MANT_F32 : VOP1_Real_si <0x40>; 392defm V_CLREXCP : VOP1_Real_si <0x41>; 393defm V_MOVRELD_B32 : VOP1_Real_si <0x42>; 394defm V_MOVRELS_B32 : VOP1_Real_si <0x43>; 395defm V_MOVRELSD_B32 : VOP1_Real_si <0x44>; 396 397//===----------------------------------------------------------------------===// 398// CI 399//===----------------------------------------------------------------------===// 400 401multiclass VOP1_Real_ci <bits<9> op> { 402 let AssemblerPredicates = [isCIOnly], DecoderNamespace = "CI" in { 403 def _e32_ci : 404 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>, 405 VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>; 406 def _e64_ci : 407 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 408 VOP3e_si <{1, 1, op{6-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 409 } 410} 411 412defm V_TRUNC_F64 : VOP1_Real_ci <0x17>; 413defm V_CEIL_F64 : VOP1_Real_ci <0x18>; 414defm V_FLOOR_F64 : VOP1_Real_ci <0x1A>; 415defm V_RNDNE_F64 : VOP1_Real_ci <0x19>; 416defm V_LOG_LEGACY_F32 : VOP1_Real_ci <0x45>; 417defm V_EXP_LEGACY_F32 : VOP1_Real_ci <0x46>; 418 419//===----------------------------------------------------------------------===// 420// VI 421//===----------------------------------------------------------------------===// 422 423class VOP1_SDWA <bits<8> op, VOP1_Pseudo ps, VOPProfile P = ps.Pfl> : 424 VOP_SDWA <ps.OpName, P> { 425 let Defs = ps.Defs; 426 let Uses = ps.Uses; 427 let SchedRW = ps.SchedRW; 428 let hasSideEffects = ps.hasSideEffects; 429 let AsmMatchConverter = "cvtSdwaVOP1"; 430 431 bits<8> vdst; 432 let Inst{8-0} = 0xf9; // sdwa 433 let Inst{16-9} = op; 434 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 435 let Inst{31-25} = 0x3f; // encoding 436} 437 438class VOP1_DPP <bits<8> op, VOP1_Pseudo ps, VOPProfile P = ps.Pfl> : 439 VOP_DPP <ps.OpName, P> { 440 let Defs = ps.Defs; 441 let Uses = ps.Uses; 442 let SchedRW = ps.SchedRW; 443 let hasSideEffects = ps.hasSideEffects; 444 445 bits<8> vdst; 446 let Inst{8-0} = 0xfa; // dpp 447 let Inst{16-9} = op; 448 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 449 let Inst{31-25} = 0x3f; //encoding 450} 451 452multiclass VOP1_Real_vi <bits<10> op> { 453 let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in { 454 def _e32_vi : 455 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>, 456 VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>; 457 def _e64_vi : 458 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 459 VOP3e_vi <!add(0x140, op), !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 460 } 461 462 // for now left sdwa/dpp only for asm/dasm 463 // TODO: add corresponding pseudo 464 def _sdwa : VOP1_SDWA<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32")>; 465 def _dpp : VOP1_DPP<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32")>; 466} 467 468defm V_NOP : VOP1_Real_vi <0x0>; 469defm V_MOV_B32 : VOP1_Real_vi <0x1>; 470defm V_CVT_I32_F64 : VOP1_Real_vi <0x3>; 471defm V_CVT_F64_I32 : VOP1_Real_vi <0x4>; 472defm V_CVT_F32_I32 : VOP1_Real_vi <0x5>; 473defm V_CVT_F32_U32 : VOP1_Real_vi <0x6>; 474defm V_CVT_U32_F32 : VOP1_Real_vi <0x7>; 475defm V_CVT_I32_F32 : VOP1_Real_vi <0x8>; 476defm V_CVT_F16_F32 : VOP1_Real_vi <0xa>; 477defm V_CVT_F32_F16 : VOP1_Real_vi <0xb>; 478defm V_CVT_RPI_I32_F32 : VOP1_Real_vi <0xc>; 479defm V_CVT_FLR_I32_F32 : VOP1_Real_vi <0xd>; 480defm V_CVT_OFF_F32_I4 : VOP1_Real_vi <0xe>; 481defm V_CVT_F32_F64 : VOP1_Real_vi <0xf>; 482defm V_CVT_F64_F32 : VOP1_Real_vi <0x10>; 483defm V_CVT_F32_UBYTE0 : VOP1_Real_vi <0x11>; 484defm V_CVT_F32_UBYTE1 : VOP1_Real_vi <0x12>; 485defm V_CVT_F32_UBYTE2 : VOP1_Real_vi <0x13>; 486defm V_CVT_F32_UBYTE3 : VOP1_Real_vi <0x14>; 487defm V_CVT_U32_F64 : VOP1_Real_vi <0x15>; 488defm V_CVT_F64_U32 : VOP1_Real_vi <0x16>; 489defm V_FRACT_F32 : VOP1_Real_vi <0x1b>; 490defm V_TRUNC_F32 : VOP1_Real_vi <0x1c>; 491defm V_CEIL_F32 : VOP1_Real_vi <0x1d>; 492defm V_RNDNE_F32 : VOP1_Real_vi <0x1e>; 493defm V_FLOOR_F32 : VOP1_Real_vi <0x1f>; 494defm V_EXP_F32 : VOP1_Real_vi <0x20>; 495defm V_LOG_F32 : VOP1_Real_vi <0x21>; 496defm V_RCP_F32 : VOP1_Real_vi <0x22>; 497defm V_RCP_IFLAG_F32 : VOP1_Real_vi <0x23>; 498defm V_RSQ_F32 : VOP1_Real_vi <0x24>; 499defm V_RCP_F64 : VOP1_Real_vi <0x25>; 500defm V_RSQ_F64 : VOP1_Real_vi <0x26>; 501defm V_SQRT_F32 : VOP1_Real_vi <0x27>; 502defm V_SQRT_F64 : VOP1_Real_vi <0x28>; 503defm V_SIN_F32 : VOP1_Real_vi <0x29>; 504defm V_COS_F32 : VOP1_Real_vi <0x2a>; 505defm V_NOT_B32 : VOP1_Real_vi <0x2b>; 506defm V_BFREV_B32 : VOP1_Real_vi <0x2c>; 507defm V_FFBH_U32 : VOP1_Real_vi <0x2d>; 508defm V_FFBL_B32 : VOP1_Real_vi <0x2e>; 509defm V_FFBH_I32 : VOP1_Real_vi <0x2f>; 510defm V_FREXP_EXP_I32_F64 : VOP1_Real_vi <0x30>; 511defm V_FREXP_MANT_F64 : VOP1_Real_vi <0x31>; 512defm V_FRACT_F64 : VOP1_Real_vi <0x32>; 513defm V_FREXP_EXP_I32_F32 : VOP1_Real_vi <0x33>; 514defm V_FREXP_MANT_F32 : VOP1_Real_vi <0x34>; 515defm V_CLREXCP : VOP1_Real_vi <0x35>; 516defm V_MOVRELD_B32 : VOP1_Real_vi <0x36>; 517defm V_MOVRELS_B32 : VOP1_Real_vi <0x37>; 518defm V_MOVRELSD_B32 : VOP1_Real_vi <0x38>; 519defm V_TRUNC_F64 : VOP1_Real_vi <0x17>; 520defm V_CEIL_F64 : VOP1_Real_vi <0x18>; 521defm V_FLOOR_F64 : VOP1_Real_vi <0x1A>; 522defm V_RNDNE_F64 : VOP1_Real_vi <0x19>; 523defm V_LOG_LEGACY_F32 : VOP1_Real_vi <0x4c>; 524defm V_EXP_LEGACY_F32 : VOP1_Real_vi <0x4b>; 525defm V_CVT_F16_U16 : VOP1_Real_vi <0x39>; 526defm V_CVT_F16_I16 : VOP1_Real_vi <0x3a>; 527defm V_CVT_U16_F16 : VOP1_Real_vi <0x3b>; 528defm V_CVT_I16_F16 : VOP1_Real_vi <0x3c>; 529defm V_RCP_F16 : VOP1_Real_vi <0x3d>; 530defm V_SQRT_F16 : VOP1_Real_vi <0x3e>; 531defm V_RSQ_F16 : VOP1_Real_vi <0x3f>; 532defm V_LOG_F16 : VOP1_Real_vi <0x40>; 533defm V_EXP_F16 : VOP1_Real_vi <0x41>; 534defm V_FREXP_MANT_F16 : VOP1_Real_vi <0x42>; 535defm V_FREXP_EXP_I16_F16 : VOP1_Real_vi <0x43>; 536defm V_FLOOR_F16 : VOP1_Real_vi <0x44>; 537defm V_CEIL_F16 : VOP1_Real_vi <0x45>; 538defm V_TRUNC_F16 : VOP1_Real_vi <0x46>; 539defm V_RNDNE_F16 : VOP1_Real_vi <0x47>; 540defm V_FRACT_F16 : VOP1_Real_vi <0x48>; 541defm V_SIN_F16 : VOP1_Real_vi <0x49>; 542defm V_COS_F16 : VOP1_Real_vi <0x4a>; 543 544 545// Copy of v_mov_b32 with $vdst as a use operand for use with VGPR 546// indexing mode. vdst can't be treated as a def for codegen purposes, 547// and an implicit use and def of the super register should be added. 548def V_MOV_B32_indirect : VPseudoInstSI<(outs), 549 (ins getVALUDstForVT<i32>.ret:$vdst, getVOPSrc0ForVT<i32>.ret:$src0)>, 550 PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT<i32>.ret:$vdst, 551 getVOPSrc0ForVT<i32>.ret:$src0)> { 552 let VOP1 = 1; 553 let SubtargetPredicate = isVI; 554} 555 556// This is a pseudo variant of the v_movreld_b32 instruction in which the 557// vector operand appears only twice, once as def and once as use. Using this 558// pseudo avoids problems with the Two Address instructions pass. 559class V_MOVRELD_B32_pseudo<RegisterClass rc> : VPseudoInstSI < 560 (outs rc:$vdst), 561 (ins rc:$vsrc, VSrc_b32:$val, i32imm:$offset)> { 562 let VOP1 = 1; 563 564 let Constraints = "$vsrc = $vdst"; 565 let Uses = [M0, EXEC]; 566 567 let SubtargetPredicate = HasMovrel; 568} 569 570def V_MOVRELD_B32_V1 : V_MOVRELD_B32_pseudo<VGPR_32>; 571def V_MOVRELD_B32_V2 : V_MOVRELD_B32_pseudo<VReg_64>; 572def V_MOVRELD_B32_V4 : V_MOVRELD_B32_pseudo<VReg_128>; 573def V_MOVRELD_B32_V8 : V_MOVRELD_B32_pseudo<VReg_256>; 574def V_MOVRELD_B32_V16 : V_MOVRELD_B32_pseudo<VReg_512>; 575 576let Predicates = [isVI] in { 577 578def : Pat < 579 (i32 (int_amdgcn_mov_dpp i32:$src, imm:$dpp_ctrl, imm:$row_mask, imm:$bank_mask, 580 imm:$bound_ctrl)), 581 (V_MOV_B32_dpp $src, (as_i32imm $dpp_ctrl), (as_i32imm $row_mask), 582 (as_i32imm $bank_mask), (as_i1imm $bound_ctrl)) 583>; 584 585 586def : Pat< 587 (i32 (anyext i16:$src)), 588 (COPY $src) 589>; 590 591def : Pat< 592 (i64 (anyext i16:$src)), 593 (REG_SEQUENCE VReg_64, 594 (i32 (COPY $src)), sub0, 595 (V_MOV_B32_e32 (i32 0)), sub1) 596>; 597 598def : Pat< 599 (i16 (trunc i32:$src)), 600 (COPY $src) 601>; 602 603def : Pat< 604 (i1 (trunc i16:$src)), 605 (COPY $src) 606>; 607 608 609def : Pat < 610 (i16 (trunc i64:$src)), 611 (EXTRACT_SUBREG $src, sub0) 612>; 613 614} // End Predicates = [isVI] 615