1//===-- VIInstrFormats.td - VI Instruction Encodings ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// VI Instruction format definitions.
11//
12//===----------------------------------------------------------------------===//
13
14class MUBUFe_vi <bits<7> op> : Enc64 {
15  bits<12> offset;
16  bits<1> offen;
17  bits<1> idxen;
18  bits<1> glc;
19  bits<1> lds;
20  bits<8> vaddr;
21  bits<8> vdata;
22  bits<7> srsrc;
23  bits<1> slc;
24  bits<1> tfe;
25  bits<8> soffset;
26
27  let Inst{11-0} = offset;
28  let Inst{12} = offen;
29  let Inst{13} = idxen;
30  let Inst{14} = glc;
31  let Inst{16} = lds;
32  let Inst{17} = slc;
33  let Inst{24-18} = op;
34  let Inst{31-26} = 0x38; //encoding
35  let Inst{39-32} = vaddr;
36  let Inst{47-40} = vdata;
37  let Inst{52-48} = srsrc{6-2};
38  let Inst{55} = tfe;
39  let Inst{63-56} = soffset;
40}
41
42class MTBUFe_vi <bits<4> op> : Enc64 {
43  bits<12> offset;
44  bits<1>  offen;
45  bits<1>  idxen;
46  bits<1>  glc;
47  bits<4>  dfmt;
48  bits<3>  nfmt;
49  bits<8>  vaddr;
50  bits<8>  vdata;
51  bits<7>  srsrc;
52  bits<1>  slc;
53  bits<1>  tfe;
54  bits<8>  soffset;
55
56  let Inst{11-0}  = offset;
57  let Inst{12}    = offen;
58  let Inst{13}    = idxen;
59  let Inst{14}    = glc;
60  let Inst{18-15} = op;
61  let Inst{22-19} = dfmt;
62  let Inst{25-23} = nfmt;
63  let Inst{31-26} = 0x3a; //encoding
64  let Inst{39-32} = vaddr;
65  let Inst{47-40} = vdata;
66  let Inst{52-48} = srsrc{6-2};
67  let Inst{54}    = slc;
68  let Inst{55}    = tfe;
69  let Inst{63-56} = soffset;
70}
71
72class VOP3a_vi <bits<10> op> : Enc64 {
73  bits<2> src0_modifiers;
74  bits<9> src0;
75  bits<2> src1_modifiers;
76  bits<9> src1;
77  bits<2> src2_modifiers;
78  bits<9> src2;
79  bits<1> clamp;
80  bits<2> omod;
81
82  let Inst{8}     = src0_modifiers{1};
83  let Inst{9}     = src1_modifiers{1};
84  let Inst{10}    = src2_modifiers{1};
85  let Inst{15}    = clamp;
86  let Inst{25-16} = op;
87  let Inst{31-26} = 0x34; //encoding
88  let Inst{40-32} = src0;
89  let Inst{49-41} = src1;
90  let Inst{58-50} = src2;
91  let Inst{60-59} = omod;
92  let Inst{61} = src0_modifiers{0};
93  let Inst{62} = src1_modifiers{0};
94  let Inst{63} = src2_modifiers{0};
95}
96
97class VOP3e_vi <bits<10> op> : VOP3a_vi <op> {
98  bits<8> vdst;
99
100  let Inst{7-0} = vdst;
101}
102
103// Encoding used for VOPC instructions encoded as VOP3
104// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
105class VOP3ce_vi <bits<10> op> : VOP3a_vi <op> {
106  bits<8> sdst;
107
108  let Inst{7-0} = sdst;
109}
110
111class VOP3be_vi <bits<10> op> : Enc64 {
112  bits<8> vdst;
113  bits<2> src0_modifiers;
114  bits<9> src0;
115  bits<2> src1_modifiers;
116  bits<9> src1;
117  bits<2> src2_modifiers;
118  bits<9> src2;
119  bits<7> sdst;
120  bits<2> omod;
121  bits<1> clamp;
122
123  let Inst{7-0} = vdst;
124  let Inst{14-8} = sdst;
125  let Inst{15} = clamp;
126  let Inst{25-16} = op;
127  let Inst{31-26} = 0x34; //encoding
128  let Inst{40-32} = src0;
129  let Inst{49-41} = src1;
130  let Inst{58-50} = src2;
131  let Inst{60-59} = omod;
132  let Inst{61} = src0_modifiers{0};
133  let Inst{62} = src1_modifiers{0};
134  let Inst{63} = src2_modifiers{0};
135}
136
137class VOP_DPP <dag outs, dag ins, string asm, list<dag> pattern, bit HasMods = 0> :
138    VOPAnyCommon <outs, ins, asm, pattern> {
139  let DPP = 1;
140  let Size = 8;
141
142  let AsmMatchConverter = !if(!eq(HasMods,1), "cvtDPP", "");
143  let AsmVariantName = AMDGPUAsmVariants.DPP;
144}
145
146class VOP_DPPe : Enc64 {
147  bits<2> src0_modifiers;
148  bits<8> src0;
149  bits<2> src1_modifiers;
150  bits<9> dpp_ctrl;
151  bits<1> bound_ctrl;
152  bits<4> bank_mask;
153  bits<4> row_mask;
154
155  let Inst{39-32} = src0;
156  let Inst{48-40} = dpp_ctrl;
157  let Inst{51}    = bound_ctrl;
158  let Inst{52}    = src0_modifiers{0}; // src0_neg
159  let Inst{53}    = src0_modifiers{1}; // src0_abs
160  let Inst{54}    = src1_modifiers{0}; // src1_neg
161  let Inst{55}    = src1_modifiers{1}; // src1_abs
162  let Inst{59-56} = bank_mask;
163  let Inst{63-60} = row_mask;
164}
165
166class VOP1_DPPe <bits<8> op> : VOP_DPPe {
167  bits<8> vdst;
168
169  let Inst{8-0} = 0xfa; // dpp
170  let Inst{16-9} = op;
171  let Inst{24-17} = vdst;
172  let Inst{31-25} = 0x3f; //encoding
173}
174
175class VOP2_DPPe <bits<6> op> : VOP_DPPe {
176  bits<8> vdst;
177  bits<8> src1;
178
179  let Inst{8-0} = 0xfa; //dpp
180  let Inst{16-9} = src1;
181  let Inst{24-17} = vdst;
182  let Inst{30-25} = op;
183  let Inst{31} = 0x0; //encoding
184}
185
186class VOP_SDWA <dag outs, dag ins, string asm, list<dag> pattern, bit HasMods = 0> :
187    VOPAnyCommon <outs, ins, asm, pattern> {
188  let SDWA = 1;
189  let Size = 8;
190  let AsmVariantName = AMDGPUAsmVariants.SDWA;
191}
192
193class VOP_SDWAe : Enc64 {
194  bits<8> src0;
195  bits<3> src0_sel;
196  bits<2> src0_fmodifiers; // {abs,neg}
197  bits<1> src0_imodifiers; // sext
198  bits<3> src1_sel;
199  bits<2> src1_fmodifiers;
200  bits<1> src1_imodifiers;
201  bits<3> dst_sel;
202  bits<2> dst_unused;
203  bits<1> clamp;
204
205  let Inst{39-32} = src0;
206  let Inst{42-40} = dst_sel;
207  let Inst{44-43} = dst_unused;
208  let Inst{45} = clamp;
209  let Inst{50-48} = src0_sel;
210  let Inst{53-52} = src0_fmodifiers;
211  let Inst{51} = src0_imodifiers;
212  let Inst{58-56} = src1_sel;
213  let Inst{61-60} = src1_fmodifiers;
214  let Inst{59} = src1_imodifiers;
215}
216
217class VOP1_SDWAe <bits<8> op> : VOP_SDWAe {
218  bits<8> vdst;
219
220  let Inst{8-0} = 0xf9; // sdwa
221  let Inst{16-9} = op;
222  let Inst{24-17} = vdst;
223  let Inst{31-25} = 0x3f; // encoding
224}
225
226class VOP2_SDWAe <bits<6> op> : VOP_SDWAe {
227  bits<8> vdst;
228  bits<8> src1;
229
230  let Inst{8-0} = 0xf9; // sdwa
231  let Inst{16-9} = src1;
232  let Inst{24-17} = vdst;
233  let Inst{30-25} = op;
234  let Inst{31} = 0x0; // encoding
235}
236
237class VOPC_SDWAe <bits<8> op> : VOP_SDWAe {
238  bits<8> src1;
239
240  let Inst{8-0} = 0xf9; // sdwa
241  let Inst{16-9} = src1;
242  let Inst{24-17} = op;
243  let Inst{31-25} = 0x3e; // encoding
244
245  // VOPC disallows dst_sel and dst_unused as they have no effect on destination
246  let Inst{42-40} = 0x6;
247  let Inst{44-43} = 0x2;
248}
249
250class EXPe_vi : EXPe {
251  let Inst{31-26} = 0x31; //encoding
252}
253
254class VINTRPe_vi <bits<2> op> : VINTRPe <op> {
255  let Inst{31-26} = 0x35; // encoding
256}
257