1//===-- VIInstrFormats.td - VI Instruction Encodings ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// VI Instruction format definitions.
11//
12//===----------------------------------------------------------------------===//
13
14class DSe_vi <bits<8> op> : Enc64 {
15  bits<8> vdst;
16  bits<1> gds;
17  bits<8> addr;
18  bits<8> data0;
19  bits<8> data1;
20  bits<8> offset0;
21  bits<8> offset1;
22
23  let Inst{7-0} = offset0;
24  let Inst{15-8} = offset1;
25  let Inst{16} = gds;
26  let Inst{24-17} = op;
27  let Inst{31-26} = 0x36; //encoding
28  let Inst{39-32} = addr;
29  let Inst{47-40} = data0;
30  let Inst{55-48} = data1;
31  let Inst{63-56} = vdst;
32}
33
34class MUBUFe_vi <bits<7> op> : Enc64 {
35  bits<12> offset;
36  bits<1> offen;
37  bits<1> idxen;
38  bits<1> glc;
39  bits<1> lds;
40  bits<8> vaddr;
41  bits<8> vdata;
42  bits<7> srsrc;
43  bits<1> slc;
44  bits<1> tfe;
45  bits<8> soffset;
46
47  let Inst{11-0} = offset;
48  let Inst{12} = offen;
49  let Inst{13} = idxen;
50  let Inst{14} = glc;
51  let Inst{16} = lds;
52  let Inst{17} = slc;
53  let Inst{24-18} = op;
54  let Inst{31-26} = 0x38; //encoding
55  let Inst{39-32} = vaddr;
56  let Inst{47-40} = vdata;
57  let Inst{52-48} = srsrc{6-2};
58  let Inst{55} = tfe;
59  let Inst{63-56} = soffset;
60}
61
62class MTBUFe_vi <bits<4> op> : Enc64 {
63  bits<12> offset;
64  bits<1>  offen;
65  bits<1>  idxen;
66  bits<1>  glc;
67  bits<4>  dfmt;
68  bits<3>  nfmt;
69  bits<8>  vaddr;
70  bits<8>  vdata;
71  bits<7>  srsrc;
72  bits<1>  slc;
73  bits<1>  tfe;
74  bits<8>  soffset;
75
76  let Inst{11-0}  = offset;
77  let Inst{12}    = offen;
78  let Inst{13}    = idxen;
79  let Inst{14}    = glc;
80  let Inst{18-15} = op;
81  let Inst{22-19} = dfmt;
82  let Inst{25-23} = nfmt;
83  let Inst{31-26} = 0x3a; //encoding
84  let Inst{39-32} = vaddr;
85  let Inst{47-40} = vdata;
86  let Inst{52-48} = srsrc{6-2};
87  let Inst{54}    = slc;
88  let Inst{55}    = tfe;
89  let Inst{63-56} = soffset;
90}
91
92class SMEMe_vi <bits<8> op, bit imm> : Enc64 {
93  bits<7>  sbase;
94  bits<7>  sdata;
95  bits<1>  glc;
96  bits<20> offset;
97
98  let Inst{5-0}   = sbase{6-1};
99  let Inst{12-6}  = sdata;
100  let Inst{16}    = glc;
101  let Inst{17}    = imm;
102  let Inst{25-18} = op;
103  let Inst{31-26} = 0x30; //encoding
104  let Inst{51-32} = offset;
105}
106
107class VOP3a_vi <bits<10> op> : Enc64 {
108  bits<2> src0_modifiers;
109  bits<9> src0;
110  bits<2> src1_modifiers;
111  bits<9> src1;
112  bits<2> src2_modifiers;
113  bits<9> src2;
114  bits<1> clamp;
115  bits<2> omod;
116
117  let Inst{8}     = src0_modifiers{1};
118  let Inst{9}     = src1_modifiers{1};
119  let Inst{10}    = src2_modifiers{1};
120  let Inst{15}    = clamp;
121  let Inst{25-16} = op;
122  let Inst{31-26} = 0x34; //encoding
123  let Inst{40-32} = src0;
124  let Inst{49-41} = src1;
125  let Inst{58-50} = src2;
126  let Inst{60-59} = omod;
127  let Inst{61} = src0_modifiers{0};
128  let Inst{62} = src1_modifiers{0};
129  let Inst{63} = src2_modifiers{0};
130}
131
132class VOP3e_vi <bits<10> op> : VOP3a_vi <op> {
133  bits<8> vdst;
134
135  let Inst{7-0} = vdst;
136}
137
138// Encoding used for VOPC instructions encoded as VOP3
139// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
140class VOP3ce_vi <bits<10> op> : VOP3a_vi <op> {
141  bits<8> sdst;
142
143  let Inst{7-0} = sdst;
144}
145
146class VOP3be_vi <bits<10> op> : Enc64 {
147  bits<8> vdst;
148  bits<2> src0_modifiers;
149  bits<9> src0;
150  bits<2> src1_modifiers;
151  bits<9> src1;
152  bits<2> src2_modifiers;
153  bits<9> src2;
154  bits<7> sdst;
155  bits<2> omod;
156  bits<1> clamp;
157
158  let Inst{7-0} = vdst;
159  let Inst{14-8} = sdst;
160  let Inst{15} = clamp;
161  let Inst{25-16} = op;
162  let Inst{31-26} = 0x34; //encoding
163  let Inst{40-32} = src0;
164  let Inst{49-41} = src1;
165  let Inst{58-50} = src2;
166  let Inst{60-59} = omod;
167  let Inst{61} = src0_modifiers{0};
168  let Inst{62} = src1_modifiers{0};
169  let Inst{63} = src2_modifiers{0};
170}
171
172class VOP_DPP <dag outs, dag ins, string asm, list<dag> pattern> :
173    VOPAnyCommon <outs, ins, asm, pattern> {
174  let Size = 8;
175}
176
177class VOP_DPPe : Enc64 {
178  bits<2> src0_modifiers;
179  bits<8> src0;
180  bits<2> src1_modifiers;
181  bits<9> dpp_ctrl;
182  bits<1> bound_ctrl;
183  bits<4> bank_mask;
184  bits<4> row_mask;
185
186  let Inst{39-32} = src0;
187  let Inst{48-40} = dpp_ctrl;
188  let Inst{51}    = bound_ctrl;
189  let Inst{52}    = src0_modifiers{0}; // src0_neg
190  let Inst{53}    = src0_modifiers{1}; // src0_abs
191  let Inst{54}    = src1_modifiers{0}; // src1_neg
192  let Inst{55}    = src1_modifiers{1}; // src1_abs
193  let Inst{59-56} = bank_mask;
194  let Inst{63-60} = row_mask;
195}
196
197class VOP1_DPPe <bits<8> op> : VOP_DPPe {
198  bits<8> vdst;
199
200  let Inst{8-0} = 0xfa; // dpp
201  let Inst{16-9} = op;
202  let Inst{24-17} = vdst;
203  let Inst{31-25} = 0x3f; //encoding
204}
205
206class VOP2_DPPe <bits<6> op> : Enc32 {
207  bits<8> vdst;
208  bits<8> src1;
209
210  let Inst{8-0} = 0xfa; //dpp
211  let Inst{16-9} = src1;
212  let Inst{24-17} = vdst;
213  let Inst{30-25} = op;
214  let Inst{31} = 0x0; //encoding
215}
216
217class EXPe_vi : EXPe {
218  let Inst{31-26} = 0x31; //encoding
219}
220
221class VINTRPe_vi <bits<2> op> : VINTRPe <op> {
222  let Inst{31-26} = 0x35; // encoding
223}
224