1 //===-- AMDGPUPALMetadata.cpp - Accumulate and print AMDGPU PAL metadata -===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// 11 /// This class has methods called by AMDGPUAsmPrinter to accumulate and print 12 /// the PAL metadata. 13 // 14 //===----------------------------------------------------------------------===// 15 // 16 17 #include "AMDGPUPALMetadata.h" 18 #include "AMDGPU.h" 19 #include "AMDGPUAsmPrinter.h" 20 #include "MCTargetDesc/AMDGPUTargetStreamer.h" 21 #include "SIDefines.h" 22 #include "llvm/BinaryFormat/ELF.h" 23 #include "llvm/IR/CallingConv.h" 24 #include "llvm/IR/Constants.h" 25 #include "llvm/IR/Module.h" 26 #include "llvm/Support/AMDGPUMetadata.h" 27 #include "llvm/Support/EndianStream.h" 28 29 using namespace llvm; 30 using namespace llvm::AMDGPU; 31 32 // Read the PAL metadata from IR metadata, where it was put by the frontend. 33 void AMDGPUPALMetadata::readFromIR(Module &M) { 34 auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata.msgpack"); 35 if (NamedMD && NamedMD->getNumOperands()) { 36 // This is the new msgpack format for metadata. It is a NamedMD containing 37 // an MDTuple containing an MDString containing the msgpack data. 38 BlobType = ELF::NT_AMDGPU_METADATA; 39 auto MDN = dyn_cast<MDTuple>(NamedMD->getOperand(0)); 40 if (MDN && MDN->getNumOperands()) { 41 if (auto MDS = dyn_cast<MDString>(MDN->getOperand(0))) 42 setFromMsgPackBlob(MDS->getString()); 43 } 44 return; 45 } 46 BlobType = ELF::NT_AMD_AMDGPU_PAL_METADATA; 47 NamedMD = M.getNamedMetadata("amdgpu.pal.metadata"); 48 if (!NamedMD || !NamedMD->getNumOperands()) { 49 // Emit msgpack metadata by default 50 BlobType = ELF::NT_AMDGPU_METADATA; 51 return; 52 } 53 // This is the old reg=value pair format for metadata. It is a NamedMD 54 // containing an MDTuple containing a number of MDNodes each of which is an 55 // integer value, and each two integer values forms a key=value pair that we 56 // store as Registers[key]=value in the map. 57 auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0)); 58 if (!Tuple) 59 return; 60 for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) { 61 auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I)); 62 auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1)); 63 if (!Key || !Val) 64 continue; 65 setRegister(Key->getZExtValue(), Val->getZExtValue()); 66 } 67 } 68 69 // Set PAL metadata from a binary blob from the applicable .note record. 70 // Returns false if bad format. Blob must remain valid for the lifetime of the 71 // Metadata. 72 bool AMDGPUPALMetadata::setFromBlob(unsigned Type, StringRef Blob) { 73 BlobType = Type; 74 if (Type == ELF::NT_AMD_AMDGPU_PAL_METADATA) 75 return setFromLegacyBlob(Blob); 76 return setFromMsgPackBlob(Blob); 77 } 78 79 // Set PAL metadata from legacy (array of key=value pairs) blob. 80 bool AMDGPUPALMetadata::setFromLegacyBlob(StringRef Blob) { 81 auto Data = reinterpret_cast<const uint32_t *>(Blob.data()); 82 for (unsigned I = 0; I != Blob.size() / sizeof(uint32_t) / 2; ++I) 83 setRegister(Data[I * 2], Data[I * 2 + 1]); 84 return true; 85 } 86 87 // Set PAL metadata from msgpack blob. 88 bool AMDGPUPALMetadata::setFromMsgPackBlob(StringRef Blob) { 89 msgpack::Reader Reader(Blob); 90 return MsgPackDoc.readFromBlob(Blob, /*Multi=*/false); 91 } 92 93 // Given the calling convention, calculate the register number for rsrc1. In 94 // principle the register number could change in future hardware, but we know 95 // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so 96 // we can use fixed values. 97 static unsigned getRsrc1Reg(CallingConv::ID CC) { 98 switch (CC) { 99 default: 100 return PALMD::R_2E12_COMPUTE_PGM_RSRC1; 101 case CallingConv::AMDGPU_LS: 102 return PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS; 103 case CallingConv::AMDGPU_HS: 104 return PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS; 105 case CallingConv::AMDGPU_ES: 106 return PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES; 107 case CallingConv::AMDGPU_GS: 108 return PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS; 109 case CallingConv::AMDGPU_VS: 110 return PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS; 111 case CallingConv::AMDGPU_PS: 112 return PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS; 113 } 114 } 115 116 // Calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used 117 // with a constant offset to access any non-register shader-specific PAL 118 // metadata key. 119 static unsigned getScratchSizeKey(CallingConv::ID CC) { 120 switch (CC) { 121 case CallingConv::AMDGPU_PS: 122 return PALMD::Key::PS_SCRATCH_SIZE; 123 case CallingConv::AMDGPU_VS: 124 return PALMD::Key::VS_SCRATCH_SIZE; 125 case CallingConv::AMDGPU_GS: 126 return PALMD::Key::GS_SCRATCH_SIZE; 127 case CallingConv::AMDGPU_ES: 128 return PALMD::Key::ES_SCRATCH_SIZE; 129 case CallingConv::AMDGPU_HS: 130 return PALMD::Key::HS_SCRATCH_SIZE; 131 case CallingConv::AMDGPU_LS: 132 return PALMD::Key::LS_SCRATCH_SIZE; 133 default: 134 return PALMD::Key::CS_SCRATCH_SIZE; 135 } 136 } 137 138 // Set the rsrc1 register in the metadata for a particular shader stage. 139 // In fact this ORs the value into any previous setting of the register. 140 void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, unsigned Val) { 141 setRegister(getRsrc1Reg(CC), Val); 142 } 143 144 // Set the rsrc2 register in the metadata for a particular shader stage. 145 // In fact this ORs the value into any previous setting of the register. 146 void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, unsigned Val) { 147 setRegister(getRsrc1Reg(CC) + 1, Val); 148 } 149 150 // Set the SPI_PS_INPUT_ENA register in the metadata. 151 // In fact this ORs the value into any previous setting of the register. 152 void AMDGPUPALMetadata::setSpiPsInputEna(unsigned Val) { 153 setRegister(PALMD::R_A1B3_SPI_PS_INPUT_ENA, Val); 154 } 155 156 // Set the SPI_PS_INPUT_ADDR register in the metadata. 157 // In fact this ORs the value into any previous setting of the register. 158 void AMDGPUPALMetadata::setSpiPsInputAddr(unsigned Val) { 159 setRegister(PALMD::R_A1B4_SPI_PS_INPUT_ADDR, Val); 160 } 161 162 // Get a register from the metadata, or 0 if not currently set. 163 unsigned AMDGPUPALMetadata::getRegister(unsigned Reg) { 164 auto Regs = getRegisters(); 165 auto It = Regs.find(MsgPackDoc.getNode(Reg)); 166 if (It == Regs.end()) 167 return 0; 168 auto N = It->second; 169 if (N.getKind() != msgpack::Type::UInt) 170 return 0; 171 return N.getUInt(); 172 } 173 174 // Set a register in the metadata. 175 // In fact this ORs the value into any previous setting of the register. 176 void AMDGPUPALMetadata::setRegister(unsigned Reg, unsigned Val) { 177 if (!isLegacy()) { 178 // In the new MsgPack format, ignore register numbered >= 0x10000000. It 179 // is a PAL ABI pseudo-register in the old non-MsgPack format. 180 if (Reg >= 0x10000000) 181 return; 182 } 183 auto &N = getRegisters()[MsgPackDoc.getNode(Reg)]; 184 if (N.getKind() == msgpack::Type::UInt) 185 Val |= N.getUInt(); 186 N = N.getDocument()->getNode(Val); 187 } 188 189 // Set the entry point name for one shader. 190 void AMDGPUPALMetadata::setEntryPoint(unsigned CC, StringRef Name) { 191 if (isLegacy()) 192 return; 193 // Msgpack format. 194 getHwStage(CC)[".entry_point"] = MsgPackDoc.getNode(Name, /*Copy=*/true); 195 } 196 197 // Set the number of used vgprs in the metadata. This is an optional 198 // advisory record for logging etc; wave dispatch actually uses the rsrc1 199 // register for the shader stage to determine the number of vgprs to 200 // allocate. 201 void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, unsigned Val) { 202 if (isLegacy()) { 203 // Old non-msgpack format. 204 unsigned NumUsedVgprsKey = getScratchSizeKey(CC) + 205 PALMD::Key::VS_NUM_USED_VGPRS - 206 PALMD::Key::VS_SCRATCH_SIZE; 207 setRegister(NumUsedVgprsKey, Val); 208 return; 209 } 210 // Msgpack format. 211 getHwStage(CC)[".vgpr_count"] = MsgPackDoc.getNode(Val); 212 } 213 214 // Set the number of used sgprs in the metadata. This is an optional advisory 215 // record for logging etc; wave dispatch actually uses the rsrc1 register for 216 // the shader stage to determine the number of sgprs to allocate. 217 void AMDGPUPALMetadata::setNumUsedSgprs(CallingConv::ID CC, unsigned Val) { 218 if (isLegacy()) { 219 // Old non-msgpack format. 220 unsigned NumUsedSgprsKey = getScratchSizeKey(CC) + 221 PALMD::Key::VS_NUM_USED_SGPRS - 222 PALMD::Key::VS_SCRATCH_SIZE; 223 setRegister(NumUsedSgprsKey, Val); 224 return; 225 } 226 // Msgpack format. 227 getHwStage(CC)[".sgpr_count"] = MsgPackDoc.getNode(Val); 228 } 229 230 // Set the scratch size in the metadata. 231 void AMDGPUPALMetadata::setScratchSize(CallingConv::ID CC, unsigned Val) { 232 if (isLegacy()) { 233 // Old non-msgpack format. 234 setRegister(getScratchSizeKey(CC), Val); 235 return; 236 } 237 // Msgpack format. 238 getHwStage(CC)[".scratch_memory_size"] = MsgPackDoc.getNode(Val); 239 } 240 241 // Set the hardware register bit in PAL metadata to enable wave32 on the 242 // shader of the given calling convention. 243 void AMDGPUPALMetadata::setWave32(unsigned CC) { 244 switch (CC) { 245 case CallingConv::AMDGPU_HS: 246 setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_HS_W32_EN(1)); 247 break; 248 case CallingConv::AMDGPU_GS: 249 setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_GS_W32_EN(1)); 250 break; 251 case CallingConv::AMDGPU_VS: 252 setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_VS_W32_EN(1)); 253 break; 254 case CallingConv::AMDGPU_PS: 255 setRegister(PALMD::R_A1B6_SPI_PS_IN_CONTROL, S_0286D8_PS_W32_EN(1)); 256 break; 257 case CallingConv::AMDGPU_CS: 258 setRegister(PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, 259 S_00B800_CS_W32_EN(1)); 260 break; 261 } 262 } 263 264 // Convert a register number to name, for display by toString(). 265 // Returns nullptr if none. 266 static const char *getRegisterName(unsigned RegNum) { 267 // Table of registers. 268 static const struct RegInfo { 269 unsigned Num; 270 const char *Name; 271 } RegInfoTable[] = { 272 // Registers that code generation sets/modifies metadata for. 273 {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS, "SPI_SHADER_PGM_RSRC1_VS"}, 274 {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS + 1, "SPI_SHADER_PGM_RSRC2_VS"}, 275 {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS, "SPI_SHADER_PGM_RSRC1_LS"}, 276 {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS + 1, "SPI_SHADER_PGM_RSRC2_LS"}, 277 {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS, "SPI_SHADER_PGM_RSRC1_HS"}, 278 {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS + 1, "SPI_SHADER_PGM_RSRC2_HS"}, 279 {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES, "SPI_SHADER_PGM_RSRC1_ES"}, 280 {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1, "SPI_SHADER_PGM_RSRC2_ES"}, 281 {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS, "SPI_SHADER_PGM_RSRC1_GS"}, 282 {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1, "SPI_SHADER_PGM_RSRC2_GS"}, 283 {PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, "COMPUTE_DISPATCH_INITIATOR"}, 284 {PALMD::R_2E12_COMPUTE_PGM_RSRC1, "COMPUTE_PGM_RSRC1"}, 285 {PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1, "COMPUTE_PGM_RSRC2"}, 286 {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS, "SPI_SHADER_PGM_RSRC1_PS"}, 287 {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1, "SPI_SHADER_PGM_RSRC2_PS"}, 288 {PALMD::R_A1B3_SPI_PS_INPUT_ENA, "SPI_PS_INPUT_ENA"}, 289 {PALMD::R_A1B4_SPI_PS_INPUT_ADDR, "SPI_PS_INPUT_ADDR"}, 290 {PALMD::R_A1B6_SPI_PS_IN_CONTROL, "SPI_PS_IN_CONTROL"}, 291 {PALMD::R_A2D5_VGT_SHADER_STAGES_EN, "VGT_SHADER_STAGES_EN"}, 292 293 // Registers not known to code generation. 294 {0x2c07, "SPI_SHADER_PGM_RSRC3_PS"}, 295 {0x2c46, "SPI_SHADER_PGM_RSRC3_VS"}, 296 {0x2c87, "SPI_SHADER_PGM_RSRC3_GS"}, 297 {0x2cc7, "SPI_SHADER_PGM_RSRC3_ES"}, 298 {0x2d07, "SPI_SHADER_PGM_RSRC3_HS"}, 299 {0x2d47, "SPI_SHADER_PGM_RSRC3_LS"}, 300 301 {0xa1c3, "SPI_SHADER_POS_FORMAT"}, 302 {0xa1b1, "SPI_VS_OUT_CONFIG"}, 303 {0xa207, "PA_CL_VS_OUT_CNTL"}, 304 {0xa204, "PA_CL_CLIP_CNTL"}, 305 {0xa206, "PA_CL_VTE_CNTL"}, 306 {0xa2f9, "PA_SU_VTX_CNTL"}, 307 {0xa293, "PA_SC_MODE_CNTL_1"}, 308 {0xa2a1, "VGT_PRIMITIVEID_EN"}, 309 {0x2c81, "SPI_SHADER_PGM_RSRC4_GS"}, 310 {0x2e18, "COMPUTE_TMPRING_SIZE"}, 311 {0xa1b5, "SPI_INTERP_CONTROL_0"}, 312 {0xa1ba, "SPI_TMPRING_SIZE"}, 313 {0xa1c4, "SPI_SHADER_Z_FORMAT"}, 314 {0xa1c5, "SPI_SHADER_COL_FORMAT"}, 315 {0xa203, "DB_SHADER_CONTROL"}, 316 {0xa08f, "CB_SHADER_MASK"}, 317 {0xa191, "SPI_PS_INPUT_CNTL_0"}, 318 {0xa192, "SPI_PS_INPUT_CNTL_1"}, 319 {0xa193, "SPI_PS_INPUT_CNTL_2"}, 320 {0xa194, "SPI_PS_INPUT_CNTL_3"}, 321 {0xa195, "SPI_PS_INPUT_CNTL_4"}, 322 {0xa196, "SPI_PS_INPUT_CNTL_5"}, 323 {0xa197, "SPI_PS_INPUT_CNTL_6"}, 324 {0xa198, "SPI_PS_INPUT_CNTL_7"}, 325 {0xa199, "SPI_PS_INPUT_CNTL_8"}, 326 {0xa19a, "SPI_PS_INPUT_CNTL_9"}, 327 {0xa19b, "SPI_PS_INPUT_CNTL_10"}, 328 {0xa19c, "SPI_PS_INPUT_CNTL_11"}, 329 {0xa19d, "SPI_PS_INPUT_CNTL_12"}, 330 {0xa19e, "SPI_PS_INPUT_CNTL_13"}, 331 {0xa19f, "SPI_PS_INPUT_CNTL_14"}, 332 {0xa1a0, "SPI_PS_INPUT_CNTL_15"}, 333 {0xa1a1, "SPI_PS_INPUT_CNTL_16"}, 334 {0xa1a2, "SPI_PS_INPUT_CNTL_17"}, 335 {0xa1a3, "SPI_PS_INPUT_CNTL_18"}, 336 {0xa1a4, "SPI_PS_INPUT_CNTL_19"}, 337 {0xa1a5, "SPI_PS_INPUT_CNTL_20"}, 338 {0xa1a6, "SPI_PS_INPUT_CNTL_21"}, 339 {0xa1a7, "SPI_PS_INPUT_CNTL_22"}, 340 {0xa1a8, "SPI_PS_INPUT_CNTL_23"}, 341 {0xa1a9, "SPI_PS_INPUT_CNTL_24"}, 342 {0xa1aa, "SPI_PS_INPUT_CNTL_25"}, 343 {0xa1ab, "SPI_PS_INPUT_CNTL_26"}, 344 {0xa1ac, "SPI_PS_INPUT_CNTL_27"}, 345 {0xa1ad, "SPI_PS_INPUT_CNTL_28"}, 346 {0xa1ae, "SPI_PS_INPUT_CNTL_29"}, 347 {0xa1af, "SPI_PS_INPUT_CNTL_30"}, 348 {0xa1b0, "SPI_PS_INPUT_CNTL_31"}, 349 350 {0xa2ce, "VGT_GS_MAX_VERT_OUT"}, 351 {0xa2ab, "VGT_ESGS_RING_ITEMSIZE"}, 352 {0xa290, "VGT_GS_MODE"}, 353 {0xa291, "VGT_GS_ONCHIP_CNTL"}, 354 {0xa2d7, "VGT_GS_VERT_ITEMSIZE"}, 355 {0xa2d8, "VGT_GS_VERT_ITEMSIZE_1"}, 356 {0xa2d9, "VGT_GS_VERT_ITEMSIZE_2"}, 357 {0xa2da, "VGT_GS_VERT_ITEMSIZE_3"}, 358 {0xa298, "VGT_GSVS_RING_OFFSET_1"}, 359 {0xa299, "VGT_GSVS_RING_OFFSET_2"}, 360 {0xa29a, "VGT_GSVS_RING_OFFSET_3"}, 361 362 {0xa2e4, "VGT_GS_INSTANCE_CNT"}, 363 {0xa297, "VGT_GS_PER_VS"}, 364 {0xa29b, "VGT_GS_OUT_PRIM_TYPE"}, 365 {0xa2ac, "VGT_GSVS_RING_ITEMSIZE"}, 366 367 {0xa2ad, "VGT_REUSE_OFF"}, 368 {0xa1b8, "SPI_BARYC_CNTL"}, 369 370 {0x2c4c, "SPI_SHADER_USER_DATA_VS_0"}, 371 {0x2c4d, "SPI_SHADER_USER_DATA_VS_1"}, 372 {0x2c4e, "SPI_SHADER_USER_DATA_VS_2"}, 373 {0x2c4f, "SPI_SHADER_USER_DATA_VS_3"}, 374 {0x2c50, "SPI_SHADER_USER_DATA_VS_4"}, 375 {0x2c51, "SPI_SHADER_USER_DATA_VS_5"}, 376 {0x2c52, "SPI_SHADER_USER_DATA_VS_6"}, 377 {0x2c53, "SPI_SHADER_USER_DATA_VS_7"}, 378 {0x2c54, "SPI_SHADER_USER_DATA_VS_8"}, 379 {0x2c55, "SPI_SHADER_USER_DATA_VS_9"}, 380 {0x2c56, "SPI_SHADER_USER_DATA_VS_10"}, 381 {0x2c57, "SPI_SHADER_USER_DATA_VS_11"}, 382 {0x2c58, "SPI_SHADER_USER_DATA_VS_12"}, 383 {0x2c59, "SPI_SHADER_USER_DATA_VS_13"}, 384 {0x2c5a, "SPI_SHADER_USER_DATA_VS_14"}, 385 {0x2c5b, "SPI_SHADER_USER_DATA_VS_15"}, 386 {0x2c5c, "SPI_SHADER_USER_DATA_VS_16"}, 387 {0x2c5d, "SPI_SHADER_USER_DATA_VS_17"}, 388 {0x2c5e, "SPI_SHADER_USER_DATA_VS_18"}, 389 {0x2c5f, "SPI_SHADER_USER_DATA_VS_19"}, 390 {0x2c60, "SPI_SHADER_USER_DATA_VS_20"}, 391 {0x2c61, "SPI_SHADER_USER_DATA_VS_21"}, 392 {0x2c62, "SPI_SHADER_USER_DATA_VS_22"}, 393 {0x2c63, "SPI_SHADER_USER_DATA_VS_23"}, 394 {0x2c64, "SPI_SHADER_USER_DATA_VS_24"}, 395 {0x2c65, "SPI_SHADER_USER_DATA_VS_25"}, 396 {0x2c66, "SPI_SHADER_USER_DATA_VS_26"}, 397 {0x2c67, "SPI_SHADER_USER_DATA_VS_27"}, 398 {0x2c68, "SPI_SHADER_USER_DATA_VS_28"}, 399 {0x2c69, "SPI_SHADER_USER_DATA_VS_29"}, 400 {0x2c6a, "SPI_SHADER_USER_DATA_VS_30"}, 401 {0x2c6b, "SPI_SHADER_USER_DATA_VS_31"}, 402 403 {0x2c8c, "SPI_SHADER_USER_DATA_GS_0"}, 404 {0x2c8d, "SPI_SHADER_USER_DATA_GS_1"}, 405 {0x2c8e, "SPI_SHADER_USER_DATA_GS_2"}, 406 {0x2c8f, "SPI_SHADER_USER_DATA_GS_3"}, 407 {0x2c90, "SPI_SHADER_USER_DATA_GS_4"}, 408 {0x2c91, "SPI_SHADER_USER_DATA_GS_5"}, 409 {0x2c92, "SPI_SHADER_USER_DATA_GS_6"}, 410 {0x2c93, "SPI_SHADER_USER_DATA_GS_7"}, 411 {0x2c94, "SPI_SHADER_USER_DATA_GS_8"}, 412 {0x2c95, "SPI_SHADER_USER_DATA_GS_9"}, 413 {0x2c96, "SPI_SHADER_USER_DATA_GS_10"}, 414 {0x2c97, "SPI_SHADER_USER_DATA_GS_11"}, 415 {0x2c98, "SPI_SHADER_USER_DATA_GS_12"}, 416 {0x2c99, "SPI_SHADER_USER_DATA_GS_13"}, 417 {0x2c9a, "SPI_SHADER_USER_DATA_GS_14"}, 418 {0x2c9b, "SPI_SHADER_USER_DATA_GS_15"}, 419 {0x2c9c, "SPI_SHADER_USER_DATA_GS_16"}, 420 {0x2c9d, "SPI_SHADER_USER_DATA_GS_17"}, 421 {0x2c9e, "SPI_SHADER_USER_DATA_GS_18"}, 422 {0x2c9f, "SPI_SHADER_USER_DATA_GS_19"}, 423 {0x2ca0, "SPI_SHADER_USER_DATA_GS_20"}, 424 {0x2ca1, "SPI_SHADER_USER_DATA_GS_21"}, 425 {0x2ca2, "SPI_SHADER_USER_DATA_GS_22"}, 426 {0x2ca3, "SPI_SHADER_USER_DATA_GS_23"}, 427 {0x2ca4, "SPI_SHADER_USER_DATA_GS_24"}, 428 {0x2ca5, "SPI_SHADER_USER_DATA_GS_25"}, 429 {0x2ca6, "SPI_SHADER_USER_DATA_GS_26"}, 430 {0x2ca7, "SPI_SHADER_USER_DATA_GS_27"}, 431 {0x2ca8, "SPI_SHADER_USER_DATA_GS_28"}, 432 {0x2ca9, "SPI_SHADER_USER_DATA_GS_29"}, 433 {0x2caa, "SPI_SHADER_USER_DATA_GS_30"}, 434 {0x2cab, "SPI_SHADER_USER_DATA_GS_31"}, 435 436 {0x2ccc, "SPI_SHADER_USER_DATA_ES_0"}, 437 {0x2ccd, "SPI_SHADER_USER_DATA_ES_1"}, 438 {0x2cce, "SPI_SHADER_USER_DATA_ES_2"}, 439 {0x2ccf, "SPI_SHADER_USER_DATA_ES_3"}, 440 {0x2cd0, "SPI_SHADER_USER_DATA_ES_4"}, 441 {0x2cd1, "SPI_SHADER_USER_DATA_ES_5"}, 442 {0x2cd2, "SPI_SHADER_USER_DATA_ES_6"}, 443 {0x2cd3, "SPI_SHADER_USER_DATA_ES_7"}, 444 {0x2cd4, "SPI_SHADER_USER_DATA_ES_8"}, 445 {0x2cd5, "SPI_SHADER_USER_DATA_ES_9"}, 446 {0x2cd6, "SPI_SHADER_USER_DATA_ES_10"}, 447 {0x2cd7, "SPI_SHADER_USER_DATA_ES_11"}, 448 {0x2cd8, "SPI_SHADER_USER_DATA_ES_12"}, 449 {0x2cd9, "SPI_SHADER_USER_DATA_ES_13"}, 450 {0x2cda, "SPI_SHADER_USER_DATA_ES_14"}, 451 {0x2cdb, "SPI_SHADER_USER_DATA_ES_15"}, 452 {0x2cdc, "SPI_SHADER_USER_DATA_ES_16"}, 453 {0x2cdd, "SPI_SHADER_USER_DATA_ES_17"}, 454 {0x2cde, "SPI_SHADER_USER_DATA_ES_18"}, 455 {0x2cdf, "SPI_SHADER_USER_DATA_ES_19"}, 456 {0x2ce0, "SPI_SHADER_USER_DATA_ES_20"}, 457 {0x2ce1, "SPI_SHADER_USER_DATA_ES_21"}, 458 {0x2ce2, "SPI_SHADER_USER_DATA_ES_22"}, 459 {0x2ce3, "SPI_SHADER_USER_DATA_ES_23"}, 460 {0x2ce4, "SPI_SHADER_USER_DATA_ES_24"}, 461 {0x2ce5, "SPI_SHADER_USER_DATA_ES_25"}, 462 {0x2ce6, "SPI_SHADER_USER_DATA_ES_26"}, 463 {0x2ce7, "SPI_SHADER_USER_DATA_ES_27"}, 464 {0x2ce8, "SPI_SHADER_USER_DATA_ES_28"}, 465 {0x2ce9, "SPI_SHADER_USER_DATA_ES_29"}, 466 {0x2cea, "SPI_SHADER_USER_DATA_ES_30"}, 467 {0x2ceb, "SPI_SHADER_USER_DATA_ES_31"}, 468 469 {0x2c0c, "SPI_SHADER_USER_DATA_PS_0"}, 470 {0x2c0d, "SPI_SHADER_USER_DATA_PS_1"}, 471 {0x2c0e, "SPI_SHADER_USER_DATA_PS_2"}, 472 {0x2c0f, "SPI_SHADER_USER_DATA_PS_3"}, 473 {0x2c10, "SPI_SHADER_USER_DATA_PS_4"}, 474 {0x2c11, "SPI_SHADER_USER_DATA_PS_5"}, 475 {0x2c12, "SPI_SHADER_USER_DATA_PS_6"}, 476 {0x2c13, "SPI_SHADER_USER_DATA_PS_7"}, 477 {0x2c14, "SPI_SHADER_USER_DATA_PS_8"}, 478 {0x2c15, "SPI_SHADER_USER_DATA_PS_9"}, 479 {0x2c16, "SPI_SHADER_USER_DATA_PS_10"}, 480 {0x2c17, "SPI_SHADER_USER_DATA_PS_11"}, 481 {0x2c18, "SPI_SHADER_USER_DATA_PS_12"}, 482 {0x2c19, "SPI_SHADER_USER_DATA_PS_13"}, 483 {0x2c1a, "SPI_SHADER_USER_DATA_PS_14"}, 484 {0x2c1b, "SPI_SHADER_USER_DATA_PS_15"}, 485 {0x2c1c, "SPI_SHADER_USER_DATA_PS_16"}, 486 {0x2c1d, "SPI_SHADER_USER_DATA_PS_17"}, 487 {0x2c1e, "SPI_SHADER_USER_DATA_PS_18"}, 488 {0x2c1f, "SPI_SHADER_USER_DATA_PS_19"}, 489 {0x2c20, "SPI_SHADER_USER_DATA_PS_20"}, 490 {0x2c21, "SPI_SHADER_USER_DATA_PS_21"}, 491 {0x2c22, "SPI_SHADER_USER_DATA_PS_22"}, 492 {0x2c23, "SPI_SHADER_USER_DATA_PS_23"}, 493 {0x2c24, "SPI_SHADER_USER_DATA_PS_24"}, 494 {0x2c25, "SPI_SHADER_USER_DATA_PS_25"}, 495 {0x2c26, "SPI_SHADER_USER_DATA_PS_26"}, 496 {0x2c27, "SPI_SHADER_USER_DATA_PS_27"}, 497 {0x2c28, "SPI_SHADER_USER_DATA_PS_28"}, 498 {0x2c29, "SPI_SHADER_USER_DATA_PS_29"}, 499 {0x2c2a, "SPI_SHADER_USER_DATA_PS_30"}, 500 {0x2c2b, "SPI_SHADER_USER_DATA_PS_31"}, 501 502 {0x2e40, "COMPUTE_USER_DATA_0"}, 503 {0x2e41, "COMPUTE_USER_DATA_1"}, 504 {0x2e42, "COMPUTE_USER_DATA_2"}, 505 {0x2e43, "COMPUTE_USER_DATA_3"}, 506 {0x2e44, "COMPUTE_USER_DATA_4"}, 507 {0x2e45, "COMPUTE_USER_DATA_5"}, 508 {0x2e46, "COMPUTE_USER_DATA_6"}, 509 {0x2e47, "COMPUTE_USER_DATA_7"}, 510 {0x2e48, "COMPUTE_USER_DATA_8"}, 511 {0x2e49, "COMPUTE_USER_DATA_9"}, 512 {0x2e4a, "COMPUTE_USER_DATA_10"}, 513 {0x2e4b, "COMPUTE_USER_DATA_11"}, 514 {0x2e4c, "COMPUTE_USER_DATA_12"}, 515 {0x2e4d, "COMPUTE_USER_DATA_13"}, 516 {0x2e4e, "COMPUTE_USER_DATA_14"}, 517 {0x2e4f, "COMPUTE_USER_DATA_15"}, 518 519 {0x2e07, "COMPUTE_NUM_THREAD_X"}, 520 {0x2e08, "COMPUTE_NUM_THREAD_Y"}, 521 {0x2e09, "COMPUTE_NUM_THREAD_Z"}, 522 {0xa2db, "VGT_TF_PARAM"}, 523 {0xa2d6, "VGT_LS_HS_CONFIG"}, 524 {0xa287, "VGT_HOS_MIN_TESS_LEVEL"}, 525 {0xa286, "VGT_HOS_MAX_TESS_LEVEL"}, 526 {0xa2f8, "PA_SC_AA_CONFIG"}, 527 {0xa310, "PA_SC_SHADER_CONTROL"}, 528 {0xa313, "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"}, 529 530 {0x2d0c, "SPI_SHADER_USER_DATA_HS_0"}, 531 {0x2d0d, "SPI_SHADER_USER_DATA_HS_1"}, 532 {0x2d0e, "SPI_SHADER_USER_DATA_HS_2"}, 533 {0x2d0f, "SPI_SHADER_USER_DATA_HS_3"}, 534 {0x2d10, "SPI_SHADER_USER_DATA_HS_4"}, 535 {0x2d11, "SPI_SHADER_USER_DATA_HS_5"}, 536 {0x2d12, "SPI_SHADER_USER_DATA_HS_6"}, 537 {0x2d13, "SPI_SHADER_USER_DATA_HS_7"}, 538 {0x2d14, "SPI_SHADER_USER_DATA_HS_8"}, 539 {0x2d15, "SPI_SHADER_USER_DATA_HS_9"}, 540 {0x2d16, "SPI_SHADER_USER_DATA_HS_10"}, 541 {0x2d17, "SPI_SHADER_USER_DATA_HS_11"}, 542 {0x2d18, "SPI_SHADER_USER_DATA_HS_12"}, 543 {0x2d19, "SPI_SHADER_USER_DATA_HS_13"}, 544 {0x2d1a, "SPI_SHADER_USER_DATA_HS_14"}, 545 {0x2d1b, "SPI_SHADER_USER_DATA_HS_15"}, 546 {0x2d1c, "SPI_SHADER_USER_DATA_HS_16"}, 547 {0x2d1d, "SPI_SHADER_USER_DATA_HS_17"}, 548 {0x2d1e, "SPI_SHADER_USER_DATA_HS_18"}, 549 {0x2d1f, "SPI_SHADER_USER_DATA_HS_19"}, 550 {0x2d20, "SPI_SHADER_USER_DATA_HS_20"}, 551 {0x2d21, "SPI_SHADER_USER_DATA_HS_21"}, 552 {0x2d22, "SPI_SHADER_USER_DATA_HS_22"}, 553 {0x2d23, "SPI_SHADER_USER_DATA_HS_23"}, 554 {0x2d24, "SPI_SHADER_USER_DATA_HS_24"}, 555 {0x2d25, "SPI_SHADER_USER_DATA_HS_25"}, 556 {0x2d26, "SPI_SHADER_USER_DATA_HS_26"}, 557 {0x2d27, "SPI_SHADER_USER_DATA_HS_27"}, 558 {0x2d28, "SPI_SHADER_USER_DATA_HS_28"}, 559 {0x2d29, "SPI_SHADER_USER_DATA_HS_29"}, 560 {0x2d2a, "SPI_SHADER_USER_DATA_HS_30"}, 561 {0x2d2b, "SPI_SHADER_USER_DATA_HS_31"}, 562 563 {0x2d4c, "SPI_SHADER_USER_DATA_LS_0"}, 564 {0x2d4d, "SPI_SHADER_USER_DATA_LS_1"}, 565 {0x2d4e, "SPI_SHADER_USER_DATA_LS_2"}, 566 {0x2d4f, "SPI_SHADER_USER_DATA_LS_3"}, 567 {0x2d50, "SPI_SHADER_USER_DATA_LS_4"}, 568 {0x2d51, "SPI_SHADER_USER_DATA_LS_5"}, 569 {0x2d52, "SPI_SHADER_USER_DATA_LS_6"}, 570 {0x2d53, "SPI_SHADER_USER_DATA_LS_7"}, 571 {0x2d54, "SPI_SHADER_USER_DATA_LS_8"}, 572 {0x2d55, "SPI_SHADER_USER_DATA_LS_9"}, 573 {0x2d56, "SPI_SHADER_USER_DATA_LS_10"}, 574 {0x2d57, "SPI_SHADER_USER_DATA_LS_11"}, 575 {0x2d58, "SPI_SHADER_USER_DATA_LS_12"}, 576 {0x2d59, "SPI_SHADER_USER_DATA_LS_13"}, 577 {0x2d5a, "SPI_SHADER_USER_DATA_LS_14"}, 578 {0x2d5b, "SPI_SHADER_USER_DATA_LS_15"}, 579 580 {0xa2aa, "IA_MULTI_VGT_PARAM"}, 581 {0xa2a5, "VGT_GS_MAX_PRIMS_PER_SUBGROUP"}, 582 {0xa2e6, "VGT_STRMOUT_BUFFER_CONFIG"}, 583 {0xa2e5, "VGT_STRMOUT_CONFIG"}, 584 {0xa2b5, "VGT_STRMOUT_VTX_STRIDE_0"}, 585 {0xa2b9, "VGT_STRMOUT_VTX_STRIDE_1"}, 586 {0xa2bd, "VGT_STRMOUT_VTX_STRIDE_2"}, 587 {0xa2c1, "VGT_STRMOUT_VTX_STRIDE_3"}, 588 {0xa316, "VGT_VERTEX_REUSE_BLOCK_CNTL"}, 589 590 {0, nullptr}}; 591 auto Entry = RegInfoTable; 592 for (; Entry->Num && Entry->Num != RegNum; ++Entry) 593 ; 594 return Entry->Name; 595 } 596 597 // Convert the accumulated PAL metadata into an asm directive. 598 void AMDGPUPALMetadata::toString(std::string &String) { 599 String.clear(); 600 if (!BlobType) 601 return; 602 raw_string_ostream Stream(String); 603 if (isLegacy()) { 604 if (MsgPackDoc.getRoot().getKind() == msgpack::Type::Nil) 605 return; 606 // Old linear reg=val format. 607 Stream << '\t' << AMDGPU::PALMD::AssemblerDirective << ' '; 608 auto Regs = getRegisters(); 609 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) { 610 if (I != Regs.begin()) 611 Stream << ','; 612 unsigned Reg = I->first.getUInt(); 613 unsigned Val = I->second.getUInt(); 614 Stream << "0x" << Twine::utohexstr(Reg) << ",0x" << Twine::utohexstr(Val); 615 } 616 Stream << '\n'; 617 return; 618 } 619 620 // New msgpack-based format -- output as YAML (with unsigned numbers in hex), 621 // but first change the registers map to use names. 622 MsgPackDoc.setHexMode(); 623 auto &RegsObj = refRegisters(); 624 auto OrigRegs = RegsObj.getMap(); 625 RegsObj = MsgPackDoc.getMapNode(); 626 for (auto I : OrigRegs) { 627 auto Key = I.first; 628 if (const char *RegName = getRegisterName(Key.getUInt())) { 629 std::string KeyName = Key.toString(); 630 KeyName += " ("; 631 KeyName += RegName; 632 KeyName += ')'; 633 Key = MsgPackDoc.getNode(KeyName, /*Copy=*/true); 634 } 635 RegsObj.getMap()[Key] = I.second; 636 } 637 638 // Output as YAML. 639 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveBegin << '\n'; 640 MsgPackDoc.toYAML(Stream); 641 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveEnd << '\n'; 642 643 // Restore original registers map. 644 RegsObj = OrigRegs; 645 } 646 647 // Convert the accumulated PAL metadata into a binary blob for writing as 648 // a .note record of the specified AMD type. Returns an empty blob if 649 // there is no PAL metadata, 650 void AMDGPUPALMetadata::toBlob(unsigned Type, std::string &Blob) { 651 if (Type == ELF::NT_AMD_AMDGPU_PAL_METADATA) 652 toLegacyBlob(Blob); 653 else if (Type) 654 toMsgPackBlob(Blob); 655 } 656 657 void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) { 658 Blob.clear(); 659 auto Registers = getRegisters(); 660 if (Registers.getMap().empty()) 661 return; 662 raw_string_ostream OS(Blob); 663 support::endian::Writer EW(OS, support::endianness::little); 664 for (auto I : Registers.getMap()) { 665 EW.write(uint32_t(I.first.getUInt())); 666 EW.write(uint32_t(I.second.getUInt())); 667 } 668 } 669 670 void AMDGPUPALMetadata::toMsgPackBlob(std::string &Blob) { 671 Blob.clear(); 672 MsgPackDoc.writeToBlob(Blob); 673 } 674 675 // Set PAL metadata from YAML text. Returns false if failed. 676 bool AMDGPUPALMetadata::setFromString(StringRef S) { 677 BlobType = ELF::NT_AMDGPU_METADATA; 678 if (!MsgPackDoc.fromYAML(S)) 679 return false; 680 681 // In the registers map, some keys may be of the form "0xa191 682 // (SPI_PS_INPUT_CNTL_0)", in which case the YAML input code made it a 683 // string. We need to turn it into a number. 684 auto &RegsObj = refRegisters(); 685 auto OrigRegs = RegsObj; 686 RegsObj = MsgPackDoc.getMapNode(); 687 Registers = RegsObj.getMap(); 688 bool Ok = true; 689 for (auto I : OrigRegs.getMap()) { 690 auto Key = I.first; 691 if (Key.getKind() == msgpack::Type::String) { 692 StringRef S = Key.getString(); 693 uint64_t Val; 694 if (S.consumeInteger(0, Val)) { 695 Ok = false; 696 errs() << "Unrecognized PAL metadata register key '" << S << "'\n"; 697 continue; 698 } 699 Key = MsgPackDoc.getNode(uint64_t(Val)); 700 } 701 Registers.getMap()[Key] = I.second; 702 } 703 return Ok; 704 } 705 706 // Reference (create if necessary) the node for the registers map. 707 msgpack::DocNode &AMDGPUPALMetadata::refRegisters() { 708 auto &N = 709 MsgPackDoc.getRoot() 710 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")] 711 .getArray(/*Convert=*/true)[0] 712 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".registers")]; 713 N.getMap(/*Convert=*/true); 714 return N; 715 } 716 717 // Get (create if necessary) the registers map. 718 msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() { 719 if (Registers.isEmpty()) 720 Registers = refRegisters(); 721 return Registers.getMap(); 722 } 723 724 // Return the PAL metadata hardware shader stage name. 725 static const char *getStageName(CallingConv::ID CC) { 726 switch (CC) { 727 case CallingConv::AMDGPU_PS: 728 return ".ps"; 729 case CallingConv::AMDGPU_VS: 730 return ".vs"; 731 case CallingConv::AMDGPU_GS: 732 return ".gs"; 733 case CallingConv::AMDGPU_ES: 734 return ".es"; 735 case CallingConv::AMDGPU_HS: 736 return ".hs"; 737 case CallingConv::AMDGPU_LS: 738 return ".ls"; 739 case CallingConv::AMDGPU_Gfx: 740 llvm_unreachable("Callable shader has no hardware stage"); 741 default: 742 return ".cs"; 743 } 744 } 745 746 // Get (create if necessary) the .hardware_stages entry for the given calling 747 // convention. 748 msgpack::MapDocNode AMDGPUPALMetadata::getHwStage(unsigned CC) { 749 if (HwStages.isEmpty()) 750 HwStages = MsgPackDoc.getRoot() 751 .getMap(/*Convert=*/true)["amdpal.pipelines"] 752 .getArray(/*Convert=*/true)[0] 753 .getMap(/*Convert=*/true)[".hardware_stages"] 754 .getMap(/*Convert=*/true); 755 return HwStages.getMap()[getStageName(CC)].getMap(/*Convert=*/true); 756 } 757 758 // Get .note record vendor name of metadata blob to be emitted. 759 const char *AMDGPUPALMetadata::getVendor() const { 760 return isLegacy() ? ElfNote::NoteNameV2 : ElfNote::NoteNameV3; 761 } 762 763 // Get .note record type of metadata blob to be emitted: 764 // ELF::NT_AMD_AMDGPU_PAL_METADATA (legacy key=val format), or 765 // ELF::NT_AMDGPU_METADATA (MsgPack format), or 766 // 0 (no PAL metadata). 767 unsigned AMDGPUPALMetadata::getType() const { 768 return BlobType; 769 } 770 771 // Return whether the blob type is legacy PAL metadata. 772 bool AMDGPUPALMetadata::isLegacy() const { 773 return BlobType == ELF::NT_AMD_AMDGPU_PAL_METADATA; 774 } 775 776 // Set legacy PAL metadata format. 777 void AMDGPUPALMetadata::setLegacy() { 778 BlobType = ELF::NT_AMD_AMDGPU_PAL_METADATA; 779 } 780 781 // Erase all PAL metadata. 782 void AMDGPUPALMetadata::reset() { 783 MsgPackDoc.clear(); 784 Registers = MsgPackDoc.getEmptyNode(); 785 HwStages = MsgPackDoc.getEmptyNode(); 786 } 787