1 //===-- AMDGPUBaseInfo.h - Top level definitions for AMDGPU -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H 11 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H 12 13 #include "AMDKernelCodeT.h" 14 #include "llvm/IR/CallingConv.h" 15 16 #define GET_INSTRINFO_OPERAND_ENUM 17 #include "AMDGPUGenInstrInfo.inc" 18 #undef GET_INSTRINFO_OPERAND_ENUM 19 20 namespace llvm { 21 22 class FeatureBitset; 23 class Function; 24 class GlobalValue; 25 class MCContext; 26 class MCInstrDesc; 27 class MCRegisterClass; 28 class MCRegisterInfo; 29 class MCSection; 30 class MCSubtargetInfo; 31 32 namespace AMDGPU { 33 34 LLVM_READONLY 35 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx); 36 37 struct IsaVersion { 38 unsigned Major; 39 unsigned Minor; 40 unsigned Stepping; 41 }; 42 43 IsaVersion getIsaVersion(const FeatureBitset &Features); 44 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, 45 const FeatureBitset &Features); 46 MCSection *getHSATextSection(MCContext &Ctx); 47 48 MCSection *getHSADataGlobalAgentSection(MCContext &Ctx); 49 50 MCSection *getHSADataGlobalProgramSection(MCContext &Ctx); 51 52 MCSection *getHSARodataReadonlyAgentSection(MCContext &Ctx); 53 54 bool isGroupSegment(const GlobalValue *GV); 55 bool isGlobalSegment(const GlobalValue *GV); 56 bool isReadOnlySegment(const GlobalValue *GV); 57 58 /// \returns True if constants should be emitted to .text section for given 59 /// target triple \p TT, false otherwise. 60 bool shouldEmitConstantsToTextSection(const Triple &TT); 61 62 /// \returns Integer value requested using \p F's \p Name attribute. 63 /// 64 /// \returns \p Default if attribute is not present. 65 /// 66 /// \returns \p Default and emits error if requested value cannot be converted 67 /// to integer. 68 int getIntegerAttribute(const Function &F, StringRef Name, int Default); 69 70 /// \returns A pair of integer values requested using \p F's \p Name attribute 71 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired 72 /// is false). 73 /// 74 /// \returns \p Default if attribute is not present. 75 /// 76 /// \returns \p Default and emits error if one of the requested values cannot be 77 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is 78 /// not present. 79 std::pair<int, int> getIntegerPairAttribute(const Function &F, 80 StringRef Name, 81 std::pair<int, int> Default, 82 bool OnlyFirstRequired = false); 83 84 /// \returns Waitcnt bit mask for given isa \p Version. 85 unsigned getWaitcntBitMask(IsaVersion Version); 86 87 /// \returns Vmcnt bit mask for given isa \p Version. 88 unsigned getVmcntBitMask(IsaVersion Version); 89 90 /// \returns Expcnt bit mask for given isa \p Version. 91 unsigned getExpcntBitMask(IsaVersion Version); 92 93 /// \returns Lgkmcnt bit mask for given isa \p Version. 94 unsigned getLgkmcntBitMask(IsaVersion Version); 95 96 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version. 97 unsigned decodeVmcnt(IsaVersion Version, unsigned Waitcnt); 98 99 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version. 100 unsigned decodeExpcnt(IsaVersion Version, unsigned Waitcnt); 101 102 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version. 103 unsigned decodeLgkmcnt(IsaVersion Version, unsigned Waitcnt); 104 105 /// \brief Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa 106 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and 107 /// \p Lgkmcnt respectively. 108 /// 109 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows: 110 /// \p Vmcnt = \p Waitcnt[3:0] 111 /// \p Expcnt = \p Waitcnt[6:4] 112 /// \p Lgkmcnt = \p Waitcnt[11:8] 113 void decodeWaitcnt(IsaVersion Version, unsigned Waitcnt, 114 unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt); 115 116 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version. 117 unsigned encodeVmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Vmcnt); 118 119 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version. 120 unsigned encodeExpcnt(IsaVersion Version, unsigned Waitcnt, unsigned Expcnt); 121 122 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version. 123 unsigned encodeLgkmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Lgkmcnt); 124 125 /// \brief Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa 126 /// \p Version. 127 /// 128 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows: 129 /// Waitcnt[3:0] = \p Vmcnt 130 /// Waitcnt[6:4] = \p Expcnt 131 /// Waitcnt[11:8] = \p Lgkmcnt 132 /// 133 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given 134 /// isa \p Version. 135 unsigned encodeWaitcnt(IsaVersion Version, 136 unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt); 137 138 unsigned getInitialPSInputAddr(const Function &F); 139 140 bool isShader(CallingConv::ID cc); 141 bool isCompute(CallingConv::ID cc); 142 143 bool isSI(const MCSubtargetInfo &STI); 144 bool isCI(const MCSubtargetInfo &STI); 145 bool isVI(const MCSubtargetInfo &STI); 146 147 /// If \p Reg is a pseudo reg, return the correct hardware register given 148 /// \p STI otherwise return \p Reg. 149 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI); 150 151 /// \brief Can this operand also contain immediate values? 152 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo); 153 154 /// \brief Is this floating-point operand? 155 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo); 156 157 /// \brief Does this opearnd support only inlinable literals? 158 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo); 159 160 /// \brief Get the size in bits of a register from the register class \p RC. 161 unsigned getRegBitWidth(const MCRegisterClass &RC); 162 163 /// \brief Get size of register operand 164 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, 165 unsigned OpNo); 166 167 /// \brief Is this literal inlinable 168 bool isInlinableLiteral64(int64_t Literal, bool IsVI); 169 bool isInlinableLiteral32(int32_t Literal, bool IsVI); 170 171 } // end namespace AMDGPU 172 } // end namespace llvm 173 174 #endif 175