1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "SIDefines.h"
13 #include "llvm/IR/CallingConv.h"
14 #include "llvm/Support/Alignment.h"
15 
16 struct amd_kernel_code_t;
17 
18 namespace llvm {
19 
20 struct Align;
21 class Argument;
22 class Function;
23 class GCNSubtarget;
24 class GlobalValue;
25 class MCRegisterClass;
26 class MCRegisterInfo;
27 class MCSubtargetInfo;
28 class StringRef;
29 class Triple;
30 
31 namespace amdhsa {
32 struct kernel_descriptor_t;
33 }
34 
35 namespace AMDGPU {
36 
37 struct IsaVersion;
38 
39 /// \returns HSA OS ABI Version identification.
40 Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
41 /// \returns True if HSA OS ABI Version identification is 2,
42 /// false otherwise.
43 bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
44 /// \returns True if HSA OS ABI Version identification is 3,
45 /// false otherwise.
46 bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
47 /// \returns True if HSA OS ABI Version identification is 4,
48 /// false otherwise.
49 bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
50 /// \returns True if HSA OS ABI Version identification is 3 or 4,
51 /// false otherwise.
52 bool isHsaAbiVersion3Or4(const MCSubtargetInfo *STI);
53 
54 struct GcnBufferFormatInfo {
55   unsigned Format;
56   unsigned BitsPerComp;
57   unsigned NumComponents;
58   unsigned NumFormat;
59   unsigned DataFormat;
60 };
61 
62 #define GET_MIMGBaseOpcode_DECL
63 #define GET_MIMGDim_DECL
64 #define GET_MIMGEncoding_DECL
65 #define GET_MIMGLZMapping_DECL
66 #define GET_MIMGMIPMapping_DECL
67 #define GET_MIMGBiASMapping_DECL
68 #include "AMDGPUGenSearchableTables.inc"
69 
70 namespace IsaInfo {
71 
72 enum {
73   // The closed Vulkan driver sets 96, which limits the wave count to 8 but
74   // doesn't spill SGPRs as much as when 80 is set.
75   FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
76   TRAP_NUM_SGPRS = 16
77 };
78 
79 enum class TargetIDSetting {
80   Unsupported,
81   Any,
82   Off,
83   On
84 };
85 
86 class AMDGPUTargetID {
87 private:
88   const MCSubtargetInfo &STI;
89   TargetIDSetting XnackSetting;
90   TargetIDSetting SramEccSetting;
91 
92 public:
93   explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
94   ~AMDGPUTargetID() = default;
95 
96   /// \return True if the current xnack setting is not "Unsupported".
97   bool isXnackSupported() const {
98     return XnackSetting != TargetIDSetting::Unsupported;
99   }
100 
101   /// \returns True if the current xnack setting is "On" or "Any".
102   bool isXnackOnOrAny() const {
103     return XnackSetting == TargetIDSetting::On ||
104         XnackSetting == TargetIDSetting::Any;
105   }
106 
107   /// \returns True if current xnack setting is "On" or "Off",
108   /// false otherwise.
109   bool isXnackOnOrOff() const {
110     return getXnackSetting() == TargetIDSetting::On ||
111         getXnackSetting() == TargetIDSetting::Off;
112   }
113 
114   /// \returns The current xnack TargetIDSetting, possible options are
115   /// "Unsupported", "Any", "Off", and "On".
116   TargetIDSetting getXnackSetting() const {
117     return XnackSetting;
118   }
119 
120   /// Sets xnack setting to \p NewXnackSetting.
121   void setXnackSetting(TargetIDSetting NewXnackSetting) {
122     XnackSetting = NewXnackSetting;
123   }
124 
125   /// \return True if the current sramecc setting is not "Unsupported".
126   bool isSramEccSupported() const {
127     return SramEccSetting != TargetIDSetting::Unsupported;
128   }
129 
130   /// \returns True if the current sramecc setting is "On" or "Any".
131   bool isSramEccOnOrAny() const {
132   return SramEccSetting == TargetIDSetting::On ||
133       SramEccSetting == TargetIDSetting::Any;
134   }
135 
136   /// \returns True if current sramecc setting is "On" or "Off",
137   /// false otherwise.
138   bool isSramEccOnOrOff() const {
139     return getSramEccSetting() == TargetIDSetting::On ||
140         getSramEccSetting() == TargetIDSetting::Off;
141   }
142 
143   /// \returns The current sramecc TargetIDSetting, possible options are
144   /// "Unsupported", "Any", "Off", and "On".
145   TargetIDSetting getSramEccSetting() const {
146     return SramEccSetting;
147   }
148 
149   /// Sets sramecc setting to \p NewSramEccSetting.
150   void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
151     SramEccSetting = NewSramEccSetting;
152   }
153 
154   void setTargetIDFromFeaturesString(StringRef FS);
155   void setTargetIDFromTargetIDStream(StringRef TargetID);
156 
157   /// \returns String representation of an object.
158   std::string toString() const;
159 };
160 
161 /// \returns Wavefront size for given subtarget \p STI.
162 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
163 
164 /// \returns Local memory size in bytes for given subtarget \p STI.
165 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
166 
167 /// \returns Number of execution units per compute unit for given subtarget \p
168 /// STI.
169 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
170 
171 /// \returns Maximum number of work groups per compute unit for given subtarget
172 /// \p STI and limited by given \p FlatWorkGroupSize.
173 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
174                                unsigned FlatWorkGroupSize);
175 
176 /// \returns Minimum number of waves per execution unit for given subtarget \p
177 /// STI.
178 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
179 
180 /// \returns Maximum number of waves per execution unit for given subtarget \p
181 /// STI without any kind of limitation.
182 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
183 
184 /// \returns Number of waves per execution unit required to support the given \p
185 /// FlatWorkGroupSize.
186 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
187                                    unsigned FlatWorkGroupSize);
188 
189 /// \returns Minimum flat work group size for given subtarget \p STI.
190 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
191 
192 /// \returns Maximum flat work group size for given subtarget \p STI.
193 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
194 
195 /// \returns Number of waves per work group for given subtarget \p STI and
196 /// \p FlatWorkGroupSize.
197 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
198                               unsigned FlatWorkGroupSize);
199 
200 /// \returns SGPR allocation granularity for given subtarget \p STI.
201 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
202 
203 /// \returns SGPR encoding granularity for given subtarget \p STI.
204 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
205 
206 /// \returns Total number of SGPRs for given subtarget \p STI.
207 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
208 
209 /// \returns Addressable number of SGPRs for given subtarget \p STI.
210 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
211 
212 /// \returns Minimum number of SGPRs that meets the given number of waves per
213 /// execution unit requirement for given subtarget \p STI.
214 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
215 
216 /// \returns Maximum number of SGPRs that meets the given number of waves per
217 /// execution unit requirement for given subtarget \p STI.
218 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
219                         bool Addressable);
220 
221 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
222 /// STI when the given special registers are used.
223 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
224                           bool FlatScrUsed, bool XNACKUsed);
225 
226 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
227 /// STI when the given special registers are used. XNACK is inferred from
228 /// \p STI.
229 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
230                           bool FlatScrUsed);
231 
232 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
233 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
234 /// register counts.
235 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
236 
237 /// \returns VGPR allocation granularity for given subtarget \p STI.
238 ///
239 /// For subtargets which support it, \p EnableWavefrontSize32 should match
240 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
241 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
242                              Optional<bool> EnableWavefrontSize32 = None);
243 
244 /// \returns VGPR encoding granularity for given subtarget \p STI.
245 ///
246 /// For subtargets which support it, \p EnableWavefrontSize32 should match
247 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
248 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
249                                 Optional<bool> EnableWavefrontSize32 = None);
250 
251 /// \returns Total number of VGPRs for given subtarget \p STI.
252 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
253 
254 /// \returns Addressable number of VGPRs for given subtarget \p STI.
255 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
256 
257 /// \returns Minimum number of VGPRs that meets given number of waves per
258 /// execution unit requirement for given subtarget \p STI.
259 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
260 
261 /// \returns Maximum number of VGPRs that meets given number of waves per
262 /// execution unit requirement for given subtarget \p STI.
263 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
264 
265 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
266 /// \p NumVGPRs are used.
267 ///
268 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
269 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
270 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
271                           Optional<bool> EnableWavefrontSize32 = None);
272 
273 } // end namespace IsaInfo
274 
275 LLVM_READONLY
276 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
277 
278 LLVM_READONLY
279 int getSOPPWithRelaxation(uint16_t Opcode);
280 
281 struct MIMGBaseOpcodeInfo {
282   MIMGBaseOpcode BaseOpcode;
283   bool Store;
284   bool Atomic;
285   bool AtomicX2;
286   bool Sampler;
287   bool Gather4;
288 
289   uint8_t NumExtraArgs;
290   bool Gradients;
291   bool G16;
292   bool Coordinates;
293   bool LodOrClampOrMip;
294   bool HasD16;
295   bool MSAA;
296   bool BVH;
297 };
298 
299 LLVM_READONLY
300 const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
301 
302 LLVM_READONLY
303 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
304 
305 struct MIMGDimInfo {
306   MIMGDim Dim;
307   uint8_t NumCoords;
308   uint8_t NumGradients;
309   bool MSAA;
310   bool DA;
311   uint8_t Encoding;
312   const char *AsmSuffix;
313 };
314 
315 LLVM_READONLY
316 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
317 
318 LLVM_READONLY
319 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
320 
321 LLVM_READONLY
322 const MIMGDimInfo *getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix);
323 
324 struct MIMGLZMappingInfo {
325   MIMGBaseOpcode L;
326   MIMGBaseOpcode LZ;
327 };
328 
329 struct MIMGMIPMappingInfo {
330   MIMGBaseOpcode MIP;
331   MIMGBaseOpcode NONMIP;
332 };
333 
334 struct MIMGBiasMappingInfo {
335   MIMGBaseOpcode Bias;
336   MIMGBaseOpcode NoBias;
337 };
338 
339 struct MIMGG16MappingInfo {
340   MIMGBaseOpcode G;
341   MIMGBaseOpcode G16;
342 };
343 
344 LLVM_READONLY
345 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
346 
347 LLVM_READONLY
348 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
349 
350 LLVM_READONLY
351 const MIMGBiasMappingInfo *getMIMGBiasMappingInfo(unsigned Bias);
352 
353 LLVM_READONLY
354 const MIMGG16MappingInfo *getMIMGG16MappingInfo(unsigned G);
355 
356 LLVM_READONLY
357 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
358                   unsigned VDataDwords, unsigned VAddrDwords);
359 
360 LLVM_READONLY
361 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
362 
363 LLVM_READONLY
364 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
365                            const MIMGDimInfo *Dim, bool IsA16,
366                            bool IsG16Supported);
367 
368 struct MIMGInfo {
369   uint16_t Opcode;
370   uint16_t BaseOpcode;
371   uint8_t MIMGEncoding;
372   uint8_t VDataDwords;
373   uint8_t VAddrDwords;
374 };
375 
376 LLVM_READONLY
377 const MIMGInfo *getMIMGInfo(unsigned Opc);
378 
379 LLVM_READONLY
380 int getMTBUFBaseOpcode(unsigned Opc);
381 
382 LLVM_READONLY
383 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
384 
385 LLVM_READONLY
386 int getMTBUFElements(unsigned Opc);
387 
388 LLVM_READONLY
389 bool getMTBUFHasVAddr(unsigned Opc);
390 
391 LLVM_READONLY
392 bool getMTBUFHasSrsrc(unsigned Opc);
393 
394 LLVM_READONLY
395 bool getMTBUFHasSoffset(unsigned Opc);
396 
397 LLVM_READONLY
398 int getMUBUFBaseOpcode(unsigned Opc);
399 
400 LLVM_READONLY
401 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
402 
403 LLVM_READONLY
404 int getMUBUFElements(unsigned Opc);
405 
406 LLVM_READONLY
407 bool getMUBUFHasVAddr(unsigned Opc);
408 
409 LLVM_READONLY
410 bool getMUBUFHasSrsrc(unsigned Opc);
411 
412 LLVM_READONLY
413 bool getMUBUFHasSoffset(unsigned Opc);
414 
415 LLVM_READONLY
416 bool getMUBUFIsBufferInv(unsigned Opc);
417 
418 LLVM_READONLY
419 bool getSMEMIsBuffer(unsigned Opc);
420 
421 LLVM_READONLY
422 bool getVOP1IsSingle(unsigned Opc);
423 
424 LLVM_READONLY
425 bool getVOP2IsSingle(unsigned Opc);
426 
427 LLVM_READONLY
428 bool getVOP3IsSingle(unsigned Opc);
429 
430 LLVM_READONLY
431 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
432                                                   uint8_t NumComponents,
433                                                   uint8_t NumFormat,
434                                                   const MCSubtargetInfo &STI);
435 LLVM_READONLY
436 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
437                                                   const MCSubtargetInfo &STI);
438 
439 LLVM_READONLY
440 int getMCOpcode(uint16_t Opcode, unsigned Gen);
441 
442 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
443                                const MCSubtargetInfo *STI);
444 
445 amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(
446     const MCSubtargetInfo *STI);
447 
448 bool isGroupSegment(const GlobalValue *GV);
449 bool isGlobalSegment(const GlobalValue *GV);
450 bool isReadOnlySegment(const GlobalValue *GV);
451 
452 /// \returns True if constants should be emitted to .text section for given
453 /// target triple \p TT, false otherwise.
454 bool shouldEmitConstantsToTextSection(const Triple &TT);
455 
456 /// \returns Integer value requested using \p F's \p Name attribute.
457 ///
458 /// \returns \p Default if attribute is not present.
459 ///
460 /// \returns \p Default and emits error if requested value cannot be converted
461 /// to integer.
462 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
463 
464 /// \returns A pair of integer values requested using \p F's \p Name attribute
465 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
466 /// is false).
467 ///
468 /// \returns \p Default if attribute is not present.
469 ///
470 /// \returns \p Default and emits error if one of the requested values cannot be
471 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
472 /// not present.
473 std::pair<int, int> getIntegerPairAttribute(const Function &F,
474                                             StringRef Name,
475                                             std::pair<int, int> Default,
476                                             bool OnlyFirstRequired = false);
477 
478 /// Represents the counter values to wait for in an s_waitcnt instruction.
479 ///
480 /// Large values (including the maximum possible integer) can be used to
481 /// represent "don't care" waits.
482 struct Waitcnt {
483   unsigned VmCnt = ~0u;
484   unsigned ExpCnt = ~0u;
485   unsigned LgkmCnt = ~0u;
486   unsigned VsCnt = ~0u;
487 
488   Waitcnt() {}
489   Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
490       : VmCnt(VmCnt), ExpCnt(ExpCnt), LgkmCnt(LgkmCnt), VsCnt(VsCnt) {}
491 
492   static Waitcnt allZero(bool HasVscnt) {
493     return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
494   }
495   static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
496 
497   bool hasWait() const {
498     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
499   }
500 
501   bool hasWaitExceptVsCnt() const {
502     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u;
503   }
504 
505   bool hasWaitVsCnt() const {
506     return VsCnt != ~0u;
507   }
508 
509   bool dominates(const Waitcnt &Other) const {
510     return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
511            LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
512   }
513 
514   Waitcnt combined(const Waitcnt &Other) const {
515     return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
516                    std::min(LgkmCnt, Other.LgkmCnt),
517                    std::min(VsCnt, Other.VsCnt));
518   }
519 };
520 
521 /// \returns Vmcnt bit mask for given isa \p Version.
522 unsigned getVmcntBitMask(const IsaVersion &Version);
523 
524 /// \returns Expcnt bit mask for given isa \p Version.
525 unsigned getExpcntBitMask(const IsaVersion &Version);
526 
527 /// \returns Lgkmcnt bit mask for given isa \p Version.
528 unsigned getLgkmcntBitMask(const IsaVersion &Version);
529 
530 /// \returns Waitcnt bit mask for given isa \p Version.
531 unsigned getWaitcntBitMask(const IsaVersion &Version);
532 
533 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
534 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
535 
536 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
537 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
538 
539 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
540 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
541 
542 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
543 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
544 /// \p Lgkmcnt respectively.
545 ///
546 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
547 ///     \p Vmcnt = \p Waitcnt[3:0]                      (pre-gfx9 only)
548 ///     \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14]  (gfx9+ only)
549 ///     \p Expcnt = \p Waitcnt[6:4]
550 ///     \p Lgkmcnt = \p Waitcnt[11:8]                   (pre-gfx10 only)
551 ///     \p Lgkmcnt = \p Waitcnt[13:8]                   (gfx10+ only)
552 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
553                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
554 
555 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
556 
557 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
558 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
559                      unsigned Vmcnt);
560 
561 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
562 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
563                       unsigned Expcnt);
564 
565 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
566 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
567                        unsigned Lgkmcnt);
568 
569 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
570 /// \p Version.
571 ///
572 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
573 ///     Waitcnt[3:0]   = \p Vmcnt       (pre-gfx9 only)
574 ///     Waitcnt[3:0]   = \p Vmcnt[3:0]  (gfx9+ only)
575 ///     Waitcnt[6:4]   = \p Expcnt
576 ///     Waitcnt[11:8]  = \p Lgkmcnt     (pre-gfx10 only)
577 ///     Waitcnt[13:8]  = \p Lgkmcnt     (gfx10+ only)
578 ///     Waitcnt[15:14] = \p Vmcnt[5:4]  (gfx9+ only)
579 ///
580 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
581 /// isa \p Version.
582 unsigned encodeWaitcnt(const IsaVersion &Version,
583                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
584 
585 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
586 
587 namespace Hwreg {
588 
589 LLVM_READONLY
590 int64_t getHwregId(const StringRef Name);
591 
592 LLVM_READNONE
593 bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI);
594 
595 LLVM_READNONE
596 bool isValidHwreg(int64_t Id);
597 
598 LLVM_READNONE
599 bool isValidHwregOffset(int64_t Offset);
600 
601 LLVM_READNONE
602 bool isValidHwregWidth(int64_t Width);
603 
604 LLVM_READNONE
605 uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
606 
607 LLVM_READNONE
608 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
609 
610 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
611 
612 } // namespace Hwreg
613 
614 namespace Exp {
615 
616 bool getTgtName(unsigned Id, StringRef &Name, int &Index);
617 
618 LLVM_READONLY
619 unsigned getTgtId(const StringRef Name);
620 
621 LLVM_READNONE
622 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
623 
624 } // namespace Exp
625 
626 namespace MTBUFFormat {
627 
628 LLVM_READNONE
629 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
630 
631 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
632 
633 int64_t getDfmt(const StringRef Name);
634 
635 StringRef getDfmtName(unsigned Id);
636 
637 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
638 
639 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
640 
641 bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
642 
643 bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
644 
645 int64_t getUnifiedFormat(const StringRef Name);
646 
647 StringRef getUnifiedFormatName(unsigned Id);
648 
649 bool isValidUnifiedFormat(unsigned Val);
650 
651 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt);
652 
653 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
654 
655 unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
656 
657 } // namespace MTBUFFormat
658 
659 namespace SendMsg {
660 
661 LLVM_READONLY
662 int64_t getMsgId(const StringRef Name);
663 
664 LLVM_READONLY
665 int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
666 
667 LLVM_READNONE
668 StringRef getMsgName(int64_t MsgId);
669 
670 LLVM_READNONE
671 StringRef getMsgOpName(int64_t MsgId, int64_t OpId);
672 
673 LLVM_READNONE
674 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict = true);
675 
676 LLVM_READNONE
677 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
678                   bool Strict = true);
679 
680 LLVM_READNONE
681 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
682                       const MCSubtargetInfo &STI, bool Strict = true);
683 
684 LLVM_READNONE
685 bool msgRequiresOp(int64_t MsgId);
686 
687 LLVM_READNONE
688 bool msgSupportsStream(int64_t MsgId, int64_t OpId);
689 
690 void decodeMsg(unsigned Val,
691                uint16_t &MsgId,
692                uint16_t &OpId,
693                uint16_t &StreamId);
694 
695 LLVM_READNONE
696 uint64_t encodeMsg(uint64_t MsgId,
697                    uint64_t OpId,
698                    uint64_t StreamId);
699 
700 } // namespace SendMsg
701 
702 
703 unsigned getInitialPSInputAddr(const Function &F);
704 
705 bool getHasColorExport(const Function &F);
706 
707 bool getHasDepthExport(const Function &F);
708 
709 LLVM_READNONE
710 bool isShader(CallingConv::ID CC);
711 
712 LLVM_READNONE
713 bool isGraphics(CallingConv::ID CC);
714 
715 LLVM_READNONE
716 bool isCompute(CallingConv::ID CC);
717 
718 LLVM_READNONE
719 bool isEntryFunctionCC(CallingConv::ID CC);
720 
721 // These functions are considered entrypoints into the current module, i.e. they
722 // are allowed to be called from outside the current module. This is different
723 // from isEntryFunctionCC, which is only true for functions that are entered by
724 // the hardware. Module entry points include all entry functions but also
725 // include functions that can be called from other functions inside or outside
726 // the current module. Module entry functions are allowed to allocate LDS.
727 LLVM_READNONE
728 bool isModuleEntryFunctionCC(CallingConv::ID CC);
729 
730 // FIXME: Remove this when calling conventions cleaned up
731 LLVM_READNONE
732 inline bool isKernel(CallingConv::ID CC) {
733   switch (CC) {
734   case CallingConv::AMDGPU_KERNEL:
735   case CallingConv::SPIR_KERNEL:
736     return true;
737   default:
738     return false;
739   }
740 }
741 
742 bool hasXNACK(const MCSubtargetInfo &STI);
743 bool hasSRAMECC(const MCSubtargetInfo &STI);
744 bool hasMIMG_R128(const MCSubtargetInfo &STI);
745 bool hasGFX10A16(const MCSubtargetInfo &STI);
746 bool hasG16(const MCSubtargetInfo &STI);
747 bool hasPackedD16(const MCSubtargetInfo &STI);
748 
749 bool isSI(const MCSubtargetInfo &STI);
750 bool isCI(const MCSubtargetInfo &STI);
751 bool isVI(const MCSubtargetInfo &STI);
752 bool isGFX9(const MCSubtargetInfo &STI);
753 bool isGFX9Plus(const MCSubtargetInfo &STI);
754 bool isGFX10(const MCSubtargetInfo &STI);
755 bool isGFX10Plus(const MCSubtargetInfo &STI);
756 bool isGCN3Encoding(const MCSubtargetInfo &STI);
757 bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
758 bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
759 bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
760 bool isGFX90A(const MCSubtargetInfo &STI);
761 bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI);
762 
763 /// Is Reg - scalar register
764 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
765 
766 /// Is there any intersection between registers
767 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
768 
769 /// If \p Reg is a pseudo reg, return the correct hardware register given
770 /// \p STI otherwise return \p Reg.
771 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
772 
773 /// Convert hardware register \p Reg to a pseudo register
774 LLVM_READNONE
775 unsigned mc2PseudoReg(unsigned Reg);
776 
777 /// Can this operand also contain immediate values?
778 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
779 
780 /// Is this floating-point operand?
781 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
782 
783 /// Does this operand support only inlinable literals?
784 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
785 
786 /// Get the size in bits of a register from the register class \p RC.
787 unsigned getRegBitWidth(unsigned RCID);
788 
789 /// Get the size in bits of a register from the register class \p RC.
790 unsigned getRegBitWidth(const MCRegisterClass &RC);
791 
792 /// Get size of register operand
793 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
794                            unsigned OpNo);
795 
796 LLVM_READNONE
797 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
798   switch (OpInfo.OperandType) {
799   case AMDGPU::OPERAND_REG_IMM_INT32:
800   case AMDGPU::OPERAND_REG_IMM_FP32:
801   case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
802   case AMDGPU::OPERAND_REG_INLINE_C_INT32:
803   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
804   case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
805   case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
806   case AMDGPU::OPERAND_REG_IMM_V2INT32:
807   case AMDGPU::OPERAND_REG_IMM_V2FP32:
808   case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
809   case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
810   case AMDGPU::OPERAND_KIMM32:
811   case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 4
812     return 4;
813 
814   case AMDGPU::OPERAND_REG_IMM_INT64:
815   case AMDGPU::OPERAND_REG_IMM_FP64:
816   case AMDGPU::OPERAND_REG_INLINE_C_INT64:
817   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
818   case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
819     return 8;
820 
821   case AMDGPU::OPERAND_REG_IMM_INT16:
822   case AMDGPU::OPERAND_REG_IMM_FP16:
823   case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
824   case AMDGPU::OPERAND_REG_INLINE_C_INT16:
825   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
826   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
827   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
828   case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
829   case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
830   case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
831   case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
832   case AMDGPU::OPERAND_REG_IMM_V2INT16:
833   case AMDGPU::OPERAND_REG_IMM_V2FP16:
834     return 2;
835 
836   default:
837     llvm_unreachable("unhandled operand type");
838   }
839 }
840 
841 LLVM_READNONE
842 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
843   return getOperandSize(Desc.OpInfo[OpNo]);
844 }
845 
846 /// Is this literal inlinable, and not one of the values intended for floating
847 /// point values.
848 LLVM_READNONE
849 inline bool isInlinableIntLiteral(int64_t Literal) {
850   return Literal >= -16 && Literal <= 64;
851 }
852 
853 /// Is this literal inlinable
854 LLVM_READNONE
855 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
856 
857 LLVM_READNONE
858 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
859 
860 LLVM_READNONE
861 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
862 
863 LLVM_READNONE
864 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
865 
866 LLVM_READNONE
867 bool isInlinableIntLiteralV216(int32_t Literal);
868 
869 LLVM_READNONE
870 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
871 
872 bool isArgPassedInSGPR(const Argument *Arg);
873 
874 LLVM_READONLY
875 bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
876                                       int64_t EncodedOffset);
877 
878 LLVM_READONLY
879 bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,
880                                     int64_t EncodedOffset,
881                                     bool IsBuffer);
882 
883 /// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
884 /// offsets.
885 uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
886 
887 /// \returns The encoding that will be used for \p ByteOffset in the
888 /// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
889 /// S_LOAD instructions have a signed offset, on other subtargets it is
890 /// unsigned. S_BUFFER has an unsigned offset for all subtargets.
891 Optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
892                                        int64_t ByteOffset, bool IsBuffer);
893 
894 /// \return The encoding that can be used for a 32-bit literal offset in an SMRD
895 /// instruction. This is only useful on CI.s
896 Optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
897                                                 int64_t ByteOffset);
898 
899 /// For FLAT segment the offset must be positive;
900 /// MSB is ignored and forced to zero.
901 ///
902 /// \return The number of bits available for the offset field in flat
903 /// instructions.
904 unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed);
905 
906 /// \returns true if this offset is small enough to fit in the SMRD
907 /// offset field.  \p ByteOffset should be the offset in bytes and
908 /// not the encoded offset.
909 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
910 
911 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
912                       const GCNSubtarget *Subtarget,
913                       Align Alignment = Align(4));
914 
915 LLVM_READNONE
916 inline bool isLegal64BitDPPControl(unsigned DC) {
917   return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
918 }
919 
920 /// \returns true if the intrinsic is divergent
921 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
922 
923 // Track defaults for fields in the MODE registser.
924 struct SIModeRegisterDefaults {
925   /// Floating point opcodes that support exception flag gathering quiet and
926   /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
927   /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
928   /// quieting.
929   bool IEEE : 1;
930 
931   /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
932   /// clamp NaN to zero; otherwise, pass NaN through.
933   bool DX10Clamp : 1;
934 
935   /// If this is set, neither input or output denormals are flushed for most f32
936   /// instructions.
937   bool FP32InputDenormals : 1;
938   bool FP32OutputDenormals : 1;
939 
940   /// If this is set, neither input or output denormals are flushed for both f64
941   /// and f16/v2f16 instructions.
942   bool FP64FP16InputDenormals : 1;
943   bool FP64FP16OutputDenormals : 1;
944 
945   SIModeRegisterDefaults() :
946     IEEE(true),
947     DX10Clamp(true),
948     FP32InputDenormals(true),
949     FP32OutputDenormals(true),
950     FP64FP16InputDenormals(true),
951     FP64FP16OutputDenormals(true) {}
952 
953   SIModeRegisterDefaults(const Function &F);
954 
955   static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) {
956     SIModeRegisterDefaults Mode;
957     Mode.IEEE = !AMDGPU::isShader(CC);
958     return Mode;
959   }
960 
961   bool operator ==(const SIModeRegisterDefaults Other) const {
962     return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
963            FP32InputDenormals == Other.FP32InputDenormals &&
964            FP32OutputDenormals == Other.FP32OutputDenormals &&
965            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
966            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
967   }
968 
969   bool allFP32Denormals() const {
970     return FP32InputDenormals && FP32OutputDenormals;
971   }
972 
973   bool allFP64FP16Denormals() const {
974     return FP64FP16InputDenormals && FP64FP16OutputDenormals;
975   }
976 
977   /// Get the encoding value for the FP_DENORM bits of the mode register for the
978   /// FP32 denormal mode.
979   uint32_t fpDenormModeSPValue() const {
980     if (FP32InputDenormals && FP32OutputDenormals)
981       return FP_DENORM_FLUSH_NONE;
982     if (FP32InputDenormals)
983       return FP_DENORM_FLUSH_OUT;
984     if (FP32OutputDenormals)
985       return FP_DENORM_FLUSH_IN;
986     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
987   }
988 
989   /// Get the encoding value for the FP_DENORM bits of the mode register for the
990   /// FP64/FP16 denormal mode.
991   uint32_t fpDenormModeDPValue() const {
992     if (FP64FP16InputDenormals && FP64FP16OutputDenormals)
993       return FP_DENORM_FLUSH_NONE;
994     if (FP64FP16InputDenormals)
995       return FP_DENORM_FLUSH_OUT;
996     if (FP64FP16OutputDenormals)
997       return FP_DENORM_FLUSH_IN;
998     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
999   }
1000 
1001   /// Returns true if a flag is compatible if it's enabled in the callee, but
1002   /// disabled in the caller.
1003   static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
1004     return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
1005   }
1006 
1007   // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
1008   // be able to override.
1009   bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
1010     if (DX10Clamp != CalleeMode.DX10Clamp)
1011       return false;
1012     if (IEEE != CalleeMode.IEEE)
1013       return false;
1014 
1015     // Allow inlining denormals enabled into denormals flushed functions.
1016     return oneWayCompatible(FP64FP16InputDenormals, CalleeMode.FP64FP16InputDenormals) &&
1017            oneWayCompatible(FP64FP16OutputDenormals, CalleeMode.FP64FP16OutputDenormals) &&
1018            oneWayCompatible(FP32InputDenormals, CalleeMode.FP32InputDenormals) &&
1019            oneWayCompatible(FP32OutputDenormals, CalleeMode.FP32OutputDenormals);
1020   }
1021 };
1022 
1023 } // end namespace AMDGPU
1024 
1025 raw_ostream &operator<<(raw_ostream &OS,
1026                         const AMDGPU::IsaInfo::TargetIDSetting S);
1027 
1028 } // end namespace llvm
1029 
1030 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
1031