1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "SIDefines.h"
13 #include "llvm/IR/CallingConv.h"
14 #include "llvm/Support/Alignment.h"
15 
16 struct amd_kernel_code_t;
17 
18 namespace llvm {
19 
20 struct Align;
21 class Argument;
22 class Function;
23 class GCNSubtarget;
24 class GlobalValue;
25 class MCRegisterClass;
26 class MCRegisterInfo;
27 class MCSubtargetInfo;
28 class StringRef;
29 class Triple;
30 
31 namespace amdhsa {
32 struct kernel_descriptor_t;
33 }
34 
35 namespace AMDGPU {
36 
37 struct IsaVersion;
38 
39 /// \returns HSA OS ABI Version identification.
40 Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
41 /// \returns True if HSA OS ABI Version identification is 2,
42 /// false otherwise.
43 bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
44 /// \returns True if HSA OS ABI Version identification is 3,
45 /// false otherwise.
46 bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
47 
48 struct GcnBufferFormatInfo {
49   unsigned Format;
50   unsigned BitsPerComp;
51   unsigned NumComponents;
52   unsigned NumFormat;
53   unsigned DataFormat;
54 };
55 
56 #define GET_MIMGBaseOpcode_DECL
57 #define GET_MIMGDim_DECL
58 #define GET_MIMGEncoding_DECL
59 #define GET_MIMGLZMapping_DECL
60 #define GET_MIMGMIPMapping_DECL
61 #include "AMDGPUGenSearchableTables.inc"
62 
63 namespace IsaInfo {
64 
65 enum {
66   // The closed Vulkan driver sets 96, which limits the wave count to 8 but
67   // doesn't spill SGPRs as much as when 80 is set.
68   FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
69   TRAP_NUM_SGPRS = 16
70 };
71 
72 enum class TargetIDSetting {
73   Unsupported,
74   Any,
75   Off,
76   On
77 };
78 
79 class AMDGPUTargetID {
80 private:
81   TargetIDSetting XnackSetting;
82   TargetIDSetting SramEccSetting;
83 
84 public:
85   explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
86   ~AMDGPUTargetID() = default;
87 
88   /// \return True if the current xnack setting is not "Unsupported".
89   bool isXnackSupported() const {
90     return XnackSetting != TargetIDSetting::Unsupported;
91   }
92 
93   /// \returns True if the current xnack setting is "On" or "Any".
94   bool isXnackOnOrAny() const {
95     return XnackSetting == TargetIDSetting::On ||
96         XnackSetting == TargetIDSetting::Any;
97   }
98 
99   /// \returns True if current xnack setting is "On" or "Off",
100   /// false otherwise.
101   bool isXnackOnOrOff() const {
102     return getXnackSetting() == TargetIDSetting::On ||
103         getXnackSetting() == TargetIDSetting::Off;
104   }
105 
106   /// \returns The current xnack TargetIDSetting, possible options are
107   /// "Unsupported", "Any", "Off", and "On".
108   TargetIDSetting getXnackSetting() const {
109     return XnackSetting;
110   }
111 
112   /// Sets xnack setting to \p NewXnackSetting.
113   void setXnackSetting(TargetIDSetting NewXnackSetting) {
114     XnackSetting = NewXnackSetting;
115   }
116 
117   /// \return True if the current sramecc setting is not "Unsupported".
118   bool isSramEccSupported() const {
119     return SramEccSetting != TargetIDSetting::Unsupported;
120   }
121 
122   /// \returns True if the current sramecc setting is "On" or "Any".
123   bool isSramEccOnOrAny() const {
124   return SramEccSetting == TargetIDSetting::On ||
125       SramEccSetting == TargetIDSetting::Any;
126   }
127 
128   /// \returns True if current sramecc setting is "On" or "Off",
129   /// false otherwise.
130   bool isSramEccOnOrOff() const {
131     return getSramEccSetting() == TargetIDSetting::On ||
132         getSramEccSetting() == TargetIDSetting::Off;
133   }
134 
135   /// \returns The current sramecc TargetIDSetting, possible options are
136   /// "Unsupported", "Any", "Off", and "On".
137   TargetIDSetting getSramEccSetting() const {
138     return SramEccSetting;
139   }
140 
141   /// Sets sramecc setting to \p NewSramEccSetting.
142   void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
143     SramEccSetting = NewSramEccSetting;
144   }
145 
146   void setTargetIDFromFeaturesString(StringRef FS);
147   void setTargetIDFromTargetIDStream(StringRef TargetID);
148 };
149 
150 /// Streams isa version string for given subtarget \p STI into \p Stream.
151 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream);
152 
153 /// \returns Wavefront size for given subtarget \p STI.
154 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
155 
156 /// \returns Local memory size in bytes for given subtarget \p STI.
157 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
158 
159 /// \returns Number of execution units per compute unit for given subtarget \p
160 /// STI.
161 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
162 
163 /// \returns Maximum number of work groups per compute unit for given subtarget
164 /// \p STI and limited by given \p FlatWorkGroupSize.
165 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
166                                unsigned FlatWorkGroupSize);
167 
168 /// \returns Minimum number of waves per execution unit for given subtarget \p
169 /// STI.
170 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
171 
172 /// \returns Maximum number of waves per execution unit for given subtarget \p
173 /// STI without any kind of limitation.
174 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
175 
176 /// \returns Number of waves per execution unit required to support the given \p
177 /// FlatWorkGroupSize.
178 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
179                                    unsigned FlatWorkGroupSize);
180 
181 /// \returns Minimum flat work group size for given subtarget \p STI.
182 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
183 
184 /// \returns Maximum flat work group size for given subtarget \p STI.
185 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
186 
187 /// \returns Number of waves per work group for given subtarget \p STI and
188 /// \p FlatWorkGroupSize.
189 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
190                               unsigned FlatWorkGroupSize);
191 
192 /// \returns SGPR allocation granularity for given subtarget \p STI.
193 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
194 
195 /// \returns SGPR encoding granularity for given subtarget \p STI.
196 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
197 
198 /// \returns Total number of SGPRs for given subtarget \p STI.
199 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
200 
201 /// \returns Addressable number of SGPRs for given subtarget \p STI.
202 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
203 
204 /// \returns Minimum number of SGPRs that meets the given number of waves per
205 /// execution unit requirement for given subtarget \p STI.
206 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
207 
208 /// \returns Maximum number of SGPRs that meets the given number of waves per
209 /// execution unit requirement for given subtarget \p STI.
210 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
211                         bool Addressable);
212 
213 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
214 /// STI when the given special registers are used.
215 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
216                           bool FlatScrUsed, bool XNACKUsed);
217 
218 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
219 /// STI when the given special registers are used. XNACK is inferred from
220 /// \p STI.
221 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
222                           bool FlatScrUsed);
223 
224 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
225 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
226 /// register counts.
227 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
228 
229 /// \returns VGPR allocation granularity for given subtarget \p STI.
230 ///
231 /// For subtargets which support it, \p EnableWavefrontSize32 should match
232 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
233 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
234                              Optional<bool> EnableWavefrontSize32 = None);
235 
236 /// \returns VGPR encoding granularity for given subtarget \p STI.
237 ///
238 /// For subtargets which support it, \p EnableWavefrontSize32 should match
239 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
240 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
241                                 Optional<bool> EnableWavefrontSize32 = None);
242 
243 /// \returns Total number of VGPRs for given subtarget \p STI.
244 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
245 
246 /// \returns Addressable number of VGPRs for given subtarget \p STI.
247 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
248 
249 /// \returns Minimum number of VGPRs that meets given number of waves per
250 /// execution unit requirement for given subtarget \p STI.
251 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
252 
253 /// \returns Maximum number of VGPRs that meets given number of waves per
254 /// execution unit requirement for given subtarget \p STI.
255 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
256 
257 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
258 /// \p NumVGPRs are used.
259 ///
260 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
261 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
262 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
263                           Optional<bool> EnableWavefrontSize32 = None);
264 
265 } // end namespace IsaInfo
266 
267 LLVM_READONLY
268 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
269 
270 LLVM_READONLY
271 int getSOPPWithRelaxation(uint16_t Opcode);
272 
273 struct MIMGBaseOpcodeInfo {
274   MIMGBaseOpcode BaseOpcode;
275   bool Store;
276   bool Atomic;
277   bool AtomicX2;
278   bool Sampler;
279   bool Gather4;
280 
281   uint8_t NumExtraArgs;
282   bool Gradients;
283   bool G16;
284   bool Coordinates;
285   bool LodOrClampOrMip;
286   bool HasD16;
287   bool MSAA;
288 };
289 
290 LLVM_READONLY
291 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
292 
293 struct MIMGDimInfo {
294   MIMGDim Dim;
295   uint8_t NumCoords;
296   uint8_t NumGradients;
297   bool MSAA;
298   bool DA;
299   uint8_t Encoding;
300   const char *AsmSuffix;
301 };
302 
303 LLVM_READONLY
304 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
305 
306 LLVM_READONLY
307 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
308 
309 LLVM_READONLY
310 const MIMGDimInfo *getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix);
311 
312 struct MIMGLZMappingInfo {
313   MIMGBaseOpcode L;
314   MIMGBaseOpcode LZ;
315 };
316 
317 struct MIMGMIPMappingInfo {
318   MIMGBaseOpcode MIP;
319   MIMGBaseOpcode NONMIP;
320 };
321 
322 struct MIMGG16MappingInfo {
323   MIMGBaseOpcode G;
324   MIMGBaseOpcode G16;
325 };
326 
327 LLVM_READONLY
328 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
329 
330 LLVM_READONLY
331 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
332 
333 LLVM_READONLY
334 const MIMGG16MappingInfo *getMIMGG16MappingInfo(unsigned G);
335 
336 LLVM_READONLY
337 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
338                   unsigned VDataDwords, unsigned VAddrDwords);
339 
340 LLVM_READONLY
341 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
342 
343 struct MIMGInfo {
344   uint16_t Opcode;
345   uint16_t BaseOpcode;
346   uint8_t MIMGEncoding;
347   uint8_t VDataDwords;
348   uint8_t VAddrDwords;
349 };
350 
351 LLVM_READONLY
352 const MIMGInfo *getMIMGInfo(unsigned Opc);
353 
354 LLVM_READONLY
355 int getMTBUFBaseOpcode(unsigned Opc);
356 
357 LLVM_READONLY
358 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
359 
360 LLVM_READONLY
361 int getMTBUFElements(unsigned Opc);
362 
363 LLVM_READONLY
364 bool getMTBUFHasVAddr(unsigned Opc);
365 
366 LLVM_READONLY
367 bool getMTBUFHasSrsrc(unsigned Opc);
368 
369 LLVM_READONLY
370 bool getMTBUFHasSoffset(unsigned Opc);
371 
372 LLVM_READONLY
373 int getMUBUFBaseOpcode(unsigned Opc);
374 
375 LLVM_READONLY
376 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
377 
378 LLVM_READONLY
379 int getMUBUFElements(unsigned Opc);
380 
381 LLVM_READONLY
382 bool getMUBUFHasVAddr(unsigned Opc);
383 
384 LLVM_READONLY
385 bool getMUBUFHasSrsrc(unsigned Opc);
386 
387 LLVM_READONLY
388 bool getMUBUFHasSoffset(unsigned Opc);
389 
390 LLVM_READONLY
391 bool getSMEMIsBuffer(unsigned Opc);
392 
393 LLVM_READONLY
394 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
395                                                   uint8_t NumComponents,
396                                                   uint8_t NumFormat,
397                                                   const MCSubtargetInfo &STI);
398 LLVM_READONLY
399 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
400                                                   const MCSubtargetInfo &STI);
401 
402 LLVM_READONLY
403 int getMCOpcode(uint16_t Opcode, unsigned Gen);
404 
405 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
406                                const MCSubtargetInfo *STI);
407 
408 amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(
409     const MCSubtargetInfo *STI);
410 
411 bool isGroupSegment(const GlobalValue *GV);
412 bool isGlobalSegment(const GlobalValue *GV);
413 bool isReadOnlySegment(const GlobalValue *GV);
414 
415 /// \returns True if constants should be emitted to .text section for given
416 /// target triple \p TT, false otherwise.
417 bool shouldEmitConstantsToTextSection(const Triple &TT);
418 
419 /// \returns Integer value requested using \p F's \p Name attribute.
420 ///
421 /// \returns \p Default if attribute is not present.
422 ///
423 /// \returns \p Default and emits error if requested value cannot be converted
424 /// to integer.
425 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
426 
427 /// \returns A pair of integer values requested using \p F's \p Name attribute
428 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
429 /// is false).
430 ///
431 /// \returns \p Default if attribute is not present.
432 ///
433 /// \returns \p Default and emits error if one of the requested values cannot be
434 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
435 /// not present.
436 std::pair<int, int> getIntegerPairAttribute(const Function &F,
437                                             StringRef Name,
438                                             std::pair<int, int> Default,
439                                             bool OnlyFirstRequired = false);
440 
441 /// Represents the counter values to wait for in an s_waitcnt instruction.
442 ///
443 /// Large values (including the maximum possible integer) can be used to
444 /// represent "don't care" waits.
445 struct Waitcnt {
446   unsigned VmCnt = ~0u;
447   unsigned ExpCnt = ~0u;
448   unsigned LgkmCnt = ~0u;
449   unsigned VsCnt = ~0u;
450 
451   Waitcnt() {}
452   Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
453       : VmCnt(VmCnt), ExpCnt(ExpCnt), LgkmCnt(LgkmCnt), VsCnt(VsCnt) {}
454 
455   static Waitcnt allZero(bool HasVscnt) {
456     return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
457   }
458   static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
459 
460   bool hasWait() const {
461     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
462   }
463 
464   bool dominates(const Waitcnt &Other) const {
465     return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
466            LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
467   }
468 
469   Waitcnt combined(const Waitcnt &Other) const {
470     return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
471                    std::min(LgkmCnt, Other.LgkmCnt),
472                    std::min(VsCnt, Other.VsCnt));
473   }
474 };
475 
476 /// \returns Vmcnt bit mask for given isa \p Version.
477 unsigned getVmcntBitMask(const IsaVersion &Version);
478 
479 /// \returns Expcnt bit mask for given isa \p Version.
480 unsigned getExpcntBitMask(const IsaVersion &Version);
481 
482 /// \returns Lgkmcnt bit mask for given isa \p Version.
483 unsigned getLgkmcntBitMask(const IsaVersion &Version);
484 
485 /// \returns Waitcnt bit mask for given isa \p Version.
486 unsigned getWaitcntBitMask(const IsaVersion &Version);
487 
488 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
489 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
490 
491 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
492 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
493 
494 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
495 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
496 
497 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
498 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
499 /// \p Lgkmcnt respectively.
500 ///
501 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
502 ///     \p Vmcnt = \p Waitcnt[3:0]                      (pre-gfx9 only)
503 ///     \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14]  (gfx9+ only)
504 ///     \p Expcnt = \p Waitcnt[6:4]
505 ///     \p Lgkmcnt = \p Waitcnt[11:8]                   (pre-gfx10 only)
506 ///     \p Lgkmcnt = \p Waitcnt[13:8]                   (gfx10+ only)
507 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
508                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
509 
510 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
511 
512 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
513 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
514                      unsigned Vmcnt);
515 
516 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
517 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
518                       unsigned Expcnt);
519 
520 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
521 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
522                        unsigned Lgkmcnt);
523 
524 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
525 /// \p Version.
526 ///
527 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
528 ///     Waitcnt[3:0]   = \p Vmcnt       (pre-gfx9 only)
529 ///     Waitcnt[3:0]   = \p Vmcnt[3:0]  (gfx9+ only)
530 ///     Waitcnt[6:4]   = \p Expcnt
531 ///     Waitcnt[11:8]  = \p Lgkmcnt     (pre-gfx10 only)
532 ///     Waitcnt[13:8]  = \p Lgkmcnt     (gfx10+ only)
533 ///     Waitcnt[15:14] = \p Vmcnt[5:4]  (gfx9+ only)
534 ///
535 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
536 /// isa \p Version.
537 unsigned encodeWaitcnt(const IsaVersion &Version,
538                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
539 
540 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
541 
542 namespace Hwreg {
543 
544 LLVM_READONLY
545 int64_t getHwregId(const StringRef Name);
546 
547 LLVM_READNONE
548 bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI);
549 
550 LLVM_READNONE
551 bool isValidHwreg(int64_t Id);
552 
553 LLVM_READNONE
554 bool isValidHwregOffset(int64_t Offset);
555 
556 LLVM_READNONE
557 bool isValidHwregWidth(int64_t Width);
558 
559 LLVM_READNONE
560 uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
561 
562 LLVM_READNONE
563 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
564 
565 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
566 
567 } // namespace Hwreg
568 
569 namespace Exp {
570 
571 bool getTgtName(unsigned Id, StringRef &Name, int &Index);
572 
573 LLVM_READONLY
574 unsigned getTgtId(const StringRef Name);
575 
576 LLVM_READNONE
577 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
578 
579 } // namespace Exp
580 
581 namespace MTBUFFormat {
582 
583 LLVM_READNONE
584 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
585 
586 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
587 
588 int64_t getDfmt(const StringRef Name);
589 
590 StringRef getDfmtName(unsigned Id);
591 
592 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
593 
594 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
595 
596 bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
597 
598 bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
599 
600 int64_t getUnifiedFormat(const StringRef Name);
601 
602 StringRef getUnifiedFormatName(unsigned Id);
603 
604 bool isValidUnifiedFormat(unsigned Val);
605 
606 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt);
607 
608 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
609 
610 unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
611 
612 } // namespace MTBUFFormat
613 
614 namespace SendMsg {
615 
616 LLVM_READONLY
617 int64_t getMsgId(const StringRef Name);
618 
619 LLVM_READONLY
620 int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
621 
622 LLVM_READNONE
623 StringRef getMsgName(int64_t MsgId);
624 
625 LLVM_READNONE
626 StringRef getMsgOpName(int64_t MsgId, int64_t OpId);
627 
628 LLVM_READNONE
629 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict = true);
630 
631 LLVM_READNONE
632 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
633                   bool Strict = true);
634 
635 LLVM_READNONE
636 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
637                       const MCSubtargetInfo &STI, bool Strict = true);
638 
639 LLVM_READNONE
640 bool msgRequiresOp(int64_t MsgId);
641 
642 LLVM_READNONE
643 bool msgSupportsStream(int64_t MsgId, int64_t OpId);
644 
645 void decodeMsg(unsigned Val,
646                uint16_t &MsgId,
647                uint16_t &OpId,
648                uint16_t &StreamId);
649 
650 LLVM_READNONE
651 uint64_t encodeMsg(uint64_t MsgId,
652                    uint64_t OpId,
653                    uint64_t StreamId);
654 
655 } // namespace SendMsg
656 
657 
658 unsigned getInitialPSInputAddr(const Function &F);
659 
660 LLVM_READNONE
661 bool isShader(CallingConv::ID CC);
662 
663 LLVM_READNONE
664 bool isGraphics(CallingConv::ID CC);
665 
666 LLVM_READNONE
667 bool isCompute(CallingConv::ID CC);
668 
669 LLVM_READNONE
670 bool isEntryFunctionCC(CallingConv::ID CC);
671 
672 // These functions are considered entrypoints into the current module, i.e. they
673 // are allowed to be called from outside the current module. This is different
674 // from isEntryFunctionCC, which is only true for functions that are entered by
675 // the hardware. Module entry points include all entry functions but also
676 // include functions that can be called from other functions inside or outside
677 // the current module. Module entry functions are allowed to allocate LDS.
678 LLVM_READNONE
679 bool isModuleEntryFunctionCC(CallingConv::ID CC);
680 
681 // FIXME: Remove this when calling conventions cleaned up
682 LLVM_READNONE
683 inline bool isKernel(CallingConv::ID CC) {
684   switch (CC) {
685   case CallingConv::AMDGPU_KERNEL:
686   case CallingConv::SPIR_KERNEL:
687     return true;
688   default:
689     return false;
690   }
691 }
692 
693 bool hasXNACK(const MCSubtargetInfo &STI);
694 bool hasSRAMECC(const MCSubtargetInfo &STI);
695 bool hasMIMG_R128(const MCSubtargetInfo &STI);
696 bool hasGFX10A16(const MCSubtargetInfo &STI);
697 bool hasG16(const MCSubtargetInfo &STI);
698 bool hasPackedD16(const MCSubtargetInfo &STI);
699 
700 bool isSI(const MCSubtargetInfo &STI);
701 bool isCI(const MCSubtargetInfo &STI);
702 bool isVI(const MCSubtargetInfo &STI);
703 bool isGFX9(const MCSubtargetInfo &STI);
704 bool isGFX9Plus(const MCSubtargetInfo &STI);
705 bool isGFX10(const MCSubtargetInfo &STI);
706 bool isGFX10Plus(const MCSubtargetInfo &STI);
707 bool isGCN3Encoding(const MCSubtargetInfo &STI);
708 bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
709 bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
710 bool isGFX90A(const MCSubtargetInfo &STI);
711 
712 /// Is Reg - scalar register
713 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
714 
715 /// Is there any intersection between registers
716 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
717 
718 /// If \p Reg is a pseudo reg, return the correct hardware register given
719 /// \p STI otherwise return \p Reg.
720 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
721 
722 /// Convert hardware register \p Reg to a pseudo register
723 LLVM_READNONE
724 unsigned mc2PseudoReg(unsigned Reg);
725 
726 /// Can this operand also contain immediate values?
727 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
728 
729 /// Is this floating-point operand?
730 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
731 
732 /// Does this opearnd support only inlinable literals?
733 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
734 
735 /// Get the size in bits of a register from the register class \p RC.
736 unsigned getRegBitWidth(unsigned RCID);
737 
738 /// Get the size in bits of a register from the register class \p RC.
739 unsigned getRegBitWidth(const MCRegisterClass &RC);
740 
741 /// Get size of register operand
742 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
743                            unsigned OpNo);
744 
745 LLVM_READNONE
746 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
747   switch (OpInfo.OperandType) {
748   case AMDGPU::OPERAND_REG_IMM_INT32:
749   case AMDGPU::OPERAND_REG_IMM_FP32:
750   case AMDGPU::OPERAND_REG_INLINE_C_INT32:
751   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
752   case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
753   case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
754   case AMDGPU::OPERAND_REG_IMM_V2INT32:
755   case AMDGPU::OPERAND_REG_IMM_V2FP32:
756   case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
757   case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
758     return 4;
759 
760   case AMDGPU::OPERAND_REG_IMM_INT64:
761   case AMDGPU::OPERAND_REG_IMM_FP64:
762   case AMDGPU::OPERAND_REG_INLINE_C_INT64:
763   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
764   case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
765     return 8;
766 
767   case AMDGPU::OPERAND_REG_IMM_INT16:
768   case AMDGPU::OPERAND_REG_IMM_FP16:
769   case AMDGPU::OPERAND_REG_INLINE_C_INT16:
770   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
771   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
772   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
773   case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
774   case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
775   case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
776   case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
777   case AMDGPU::OPERAND_REG_IMM_V2INT16:
778   case AMDGPU::OPERAND_REG_IMM_V2FP16:
779     return 2;
780 
781   default:
782     llvm_unreachable("unhandled operand type");
783   }
784 }
785 
786 LLVM_READNONE
787 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
788   return getOperandSize(Desc.OpInfo[OpNo]);
789 }
790 
791 /// Is this literal inlinable, and not one of the values intended for floating
792 /// point values.
793 LLVM_READNONE
794 inline bool isInlinableIntLiteral(int64_t Literal) {
795   return Literal >= -16 && Literal <= 64;
796 }
797 
798 /// Is this literal inlinable
799 LLVM_READNONE
800 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
801 
802 LLVM_READNONE
803 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
804 
805 LLVM_READNONE
806 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
807 
808 LLVM_READNONE
809 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
810 
811 LLVM_READNONE
812 bool isInlinableIntLiteralV216(int32_t Literal);
813 
814 LLVM_READNONE
815 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
816 
817 bool isArgPassedInSGPR(const Argument *Arg);
818 
819 LLVM_READONLY
820 bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
821                                       int64_t EncodedOffset);
822 
823 LLVM_READONLY
824 bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,
825                                     int64_t EncodedOffset,
826                                     bool IsBuffer);
827 
828 /// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
829 /// offsets.
830 uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
831 
832 /// \returns The encoding that will be used for \p ByteOffset in the
833 /// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
834 /// S_LOAD instructions have a signed offset, on other subtargets it is
835 /// unsigned. S_BUFFER has an unsigned offset for all subtargets.
836 Optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
837                                        int64_t ByteOffset, bool IsBuffer);
838 
839 /// \return The encoding that can be used for a 32-bit literal offset in an SMRD
840 /// instruction. This is only useful on CI.s
841 Optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
842                                                 int64_t ByteOffset);
843 
844 /// For FLAT segment the offset must be positive;
845 /// MSB is ignored and forced to zero.
846 ///
847 /// \return The number of bits available for the offset field in flat
848 /// instructions.
849 unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed);
850 
851 /// \returns true if this offset is small enough to fit in the SMRD
852 /// offset field.  \p ByteOffset should be the offset in bytes and
853 /// not the encoded offset.
854 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
855 
856 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
857                       const GCNSubtarget *Subtarget,
858                       Align Alignment = Align(4));
859 
860 LLVM_READNONE
861 inline bool isLegal64BitDPPControl(unsigned DC) {
862   return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
863 }
864 
865 /// \returns true if the intrinsic is divergent
866 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
867 
868 // Track defaults for fields in the MODE registser.
869 struct SIModeRegisterDefaults {
870   /// Floating point opcodes that support exception flag gathering quiet and
871   /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
872   /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
873   /// quieting.
874   bool IEEE : 1;
875 
876   /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
877   /// clamp NaN to zero; otherwise, pass NaN through.
878   bool DX10Clamp : 1;
879 
880   /// If this is set, neither input or output denormals are flushed for most f32
881   /// instructions.
882   bool FP32InputDenormals : 1;
883   bool FP32OutputDenormals : 1;
884 
885   /// If this is set, neither input or output denormals are flushed for both f64
886   /// and f16/v2f16 instructions.
887   bool FP64FP16InputDenormals : 1;
888   bool FP64FP16OutputDenormals : 1;
889 
890   SIModeRegisterDefaults() :
891     IEEE(true),
892     DX10Clamp(true),
893     FP32InputDenormals(true),
894     FP32OutputDenormals(true),
895     FP64FP16InputDenormals(true),
896     FP64FP16OutputDenormals(true) {}
897 
898   SIModeRegisterDefaults(const Function &F);
899 
900   static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) {
901     SIModeRegisterDefaults Mode;
902     Mode.IEEE = !AMDGPU::isShader(CC);
903     return Mode;
904   }
905 
906   bool operator ==(const SIModeRegisterDefaults Other) const {
907     return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
908            FP32InputDenormals == Other.FP32InputDenormals &&
909            FP32OutputDenormals == Other.FP32OutputDenormals &&
910            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
911            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
912   }
913 
914   bool allFP32Denormals() const {
915     return FP32InputDenormals && FP32OutputDenormals;
916   }
917 
918   bool allFP64FP16Denormals() const {
919     return FP64FP16InputDenormals && FP64FP16OutputDenormals;
920   }
921 
922   /// Get the encoding value for the FP_DENORM bits of the mode register for the
923   /// FP32 denormal mode.
924   uint32_t fpDenormModeSPValue() const {
925     if (FP32InputDenormals && FP32OutputDenormals)
926       return FP_DENORM_FLUSH_NONE;
927     if (FP32InputDenormals)
928       return FP_DENORM_FLUSH_OUT;
929     if (FP32OutputDenormals)
930       return FP_DENORM_FLUSH_IN;
931     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
932   }
933 
934   /// Get the encoding value for the FP_DENORM bits of the mode register for the
935   /// FP64/FP16 denormal mode.
936   uint32_t fpDenormModeDPValue() const {
937     if (FP64FP16InputDenormals && FP64FP16OutputDenormals)
938       return FP_DENORM_FLUSH_NONE;
939     if (FP64FP16InputDenormals)
940       return FP_DENORM_FLUSH_OUT;
941     if (FP64FP16OutputDenormals)
942       return FP_DENORM_FLUSH_IN;
943     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
944   }
945 
946   /// Returns true if a flag is compatible if it's enabled in the callee, but
947   /// disabled in the caller.
948   static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
949     return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
950   }
951 
952   // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
953   // be able to override.
954   bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
955     if (DX10Clamp != CalleeMode.DX10Clamp)
956       return false;
957     if (IEEE != CalleeMode.IEEE)
958       return false;
959 
960     // Allow inlining denormals enabled into denormals flushed functions.
961     return oneWayCompatible(FP64FP16InputDenormals, CalleeMode.FP64FP16InputDenormals) &&
962            oneWayCompatible(FP64FP16OutputDenormals, CalleeMode.FP64FP16OutputDenormals) &&
963            oneWayCompatible(FP32InputDenormals, CalleeMode.FP32InputDenormals) &&
964            oneWayCompatible(FP32OutputDenormals, CalleeMode.FP32OutputDenormals);
965   }
966 };
967 
968 } // end namespace AMDGPU
969 
970 raw_ostream &operator<<(raw_ostream &OS,
971                         const AMDGPU::IsaInfo::TargetIDSetting S);
972 
973 } // end namespace llvm
974 
975 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
976