1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "SIDefines.h"
13 #include "llvm/IR/CallingConv.h"
14 #include "llvm/Support/Alignment.h"
15 
16 struct amd_kernel_code_t;
17 
18 namespace llvm {
19 
20 struct Align;
21 class Argument;
22 class Function;
23 class GCNSubtarget;
24 class GlobalValue;
25 class MCRegisterClass;
26 class MCRegisterInfo;
27 class MCSubtargetInfo;
28 class StringRef;
29 class Triple;
30 
31 namespace amdhsa {
32 struct kernel_descriptor_t;
33 }
34 
35 namespace AMDGPU {
36 
37 struct IsaVersion;
38 
39 /// \returns HSA OS ABI Version identification.
40 Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
41 /// \returns True if HSA OS ABI Version identification is 2,
42 /// false otherwise.
43 bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
44 /// \returns True if HSA OS ABI Version identification is 3,
45 /// false otherwise.
46 bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
47 /// \returns True if HSA OS ABI Version identification is 4,
48 /// false otherwise.
49 bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
50 /// \returns True if HSA OS ABI Version identification is 3 or 4,
51 /// false otherwise.
52 bool isHsaAbiVersion3Or4(const MCSubtargetInfo *STI);
53 
54 struct GcnBufferFormatInfo {
55   unsigned Format;
56   unsigned BitsPerComp;
57   unsigned NumComponents;
58   unsigned NumFormat;
59   unsigned DataFormat;
60 };
61 
62 #define GET_MIMGBaseOpcode_DECL
63 #define GET_MIMGDim_DECL
64 #define GET_MIMGEncoding_DECL
65 #define GET_MIMGLZMapping_DECL
66 #define GET_MIMGMIPMapping_DECL
67 #include "AMDGPUGenSearchableTables.inc"
68 
69 namespace IsaInfo {
70 
71 enum {
72   // The closed Vulkan driver sets 96, which limits the wave count to 8 but
73   // doesn't spill SGPRs as much as when 80 is set.
74   FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
75   TRAP_NUM_SGPRS = 16
76 };
77 
78 enum class TargetIDSetting {
79   Unsupported,
80   Any,
81   Off,
82   On
83 };
84 
85 class AMDGPUTargetID {
86 private:
87   const MCSubtargetInfo &STI;
88   TargetIDSetting XnackSetting;
89   TargetIDSetting SramEccSetting;
90 
91 public:
92   explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
93   ~AMDGPUTargetID() = default;
94 
95   /// \return True if the current xnack setting is not "Unsupported".
96   bool isXnackSupported() const {
97     return XnackSetting != TargetIDSetting::Unsupported;
98   }
99 
100   /// \returns True if the current xnack setting is "On" or "Any".
101   bool isXnackOnOrAny() const {
102     return XnackSetting == TargetIDSetting::On ||
103         XnackSetting == TargetIDSetting::Any;
104   }
105 
106   /// \returns True if current xnack setting is "On" or "Off",
107   /// false otherwise.
108   bool isXnackOnOrOff() const {
109     return getXnackSetting() == TargetIDSetting::On ||
110         getXnackSetting() == TargetIDSetting::Off;
111   }
112 
113   /// \returns The current xnack TargetIDSetting, possible options are
114   /// "Unsupported", "Any", "Off", and "On".
115   TargetIDSetting getXnackSetting() const {
116     return XnackSetting;
117   }
118 
119   /// Sets xnack setting to \p NewXnackSetting.
120   void setXnackSetting(TargetIDSetting NewXnackSetting) {
121     XnackSetting = NewXnackSetting;
122   }
123 
124   /// \return True if the current sramecc setting is not "Unsupported".
125   bool isSramEccSupported() const {
126     return SramEccSetting != TargetIDSetting::Unsupported;
127   }
128 
129   /// \returns True if the current sramecc setting is "On" or "Any".
130   bool isSramEccOnOrAny() const {
131   return SramEccSetting == TargetIDSetting::On ||
132       SramEccSetting == TargetIDSetting::Any;
133   }
134 
135   /// \returns True if current sramecc setting is "On" or "Off",
136   /// false otherwise.
137   bool isSramEccOnOrOff() const {
138     return getSramEccSetting() == TargetIDSetting::On ||
139         getSramEccSetting() == TargetIDSetting::Off;
140   }
141 
142   /// \returns The current sramecc TargetIDSetting, possible options are
143   /// "Unsupported", "Any", "Off", and "On".
144   TargetIDSetting getSramEccSetting() const {
145     return SramEccSetting;
146   }
147 
148   /// Sets sramecc setting to \p NewSramEccSetting.
149   void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
150     SramEccSetting = NewSramEccSetting;
151   }
152 
153   void setTargetIDFromFeaturesString(StringRef FS);
154   void setTargetIDFromTargetIDStream(StringRef TargetID);
155 
156   /// \returns String representation of an object.
157   std::string toString() const;
158 };
159 
160 /// \returns Wavefront size for given subtarget \p STI.
161 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
162 
163 /// \returns Local memory size in bytes for given subtarget \p STI.
164 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
165 
166 /// \returns Number of execution units per compute unit for given subtarget \p
167 /// STI.
168 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
169 
170 /// \returns Maximum number of work groups per compute unit for given subtarget
171 /// \p STI and limited by given \p FlatWorkGroupSize.
172 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
173                                unsigned FlatWorkGroupSize);
174 
175 /// \returns Minimum number of waves per execution unit for given subtarget \p
176 /// STI.
177 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
178 
179 /// \returns Maximum number of waves per execution unit for given subtarget \p
180 /// STI without any kind of limitation.
181 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
182 
183 /// \returns Number of waves per execution unit required to support the given \p
184 /// FlatWorkGroupSize.
185 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
186                                    unsigned FlatWorkGroupSize);
187 
188 /// \returns Minimum flat work group size for given subtarget \p STI.
189 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
190 
191 /// \returns Maximum flat work group size for given subtarget \p STI.
192 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
193 
194 /// \returns Number of waves per work group for given subtarget \p STI and
195 /// \p FlatWorkGroupSize.
196 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
197                               unsigned FlatWorkGroupSize);
198 
199 /// \returns SGPR allocation granularity for given subtarget \p STI.
200 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
201 
202 /// \returns SGPR encoding granularity for given subtarget \p STI.
203 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
204 
205 /// \returns Total number of SGPRs for given subtarget \p STI.
206 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
207 
208 /// \returns Addressable number of SGPRs for given subtarget \p STI.
209 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
210 
211 /// \returns Minimum number of SGPRs that meets the given number of waves per
212 /// execution unit requirement for given subtarget \p STI.
213 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
214 
215 /// \returns Maximum number of SGPRs that meets the given number of waves per
216 /// execution unit requirement for given subtarget \p STI.
217 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
218                         bool Addressable);
219 
220 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
221 /// STI when the given special registers are used.
222 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
223                           bool FlatScrUsed, bool XNACKUsed);
224 
225 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
226 /// STI when the given special registers are used. XNACK is inferred from
227 /// \p STI.
228 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
229                           bool FlatScrUsed);
230 
231 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
232 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
233 /// register counts.
234 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
235 
236 /// \returns VGPR allocation granularity for given subtarget \p STI.
237 ///
238 /// For subtargets which support it, \p EnableWavefrontSize32 should match
239 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
240 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
241                              Optional<bool> EnableWavefrontSize32 = None);
242 
243 /// \returns VGPR encoding granularity for given subtarget \p STI.
244 ///
245 /// For subtargets which support it, \p EnableWavefrontSize32 should match
246 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
247 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
248                                 Optional<bool> EnableWavefrontSize32 = None);
249 
250 /// \returns Total number of VGPRs for given subtarget \p STI.
251 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
252 
253 /// \returns Addressable number of VGPRs for given subtarget \p STI.
254 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
255 
256 /// \returns Minimum number of VGPRs that meets given number of waves per
257 /// execution unit requirement for given subtarget \p STI.
258 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
259 
260 /// \returns Maximum number of VGPRs that meets given number of waves per
261 /// execution unit requirement for given subtarget \p STI.
262 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
263 
264 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
265 /// \p NumVGPRs are used.
266 ///
267 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
268 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
269 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
270                           Optional<bool> EnableWavefrontSize32 = None);
271 
272 } // end namespace IsaInfo
273 
274 LLVM_READONLY
275 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
276 
277 LLVM_READONLY
278 int getSOPPWithRelaxation(uint16_t Opcode);
279 
280 struct MIMGBaseOpcodeInfo {
281   MIMGBaseOpcode BaseOpcode;
282   bool Store;
283   bool Atomic;
284   bool AtomicX2;
285   bool Sampler;
286   bool Gather4;
287 
288   uint8_t NumExtraArgs;
289   bool Gradients;
290   bool G16;
291   bool Coordinates;
292   bool LodOrClampOrMip;
293   bool HasD16;
294   bool MSAA;
295 };
296 
297 LLVM_READONLY
298 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
299 
300 struct MIMGDimInfo {
301   MIMGDim Dim;
302   uint8_t NumCoords;
303   uint8_t NumGradients;
304   bool MSAA;
305   bool DA;
306   uint8_t Encoding;
307   const char *AsmSuffix;
308 };
309 
310 LLVM_READONLY
311 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
312 
313 LLVM_READONLY
314 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
315 
316 LLVM_READONLY
317 const MIMGDimInfo *getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix);
318 
319 struct MIMGLZMappingInfo {
320   MIMGBaseOpcode L;
321   MIMGBaseOpcode LZ;
322 };
323 
324 struct MIMGMIPMappingInfo {
325   MIMGBaseOpcode MIP;
326   MIMGBaseOpcode NONMIP;
327 };
328 
329 struct MIMGG16MappingInfo {
330   MIMGBaseOpcode G;
331   MIMGBaseOpcode G16;
332 };
333 
334 LLVM_READONLY
335 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
336 
337 LLVM_READONLY
338 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
339 
340 LLVM_READONLY
341 const MIMGG16MappingInfo *getMIMGG16MappingInfo(unsigned G);
342 
343 LLVM_READONLY
344 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
345                   unsigned VDataDwords, unsigned VAddrDwords);
346 
347 LLVM_READONLY
348 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
349 
350 struct MIMGInfo {
351   uint16_t Opcode;
352   uint16_t BaseOpcode;
353   uint8_t MIMGEncoding;
354   uint8_t VDataDwords;
355   uint8_t VAddrDwords;
356 };
357 
358 LLVM_READONLY
359 const MIMGInfo *getMIMGInfo(unsigned Opc);
360 
361 LLVM_READONLY
362 int getMTBUFBaseOpcode(unsigned Opc);
363 
364 LLVM_READONLY
365 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
366 
367 LLVM_READONLY
368 int getMTBUFElements(unsigned Opc);
369 
370 LLVM_READONLY
371 bool getMTBUFHasVAddr(unsigned Opc);
372 
373 LLVM_READONLY
374 bool getMTBUFHasSrsrc(unsigned Opc);
375 
376 LLVM_READONLY
377 bool getMTBUFHasSoffset(unsigned Opc);
378 
379 LLVM_READONLY
380 int getMUBUFBaseOpcode(unsigned Opc);
381 
382 LLVM_READONLY
383 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
384 
385 LLVM_READONLY
386 int getMUBUFElements(unsigned Opc);
387 
388 LLVM_READONLY
389 bool getMUBUFHasVAddr(unsigned Opc);
390 
391 LLVM_READONLY
392 bool getMUBUFHasSrsrc(unsigned Opc);
393 
394 LLVM_READONLY
395 bool getMUBUFHasSoffset(unsigned Opc);
396 
397 LLVM_READONLY
398 bool getSMEMIsBuffer(unsigned Opc);
399 
400 LLVM_READONLY
401 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
402                                                   uint8_t NumComponents,
403                                                   uint8_t NumFormat,
404                                                   const MCSubtargetInfo &STI);
405 LLVM_READONLY
406 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
407                                                   const MCSubtargetInfo &STI);
408 
409 LLVM_READONLY
410 int getMCOpcode(uint16_t Opcode, unsigned Gen);
411 
412 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
413                                const MCSubtargetInfo *STI);
414 
415 amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(
416     const MCSubtargetInfo *STI);
417 
418 bool isGroupSegment(const GlobalValue *GV);
419 bool isGlobalSegment(const GlobalValue *GV);
420 bool isReadOnlySegment(const GlobalValue *GV);
421 
422 /// \returns True if constants should be emitted to .text section for given
423 /// target triple \p TT, false otherwise.
424 bool shouldEmitConstantsToTextSection(const Triple &TT);
425 
426 /// \returns Integer value requested using \p F's \p Name attribute.
427 ///
428 /// \returns \p Default if attribute is not present.
429 ///
430 /// \returns \p Default and emits error if requested value cannot be converted
431 /// to integer.
432 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
433 
434 /// \returns A pair of integer values requested using \p F's \p Name attribute
435 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
436 /// is false).
437 ///
438 /// \returns \p Default if attribute is not present.
439 ///
440 /// \returns \p Default and emits error if one of the requested values cannot be
441 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
442 /// not present.
443 std::pair<int, int> getIntegerPairAttribute(const Function &F,
444                                             StringRef Name,
445                                             std::pair<int, int> Default,
446                                             bool OnlyFirstRequired = false);
447 
448 /// Represents the counter values to wait for in an s_waitcnt instruction.
449 ///
450 /// Large values (including the maximum possible integer) can be used to
451 /// represent "don't care" waits.
452 struct Waitcnt {
453   unsigned VmCnt = ~0u;
454   unsigned ExpCnt = ~0u;
455   unsigned LgkmCnt = ~0u;
456   unsigned VsCnt = ~0u;
457 
458   Waitcnt() {}
459   Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
460       : VmCnt(VmCnt), ExpCnt(ExpCnt), LgkmCnt(LgkmCnt), VsCnt(VsCnt) {}
461 
462   static Waitcnt allZero(bool HasVscnt) {
463     return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
464   }
465   static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
466 
467   bool hasWait() const {
468     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
469   }
470 
471   bool dominates(const Waitcnt &Other) const {
472     return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
473            LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
474   }
475 
476   Waitcnt combined(const Waitcnt &Other) const {
477     return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
478                    std::min(LgkmCnt, Other.LgkmCnt),
479                    std::min(VsCnt, Other.VsCnt));
480   }
481 };
482 
483 /// \returns Vmcnt bit mask for given isa \p Version.
484 unsigned getVmcntBitMask(const IsaVersion &Version);
485 
486 /// \returns Expcnt bit mask for given isa \p Version.
487 unsigned getExpcntBitMask(const IsaVersion &Version);
488 
489 /// \returns Lgkmcnt bit mask for given isa \p Version.
490 unsigned getLgkmcntBitMask(const IsaVersion &Version);
491 
492 /// \returns Waitcnt bit mask for given isa \p Version.
493 unsigned getWaitcntBitMask(const IsaVersion &Version);
494 
495 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
496 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
497 
498 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
499 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
500 
501 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
502 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
503 
504 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
505 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
506 /// \p Lgkmcnt respectively.
507 ///
508 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
509 ///     \p Vmcnt = \p Waitcnt[3:0]                      (pre-gfx9 only)
510 ///     \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14]  (gfx9+ only)
511 ///     \p Expcnt = \p Waitcnt[6:4]
512 ///     \p Lgkmcnt = \p Waitcnt[11:8]                   (pre-gfx10 only)
513 ///     \p Lgkmcnt = \p Waitcnt[13:8]                   (gfx10+ only)
514 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
515                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
516 
517 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
518 
519 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
520 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
521                      unsigned Vmcnt);
522 
523 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
524 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
525                       unsigned Expcnt);
526 
527 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
528 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
529                        unsigned Lgkmcnt);
530 
531 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
532 /// \p Version.
533 ///
534 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
535 ///     Waitcnt[3:0]   = \p Vmcnt       (pre-gfx9 only)
536 ///     Waitcnt[3:0]   = \p Vmcnt[3:0]  (gfx9+ only)
537 ///     Waitcnt[6:4]   = \p Expcnt
538 ///     Waitcnt[11:8]  = \p Lgkmcnt     (pre-gfx10 only)
539 ///     Waitcnt[13:8]  = \p Lgkmcnt     (gfx10+ only)
540 ///     Waitcnt[15:14] = \p Vmcnt[5:4]  (gfx9+ only)
541 ///
542 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
543 /// isa \p Version.
544 unsigned encodeWaitcnt(const IsaVersion &Version,
545                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
546 
547 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
548 
549 namespace Hwreg {
550 
551 LLVM_READONLY
552 int64_t getHwregId(const StringRef Name);
553 
554 LLVM_READNONE
555 bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI);
556 
557 LLVM_READNONE
558 bool isValidHwreg(int64_t Id);
559 
560 LLVM_READNONE
561 bool isValidHwregOffset(int64_t Offset);
562 
563 LLVM_READNONE
564 bool isValidHwregWidth(int64_t Width);
565 
566 LLVM_READNONE
567 uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
568 
569 LLVM_READNONE
570 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
571 
572 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
573 
574 } // namespace Hwreg
575 
576 namespace Exp {
577 
578 bool getTgtName(unsigned Id, StringRef &Name, int &Index);
579 
580 LLVM_READONLY
581 unsigned getTgtId(const StringRef Name);
582 
583 LLVM_READNONE
584 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
585 
586 } // namespace Exp
587 
588 namespace MTBUFFormat {
589 
590 LLVM_READNONE
591 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
592 
593 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
594 
595 int64_t getDfmt(const StringRef Name);
596 
597 StringRef getDfmtName(unsigned Id);
598 
599 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
600 
601 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
602 
603 bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
604 
605 bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
606 
607 int64_t getUnifiedFormat(const StringRef Name);
608 
609 StringRef getUnifiedFormatName(unsigned Id);
610 
611 bool isValidUnifiedFormat(unsigned Val);
612 
613 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt);
614 
615 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
616 
617 unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
618 
619 } // namespace MTBUFFormat
620 
621 namespace SendMsg {
622 
623 LLVM_READONLY
624 int64_t getMsgId(const StringRef Name);
625 
626 LLVM_READONLY
627 int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
628 
629 LLVM_READNONE
630 StringRef getMsgName(int64_t MsgId);
631 
632 LLVM_READNONE
633 StringRef getMsgOpName(int64_t MsgId, int64_t OpId);
634 
635 LLVM_READNONE
636 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict = true);
637 
638 LLVM_READNONE
639 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
640                   bool Strict = true);
641 
642 LLVM_READNONE
643 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
644                       const MCSubtargetInfo &STI, bool Strict = true);
645 
646 LLVM_READNONE
647 bool msgRequiresOp(int64_t MsgId);
648 
649 LLVM_READNONE
650 bool msgSupportsStream(int64_t MsgId, int64_t OpId);
651 
652 void decodeMsg(unsigned Val,
653                uint16_t &MsgId,
654                uint16_t &OpId,
655                uint16_t &StreamId);
656 
657 LLVM_READNONE
658 uint64_t encodeMsg(uint64_t MsgId,
659                    uint64_t OpId,
660                    uint64_t StreamId);
661 
662 } // namespace SendMsg
663 
664 
665 unsigned getInitialPSInputAddr(const Function &F);
666 
667 LLVM_READNONE
668 bool isShader(CallingConv::ID CC);
669 
670 LLVM_READNONE
671 bool isGraphics(CallingConv::ID CC);
672 
673 LLVM_READNONE
674 bool isCompute(CallingConv::ID CC);
675 
676 LLVM_READNONE
677 bool isEntryFunctionCC(CallingConv::ID CC);
678 
679 // These functions are considered entrypoints into the current module, i.e. they
680 // are allowed to be called from outside the current module. This is different
681 // from isEntryFunctionCC, which is only true for functions that are entered by
682 // the hardware. Module entry points include all entry functions but also
683 // include functions that can be called from other functions inside or outside
684 // the current module. Module entry functions are allowed to allocate LDS.
685 LLVM_READNONE
686 bool isModuleEntryFunctionCC(CallingConv::ID CC);
687 
688 // FIXME: Remove this when calling conventions cleaned up
689 LLVM_READNONE
690 inline bool isKernel(CallingConv::ID CC) {
691   switch (CC) {
692   case CallingConv::AMDGPU_KERNEL:
693   case CallingConv::SPIR_KERNEL:
694     return true;
695   default:
696     return false;
697   }
698 }
699 
700 bool hasXNACK(const MCSubtargetInfo &STI);
701 bool hasSRAMECC(const MCSubtargetInfo &STI);
702 bool hasMIMG_R128(const MCSubtargetInfo &STI);
703 bool hasGFX10A16(const MCSubtargetInfo &STI);
704 bool hasG16(const MCSubtargetInfo &STI);
705 bool hasPackedD16(const MCSubtargetInfo &STI);
706 
707 bool isSI(const MCSubtargetInfo &STI);
708 bool isCI(const MCSubtargetInfo &STI);
709 bool isVI(const MCSubtargetInfo &STI);
710 bool isGFX9(const MCSubtargetInfo &STI);
711 bool isGFX9Plus(const MCSubtargetInfo &STI);
712 bool isGFX10(const MCSubtargetInfo &STI);
713 bool isGFX10Plus(const MCSubtargetInfo &STI);
714 bool isGCN3Encoding(const MCSubtargetInfo &STI);
715 bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
716 bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
717 bool isGFX90A(const MCSubtargetInfo &STI);
718 
719 /// Is Reg - scalar register
720 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
721 
722 /// Is there any intersection between registers
723 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
724 
725 /// If \p Reg is a pseudo reg, return the correct hardware register given
726 /// \p STI otherwise return \p Reg.
727 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
728 
729 /// Convert hardware register \p Reg to a pseudo register
730 LLVM_READNONE
731 unsigned mc2PseudoReg(unsigned Reg);
732 
733 /// Can this operand also contain immediate values?
734 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
735 
736 /// Is this floating-point operand?
737 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
738 
739 /// Does this opearnd support only inlinable literals?
740 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
741 
742 /// Get the size in bits of a register from the register class \p RC.
743 unsigned getRegBitWidth(unsigned RCID);
744 
745 /// Get the size in bits of a register from the register class \p RC.
746 unsigned getRegBitWidth(const MCRegisterClass &RC);
747 
748 /// Get size of register operand
749 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
750                            unsigned OpNo);
751 
752 LLVM_READNONE
753 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
754   switch (OpInfo.OperandType) {
755   case AMDGPU::OPERAND_REG_IMM_INT32:
756   case AMDGPU::OPERAND_REG_IMM_FP32:
757   case AMDGPU::OPERAND_REG_INLINE_C_INT32:
758   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
759   case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
760   case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
761   case AMDGPU::OPERAND_REG_IMM_V2INT32:
762   case AMDGPU::OPERAND_REG_IMM_V2FP32:
763   case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
764   case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
765     return 4;
766 
767   case AMDGPU::OPERAND_REG_IMM_INT64:
768   case AMDGPU::OPERAND_REG_IMM_FP64:
769   case AMDGPU::OPERAND_REG_INLINE_C_INT64:
770   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
771   case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
772     return 8;
773 
774   case AMDGPU::OPERAND_REG_IMM_INT16:
775   case AMDGPU::OPERAND_REG_IMM_FP16:
776   case AMDGPU::OPERAND_REG_INLINE_C_INT16:
777   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
778   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
779   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
780   case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
781   case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
782   case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
783   case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
784   case AMDGPU::OPERAND_REG_IMM_V2INT16:
785   case AMDGPU::OPERAND_REG_IMM_V2FP16:
786     return 2;
787 
788   default:
789     llvm_unreachable("unhandled operand type");
790   }
791 }
792 
793 LLVM_READNONE
794 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
795   return getOperandSize(Desc.OpInfo[OpNo]);
796 }
797 
798 /// Is this literal inlinable, and not one of the values intended for floating
799 /// point values.
800 LLVM_READNONE
801 inline bool isInlinableIntLiteral(int64_t Literal) {
802   return Literal >= -16 && Literal <= 64;
803 }
804 
805 /// Is this literal inlinable
806 LLVM_READNONE
807 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
808 
809 LLVM_READNONE
810 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
811 
812 LLVM_READNONE
813 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
814 
815 LLVM_READNONE
816 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
817 
818 LLVM_READNONE
819 bool isInlinableIntLiteralV216(int32_t Literal);
820 
821 LLVM_READNONE
822 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
823 
824 bool isArgPassedInSGPR(const Argument *Arg);
825 
826 LLVM_READONLY
827 bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
828                                       int64_t EncodedOffset);
829 
830 LLVM_READONLY
831 bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,
832                                     int64_t EncodedOffset,
833                                     bool IsBuffer);
834 
835 /// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
836 /// offsets.
837 uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
838 
839 /// \returns The encoding that will be used for \p ByteOffset in the
840 /// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
841 /// S_LOAD instructions have a signed offset, on other subtargets it is
842 /// unsigned. S_BUFFER has an unsigned offset for all subtargets.
843 Optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
844                                        int64_t ByteOffset, bool IsBuffer);
845 
846 /// \return The encoding that can be used for a 32-bit literal offset in an SMRD
847 /// instruction. This is only useful on CI.s
848 Optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
849                                                 int64_t ByteOffset);
850 
851 /// For FLAT segment the offset must be positive;
852 /// MSB is ignored and forced to zero.
853 ///
854 /// \return The number of bits available for the offset field in flat
855 /// instructions.
856 unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed);
857 
858 /// \returns true if this offset is small enough to fit in the SMRD
859 /// offset field.  \p ByteOffset should be the offset in bytes and
860 /// not the encoded offset.
861 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
862 
863 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
864                       const GCNSubtarget *Subtarget,
865                       Align Alignment = Align(4));
866 
867 LLVM_READNONE
868 inline bool isLegal64BitDPPControl(unsigned DC) {
869   return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
870 }
871 
872 /// \returns true if the intrinsic is divergent
873 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
874 
875 // Track defaults for fields in the MODE registser.
876 struct SIModeRegisterDefaults {
877   /// Floating point opcodes that support exception flag gathering quiet and
878   /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
879   /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
880   /// quieting.
881   bool IEEE : 1;
882 
883   /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
884   /// clamp NaN to zero; otherwise, pass NaN through.
885   bool DX10Clamp : 1;
886 
887   /// If this is set, neither input or output denormals are flushed for most f32
888   /// instructions.
889   bool FP32InputDenormals : 1;
890   bool FP32OutputDenormals : 1;
891 
892   /// If this is set, neither input or output denormals are flushed for both f64
893   /// and f16/v2f16 instructions.
894   bool FP64FP16InputDenormals : 1;
895   bool FP64FP16OutputDenormals : 1;
896 
897   SIModeRegisterDefaults() :
898     IEEE(true),
899     DX10Clamp(true),
900     FP32InputDenormals(true),
901     FP32OutputDenormals(true),
902     FP64FP16InputDenormals(true),
903     FP64FP16OutputDenormals(true) {}
904 
905   SIModeRegisterDefaults(const Function &F);
906 
907   static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) {
908     SIModeRegisterDefaults Mode;
909     Mode.IEEE = !AMDGPU::isShader(CC);
910     return Mode;
911   }
912 
913   bool operator ==(const SIModeRegisterDefaults Other) const {
914     return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
915            FP32InputDenormals == Other.FP32InputDenormals &&
916            FP32OutputDenormals == Other.FP32OutputDenormals &&
917            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
918            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
919   }
920 
921   bool allFP32Denormals() const {
922     return FP32InputDenormals && FP32OutputDenormals;
923   }
924 
925   bool allFP64FP16Denormals() const {
926     return FP64FP16InputDenormals && FP64FP16OutputDenormals;
927   }
928 
929   /// Get the encoding value for the FP_DENORM bits of the mode register for the
930   /// FP32 denormal mode.
931   uint32_t fpDenormModeSPValue() const {
932     if (FP32InputDenormals && FP32OutputDenormals)
933       return FP_DENORM_FLUSH_NONE;
934     if (FP32InputDenormals)
935       return FP_DENORM_FLUSH_OUT;
936     if (FP32OutputDenormals)
937       return FP_DENORM_FLUSH_IN;
938     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
939   }
940 
941   /// Get the encoding value for the FP_DENORM bits of the mode register for the
942   /// FP64/FP16 denormal mode.
943   uint32_t fpDenormModeDPValue() const {
944     if (FP64FP16InputDenormals && FP64FP16OutputDenormals)
945       return FP_DENORM_FLUSH_NONE;
946     if (FP64FP16InputDenormals)
947       return FP_DENORM_FLUSH_OUT;
948     if (FP64FP16OutputDenormals)
949       return FP_DENORM_FLUSH_IN;
950     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
951   }
952 
953   /// Returns true if a flag is compatible if it's enabled in the callee, but
954   /// disabled in the caller.
955   static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
956     return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
957   }
958 
959   // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
960   // be able to override.
961   bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
962     if (DX10Clamp != CalleeMode.DX10Clamp)
963       return false;
964     if (IEEE != CalleeMode.IEEE)
965       return false;
966 
967     // Allow inlining denormals enabled into denormals flushed functions.
968     return oneWayCompatible(FP64FP16InputDenormals, CalleeMode.FP64FP16InputDenormals) &&
969            oneWayCompatible(FP64FP16OutputDenormals, CalleeMode.FP64FP16OutputDenormals) &&
970            oneWayCompatible(FP32InputDenormals, CalleeMode.FP32InputDenormals) &&
971            oneWayCompatible(FP32OutputDenormals, CalleeMode.FP32OutputDenormals);
972   }
973 };
974 
975 } // end namespace AMDGPU
976 
977 raw_ostream &operator<<(raw_ostream &OS,
978                         const AMDGPU::IsaInfo::TargetIDSetting S);
979 
980 } // end namespace llvm
981 
982 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
983