1 //===-- AMDGPUBaseInfo.h - Top level definitions for AMDGPU -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H 11 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H 12 13 #include "AMDKernelCodeT.h" 14 #include "llvm/IR/CallingConv.h" 15 16 #define GET_INSTRINFO_OPERAND_ENUM 17 #include "AMDGPUGenInstrInfo.inc" 18 #undef GET_INSTRINFO_OPERAND_ENUM 19 20 namespace llvm { 21 22 class FeatureBitset; 23 class Function; 24 class GlobalValue; 25 class MCContext; 26 class MCInstrDesc; 27 class MCRegisterInfo; 28 class MCSection; 29 class MCSubtargetInfo; 30 31 namespace AMDGPU { 32 33 LLVM_READONLY 34 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx); 35 36 struct IsaVersion { 37 unsigned Major; 38 unsigned Minor; 39 unsigned Stepping; 40 }; 41 42 IsaVersion getIsaVersion(const FeatureBitset &Features); 43 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, 44 const FeatureBitset &Features); 45 MCSection *getHSATextSection(MCContext &Ctx); 46 47 MCSection *getHSADataGlobalAgentSection(MCContext &Ctx); 48 49 MCSection *getHSADataGlobalProgramSection(MCContext &Ctx); 50 51 MCSection *getHSARodataReadonlyAgentSection(MCContext &Ctx); 52 53 bool isGroupSegment(const GlobalValue *GV); 54 bool isGlobalSegment(const GlobalValue *GV); 55 bool isReadOnlySegment(const GlobalValue *GV); 56 57 /// \returns Integer value requested using \p F's \p Name attribute. 58 /// 59 /// \returns \p Default if attribute is not present. 60 /// 61 /// \returns \p Default and emits error if requested value cannot be converted 62 /// to integer. 63 int getIntegerAttribute(const Function &F, StringRef Name, int Default); 64 65 /// \returns A pair of integer values requested using \p F's \p Name attribute 66 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired 67 /// is false). 68 /// 69 /// \returns \p Default if attribute is not present. 70 /// 71 /// \returns \p Default and emits error if one of the requested values cannot be 72 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is 73 /// not present. 74 std::pair<int, int> getIntegerPairAttribute(const Function &F, 75 StringRef Name, 76 std::pair<int, int> Default, 77 bool OnlyFirstRequired = false); 78 79 /// \returns Waitcnt bit mask for given isa \p Version. 80 unsigned getWaitcntBitMask(IsaVersion Version); 81 82 /// \returns Vmcnt bit mask for given isa \p Version. 83 unsigned getVmcntBitMask(IsaVersion Version); 84 85 /// \returns Expcnt bit mask for given isa \p Version. 86 unsigned getExpcntBitMask(IsaVersion Version); 87 88 /// \returns Lgkmcnt bit mask for given isa \p Version. 89 unsigned getLgkmcntBitMask(IsaVersion Version); 90 91 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version. 92 unsigned decodeVmcnt(IsaVersion Version, unsigned Waitcnt); 93 94 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version. 95 unsigned decodeExpcnt(IsaVersion Version, unsigned Waitcnt); 96 97 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version. 98 unsigned decodeLgkmcnt(IsaVersion Version, unsigned Waitcnt); 99 100 /// \brief Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa 101 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and 102 /// \p Lgkmcnt respectively. 103 /// 104 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows: 105 /// \p Vmcnt = \p Waitcnt[3:0] 106 /// \p Expcnt = \p Waitcnt[6:4] 107 /// \p Lgkmcnt = \p Waitcnt[11:8] 108 void decodeWaitcnt(IsaVersion Version, unsigned Waitcnt, 109 unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt); 110 111 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version. 112 unsigned encodeVmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Vmcnt); 113 114 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version. 115 unsigned encodeExpcnt(IsaVersion Version, unsigned Waitcnt, unsigned Expcnt); 116 117 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version. 118 unsigned encodeLgkmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Lgkmcnt); 119 120 /// \brief Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa 121 /// \p Version. 122 /// 123 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows: 124 /// Waitcnt[3:0] = \p Vmcnt 125 /// Waitcnt[6:4] = \p Expcnt 126 /// Waitcnt[11:8] = \p Lgkmcnt 127 /// 128 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given 129 /// isa \p Version. 130 unsigned encodeWaitcnt(IsaVersion Version, 131 unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt); 132 133 unsigned getInitialPSInputAddr(const Function &F); 134 135 bool isShader(CallingConv::ID cc); 136 bool isCompute(CallingConv::ID cc); 137 138 bool isSI(const MCSubtargetInfo &STI); 139 bool isCI(const MCSubtargetInfo &STI); 140 bool isVI(const MCSubtargetInfo &STI); 141 142 /// If \p Reg is a pseudo reg, return the correct hardware register given 143 /// \p STI otherwise return \p Reg. 144 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI); 145 146 /// \brief Can this operand also contain immediate values? 147 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo); 148 149 /// \brief Is this floating-point operand? 150 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo); 151 152 /// \brief Does this opearnd support only inlinable literals? 153 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo); 154 155 /// \brief Get size of register operand 156 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, 157 unsigned OpNo); 158 159 /// \brief Is this literal inlinable 160 bool isInlinableLiteral64(int64_t Literal, bool IsVI); 161 bool isInlinableLiteral32(int32_t Literal, bool IsVI); 162 163 } // end namespace AMDGPU 164 } // end namespace llvm 165 166 #endif 167