1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "AMDGPU.h"
13 #include "AMDKernelCodeT.h"
14 #include "SIDefines.h"
15 #include "llvm/IR/CallingConv.h"
16 #include "llvm/MC/MCInstrDesc.h"
17 #include "llvm/Support/AMDHSAKernelDescriptor.h"
18 #include "llvm/Support/Compiler.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/TargetParser.h"
21 #include <cstdint>
22 #include <string>
23 #include <utility>
24 
25 namespace llvm {
26 
27 class Argument;
28 class Function;
29 class GCNSubtarget;
30 class GlobalValue;
31 class MCRegisterClass;
32 class MCRegisterInfo;
33 class MCSubtargetInfo;
34 class StringRef;
35 class Triple;
36 
37 namespace AMDGPU {
38 
39 struct GcnBufferFormatInfo {
40   unsigned Format;
41   unsigned BitsPerComp;
42   unsigned NumComponents;
43   unsigned NumFormat;
44   unsigned DataFormat;
45 };
46 
47 #define GET_MIMGBaseOpcode_DECL
48 #define GET_MIMGDim_DECL
49 #define GET_MIMGEncoding_DECL
50 #define GET_MIMGLZMapping_DECL
51 #define GET_MIMGMIPMapping_DECL
52 #include "AMDGPUGenSearchableTables.inc"
53 
54 namespace IsaInfo {
55 
56 enum {
57   // The closed Vulkan driver sets 96, which limits the wave count to 8 but
58   // doesn't spill SGPRs as much as when 80 is set.
59   FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
60   TRAP_NUM_SGPRS = 16
61 };
62 
63 /// Streams isa version string for given subtarget \p STI into \p Stream.
64 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream);
65 
66 /// \returns True if given subtarget \p STI supports code object version 3,
67 /// false otherwise.
68 bool hasCodeObjectV3(const MCSubtargetInfo *STI);
69 
70 /// \returns Wavefront size for given subtarget \p STI.
71 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
72 
73 /// \returns Local memory size in bytes for given subtarget \p STI.
74 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
75 
76 /// \returns Number of execution units per compute unit for given subtarget \p
77 /// STI.
78 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
79 
80 /// \returns Maximum number of work groups per compute unit for given subtarget
81 /// \p STI and limited by given \p FlatWorkGroupSize.
82 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
83                                unsigned FlatWorkGroupSize);
84 
85 /// \returns Minimum number of waves per execution unit for given subtarget \p
86 /// STI.
87 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
88 
89 /// \returns Maximum number of waves per execution unit for given subtarget \p
90 /// STI without any kind of limitation.
91 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
92 
93 /// \returns Number of waves per execution unit required to support the given \p
94 /// FlatWorkGroupSize.
95 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
96                                    unsigned FlatWorkGroupSize);
97 
98 /// \returns Minimum flat work group size for given subtarget \p STI.
99 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
100 
101 /// \returns Maximum flat work group size for given subtarget \p STI.
102 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
103 
104 /// \returns Number of waves per work group for given subtarget \p STI and
105 /// \p FlatWorkGroupSize.
106 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
107                               unsigned FlatWorkGroupSize);
108 
109 /// \returns SGPR allocation granularity for given subtarget \p STI.
110 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
111 
112 /// \returns SGPR encoding granularity for given subtarget \p STI.
113 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
114 
115 /// \returns Total number of SGPRs for given subtarget \p STI.
116 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
117 
118 /// \returns Addressable number of SGPRs for given subtarget \p STI.
119 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
120 
121 /// \returns Minimum number of SGPRs that meets the given number of waves per
122 /// execution unit requirement for given subtarget \p STI.
123 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
124 
125 /// \returns Maximum number of SGPRs that meets the given number of waves per
126 /// execution unit requirement for given subtarget \p STI.
127 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
128                         bool Addressable);
129 
130 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
131 /// STI when the given special registers are used.
132 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
133                           bool FlatScrUsed, bool XNACKUsed);
134 
135 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
136 /// STI when the given special registers are used. XNACK is inferred from
137 /// \p STI.
138 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
139                           bool FlatScrUsed);
140 
141 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
142 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
143 /// register counts.
144 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
145 
146 /// \returns VGPR allocation granularity for given subtarget \p STI.
147 ///
148 /// For subtargets which support it, \p EnableWavefrontSize32 should match
149 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
150 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
151                              Optional<bool> EnableWavefrontSize32 = None);
152 
153 /// \returns VGPR encoding granularity for given subtarget \p STI.
154 ///
155 /// For subtargets which support it, \p EnableWavefrontSize32 should match
156 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
157 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
158                                 Optional<bool> EnableWavefrontSize32 = None);
159 
160 /// \returns Total number of VGPRs for given subtarget \p STI.
161 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
162 
163 /// \returns Addressable number of VGPRs for given subtarget \p STI.
164 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
165 
166 /// \returns Minimum number of VGPRs that meets given number of waves per
167 /// execution unit requirement for given subtarget \p STI.
168 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
169 
170 /// \returns Maximum number of VGPRs that meets given number of waves per
171 /// execution unit requirement for given subtarget \p STI.
172 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
173 
174 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
175 /// \p NumVGPRs are used.
176 ///
177 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
178 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
179 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
180                           Optional<bool> EnableWavefrontSize32 = None);
181 
182 } // end namespace IsaInfo
183 
184 LLVM_READONLY
185 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
186 
187 LLVM_READONLY
188 int getSOPPWithRelaxation(uint16_t Opcode);
189 
190 struct MIMGBaseOpcodeInfo {
191   MIMGBaseOpcode BaseOpcode;
192   bool Store;
193   bool Atomic;
194   bool AtomicX2;
195   bool Sampler;
196   bool Gather4;
197 
198   uint8_t NumExtraArgs;
199   bool Gradients;
200   bool Coordinates;
201   bool LodOrClampOrMip;
202   bool HasD16;
203 };
204 
205 LLVM_READONLY
206 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
207 
208 struct MIMGDimInfo {
209   MIMGDim Dim;
210   uint8_t NumCoords;
211   uint8_t NumGradients;
212   bool DA;
213   uint8_t Encoding;
214   const char *AsmSuffix;
215 };
216 
217 LLVM_READONLY
218 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
219 
220 LLVM_READONLY
221 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
222 
223 LLVM_READONLY
224 const MIMGDimInfo *getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix);
225 
226 struct MIMGLZMappingInfo {
227   MIMGBaseOpcode L;
228   MIMGBaseOpcode LZ;
229 };
230 
231 struct MIMGMIPMappingInfo {
232   MIMGBaseOpcode MIP;
233   MIMGBaseOpcode NONMIP;
234 };
235 
236 LLVM_READONLY
237 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
238 
239 LLVM_READONLY
240 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned L);
241 
242 LLVM_READONLY
243 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
244                   unsigned VDataDwords, unsigned VAddrDwords);
245 
246 LLVM_READONLY
247 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
248 
249 struct MIMGInfo {
250   uint16_t Opcode;
251   uint16_t BaseOpcode;
252   uint8_t MIMGEncoding;
253   uint8_t VDataDwords;
254   uint8_t VAddrDwords;
255 };
256 
257 LLVM_READONLY
258 const MIMGInfo *getMIMGInfo(unsigned Opc);
259 
260 LLVM_READONLY
261 int getMTBUFBaseOpcode(unsigned Opc);
262 
263 LLVM_READONLY
264 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
265 
266 LLVM_READONLY
267 int getMTBUFElements(unsigned Opc);
268 
269 LLVM_READONLY
270 bool getMTBUFHasVAddr(unsigned Opc);
271 
272 LLVM_READONLY
273 bool getMTBUFHasSrsrc(unsigned Opc);
274 
275 LLVM_READONLY
276 bool getMTBUFHasSoffset(unsigned Opc);
277 
278 LLVM_READONLY
279 int getMUBUFBaseOpcode(unsigned Opc);
280 
281 LLVM_READONLY
282 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
283 
284 LLVM_READONLY
285 int getMUBUFElements(unsigned Opc);
286 
287 LLVM_READONLY
288 bool getMUBUFHasVAddr(unsigned Opc);
289 
290 LLVM_READONLY
291 bool getMUBUFHasSrsrc(unsigned Opc);
292 
293 LLVM_READONLY
294 bool getMUBUFHasSoffset(unsigned Opc);
295 
296 LLVM_READONLY
297 bool getSMEMIsBuffer(unsigned Opc);
298 
299 LLVM_READONLY
300 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
301                                                   uint8_t NumComponents,
302                                                   uint8_t NumFormat,
303                                                   const MCSubtargetInfo &STI);
304 LLVM_READONLY
305 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
306                                                   const MCSubtargetInfo &STI);
307 
308 LLVM_READONLY
309 int getMCOpcode(uint16_t Opcode, unsigned Gen);
310 
311 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
312                                const MCSubtargetInfo *STI);
313 
314 amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(
315     const MCSubtargetInfo *STI);
316 
317 bool isGroupSegment(const GlobalValue *GV);
318 bool isGlobalSegment(const GlobalValue *GV);
319 bool isReadOnlySegment(const GlobalValue *GV);
320 
321 /// \returns True if constants should be emitted to .text section for given
322 /// target triple \p TT, false otherwise.
323 bool shouldEmitConstantsToTextSection(const Triple &TT);
324 
325 /// \returns Integer value requested using \p F's \p Name attribute.
326 ///
327 /// \returns \p Default if attribute is not present.
328 ///
329 /// \returns \p Default and emits error if requested value cannot be converted
330 /// to integer.
331 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
332 
333 /// \returns A pair of integer values requested using \p F's \p Name attribute
334 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
335 /// is false).
336 ///
337 /// \returns \p Default if attribute is not present.
338 ///
339 /// \returns \p Default and emits error if one of the requested values cannot be
340 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
341 /// not present.
342 std::pair<int, int> getIntegerPairAttribute(const Function &F,
343                                             StringRef Name,
344                                             std::pair<int, int> Default,
345                                             bool OnlyFirstRequired = false);
346 
347 /// Represents the counter values to wait for in an s_waitcnt instruction.
348 ///
349 /// Large values (including the maximum possible integer) can be used to
350 /// represent "don't care" waits.
351 struct Waitcnt {
352   unsigned VmCnt = ~0u;
353   unsigned ExpCnt = ~0u;
354   unsigned LgkmCnt = ~0u;
355   unsigned VsCnt = ~0u;
356 
357   Waitcnt() {}
358   Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
359       : VmCnt(VmCnt), ExpCnt(ExpCnt), LgkmCnt(LgkmCnt), VsCnt(VsCnt) {}
360 
361   static Waitcnt allZero(const IsaVersion &Version) {
362     return Waitcnt(0, 0, 0, Version.Major >= 10 ? 0 : ~0u);
363   }
364   static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
365 
366   bool hasWait() const {
367     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
368   }
369 
370   bool dominates(const Waitcnt &Other) const {
371     return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
372            LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
373   }
374 
375   Waitcnt combined(const Waitcnt &Other) const {
376     return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
377                    std::min(LgkmCnt, Other.LgkmCnt),
378                    std::min(VsCnt, Other.VsCnt));
379   }
380 };
381 
382 /// \returns Vmcnt bit mask for given isa \p Version.
383 unsigned getVmcntBitMask(const IsaVersion &Version);
384 
385 /// \returns Expcnt bit mask for given isa \p Version.
386 unsigned getExpcntBitMask(const IsaVersion &Version);
387 
388 /// \returns Lgkmcnt bit mask for given isa \p Version.
389 unsigned getLgkmcntBitMask(const IsaVersion &Version);
390 
391 /// \returns Waitcnt bit mask for given isa \p Version.
392 unsigned getWaitcntBitMask(const IsaVersion &Version);
393 
394 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
395 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
396 
397 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
398 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
399 
400 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
401 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
402 
403 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
404 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
405 /// \p Lgkmcnt respectively.
406 ///
407 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
408 ///     \p Vmcnt = \p Waitcnt[3:0]                      (pre-gfx9 only)
409 ///     \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14]  (gfx9+ only)
410 ///     \p Expcnt = \p Waitcnt[6:4]
411 ///     \p Lgkmcnt = \p Waitcnt[11:8]                   (pre-gfx10 only)
412 ///     \p Lgkmcnt = \p Waitcnt[13:8]                   (gfx10+ only)
413 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
414                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
415 
416 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
417 
418 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
419 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
420                      unsigned Vmcnt);
421 
422 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
423 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
424                       unsigned Expcnt);
425 
426 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
427 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
428                        unsigned Lgkmcnt);
429 
430 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
431 /// \p Version.
432 ///
433 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
434 ///     Waitcnt[3:0]   = \p Vmcnt       (pre-gfx9 only)
435 ///     Waitcnt[3:0]   = \p Vmcnt[3:0]  (gfx9+ only)
436 ///     Waitcnt[6:4]   = \p Expcnt
437 ///     Waitcnt[11:8]  = \p Lgkmcnt     (pre-gfx10 only)
438 ///     Waitcnt[13:8]  = \p Lgkmcnt     (gfx10+ only)
439 ///     Waitcnt[15:14] = \p Vmcnt[5:4]  (gfx9+ only)
440 ///
441 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
442 /// isa \p Version.
443 unsigned encodeWaitcnt(const IsaVersion &Version,
444                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
445 
446 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
447 
448 namespace Hwreg {
449 
450 LLVM_READONLY
451 int64_t getHwregId(const StringRef Name);
452 
453 LLVM_READNONE
454 bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI);
455 
456 LLVM_READNONE
457 bool isValidHwreg(int64_t Id);
458 
459 LLVM_READNONE
460 bool isValidHwregOffset(int64_t Offset);
461 
462 LLVM_READNONE
463 bool isValidHwregWidth(int64_t Width);
464 
465 LLVM_READNONE
466 uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
467 
468 LLVM_READNONE
469 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
470 
471 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
472 
473 } // namespace Hwreg
474 
475 namespace SendMsg {
476 
477 LLVM_READONLY
478 int64_t getMsgId(const StringRef Name);
479 
480 LLVM_READONLY
481 int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
482 
483 LLVM_READNONE
484 StringRef getMsgName(int64_t MsgId);
485 
486 LLVM_READNONE
487 StringRef getMsgOpName(int64_t MsgId, int64_t OpId);
488 
489 LLVM_READNONE
490 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict = true);
491 
492 LLVM_READNONE
493 bool isValidMsgOp(int64_t MsgId, int64_t OpId, bool Strict = true);
494 
495 LLVM_READNONE
496 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, bool Strict = true);
497 
498 LLVM_READNONE
499 bool msgRequiresOp(int64_t MsgId);
500 
501 LLVM_READNONE
502 bool msgSupportsStream(int64_t MsgId, int64_t OpId);
503 
504 void decodeMsg(unsigned Val,
505                uint16_t &MsgId,
506                uint16_t &OpId,
507                uint16_t &StreamId);
508 
509 LLVM_READNONE
510 uint64_t encodeMsg(uint64_t MsgId,
511                    uint64_t OpId,
512                    uint64_t StreamId);
513 
514 } // namespace SendMsg
515 
516 
517 unsigned getInitialPSInputAddr(const Function &F);
518 
519 LLVM_READNONE
520 bool isShader(CallingConv::ID CC);
521 
522 LLVM_READNONE
523 bool isCompute(CallingConv::ID CC);
524 
525 LLVM_READNONE
526 bool isEntryFunctionCC(CallingConv::ID CC);
527 
528 // FIXME: Remove this when calling conventions cleaned up
529 LLVM_READNONE
530 inline bool isKernel(CallingConv::ID CC) {
531   switch (CC) {
532   case CallingConv::AMDGPU_KERNEL:
533   case CallingConv::SPIR_KERNEL:
534     return true;
535   default:
536     return false;
537   }
538 }
539 
540 bool hasXNACK(const MCSubtargetInfo &STI);
541 bool hasSRAMECC(const MCSubtargetInfo &STI);
542 bool hasMIMG_R128(const MCSubtargetInfo &STI);
543 bool hasGFX10A16(const MCSubtargetInfo &STI);
544 bool hasPackedD16(const MCSubtargetInfo &STI);
545 
546 bool isSI(const MCSubtargetInfo &STI);
547 bool isCI(const MCSubtargetInfo &STI);
548 bool isVI(const MCSubtargetInfo &STI);
549 bool isGFX9(const MCSubtargetInfo &STI);
550 bool isGFX10(const MCSubtargetInfo &STI);
551 
552 /// Is Reg - scalar register
553 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
554 
555 /// Is there any intersection between registers
556 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
557 
558 /// If \p Reg is a pseudo reg, return the correct hardware register given
559 /// \p STI otherwise return \p Reg.
560 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
561 
562 /// Convert hardware register \p Reg to a pseudo register
563 LLVM_READNONE
564 unsigned mc2PseudoReg(unsigned Reg);
565 
566 /// Can this operand also contain immediate values?
567 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
568 
569 /// Is this floating-point operand?
570 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
571 
572 /// Does this opearnd support only inlinable literals?
573 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
574 
575 /// Get the size in bits of a register from the register class \p RC.
576 unsigned getRegBitWidth(unsigned RCID);
577 
578 /// Get the size in bits of a register from the register class \p RC.
579 unsigned getRegBitWidth(const MCRegisterClass &RC);
580 
581 /// Get size of register operand
582 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
583                            unsigned OpNo);
584 
585 LLVM_READNONE
586 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
587   switch (OpInfo.OperandType) {
588   case AMDGPU::OPERAND_REG_IMM_INT32:
589   case AMDGPU::OPERAND_REG_IMM_FP32:
590   case AMDGPU::OPERAND_REG_INLINE_C_INT32:
591   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
592   case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
593   case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
594     return 4;
595 
596   case AMDGPU::OPERAND_REG_IMM_INT64:
597   case AMDGPU::OPERAND_REG_IMM_FP64:
598   case AMDGPU::OPERAND_REG_INLINE_C_INT64:
599   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
600     return 8;
601 
602   case AMDGPU::OPERAND_REG_IMM_INT16:
603   case AMDGPU::OPERAND_REG_IMM_FP16:
604   case AMDGPU::OPERAND_REG_INLINE_C_INT16:
605   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
606   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
607   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
608   case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
609   case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
610   case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
611   case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
612   case AMDGPU::OPERAND_REG_IMM_V2INT16:
613   case AMDGPU::OPERAND_REG_IMM_V2FP16:
614     return 2;
615 
616   default:
617     llvm_unreachable("unhandled operand type");
618   }
619 }
620 
621 LLVM_READNONE
622 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
623   return getOperandSize(Desc.OpInfo[OpNo]);
624 }
625 
626 /// Is this literal inlinable
627 LLVM_READNONE
628 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
629 
630 LLVM_READNONE
631 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
632 
633 LLVM_READNONE
634 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
635 
636 LLVM_READNONE
637 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
638 
639 bool isArgPassedInSGPR(const Argument *Arg);
640 
641 LLVM_READONLY
642 bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
643                                       int64_t EncodedOffset);
644 
645 LLVM_READONLY
646 bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,
647                                     int64_t EncodedOffset,
648                                     bool IsBuffer);
649 
650 /// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
651 /// offsets.
652 uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
653 
654 /// \returns The encoding that will be used for \p ByteOffset in the
655 /// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
656 /// S_LOAD instructions have a signed offset, on other subtargets it is
657 /// unsigned. S_BUFFER has an unsigned offset for all subtargets.
658 Optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
659                                        int64_t ByteOffset, bool IsBuffer);
660 
661 /// \return The encoding that can be used for a 32-bit literal offset in an SMRD
662 /// instruction. This is only useful on CI.s
663 Optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
664                                                 int64_t ByteOffset);
665 
666 /// \returns true if this offset is small enough to fit in the SMRD
667 /// offset field.  \p ByteOffset should be the offset in bytes and
668 /// not the encoded offset.
669 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
670 
671 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
672                       const GCNSubtarget *Subtarget, uint32_t Align = 4);
673 
674 /// \returns true if the intrinsic is divergent
675 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
676 
677 // Track defaults for fields in the MODE registser.
678 struct SIModeRegisterDefaults {
679   /// Floating point opcodes that support exception flag gathering quiet and
680   /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
681   /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
682   /// quieting.
683   bool IEEE : 1;
684 
685   /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
686   /// clamp NaN to zero; otherwise, pass NaN through.
687   bool DX10Clamp : 1;
688 
689   /// If this is set, neither input or output denormals are flushed for most f32
690   /// instructions.
691   bool FP32InputDenormals : 1;
692   bool FP32OutputDenormals : 1;
693 
694   /// If this is set, neither input or output denormals are flushed for both f64
695   /// and f16/v2f16 instructions.
696   bool FP64FP16InputDenormals : 1;
697   bool FP64FP16OutputDenormals : 1;
698 
699   SIModeRegisterDefaults() :
700     IEEE(true),
701     DX10Clamp(true),
702     FP32InputDenormals(true),
703     FP32OutputDenormals(true),
704     FP64FP16InputDenormals(true),
705     FP64FP16OutputDenormals(true) {}
706 
707   SIModeRegisterDefaults(const Function &F);
708 
709   static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) {
710     const bool IsCompute = AMDGPU::isCompute(CC);
711 
712     SIModeRegisterDefaults Mode;
713     Mode.IEEE = IsCompute;
714     return Mode;
715   }
716 
717   bool operator ==(const SIModeRegisterDefaults Other) const {
718     return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
719            FP32InputDenormals == Other.FP32InputDenormals &&
720            FP32OutputDenormals == Other.FP32OutputDenormals &&
721            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
722            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
723   }
724 
725   bool allFP32Denormals() const {
726     return FP32InputDenormals && FP32OutputDenormals;
727   }
728 
729   bool allFP64FP16Denormals() const {
730     return FP64FP16InputDenormals && FP64FP16OutputDenormals;
731   }
732 
733   /// Get the encoding value for the FP_DENORM bits of the mode register for the
734   /// FP32 denormal mode.
735   uint32_t fpDenormModeSPValue() const {
736     if (FP32InputDenormals && FP32OutputDenormals)
737       return FP_DENORM_FLUSH_NONE;
738     if (FP32InputDenormals)
739       return FP_DENORM_FLUSH_OUT;
740     if (FP32OutputDenormals)
741       return FP_DENORM_FLUSH_IN;
742     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
743   }
744 
745   /// Get the encoding value for the FP_DENORM bits of the mode register for the
746   /// FP64/FP16 denormal mode.
747   uint32_t fpDenormModeDPValue() const {
748     if (FP64FP16InputDenormals && FP64FP16OutputDenormals)
749       return FP_DENORM_FLUSH_NONE;
750     if (FP64FP16InputDenormals)
751       return FP_DENORM_FLUSH_OUT;
752     if (FP64FP16OutputDenormals)
753       return FP_DENORM_FLUSH_IN;
754     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
755   }
756 
757   /// Returns true if a flag is compatible if it's enabled in the callee, but
758   /// disabled in the caller.
759   static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
760     return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
761   }
762 
763   // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
764   // be able to override.
765   bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
766     if (DX10Clamp != CalleeMode.DX10Clamp)
767       return false;
768     if (IEEE != CalleeMode.IEEE)
769       return false;
770 
771     // Allow inlining denormals enabled into denormals flushed functions.
772     return oneWayCompatible(FP64FP16InputDenormals, CalleeMode.FP64FP16InputDenormals) &&
773            oneWayCompatible(FP64FP16OutputDenormals, CalleeMode.FP64FP16OutputDenormals) &&
774            oneWayCompatible(FP32InputDenormals, CalleeMode.FP32InputDenormals) &&
775            oneWayCompatible(FP32OutputDenormals, CalleeMode.FP32OutputDenormals);
776   }
777 };
778 
779 LLVM_READNONE
780 bool isInlinableIntLiteral(int64_t Literal);
781 
782 } // end namespace AMDGPU
783 } // end namespace llvm
784 
785 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
786