1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
12 
13 #include "AMDGPU.h"
14 #include "AMDKernelCodeT.h"
15 #include "SIDefines.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/IR/CallingConv.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/Support/Compiler.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include <cstdint>
22 #include <utility>
23 
24 namespace llvm {
25 
26 class FeatureBitset;
27 class Function;
28 class GlobalValue;
29 class MachineMemOperand;
30 class MCContext;
31 class MCRegisterClass;
32 class MCRegisterInfo;
33 class MCSection;
34 class MCSubtargetInfo;
35 class Triple;
36 
37 namespace AMDGPU {
38 namespace IsaInfo {
39 
40 enum {
41   // The closed Vulkan driver sets 96, which limits the wave count to 8 but
42   // doesn't spill SGPRs as much as when 80 is set.
43   FIXED_NUM_SGPRS_FOR_INIT_BUG = 96
44 };
45 
46 /// \brief Instruction set architecture version.
47 struct IsaVersion {
48   unsigned Major;
49   unsigned Minor;
50   unsigned Stepping;
51 };
52 
53 /// \returns Isa version for given subtarget \p Features.
54 IsaVersion getIsaVersion(const FeatureBitset &Features);
55 
56 /// \returns Wavefront size for given subtarget \p Features.
57 unsigned getWavefrontSize(const FeatureBitset &Features);
58 
59 /// \returns Local memory size in bytes for given subtarget \p Features.
60 unsigned getLocalMemorySize(const FeatureBitset &Features);
61 
62 /// \returns Number of execution units per compute unit for given subtarget \p
63 /// Features.
64 unsigned getEUsPerCU(const FeatureBitset &Features);
65 
66 /// \returns Maximum number of work groups per compute unit for given subtarget
67 /// \p Features and limited by given \p FlatWorkGroupSize.
68 unsigned getMaxWorkGroupsPerCU(const FeatureBitset &Features,
69                                unsigned FlatWorkGroupSize);
70 
71 /// \returns Maximum number of waves per compute unit for given subtarget \p
72 /// Features without any kind of limitation.
73 unsigned getMaxWavesPerCU(const FeatureBitset &Features);
74 
75 /// \returns Maximum number of waves per compute unit for given subtarget \p
76 /// Features and limited by given \p FlatWorkGroupSize.
77 unsigned getMaxWavesPerCU(const FeatureBitset &Features,
78                           unsigned FlatWorkGroupSize);
79 
80 /// \returns Minimum number of waves per execution unit for given subtarget \p
81 /// Features.
82 unsigned getMinWavesPerEU(const FeatureBitset &Features);
83 
84 /// \returns Maximum number of waves per execution unit for given subtarget \p
85 /// Features without any kind of limitation.
86 unsigned getMaxWavesPerEU(const FeatureBitset &Features);
87 
88 /// \returns Maximum number of waves per execution unit for given subtarget \p
89 /// Features and limited by given \p FlatWorkGroupSize.
90 unsigned getMaxWavesPerEU(const FeatureBitset &Features,
91                           unsigned FlatWorkGroupSize);
92 
93 /// \returns Minimum flat work group size for given subtarget \p Features.
94 unsigned getMinFlatWorkGroupSize(const FeatureBitset &Features);
95 
96 /// \returns Maximum flat work group size for given subtarget \p Features.
97 unsigned getMaxFlatWorkGroupSize(const FeatureBitset &Features);
98 
99 /// \returns Number of waves per work group for given subtarget \p Features and
100 /// limited by given \p FlatWorkGroupSize.
101 unsigned getWavesPerWorkGroup(const FeatureBitset &Features,
102                               unsigned FlatWorkGroupSize);
103 
104 /// \returns SGPR allocation granularity for given subtarget \p Features.
105 unsigned getSGPRAllocGranule(const FeatureBitset &Features);
106 
107 /// \returns SGPR encoding granularity for given subtarget \p Features.
108 unsigned getSGPREncodingGranule(const FeatureBitset &Features);
109 
110 /// \returns Total number of SGPRs for given subtarget \p Features.
111 unsigned getTotalNumSGPRs(const FeatureBitset &Features);
112 
113 /// \returns Addressable number of SGPRs for given subtarget \p Features.
114 unsigned getAddressableNumSGPRs(const FeatureBitset &Features);
115 
116 /// \returns Minimum number of SGPRs that meets the given number of waves per
117 /// execution unit requirement for given subtarget \p Features.
118 unsigned getMinNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
119 
120 /// \returns Maximum number of SGPRs that meets the given number of waves per
121 /// execution unit requirement for given subtarget \p Features.
122 unsigned getMaxNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU,
123                         bool Addressable);
124 
125 /// \returns VGPR allocation granularity for given subtarget \p Features.
126 unsigned getVGPRAllocGranule(const FeatureBitset &Features);
127 
128 /// \returns VGPR encoding granularity for given subtarget \p Features.
129 unsigned getVGPREncodingGranule(const FeatureBitset &Features);
130 
131 /// \returns Total number of VGPRs for given subtarget \p Features.
132 unsigned getTotalNumVGPRs(const FeatureBitset &Features);
133 
134 /// \returns Addressable number of VGPRs for given subtarget \p Features.
135 unsigned getAddressableNumVGPRs(const FeatureBitset &Features);
136 
137 /// \returns Minimum number of VGPRs that meets given number of waves per
138 /// execution unit requirement for given subtarget \p Features.
139 unsigned getMinNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
140 
141 /// \returns Maximum number of VGPRs that meets given number of waves per
142 /// execution unit requirement for given subtarget \p Features.
143 unsigned getMaxNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
144 
145 } // end namespace IsaInfo
146 
147 LLVM_READONLY
148 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
149 
150 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
151                                const FeatureBitset &Features);
152 
153 bool isGroupSegment(const GlobalValue *GV, AMDGPUAS AS);
154 bool isGlobalSegment(const GlobalValue *GV, AMDGPUAS AS);
155 bool isReadOnlySegment(const GlobalValue *GV, AMDGPUAS AS);
156 
157 /// \returns True if constants should be emitted to .text section for given
158 /// target triple \p TT, false otherwise.
159 bool shouldEmitConstantsToTextSection(const Triple &TT);
160 
161 /// \returns Integer value requested using \p F's \p Name attribute.
162 ///
163 /// \returns \p Default if attribute is not present.
164 ///
165 /// \returns \p Default and emits error if requested value cannot be converted
166 /// to integer.
167 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
168 
169 /// \returns A pair of integer values requested using \p F's \p Name attribute
170 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
171 /// is false).
172 ///
173 /// \returns \p Default if attribute is not present.
174 ///
175 /// \returns \p Default and emits error if one of the requested values cannot be
176 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
177 /// not present.
178 std::pair<int, int> getIntegerPairAttribute(const Function &F,
179                                             StringRef Name,
180                                             std::pair<int, int> Default,
181                                             bool OnlyFirstRequired = false);
182 
183 /// \returns Vmcnt bit mask for given isa \p Version.
184 unsigned getVmcntBitMask(const IsaInfo::IsaVersion &Version);
185 
186 /// \returns Expcnt bit mask for given isa \p Version.
187 unsigned getExpcntBitMask(const IsaInfo::IsaVersion &Version);
188 
189 /// \returns Lgkmcnt bit mask for given isa \p Version.
190 unsigned getLgkmcntBitMask(const IsaInfo::IsaVersion &Version);
191 
192 /// \returns Waitcnt bit mask for given isa \p Version.
193 unsigned getWaitcntBitMask(const IsaInfo::IsaVersion &Version);
194 
195 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
196 unsigned decodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
197 
198 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
199 unsigned decodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
200 
201 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
202 unsigned decodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
203 
204 /// \brief Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
205 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
206 /// \p Lgkmcnt respectively.
207 ///
208 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
209 ///     \p Vmcnt = \p Waitcnt[3:0]                      (pre-gfx9 only)
210 ///     \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14]  (gfx9+ only)
211 ///     \p Expcnt = \p Waitcnt[6:4]
212 ///     \p Lgkmcnt = \p Waitcnt[11:8]
213 void decodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
214                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
215 
216 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
217 unsigned encodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
218                      unsigned Vmcnt);
219 
220 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
221 unsigned encodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
222                       unsigned Expcnt);
223 
224 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
225 unsigned encodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
226                        unsigned Lgkmcnt);
227 
228 /// \brief Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
229 /// \p Version.
230 ///
231 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
232 ///     Waitcnt[3:0]   = \p Vmcnt       (pre-gfx9 only)
233 ///     Waitcnt[3:0]   = \p Vmcnt[3:0]  (gfx9+ only)
234 ///     Waitcnt[6:4]   = \p Expcnt
235 ///     Waitcnt[11:8]  = \p Lgkmcnt
236 ///     Waitcnt[15:14] = \p Vmcnt[5:4]  (gfx9+ only)
237 ///
238 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
239 /// isa \p Version.
240 unsigned encodeWaitcnt(const IsaInfo::IsaVersion &Version,
241                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
242 
243 unsigned getInitialPSInputAddr(const Function &F);
244 
245 LLVM_READNONE
246 bool isShader(CallingConv::ID CC);
247 
248 LLVM_READNONE
249 bool isCompute(CallingConv::ID CC);
250 
251 LLVM_READNONE
252 bool isEntryFunctionCC(CallingConv::ID CC);
253 
254 // FIXME: Remove this when calling conventions cleaned up
255 LLVM_READNONE
256 inline bool isKernel(CallingConv::ID CC) {
257   switch (CC) {
258   case CallingConv::AMDGPU_KERNEL:
259   case CallingConv::SPIR_KERNEL:
260     return true;
261   default:
262     return false;
263   }
264 }
265 
266 bool isSI(const MCSubtargetInfo &STI);
267 bool isCI(const MCSubtargetInfo &STI);
268 bool isVI(const MCSubtargetInfo &STI);
269 bool isGFX9(const MCSubtargetInfo &STI);
270 
271 /// \brief Is Reg - scalar register
272 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
273 
274 /// \brief Is there any intersection between registers
275 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
276 
277 /// If \p Reg is a pseudo reg, return the correct hardware register given
278 /// \p STI otherwise return \p Reg.
279 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
280 
281 /// \brief Convert hardware register \p Reg to a pseudo register
282 LLVM_READNONE
283 unsigned mc2PseudoReg(unsigned Reg);
284 
285 /// \brief Can this operand also contain immediate values?
286 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
287 
288 /// \brief Is this floating-point operand?
289 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
290 
291 /// \brief Does this opearnd support only inlinable literals?
292 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
293 
294 /// \brief Get the size in bits of a register from the register class \p RC.
295 unsigned getRegBitWidth(unsigned RCID);
296 
297 /// \brief Get the size in bits of a register from the register class \p RC.
298 unsigned getRegBitWidth(const MCRegisterClass &RC);
299 
300 /// \brief Get size of register operand
301 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
302                            unsigned OpNo);
303 
304 LLVM_READNONE
305 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
306   switch (OpInfo.OperandType) {
307   case AMDGPU::OPERAND_REG_IMM_INT32:
308   case AMDGPU::OPERAND_REG_IMM_FP32:
309   case AMDGPU::OPERAND_REG_INLINE_C_INT32:
310   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
311     return 4;
312 
313   case AMDGPU::OPERAND_REG_IMM_INT64:
314   case AMDGPU::OPERAND_REG_IMM_FP64:
315   case AMDGPU::OPERAND_REG_INLINE_C_INT64:
316   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
317     return 8;
318 
319   case AMDGPU::OPERAND_REG_IMM_INT16:
320   case AMDGPU::OPERAND_REG_IMM_FP16:
321   case AMDGPU::OPERAND_REG_INLINE_C_INT16:
322   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
323   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
324   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
325     return 2;
326 
327   default:
328     llvm_unreachable("unhandled operand type");
329   }
330 }
331 
332 LLVM_READNONE
333 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
334   return getOperandSize(Desc.OpInfo[OpNo]);
335 }
336 
337 /// \brief Is this literal inlinable
338 LLVM_READNONE
339 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
340 
341 LLVM_READNONE
342 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
343 
344 LLVM_READNONE
345 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
346 
347 LLVM_READNONE
348 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
349 
350 bool isUniformMMO(const MachineMemOperand *MMO);
351 
352 /// \returns The encoding that will be used for \p ByteOffset in the SMRD
353 /// offset field.
354 int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
355 
356 /// \returns true if this offset is small enough to fit in the SMRD
357 /// offset field.  \p ByteOffset should be the offset in bytes and
358 /// not the encoded offset.
359 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
360 
361 } // end namespace AMDGPU
362 } // end namespace llvm
363 
364 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
365