1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "SIDefines.h"
13 #include "llvm/IR/CallingConv.h"
14 #include "llvm/Support/Alignment.h"
15 
16 struct amd_kernel_code_t;
17 
18 namespace llvm {
19 
20 struct Align;
21 class Argument;
22 class Function;
23 class GCNSubtarget;
24 class GlobalValue;
25 class MCRegisterClass;
26 class MCRegisterInfo;
27 class MCSubtargetInfo;
28 class StringRef;
29 class Triple;
30 
31 namespace amdhsa {
32 struct kernel_descriptor_t;
33 }
34 
35 namespace AMDGPU {
36 
37 struct IsaVersion;
38 
39 /// \returns HSA OS ABI Version identification.
40 Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
41 /// \returns True if HSA OS ABI Version identification is 2,
42 /// false otherwise.
43 bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
44 /// \returns True if HSA OS ABI Version identification is 3,
45 /// false otherwise.
46 bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
47 /// \returns True if HSA OS ABI Version identification is 4,
48 /// false otherwise.
49 bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
50 /// \returns True if HSA OS ABI Version identification is 5,
51 /// false otherwise.
52 bool isHsaAbiVersion5(const MCSubtargetInfo *STI);
53 /// \returns True if HSA OS ABI Version identification is 3 and above,
54 /// false otherwise.
55 bool isHsaAbiVersion3AndAbove(const MCSubtargetInfo *STI);
56 
57 /// \returns The offset of the multigrid_sync_arg argument from implicitarg_ptr
58 unsigned getMultigridSyncArgImplicitArgPosition();
59 
60 /// \returns The offset of the hostcall pointer argument from implicitarg_ptr
61 unsigned getHostcallImplicitArgPosition();
62 
63 /// \returns Code object version.
64 unsigned getAmdhsaCodeObjectVersion();
65 
66 struct GcnBufferFormatInfo {
67   unsigned Format;
68   unsigned BitsPerComp;
69   unsigned NumComponents;
70   unsigned NumFormat;
71   unsigned DataFormat;
72 };
73 
74 struct MAIInstInfo {
75   uint16_t Opcode;
76   bool is_dgemm;
77   bool is_gfx940_xdl;
78 };
79 
80 #define GET_MIMGBaseOpcode_DECL
81 #define GET_MIMGDim_DECL
82 #define GET_MIMGEncoding_DECL
83 #define GET_MIMGLZMapping_DECL
84 #define GET_MIMGMIPMapping_DECL
85 #define GET_MIMGBiASMapping_DECL
86 #define GET_MAIInstInfoTable_DECL
87 #include "AMDGPUGenSearchableTables.inc"
88 
89 namespace IsaInfo {
90 
91 enum {
92   // The closed Vulkan driver sets 96, which limits the wave count to 8 but
93   // doesn't spill SGPRs as much as when 80 is set.
94   FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
95   TRAP_NUM_SGPRS = 16
96 };
97 
98 enum class TargetIDSetting {
99   Unsupported,
100   Any,
101   Off,
102   On
103 };
104 
105 class AMDGPUTargetID {
106 private:
107   const MCSubtargetInfo &STI;
108   TargetIDSetting XnackSetting;
109   TargetIDSetting SramEccSetting;
110 
111 public:
112   explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
113   ~AMDGPUTargetID() = default;
114 
115   /// \return True if the current xnack setting is not "Unsupported".
116   bool isXnackSupported() const {
117     return XnackSetting != TargetIDSetting::Unsupported;
118   }
119 
120   /// \returns True if the current xnack setting is "On" or "Any".
121   bool isXnackOnOrAny() const {
122     return XnackSetting == TargetIDSetting::On ||
123         XnackSetting == TargetIDSetting::Any;
124   }
125 
126   /// \returns True if current xnack setting is "On" or "Off",
127   /// false otherwise.
128   bool isXnackOnOrOff() const {
129     return getXnackSetting() == TargetIDSetting::On ||
130         getXnackSetting() == TargetIDSetting::Off;
131   }
132 
133   /// \returns The current xnack TargetIDSetting, possible options are
134   /// "Unsupported", "Any", "Off", and "On".
135   TargetIDSetting getXnackSetting() const {
136     return XnackSetting;
137   }
138 
139   /// Sets xnack setting to \p NewXnackSetting.
140   void setXnackSetting(TargetIDSetting NewXnackSetting) {
141     XnackSetting = NewXnackSetting;
142   }
143 
144   /// \return True if the current sramecc setting is not "Unsupported".
145   bool isSramEccSupported() const {
146     return SramEccSetting != TargetIDSetting::Unsupported;
147   }
148 
149   /// \returns True if the current sramecc setting is "On" or "Any".
150   bool isSramEccOnOrAny() const {
151   return SramEccSetting == TargetIDSetting::On ||
152       SramEccSetting == TargetIDSetting::Any;
153   }
154 
155   /// \returns True if current sramecc setting is "On" or "Off",
156   /// false otherwise.
157   bool isSramEccOnOrOff() const {
158     return getSramEccSetting() == TargetIDSetting::On ||
159         getSramEccSetting() == TargetIDSetting::Off;
160   }
161 
162   /// \returns The current sramecc TargetIDSetting, possible options are
163   /// "Unsupported", "Any", "Off", and "On".
164   TargetIDSetting getSramEccSetting() const {
165     return SramEccSetting;
166   }
167 
168   /// Sets sramecc setting to \p NewSramEccSetting.
169   void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
170     SramEccSetting = NewSramEccSetting;
171   }
172 
173   void setTargetIDFromFeaturesString(StringRef FS);
174   void setTargetIDFromTargetIDStream(StringRef TargetID);
175 
176   /// \returns String representation of an object.
177   std::string toString() const;
178 };
179 
180 /// \returns Wavefront size for given subtarget \p STI.
181 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
182 
183 /// \returns Local memory size in bytes for given subtarget \p STI.
184 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
185 
186 /// \returns Number of execution units per compute unit for given subtarget \p
187 /// STI.
188 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
189 
190 /// \returns Maximum number of work groups per compute unit for given subtarget
191 /// \p STI and limited by given \p FlatWorkGroupSize.
192 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
193                                unsigned FlatWorkGroupSize);
194 
195 /// \returns Minimum number of waves per execution unit for given subtarget \p
196 /// STI.
197 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
198 
199 /// \returns Maximum number of waves per execution unit for given subtarget \p
200 /// STI without any kind of limitation.
201 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
202 
203 /// \returns Number of waves per execution unit required to support the given \p
204 /// FlatWorkGroupSize.
205 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
206                                    unsigned FlatWorkGroupSize);
207 
208 /// \returns Minimum flat work group size for given subtarget \p STI.
209 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
210 
211 /// \returns Maximum flat work group size for given subtarget \p STI.
212 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
213 
214 /// \returns Number of waves per work group for given subtarget \p STI and
215 /// \p FlatWorkGroupSize.
216 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
217                               unsigned FlatWorkGroupSize);
218 
219 /// \returns SGPR allocation granularity for given subtarget \p STI.
220 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
221 
222 /// \returns SGPR encoding granularity for given subtarget \p STI.
223 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
224 
225 /// \returns Total number of SGPRs for given subtarget \p STI.
226 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
227 
228 /// \returns Addressable number of SGPRs for given subtarget \p STI.
229 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
230 
231 /// \returns Minimum number of SGPRs that meets the given number of waves per
232 /// execution unit requirement for given subtarget \p STI.
233 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
234 
235 /// \returns Maximum number of SGPRs that meets the given number of waves per
236 /// execution unit requirement for given subtarget \p STI.
237 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
238                         bool Addressable);
239 
240 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
241 /// STI when the given special registers are used.
242 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
243                           bool FlatScrUsed, bool XNACKUsed);
244 
245 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
246 /// STI when the given special registers are used. XNACK is inferred from
247 /// \p STI.
248 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
249                           bool FlatScrUsed);
250 
251 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
252 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
253 /// register counts.
254 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
255 
256 /// \returns VGPR allocation granularity for given subtarget \p STI.
257 ///
258 /// For subtargets which support it, \p EnableWavefrontSize32 should match
259 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
260 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
261                              Optional<bool> EnableWavefrontSize32 = None);
262 
263 /// \returns VGPR encoding granularity for given subtarget \p STI.
264 ///
265 /// For subtargets which support it, \p EnableWavefrontSize32 should match
266 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
267 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
268                                 Optional<bool> EnableWavefrontSize32 = None);
269 
270 /// \returns Total number of VGPRs for given subtarget \p STI.
271 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
272 
273 /// \returns Addressable number of VGPRs for given subtarget \p STI.
274 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
275 
276 /// \returns Minimum number of VGPRs that meets given number of waves per
277 /// execution unit requirement for given subtarget \p STI.
278 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
279 
280 /// \returns Maximum number of VGPRs that meets given number of waves per
281 /// execution unit requirement for given subtarget \p STI.
282 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
283 
284 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
285 /// \p NumVGPRs are used.
286 ///
287 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
288 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
289 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
290                           Optional<bool> EnableWavefrontSize32 = None);
291 
292 } // end namespace IsaInfo
293 
294 LLVM_READONLY
295 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
296 
297 LLVM_READONLY
298 int getSOPPWithRelaxation(uint16_t Opcode);
299 
300 struct MIMGBaseOpcodeInfo {
301   MIMGBaseOpcode BaseOpcode;
302   bool Store;
303   bool Atomic;
304   bool AtomicX2;
305   bool Sampler;
306   bool Gather4;
307 
308   uint8_t NumExtraArgs;
309   bool Gradients;
310   bool G16;
311   bool Coordinates;
312   bool LodOrClampOrMip;
313   bool HasD16;
314   bool MSAA;
315   bool BVH;
316 };
317 
318 LLVM_READONLY
319 const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
320 
321 LLVM_READONLY
322 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
323 
324 struct MIMGDimInfo {
325   MIMGDim Dim;
326   uint8_t NumCoords;
327   uint8_t NumGradients;
328   bool MSAA;
329   bool DA;
330   uint8_t Encoding;
331   const char *AsmSuffix;
332 };
333 
334 LLVM_READONLY
335 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
336 
337 LLVM_READONLY
338 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
339 
340 LLVM_READONLY
341 const MIMGDimInfo *getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix);
342 
343 struct MIMGLZMappingInfo {
344   MIMGBaseOpcode L;
345   MIMGBaseOpcode LZ;
346 };
347 
348 struct MIMGMIPMappingInfo {
349   MIMGBaseOpcode MIP;
350   MIMGBaseOpcode NONMIP;
351 };
352 
353 struct MIMGBiasMappingInfo {
354   MIMGBaseOpcode Bias;
355   MIMGBaseOpcode NoBias;
356 };
357 
358 struct MIMGOffsetMappingInfo {
359   MIMGBaseOpcode Offset;
360   MIMGBaseOpcode NoOffset;
361 };
362 
363 struct MIMGG16MappingInfo {
364   MIMGBaseOpcode G;
365   MIMGBaseOpcode G16;
366 };
367 
368 LLVM_READONLY
369 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
370 
371 LLVM_READONLY
372 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
373 
374 LLVM_READONLY
375 const MIMGBiasMappingInfo *getMIMGBiasMappingInfo(unsigned Bias);
376 
377 LLVM_READONLY
378 const MIMGOffsetMappingInfo *getMIMGOffsetMappingInfo(unsigned Offset);
379 
380 LLVM_READONLY
381 const MIMGG16MappingInfo *getMIMGG16MappingInfo(unsigned G);
382 
383 LLVM_READONLY
384 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
385                   unsigned VDataDwords, unsigned VAddrDwords);
386 
387 LLVM_READONLY
388 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
389 
390 LLVM_READONLY
391 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
392                            const MIMGDimInfo *Dim, bool IsA16,
393                            bool IsG16Supported);
394 
395 struct MIMGInfo {
396   uint16_t Opcode;
397   uint16_t BaseOpcode;
398   uint8_t MIMGEncoding;
399   uint8_t VDataDwords;
400   uint8_t VAddrDwords;
401 };
402 
403 LLVM_READONLY
404 const MIMGInfo *getMIMGInfo(unsigned Opc);
405 
406 LLVM_READONLY
407 int getMTBUFBaseOpcode(unsigned Opc);
408 
409 LLVM_READONLY
410 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
411 
412 LLVM_READONLY
413 int getMTBUFElements(unsigned Opc);
414 
415 LLVM_READONLY
416 bool getMTBUFHasVAddr(unsigned Opc);
417 
418 LLVM_READONLY
419 bool getMTBUFHasSrsrc(unsigned Opc);
420 
421 LLVM_READONLY
422 bool getMTBUFHasSoffset(unsigned Opc);
423 
424 LLVM_READONLY
425 int getMUBUFBaseOpcode(unsigned Opc);
426 
427 LLVM_READONLY
428 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
429 
430 LLVM_READONLY
431 int getMUBUFElements(unsigned Opc);
432 
433 LLVM_READONLY
434 bool getMUBUFHasVAddr(unsigned Opc);
435 
436 LLVM_READONLY
437 bool getMUBUFHasSrsrc(unsigned Opc);
438 
439 LLVM_READONLY
440 bool getMUBUFHasSoffset(unsigned Opc);
441 
442 LLVM_READONLY
443 bool getMUBUFIsBufferInv(unsigned Opc);
444 
445 LLVM_READONLY
446 bool getSMEMIsBuffer(unsigned Opc);
447 
448 LLVM_READONLY
449 bool getVOP1IsSingle(unsigned Opc);
450 
451 LLVM_READONLY
452 bool getVOP2IsSingle(unsigned Opc);
453 
454 LLVM_READONLY
455 bool getVOP3IsSingle(unsigned Opc);
456 
457 /// Returns true if MAI operation is a double precision GEMM.
458 LLVM_READONLY
459 bool getMAIIsDGEMM(unsigned Opc);
460 
461 LLVM_READONLY
462 bool getMAIIsGFX940XDL(unsigned Opc);
463 
464 LLVM_READONLY
465 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
466                                                   uint8_t NumComponents,
467                                                   uint8_t NumFormat,
468                                                   const MCSubtargetInfo &STI);
469 LLVM_READONLY
470 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
471                                                   const MCSubtargetInfo &STI);
472 
473 LLVM_READONLY
474 int getMCOpcode(uint16_t Opcode, unsigned Gen);
475 
476 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
477                                const MCSubtargetInfo *STI);
478 
479 amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(
480     const MCSubtargetInfo *STI);
481 
482 bool isGroupSegment(const GlobalValue *GV);
483 bool isGlobalSegment(const GlobalValue *GV);
484 bool isReadOnlySegment(const GlobalValue *GV);
485 
486 /// \returns True if constants should be emitted to .text section for given
487 /// target triple \p TT, false otherwise.
488 bool shouldEmitConstantsToTextSection(const Triple &TT);
489 
490 /// \returns Integer value requested using \p F's \p Name attribute.
491 ///
492 /// \returns \p Default if attribute is not present.
493 ///
494 /// \returns \p Default and emits error if requested value cannot be converted
495 /// to integer.
496 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
497 
498 /// \returns A pair of integer values requested using \p F's \p Name attribute
499 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
500 /// is false).
501 ///
502 /// \returns \p Default if attribute is not present.
503 ///
504 /// \returns \p Default and emits error if one of the requested values cannot be
505 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
506 /// not present.
507 std::pair<int, int> getIntegerPairAttribute(const Function &F,
508                                             StringRef Name,
509                                             std::pair<int, int> Default,
510                                             bool OnlyFirstRequired = false);
511 
512 /// Represents the counter values to wait for in an s_waitcnt instruction.
513 ///
514 /// Large values (including the maximum possible integer) can be used to
515 /// represent "don't care" waits.
516 struct Waitcnt {
517   unsigned VmCnt = ~0u;
518   unsigned ExpCnt = ~0u;
519   unsigned LgkmCnt = ~0u;
520   unsigned VsCnt = ~0u;
521 
522   Waitcnt() = default;
523   Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
524       : VmCnt(VmCnt), ExpCnt(ExpCnt), LgkmCnt(LgkmCnt), VsCnt(VsCnt) {}
525 
526   static Waitcnt allZero(bool HasVscnt) {
527     return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
528   }
529   static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
530 
531   bool hasWait() const {
532     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
533   }
534 
535   bool hasWaitExceptVsCnt() const {
536     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u;
537   }
538 
539   bool hasWaitVsCnt() const {
540     return VsCnt != ~0u;
541   }
542 
543   bool dominates(const Waitcnt &Other) const {
544     return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
545            LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
546   }
547 
548   Waitcnt combined(const Waitcnt &Other) const {
549     return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
550                    std::min(LgkmCnt, Other.LgkmCnt),
551                    std::min(VsCnt, Other.VsCnt));
552   }
553 };
554 
555 /// \returns Vmcnt bit mask for given isa \p Version.
556 unsigned getVmcntBitMask(const IsaVersion &Version);
557 
558 /// \returns Expcnt bit mask for given isa \p Version.
559 unsigned getExpcntBitMask(const IsaVersion &Version);
560 
561 /// \returns Lgkmcnt bit mask for given isa \p Version.
562 unsigned getLgkmcntBitMask(const IsaVersion &Version);
563 
564 /// \returns Waitcnt bit mask for given isa \p Version.
565 unsigned getWaitcntBitMask(const IsaVersion &Version);
566 
567 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
568 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
569 
570 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
571 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
572 
573 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
574 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
575 
576 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
577 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
578 /// \p Lgkmcnt respectively.
579 ///
580 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
581 ///     \p Vmcnt = \p Waitcnt[3:0]                      (pre-gfx9 only)
582 ///     \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14]  (gfx9+ only)
583 ///     \p Expcnt = \p Waitcnt[6:4]
584 ///     \p Lgkmcnt = \p Waitcnt[11:8]                   (pre-gfx10 only)
585 ///     \p Lgkmcnt = \p Waitcnt[13:8]                   (gfx10+ only)
586 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
587                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
588 
589 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
590 
591 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
592 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
593                      unsigned Vmcnt);
594 
595 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
596 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
597                       unsigned Expcnt);
598 
599 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
600 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
601                        unsigned Lgkmcnt);
602 
603 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
604 /// \p Version.
605 ///
606 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
607 ///     Waitcnt[3:0]   = \p Vmcnt       (pre-gfx9 only)
608 ///     Waitcnt[3:0]   = \p Vmcnt[3:0]  (gfx9+ only)
609 ///     Waitcnt[6:4]   = \p Expcnt
610 ///     Waitcnt[11:8]  = \p Lgkmcnt     (pre-gfx10 only)
611 ///     Waitcnt[13:8]  = \p Lgkmcnt     (gfx10+ only)
612 ///     Waitcnt[15:14] = \p Vmcnt[5:4]  (gfx9+ only)
613 ///
614 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
615 /// isa \p Version.
616 unsigned encodeWaitcnt(const IsaVersion &Version,
617                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
618 
619 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
620 
621 namespace Hwreg {
622 
623 LLVM_READONLY
624 int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI);
625 
626 LLVM_READNONE
627 bool isValidHwreg(int64_t Id);
628 
629 LLVM_READNONE
630 bool isValidHwregOffset(int64_t Offset);
631 
632 LLVM_READNONE
633 bool isValidHwregWidth(int64_t Width);
634 
635 LLVM_READNONE
636 uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
637 
638 LLVM_READNONE
639 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
640 
641 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
642 
643 } // namespace Hwreg
644 
645 namespace DepCtr {
646 
647 int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI);
648 int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
649                  const MCSubtargetInfo &STI);
650 bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
651                               const MCSubtargetInfo &STI);
652 bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
653                   bool &IsDefault, const MCSubtargetInfo &STI);
654 
655 } // namespace DepCtr
656 
657 namespace Exp {
658 
659 bool getTgtName(unsigned Id, StringRef &Name, int &Index);
660 
661 LLVM_READONLY
662 unsigned getTgtId(const StringRef Name);
663 
664 LLVM_READNONE
665 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
666 
667 } // namespace Exp
668 
669 namespace MTBUFFormat {
670 
671 LLVM_READNONE
672 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
673 
674 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
675 
676 int64_t getDfmt(const StringRef Name);
677 
678 StringRef getDfmtName(unsigned Id);
679 
680 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
681 
682 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
683 
684 bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
685 
686 bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
687 
688 int64_t getUnifiedFormat(const StringRef Name);
689 
690 StringRef getUnifiedFormatName(unsigned Id);
691 
692 bool isValidUnifiedFormat(unsigned Val);
693 
694 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt);
695 
696 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
697 
698 unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
699 
700 } // namespace MTBUFFormat
701 
702 namespace SendMsg {
703 
704 LLVM_READONLY
705 int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI);
706 
707 LLVM_READONLY
708 int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
709 
710 LLVM_READNONE
711 StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI);
712 
713 LLVM_READNONE
714 StringRef getMsgOpName(int64_t MsgId, int64_t OpId);
715 
716 LLVM_READNONE
717 bool isValidMsgId(int64_t MsgId);
718 
719 LLVM_READNONE
720 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
721                   bool Strict = true);
722 
723 LLVM_READNONE
724 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
725                       const MCSubtargetInfo &STI, bool Strict = true);
726 
727 LLVM_READNONE
728 bool msgRequiresOp(int64_t MsgId);
729 
730 LLVM_READNONE
731 bool msgSupportsStream(int64_t MsgId, int64_t OpId);
732 
733 void decodeMsg(unsigned Val,
734                uint16_t &MsgId,
735                uint16_t &OpId,
736                uint16_t &StreamId);
737 
738 LLVM_READNONE
739 uint64_t encodeMsg(uint64_t MsgId,
740                    uint64_t OpId,
741                    uint64_t StreamId);
742 
743 } // namespace SendMsg
744 
745 
746 unsigned getInitialPSInputAddr(const Function &F);
747 
748 bool getHasColorExport(const Function &F);
749 
750 bool getHasDepthExport(const Function &F);
751 
752 LLVM_READNONE
753 bool isShader(CallingConv::ID CC);
754 
755 LLVM_READNONE
756 bool isGraphics(CallingConv::ID CC);
757 
758 LLVM_READNONE
759 bool isCompute(CallingConv::ID CC);
760 
761 LLVM_READNONE
762 bool isEntryFunctionCC(CallingConv::ID CC);
763 
764 // These functions are considered entrypoints into the current module, i.e. they
765 // are allowed to be called from outside the current module. This is different
766 // from isEntryFunctionCC, which is only true for functions that are entered by
767 // the hardware. Module entry points include all entry functions but also
768 // include functions that can be called from other functions inside or outside
769 // the current module. Module entry functions are allowed to allocate LDS.
770 LLVM_READNONE
771 bool isModuleEntryFunctionCC(CallingConv::ID CC);
772 
773 bool isKernelCC(const Function *Func);
774 
775 // FIXME: Remove this when calling conventions cleaned up
776 LLVM_READNONE
777 inline bool isKernel(CallingConv::ID CC) {
778   switch (CC) {
779   case CallingConv::AMDGPU_KERNEL:
780   case CallingConv::SPIR_KERNEL:
781     return true;
782   default:
783     return false;
784   }
785 }
786 
787 bool hasXNACK(const MCSubtargetInfo &STI);
788 bool hasSRAMECC(const MCSubtargetInfo &STI);
789 bool hasMIMG_R128(const MCSubtargetInfo &STI);
790 bool hasGFX10A16(const MCSubtargetInfo &STI);
791 bool hasG16(const MCSubtargetInfo &STI);
792 bool hasPackedD16(const MCSubtargetInfo &STI);
793 
794 bool isSI(const MCSubtargetInfo &STI);
795 bool isCI(const MCSubtargetInfo &STI);
796 bool isVI(const MCSubtargetInfo &STI);
797 bool isGFX9(const MCSubtargetInfo &STI);
798 bool isGFX9_GFX10(const MCSubtargetInfo &STI);
799 bool isGFX8Plus(const MCSubtargetInfo &STI);
800 bool isGFX9Plus(const MCSubtargetInfo &STI);
801 bool isGFX10(const MCSubtargetInfo &STI);
802 bool isGFX10Plus(const MCSubtargetInfo &STI);
803 bool isNotGFX10Plus(const MCSubtargetInfo &STI);
804 bool isGFX10Before1030(const MCSubtargetInfo &STI);
805 bool isGCN3Encoding(const MCSubtargetInfo &STI);
806 bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
807 bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
808 bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
809 bool isGFX90A(const MCSubtargetInfo &STI);
810 bool isGFX940(const MCSubtargetInfo &STI);
811 bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI);
812 bool hasMAIInsts(const MCSubtargetInfo &STI);
813 int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
814 
815 /// Is Reg - scalar register
816 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
817 
818 /// If \p Reg is a pseudo reg, return the correct hardware register given
819 /// \p STI otherwise return \p Reg.
820 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
821 
822 /// Convert hardware register \p Reg to a pseudo register
823 LLVM_READNONE
824 unsigned mc2PseudoReg(unsigned Reg);
825 
826 /// Can this operand also contain immediate values?
827 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
828 
829 /// Is this floating-point operand?
830 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
831 
832 /// Does this operand support only inlinable literals?
833 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
834 
835 /// Get the size in bits of a register from the register class \p RC.
836 unsigned getRegBitWidth(unsigned RCID);
837 
838 /// Get the size in bits of a register from the register class \p RC.
839 unsigned getRegBitWidth(const MCRegisterClass &RC);
840 
841 /// Get size of register operand
842 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
843                            unsigned OpNo);
844 
845 LLVM_READNONE
846 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
847   switch (OpInfo.OperandType) {
848   case AMDGPU::OPERAND_REG_IMM_INT32:
849   case AMDGPU::OPERAND_REG_IMM_FP32:
850   case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
851   case AMDGPU::OPERAND_REG_INLINE_C_INT32:
852   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
853   case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
854   case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
855   case AMDGPU::OPERAND_REG_IMM_V2INT32:
856   case AMDGPU::OPERAND_REG_IMM_V2FP32:
857   case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
858   case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
859   case AMDGPU::OPERAND_KIMM32:
860   case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 4
861     return 4;
862 
863   case AMDGPU::OPERAND_REG_IMM_INT64:
864   case AMDGPU::OPERAND_REG_IMM_FP64:
865   case AMDGPU::OPERAND_REG_INLINE_C_INT64:
866   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
867   case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
868     return 8;
869 
870   case AMDGPU::OPERAND_REG_IMM_INT16:
871   case AMDGPU::OPERAND_REG_IMM_FP16:
872   case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
873   case AMDGPU::OPERAND_REG_INLINE_C_INT16:
874   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
875   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
876   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
877   case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
878   case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
879   case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
880   case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
881   case AMDGPU::OPERAND_REG_IMM_V2INT16:
882   case AMDGPU::OPERAND_REG_IMM_V2FP16:
883     return 2;
884 
885   default:
886     llvm_unreachable("unhandled operand type");
887   }
888 }
889 
890 LLVM_READNONE
891 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
892   return getOperandSize(Desc.OpInfo[OpNo]);
893 }
894 
895 /// Is this literal inlinable, and not one of the values intended for floating
896 /// point values.
897 LLVM_READNONE
898 inline bool isInlinableIntLiteral(int64_t Literal) {
899   return Literal >= -16 && Literal <= 64;
900 }
901 
902 /// Is this literal inlinable
903 LLVM_READNONE
904 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
905 
906 LLVM_READNONE
907 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
908 
909 LLVM_READNONE
910 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
911 
912 LLVM_READNONE
913 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
914 
915 LLVM_READNONE
916 bool isInlinableIntLiteralV216(int32_t Literal);
917 
918 LLVM_READNONE
919 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
920 
921 bool isArgPassedInSGPR(const Argument *Arg);
922 
923 LLVM_READONLY
924 bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
925                                       int64_t EncodedOffset);
926 
927 LLVM_READONLY
928 bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,
929                                     int64_t EncodedOffset,
930                                     bool IsBuffer);
931 
932 /// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
933 /// offsets.
934 uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
935 
936 /// \returns The encoding that will be used for \p ByteOffset in the
937 /// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
938 /// S_LOAD instructions have a signed offset, on other subtargets it is
939 /// unsigned. S_BUFFER has an unsigned offset for all subtargets.
940 Optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
941                                        int64_t ByteOffset, bool IsBuffer);
942 
943 /// \return The encoding that can be used for a 32-bit literal offset in an SMRD
944 /// instruction. This is only useful on CI.s
945 Optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
946                                                 int64_t ByteOffset);
947 
948 /// For FLAT segment the offset must be positive;
949 /// MSB is ignored and forced to zero.
950 ///
951 /// \return The number of bits available for the offset field in flat
952 /// instructions.
953 unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed);
954 
955 /// \returns true if this offset is small enough to fit in the SMRD
956 /// offset field.  \p ByteOffset should be the offset in bytes and
957 /// not the encoded offset.
958 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
959 
960 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
961                       const GCNSubtarget *Subtarget,
962                       Align Alignment = Align(4));
963 
964 LLVM_READNONE
965 inline bool isLegal64BitDPPControl(unsigned DC) {
966   return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
967 }
968 
969 /// \returns true if the intrinsic is divergent
970 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
971 
972 // Track defaults for fields in the MODE register.
973 struct SIModeRegisterDefaults {
974   /// Floating point opcodes that support exception flag gathering quiet and
975   /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
976   /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
977   /// quieting.
978   bool IEEE : 1;
979 
980   /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
981   /// clamp NaN to zero; otherwise, pass NaN through.
982   bool DX10Clamp : 1;
983 
984   /// If this is set, neither input or output denormals are flushed for most f32
985   /// instructions.
986   bool FP32InputDenormals : 1;
987   bool FP32OutputDenormals : 1;
988 
989   /// If this is set, neither input or output denormals are flushed for both f64
990   /// and f16/v2f16 instructions.
991   bool FP64FP16InputDenormals : 1;
992   bool FP64FP16OutputDenormals : 1;
993 
994   SIModeRegisterDefaults() :
995     IEEE(true),
996     DX10Clamp(true),
997     FP32InputDenormals(true),
998     FP32OutputDenormals(true),
999     FP64FP16InputDenormals(true),
1000     FP64FP16OutputDenormals(true) {}
1001 
1002   SIModeRegisterDefaults(const Function &F);
1003 
1004   static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) {
1005     SIModeRegisterDefaults Mode;
1006     Mode.IEEE = !AMDGPU::isShader(CC);
1007     return Mode;
1008   }
1009 
1010   bool operator ==(const SIModeRegisterDefaults Other) const {
1011     return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
1012            FP32InputDenormals == Other.FP32InputDenormals &&
1013            FP32OutputDenormals == Other.FP32OutputDenormals &&
1014            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
1015            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
1016   }
1017 
1018   bool allFP32Denormals() const {
1019     return FP32InputDenormals && FP32OutputDenormals;
1020   }
1021 
1022   bool allFP64FP16Denormals() const {
1023     return FP64FP16InputDenormals && FP64FP16OutputDenormals;
1024   }
1025 
1026   /// Get the encoding value for the FP_DENORM bits of the mode register for the
1027   /// FP32 denormal mode.
1028   uint32_t fpDenormModeSPValue() const {
1029     if (FP32InputDenormals && FP32OutputDenormals)
1030       return FP_DENORM_FLUSH_NONE;
1031     if (FP32InputDenormals)
1032       return FP_DENORM_FLUSH_OUT;
1033     if (FP32OutputDenormals)
1034       return FP_DENORM_FLUSH_IN;
1035     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
1036   }
1037 
1038   /// Get the encoding value for the FP_DENORM bits of the mode register for the
1039   /// FP64/FP16 denormal mode.
1040   uint32_t fpDenormModeDPValue() const {
1041     if (FP64FP16InputDenormals && FP64FP16OutputDenormals)
1042       return FP_DENORM_FLUSH_NONE;
1043     if (FP64FP16InputDenormals)
1044       return FP_DENORM_FLUSH_OUT;
1045     if (FP64FP16OutputDenormals)
1046       return FP_DENORM_FLUSH_IN;
1047     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
1048   }
1049 
1050   /// Returns true if a flag is compatible if it's enabled in the callee, but
1051   /// disabled in the caller.
1052   static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
1053     return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
1054   }
1055 
1056   // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
1057   // be able to override.
1058   bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
1059     if (DX10Clamp != CalleeMode.DX10Clamp)
1060       return false;
1061     if (IEEE != CalleeMode.IEEE)
1062       return false;
1063 
1064     // Allow inlining denormals enabled into denormals flushed functions.
1065     return oneWayCompatible(FP64FP16InputDenormals, CalleeMode.FP64FP16InputDenormals) &&
1066            oneWayCompatible(FP64FP16OutputDenormals, CalleeMode.FP64FP16OutputDenormals) &&
1067            oneWayCompatible(FP32InputDenormals, CalleeMode.FP32InputDenormals) &&
1068            oneWayCompatible(FP32OutputDenormals, CalleeMode.FP32OutputDenormals);
1069   }
1070 };
1071 
1072 } // end namespace AMDGPU
1073 
1074 raw_ostream &operator<<(raw_ostream &OS,
1075                         const AMDGPU::IsaInfo::TargetIDSetting S);
1076 
1077 } // end namespace llvm
1078 
1079 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
1080