1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "SIDefines.h"
13 #include "llvm/IR/CallingConv.h"
14 #include "llvm/Support/Alignment.h"
15 
16 struct amd_kernel_code_t;
17 
18 namespace llvm {
19 
20 struct Align;
21 class Argument;
22 class Function;
23 class GCNSubtarget;
24 class GlobalValue;
25 class MCRegisterClass;
26 class MCRegisterInfo;
27 class MCSubtargetInfo;
28 class StringRef;
29 class Triple;
30 
31 namespace amdhsa {
32 struct kernel_descriptor_t;
33 }
34 
35 namespace AMDGPU {
36 
37 struct IsaVersion;
38 
39 /// \returns HSA OS ABI Version identification.
40 Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
41 /// \returns True if HSA OS ABI Version identification is 2,
42 /// false otherwise.
43 bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
44 /// \returns True if HSA OS ABI Version identification is 3,
45 /// false otherwise.
46 bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
47 /// \returns True if HSA OS ABI Version identification is 4,
48 /// false otherwise.
49 bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
50 /// \returns True if HSA OS ABI Version identification is 5,
51 /// false otherwise.
52 bool isHsaAbiVersion5(const MCSubtargetInfo *STI);
53 /// \returns True if HSA OS ABI Version identification is 3 or 4,
54 /// false otherwise.
55 bool isHsaAbiVersion3AndAbove(const MCSubtargetInfo *STI);
56 
57 /// \returns The offset of the hostcall pointer argument from implicitarg_ptr
58 unsigned getHostcallImplicitArgPosition();
59 
60 struct GcnBufferFormatInfo {
61   unsigned Format;
62   unsigned BitsPerComp;
63   unsigned NumComponents;
64   unsigned NumFormat;
65   unsigned DataFormat;
66 };
67 
68 #define GET_MIMGBaseOpcode_DECL
69 #define GET_MIMGDim_DECL
70 #define GET_MIMGEncoding_DECL
71 #define GET_MIMGLZMapping_DECL
72 #define GET_MIMGMIPMapping_DECL
73 #define GET_MIMGBiASMapping_DECL
74 #include "AMDGPUGenSearchableTables.inc"
75 
76 namespace IsaInfo {
77 
78 enum {
79   // The closed Vulkan driver sets 96, which limits the wave count to 8 but
80   // doesn't spill SGPRs as much as when 80 is set.
81   FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
82   TRAP_NUM_SGPRS = 16
83 };
84 
85 enum class TargetIDSetting {
86   Unsupported,
87   Any,
88   Off,
89   On
90 };
91 
92 class AMDGPUTargetID {
93 private:
94   const MCSubtargetInfo &STI;
95   TargetIDSetting XnackSetting;
96   TargetIDSetting SramEccSetting;
97 
98 public:
99   explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
100   ~AMDGPUTargetID() = default;
101 
102   /// \return True if the current xnack setting is not "Unsupported".
103   bool isXnackSupported() const {
104     return XnackSetting != TargetIDSetting::Unsupported;
105   }
106 
107   /// \returns True if the current xnack setting is "On" or "Any".
108   bool isXnackOnOrAny() const {
109     return XnackSetting == TargetIDSetting::On ||
110         XnackSetting == TargetIDSetting::Any;
111   }
112 
113   /// \returns True if current xnack setting is "On" or "Off",
114   /// false otherwise.
115   bool isXnackOnOrOff() const {
116     return getXnackSetting() == TargetIDSetting::On ||
117         getXnackSetting() == TargetIDSetting::Off;
118   }
119 
120   /// \returns The current xnack TargetIDSetting, possible options are
121   /// "Unsupported", "Any", "Off", and "On".
122   TargetIDSetting getXnackSetting() const {
123     return XnackSetting;
124   }
125 
126   /// Sets xnack setting to \p NewXnackSetting.
127   void setXnackSetting(TargetIDSetting NewXnackSetting) {
128     XnackSetting = NewXnackSetting;
129   }
130 
131   /// \return True if the current sramecc setting is not "Unsupported".
132   bool isSramEccSupported() const {
133     return SramEccSetting != TargetIDSetting::Unsupported;
134   }
135 
136   /// \returns True if the current sramecc setting is "On" or "Any".
137   bool isSramEccOnOrAny() const {
138   return SramEccSetting == TargetIDSetting::On ||
139       SramEccSetting == TargetIDSetting::Any;
140   }
141 
142   /// \returns True if current sramecc setting is "On" or "Off",
143   /// false otherwise.
144   bool isSramEccOnOrOff() const {
145     return getSramEccSetting() == TargetIDSetting::On ||
146         getSramEccSetting() == TargetIDSetting::Off;
147   }
148 
149   /// \returns The current sramecc TargetIDSetting, possible options are
150   /// "Unsupported", "Any", "Off", and "On".
151   TargetIDSetting getSramEccSetting() const {
152     return SramEccSetting;
153   }
154 
155   /// Sets sramecc setting to \p NewSramEccSetting.
156   void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
157     SramEccSetting = NewSramEccSetting;
158   }
159 
160   void setTargetIDFromFeaturesString(StringRef FS);
161   void setTargetIDFromTargetIDStream(StringRef TargetID);
162 
163   /// \returns String representation of an object.
164   std::string toString() const;
165 };
166 
167 /// \returns Wavefront size for given subtarget \p STI.
168 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
169 
170 /// \returns Local memory size in bytes for given subtarget \p STI.
171 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
172 
173 /// \returns Number of execution units per compute unit for given subtarget \p
174 /// STI.
175 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
176 
177 /// \returns Maximum number of work groups per compute unit for given subtarget
178 /// \p STI and limited by given \p FlatWorkGroupSize.
179 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
180                                unsigned FlatWorkGroupSize);
181 
182 /// \returns Minimum number of waves per execution unit for given subtarget \p
183 /// STI.
184 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
185 
186 /// \returns Maximum number of waves per execution unit for given subtarget \p
187 /// STI without any kind of limitation.
188 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
189 
190 /// \returns Number of waves per execution unit required to support the given \p
191 /// FlatWorkGroupSize.
192 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
193                                    unsigned FlatWorkGroupSize);
194 
195 /// \returns Minimum flat work group size for given subtarget \p STI.
196 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
197 
198 /// \returns Maximum flat work group size for given subtarget \p STI.
199 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
200 
201 /// \returns Number of waves per work group for given subtarget \p STI and
202 /// \p FlatWorkGroupSize.
203 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
204                               unsigned FlatWorkGroupSize);
205 
206 /// \returns SGPR allocation granularity for given subtarget \p STI.
207 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
208 
209 /// \returns SGPR encoding granularity for given subtarget \p STI.
210 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
211 
212 /// \returns Total number of SGPRs for given subtarget \p STI.
213 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
214 
215 /// \returns Addressable number of SGPRs for given subtarget \p STI.
216 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
217 
218 /// \returns Minimum number of SGPRs that meets the given number of waves per
219 /// execution unit requirement for given subtarget \p STI.
220 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
221 
222 /// \returns Maximum number of SGPRs that meets the given number of waves per
223 /// execution unit requirement for given subtarget \p STI.
224 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
225                         bool Addressable);
226 
227 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
228 /// STI when the given special registers are used.
229 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
230                           bool FlatScrUsed, bool XNACKUsed);
231 
232 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
233 /// STI when the given special registers are used. XNACK is inferred from
234 /// \p STI.
235 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
236                           bool FlatScrUsed);
237 
238 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
239 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
240 /// register counts.
241 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
242 
243 /// \returns VGPR allocation granularity for given subtarget \p STI.
244 ///
245 /// For subtargets which support it, \p EnableWavefrontSize32 should match
246 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
247 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
248                              Optional<bool> EnableWavefrontSize32 = None);
249 
250 /// \returns VGPR encoding granularity for given subtarget \p STI.
251 ///
252 /// For subtargets which support it, \p EnableWavefrontSize32 should match
253 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
254 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
255                                 Optional<bool> EnableWavefrontSize32 = None);
256 
257 /// \returns Total number of VGPRs for given subtarget \p STI.
258 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
259 
260 /// \returns Addressable number of VGPRs for given subtarget \p STI.
261 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
262 
263 /// \returns Minimum number of VGPRs that meets given number of waves per
264 /// execution unit requirement for given subtarget \p STI.
265 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
266 
267 /// \returns Maximum number of VGPRs that meets given number of waves per
268 /// execution unit requirement for given subtarget \p STI.
269 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
270 
271 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
272 /// \p NumVGPRs are used.
273 ///
274 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
275 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
276 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
277                           Optional<bool> EnableWavefrontSize32 = None);
278 
279 } // end namespace IsaInfo
280 
281 LLVM_READONLY
282 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
283 
284 LLVM_READONLY
285 int getSOPPWithRelaxation(uint16_t Opcode);
286 
287 struct MIMGBaseOpcodeInfo {
288   MIMGBaseOpcode BaseOpcode;
289   bool Store;
290   bool Atomic;
291   bool AtomicX2;
292   bool Sampler;
293   bool Gather4;
294 
295   uint8_t NumExtraArgs;
296   bool Gradients;
297   bool G16;
298   bool Coordinates;
299   bool LodOrClampOrMip;
300   bool HasD16;
301   bool MSAA;
302   bool BVH;
303 };
304 
305 LLVM_READONLY
306 const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
307 
308 LLVM_READONLY
309 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
310 
311 struct MIMGDimInfo {
312   MIMGDim Dim;
313   uint8_t NumCoords;
314   uint8_t NumGradients;
315   bool MSAA;
316   bool DA;
317   uint8_t Encoding;
318   const char *AsmSuffix;
319 };
320 
321 LLVM_READONLY
322 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
323 
324 LLVM_READONLY
325 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
326 
327 LLVM_READONLY
328 const MIMGDimInfo *getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix);
329 
330 struct MIMGLZMappingInfo {
331   MIMGBaseOpcode L;
332   MIMGBaseOpcode LZ;
333 };
334 
335 struct MIMGMIPMappingInfo {
336   MIMGBaseOpcode MIP;
337   MIMGBaseOpcode NONMIP;
338 };
339 
340 struct MIMGBiasMappingInfo {
341   MIMGBaseOpcode Bias;
342   MIMGBaseOpcode NoBias;
343 };
344 
345 struct MIMGOffsetMappingInfo {
346   MIMGBaseOpcode Offset;
347   MIMGBaseOpcode NoOffset;
348 };
349 
350 struct MIMGG16MappingInfo {
351   MIMGBaseOpcode G;
352   MIMGBaseOpcode G16;
353 };
354 
355 LLVM_READONLY
356 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
357 
358 LLVM_READONLY
359 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
360 
361 LLVM_READONLY
362 const MIMGBiasMappingInfo *getMIMGBiasMappingInfo(unsigned Bias);
363 
364 LLVM_READONLY
365 const MIMGOffsetMappingInfo *getMIMGOffsetMappingInfo(unsigned Offset);
366 
367 LLVM_READONLY
368 const MIMGG16MappingInfo *getMIMGG16MappingInfo(unsigned G);
369 
370 LLVM_READONLY
371 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
372                   unsigned VDataDwords, unsigned VAddrDwords);
373 
374 LLVM_READONLY
375 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
376 
377 LLVM_READONLY
378 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
379                            const MIMGDimInfo *Dim, bool IsA16,
380                            bool IsG16Supported);
381 
382 struct MIMGInfo {
383   uint16_t Opcode;
384   uint16_t BaseOpcode;
385   uint8_t MIMGEncoding;
386   uint8_t VDataDwords;
387   uint8_t VAddrDwords;
388 };
389 
390 LLVM_READONLY
391 const MIMGInfo *getMIMGInfo(unsigned Opc);
392 
393 LLVM_READONLY
394 int getMTBUFBaseOpcode(unsigned Opc);
395 
396 LLVM_READONLY
397 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
398 
399 LLVM_READONLY
400 int getMTBUFElements(unsigned Opc);
401 
402 LLVM_READONLY
403 bool getMTBUFHasVAddr(unsigned Opc);
404 
405 LLVM_READONLY
406 bool getMTBUFHasSrsrc(unsigned Opc);
407 
408 LLVM_READONLY
409 bool getMTBUFHasSoffset(unsigned Opc);
410 
411 LLVM_READONLY
412 int getMUBUFBaseOpcode(unsigned Opc);
413 
414 LLVM_READONLY
415 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
416 
417 LLVM_READONLY
418 int getMUBUFElements(unsigned Opc);
419 
420 LLVM_READONLY
421 bool getMUBUFHasVAddr(unsigned Opc);
422 
423 LLVM_READONLY
424 bool getMUBUFHasSrsrc(unsigned Opc);
425 
426 LLVM_READONLY
427 bool getMUBUFHasSoffset(unsigned Opc);
428 
429 LLVM_READONLY
430 bool getMUBUFIsBufferInv(unsigned Opc);
431 
432 LLVM_READONLY
433 bool getSMEMIsBuffer(unsigned Opc);
434 
435 LLVM_READONLY
436 bool getVOP1IsSingle(unsigned Opc);
437 
438 LLVM_READONLY
439 bool getVOP2IsSingle(unsigned Opc);
440 
441 LLVM_READONLY
442 bool getVOP3IsSingle(unsigned Opc);
443 
444 LLVM_READONLY
445 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
446                                                   uint8_t NumComponents,
447                                                   uint8_t NumFormat,
448                                                   const MCSubtargetInfo &STI);
449 LLVM_READONLY
450 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
451                                                   const MCSubtargetInfo &STI);
452 
453 LLVM_READONLY
454 int getMCOpcode(uint16_t Opcode, unsigned Gen);
455 
456 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
457                                const MCSubtargetInfo *STI);
458 
459 amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(
460     const MCSubtargetInfo *STI);
461 
462 bool isGroupSegment(const GlobalValue *GV);
463 bool isGlobalSegment(const GlobalValue *GV);
464 bool isReadOnlySegment(const GlobalValue *GV);
465 
466 /// \returns True if constants should be emitted to .text section for given
467 /// target triple \p TT, false otherwise.
468 bool shouldEmitConstantsToTextSection(const Triple &TT);
469 
470 /// \returns Integer value requested using \p F's \p Name attribute.
471 ///
472 /// \returns \p Default if attribute is not present.
473 ///
474 /// \returns \p Default and emits error if requested value cannot be converted
475 /// to integer.
476 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
477 
478 /// \returns A pair of integer values requested using \p F's \p Name attribute
479 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
480 /// is false).
481 ///
482 /// \returns \p Default if attribute is not present.
483 ///
484 /// \returns \p Default and emits error if one of the requested values cannot be
485 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
486 /// not present.
487 std::pair<int, int> getIntegerPairAttribute(const Function &F,
488                                             StringRef Name,
489                                             std::pair<int, int> Default,
490                                             bool OnlyFirstRequired = false);
491 
492 /// Represents the counter values to wait for in an s_waitcnt instruction.
493 ///
494 /// Large values (including the maximum possible integer) can be used to
495 /// represent "don't care" waits.
496 struct Waitcnt {
497   unsigned VmCnt = ~0u;
498   unsigned ExpCnt = ~0u;
499   unsigned LgkmCnt = ~0u;
500   unsigned VsCnt = ~0u;
501 
502   Waitcnt() = default;
503   Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
504       : VmCnt(VmCnt), ExpCnt(ExpCnt), LgkmCnt(LgkmCnt), VsCnt(VsCnt) {}
505 
506   static Waitcnt allZero(bool HasVscnt) {
507     return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
508   }
509   static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
510 
511   bool hasWait() const {
512     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
513   }
514 
515   bool hasWaitExceptVsCnt() const {
516     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u;
517   }
518 
519   bool hasWaitVsCnt() const {
520     return VsCnt != ~0u;
521   }
522 
523   bool dominates(const Waitcnt &Other) const {
524     return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
525            LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
526   }
527 
528   Waitcnt combined(const Waitcnt &Other) const {
529     return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
530                    std::min(LgkmCnt, Other.LgkmCnt),
531                    std::min(VsCnt, Other.VsCnt));
532   }
533 };
534 
535 /// \returns Vmcnt bit mask for given isa \p Version.
536 unsigned getVmcntBitMask(const IsaVersion &Version);
537 
538 /// \returns Expcnt bit mask for given isa \p Version.
539 unsigned getExpcntBitMask(const IsaVersion &Version);
540 
541 /// \returns Lgkmcnt bit mask for given isa \p Version.
542 unsigned getLgkmcntBitMask(const IsaVersion &Version);
543 
544 /// \returns Waitcnt bit mask for given isa \p Version.
545 unsigned getWaitcntBitMask(const IsaVersion &Version);
546 
547 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
548 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
549 
550 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
551 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
552 
553 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
554 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
555 
556 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
557 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
558 /// \p Lgkmcnt respectively.
559 ///
560 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
561 ///     \p Vmcnt = \p Waitcnt[3:0]                      (pre-gfx9 only)
562 ///     \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14]  (gfx9+ only)
563 ///     \p Expcnt = \p Waitcnt[6:4]
564 ///     \p Lgkmcnt = \p Waitcnt[11:8]                   (pre-gfx10 only)
565 ///     \p Lgkmcnt = \p Waitcnt[13:8]                   (gfx10+ only)
566 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
567                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
568 
569 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
570 
571 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
572 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
573                      unsigned Vmcnt);
574 
575 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
576 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
577                       unsigned Expcnt);
578 
579 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
580 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
581                        unsigned Lgkmcnt);
582 
583 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
584 /// \p Version.
585 ///
586 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
587 ///     Waitcnt[3:0]   = \p Vmcnt       (pre-gfx9 only)
588 ///     Waitcnt[3:0]   = \p Vmcnt[3:0]  (gfx9+ only)
589 ///     Waitcnt[6:4]   = \p Expcnt
590 ///     Waitcnt[11:8]  = \p Lgkmcnt     (pre-gfx10 only)
591 ///     Waitcnt[13:8]  = \p Lgkmcnt     (gfx10+ only)
592 ///     Waitcnt[15:14] = \p Vmcnt[5:4]  (gfx9+ only)
593 ///
594 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
595 /// isa \p Version.
596 unsigned encodeWaitcnt(const IsaVersion &Version,
597                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
598 
599 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
600 
601 namespace Hwreg {
602 
603 LLVM_READONLY
604 int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI);
605 
606 LLVM_READNONE
607 bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI);
608 
609 LLVM_READNONE
610 bool isValidHwreg(int64_t Id);
611 
612 LLVM_READNONE
613 bool isValidHwregOffset(int64_t Offset);
614 
615 LLVM_READNONE
616 bool isValidHwregWidth(int64_t Width);
617 
618 LLVM_READNONE
619 uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
620 
621 LLVM_READNONE
622 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
623 
624 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
625 
626 } // namespace Hwreg
627 
628 namespace Exp {
629 
630 bool getTgtName(unsigned Id, StringRef &Name, int &Index);
631 
632 LLVM_READONLY
633 unsigned getTgtId(const StringRef Name);
634 
635 LLVM_READNONE
636 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
637 
638 } // namespace Exp
639 
640 namespace MTBUFFormat {
641 
642 LLVM_READNONE
643 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
644 
645 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
646 
647 int64_t getDfmt(const StringRef Name);
648 
649 StringRef getDfmtName(unsigned Id);
650 
651 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
652 
653 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
654 
655 bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
656 
657 bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
658 
659 int64_t getUnifiedFormat(const StringRef Name);
660 
661 StringRef getUnifiedFormatName(unsigned Id);
662 
663 bool isValidUnifiedFormat(unsigned Val);
664 
665 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt);
666 
667 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
668 
669 unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
670 
671 } // namespace MTBUFFormat
672 
673 namespace SendMsg {
674 
675 LLVM_READONLY
676 int64_t getMsgId(const StringRef Name);
677 
678 LLVM_READONLY
679 int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
680 
681 LLVM_READNONE
682 StringRef getMsgName(int64_t MsgId);
683 
684 LLVM_READNONE
685 StringRef getMsgOpName(int64_t MsgId, int64_t OpId);
686 
687 LLVM_READNONE
688 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict = true);
689 
690 LLVM_READNONE
691 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
692                   bool Strict = true);
693 
694 LLVM_READNONE
695 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
696                       const MCSubtargetInfo &STI, bool Strict = true);
697 
698 LLVM_READNONE
699 bool msgRequiresOp(int64_t MsgId);
700 
701 LLVM_READNONE
702 bool msgSupportsStream(int64_t MsgId, int64_t OpId);
703 
704 void decodeMsg(unsigned Val,
705                uint16_t &MsgId,
706                uint16_t &OpId,
707                uint16_t &StreamId);
708 
709 LLVM_READNONE
710 uint64_t encodeMsg(uint64_t MsgId,
711                    uint64_t OpId,
712                    uint64_t StreamId);
713 
714 } // namespace SendMsg
715 
716 
717 unsigned getInitialPSInputAddr(const Function &F);
718 
719 bool getHasColorExport(const Function &F);
720 
721 bool getHasDepthExport(const Function &F);
722 
723 LLVM_READNONE
724 bool isShader(CallingConv::ID CC);
725 
726 LLVM_READNONE
727 bool isGraphics(CallingConv::ID CC);
728 
729 LLVM_READNONE
730 bool isCompute(CallingConv::ID CC);
731 
732 LLVM_READNONE
733 bool isEntryFunctionCC(CallingConv::ID CC);
734 
735 // These functions are considered entrypoints into the current module, i.e. they
736 // are allowed to be called from outside the current module. This is different
737 // from isEntryFunctionCC, which is only true for functions that are entered by
738 // the hardware. Module entry points include all entry functions but also
739 // include functions that can be called from other functions inside or outside
740 // the current module. Module entry functions are allowed to allocate LDS.
741 LLVM_READNONE
742 bool isModuleEntryFunctionCC(CallingConv::ID CC);
743 
744 bool isKernelCC(const Function *Func);
745 
746 // FIXME: Remove this when calling conventions cleaned up
747 LLVM_READNONE
748 inline bool isKernel(CallingConv::ID CC) {
749   switch (CC) {
750   case CallingConv::AMDGPU_KERNEL:
751   case CallingConv::SPIR_KERNEL:
752     return true;
753   default:
754     return false;
755   }
756 }
757 
758 bool hasXNACK(const MCSubtargetInfo &STI);
759 bool hasSRAMECC(const MCSubtargetInfo &STI);
760 bool hasMIMG_R128(const MCSubtargetInfo &STI);
761 bool hasGFX10A16(const MCSubtargetInfo &STI);
762 bool hasG16(const MCSubtargetInfo &STI);
763 bool hasPackedD16(const MCSubtargetInfo &STI);
764 
765 bool isSI(const MCSubtargetInfo &STI);
766 bool isCI(const MCSubtargetInfo &STI);
767 bool isVI(const MCSubtargetInfo &STI);
768 bool isGFX9(const MCSubtargetInfo &STI);
769 bool isGFX9Plus(const MCSubtargetInfo &STI);
770 bool isGFX10(const MCSubtargetInfo &STI);
771 bool isGFX10Plus(const MCSubtargetInfo &STI);
772 bool isGCN3Encoding(const MCSubtargetInfo &STI);
773 bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
774 bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
775 bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
776 bool isGFX90A(const MCSubtargetInfo &STI);
777 bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI);
778 
779 /// Is Reg - scalar register
780 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
781 
782 /// If \p Reg is a pseudo reg, return the correct hardware register given
783 /// \p STI otherwise return \p Reg.
784 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
785 
786 /// Convert hardware register \p Reg to a pseudo register
787 LLVM_READNONE
788 unsigned mc2PseudoReg(unsigned Reg);
789 
790 /// Can this operand also contain immediate values?
791 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
792 
793 /// Is this floating-point operand?
794 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
795 
796 /// Does this operand support only inlinable literals?
797 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
798 
799 /// Get the size in bits of a register from the register class \p RC.
800 unsigned getRegBitWidth(unsigned RCID);
801 
802 /// Get the size in bits of a register from the register class \p RC.
803 unsigned getRegBitWidth(const MCRegisterClass &RC);
804 
805 /// Get size of register operand
806 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
807                            unsigned OpNo);
808 
809 LLVM_READNONE
810 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
811   switch (OpInfo.OperandType) {
812   case AMDGPU::OPERAND_REG_IMM_INT32:
813   case AMDGPU::OPERAND_REG_IMM_FP32:
814   case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
815   case AMDGPU::OPERAND_REG_INLINE_C_INT32:
816   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
817   case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
818   case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
819   case AMDGPU::OPERAND_REG_IMM_V2INT32:
820   case AMDGPU::OPERAND_REG_IMM_V2FP32:
821   case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
822   case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
823   case AMDGPU::OPERAND_KIMM32:
824   case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 4
825     return 4;
826 
827   case AMDGPU::OPERAND_REG_IMM_INT64:
828   case AMDGPU::OPERAND_REG_IMM_FP64:
829   case AMDGPU::OPERAND_REG_INLINE_C_INT64:
830   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
831   case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
832     return 8;
833 
834   case AMDGPU::OPERAND_REG_IMM_INT16:
835   case AMDGPU::OPERAND_REG_IMM_FP16:
836   case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
837   case AMDGPU::OPERAND_REG_INLINE_C_INT16:
838   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
839   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
840   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
841   case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
842   case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
843   case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
844   case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
845   case AMDGPU::OPERAND_REG_IMM_V2INT16:
846   case AMDGPU::OPERAND_REG_IMM_V2FP16:
847     return 2;
848 
849   default:
850     llvm_unreachable("unhandled operand type");
851   }
852 }
853 
854 LLVM_READNONE
855 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
856   return getOperandSize(Desc.OpInfo[OpNo]);
857 }
858 
859 /// Is this literal inlinable, and not one of the values intended for floating
860 /// point values.
861 LLVM_READNONE
862 inline bool isInlinableIntLiteral(int64_t Literal) {
863   return Literal >= -16 && Literal <= 64;
864 }
865 
866 /// Is this literal inlinable
867 LLVM_READNONE
868 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
869 
870 LLVM_READNONE
871 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
872 
873 LLVM_READNONE
874 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
875 
876 LLVM_READNONE
877 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
878 
879 LLVM_READNONE
880 bool isInlinableIntLiteralV216(int32_t Literal);
881 
882 LLVM_READNONE
883 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
884 
885 bool isArgPassedInSGPR(const Argument *Arg);
886 
887 LLVM_READONLY
888 bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
889                                       int64_t EncodedOffset);
890 
891 LLVM_READONLY
892 bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,
893                                     int64_t EncodedOffset,
894                                     bool IsBuffer);
895 
896 /// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
897 /// offsets.
898 uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
899 
900 /// \returns The encoding that will be used for \p ByteOffset in the
901 /// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
902 /// S_LOAD instructions have a signed offset, on other subtargets it is
903 /// unsigned. S_BUFFER has an unsigned offset for all subtargets.
904 Optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
905                                        int64_t ByteOffset, bool IsBuffer);
906 
907 /// \return The encoding that can be used for a 32-bit literal offset in an SMRD
908 /// instruction. This is only useful on CI.s
909 Optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
910                                                 int64_t ByteOffset);
911 
912 /// For FLAT segment the offset must be positive;
913 /// MSB is ignored and forced to zero.
914 ///
915 /// \return The number of bits available for the offset field in flat
916 /// instructions.
917 unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed);
918 
919 /// \returns true if this offset is small enough to fit in the SMRD
920 /// offset field.  \p ByteOffset should be the offset in bytes and
921 /// not the encoded offset.
922 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
923 
924 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
925                       const GCNSubtarget *Subtarget,
926                       Align Alignment = Align(4));
927 
928 LLVM_READNONE
929 inline bool isLegal64BitDPPControl(unsigned DC) {
930   return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
931 }
932 
933 /// \returns true if the intrinsic is divergent
934 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
935 
936 // Track defaults for fields in the MODE registser.
937 struct SIModeRegisterDefaults {
938   /// Floating point opcodes that support exception flag gathering quiet and
939   /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
940   /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
941   /// quieting.
942   bool IEEE : 1;
943 
944   /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
945   /// clamp NaN to zero; otherwise, pass NaN through.
946   bool DX10Clamp : 1;
947 
948   /// If this is set, neither input or output denormals are flushed for most f32
949   /// instructions.
950   bool FP32InputDenormals : 1;
951   bool FP32OutputDenormals : 1;
952 
953   /// If this is set, neither input or output denormals are flushed for both f64
954   /// and f16/v2f16 instructions.
955   bool FP64FP16InputDenormals : 1;
956   bool FP64FP16OutputDenormals : 1;
957 
958   SIModeRegisterDefaults() :
959     IEEE(true),
960     DX10Clamp(true),
961     FP32InputDenormals(true),
962     FP32OutputDenormals(true),
963     FP64FP16InputDenormals(true),
964     FP64FP16OutputDenormals(true) {}
965 
966   SIModeRegisterDefaults(const Function &F);
967 
968   static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) {
969     SIModeRegisterDefaults Mode;
970     Mode.IEEE = !AMDGPU::isShader(CC);
971     return Mode;
972   }
973 
974   bool operator ==(const SIModeRegisterDefaults Other) const {
975     return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
976            FP32InputDenormals == Other.FP32InputDenormals &&
977            FP32OutputDenormals == Other.FP32OutputDenormals &&
978            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
979            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
980   }
981 
982   bool allFP32Denormals() const {
983     return FP32InputDenormals && FP32OutputDenormals;
984   }
985 
986   bool allFP64FP16Denormals() const {
987     return FP64FP16InputDenormals && FP64FP16OutputDenormals;
988   }
989 
990   /// Get the encoding value for the FP_DENORM bits of the mode register for the
991   /// FP32 denormal mode.
992   uint32_t fpDenormModeSPValue() const {
993     if (FP32InputDenormals && FP32OutputDenormals)
994       return FP_DENORM_FLUSH_NONE;
995     if (FP32InputDenormals)
996       return FP_DENORM_FLUSH_OUT;
997     if (FP32OutputDenormals)
998       return FP_DENORM_FLUSH_IN;
999     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
1000   }
1001 
1002   /// Get the encoding value for the FP_DENORM bits of the mode register for the
1003   /// FP64/FP16 denormal mode.
1004   uint32_t fpDenormModeDPValue() const {
1005     if (FP64FP16InputDenormals && FP64FP16OutputDenormals)
1006       return FP_DENORM_FLUSH_NONE;
1007     if (FP64FP16InputDenormals)
1008       return FP_DENORM_FLUSH_OUT;
1009     if (FP64FP16OutputDenormals)
1010       return FP_DENORM_FLUSH_IN;
1011     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
1012   }
1013 
1014   /// Returns true if a flag is compatible if it's enabled in the callee, but
1015   /// disabled in the caller.
1016   static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
1017     return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
1018   }
1019 
1020   // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
1021   // be able to override.
1022   bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
1023     if (DX10Clamp != CalleeMode.DX10Clamp)
1024       return false;
1025     if (IEEE != CalleeMode.IEEE)
1026       return false;
1027 
1028     // Allow inlining denormals enabled into denormals flushed functions.
1029     return oneWayCompatible(FP64FP16InputDenormals, CalleeMode.FP64FP16InputDenormals) &&
1030            oneWayCompatible(FP64FP16OutputDenormals, CalleeMode.FP64FP16OutputDenormals) &&
1031            oneWayCompatible(FP32InputDenormals, CalleeMode.FP32InputDenormals) &&
1032            oneWayCompatible(FP32OutputDenormals, CalleeMode.FP32OutputDenormals);
1033   }
1034 };
1035 
1036 } // end namespace AMDGPU
1037 
1038 raw_ostream &operator<<(raw_ostream &OS,
1039                         const AMDGPU::IsaInfo::TargetIDSetting S);
1040 
1041 } // end namespace llvm
1042 
1043 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
1044