1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "AMDGPU.h"
13 #include "AMDKernelCodeT.h"
14 #include "SIDefines.h"
15 #include "llvm/IR/CallingConv.h"
16 #include "llvm/MC/MCInstrDesc.h"
17 #include "llvm/Support/AMDHSAKernelDescriptor.h"
18 #include "llvm/Support/Compiler.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/TargetParser.h"
21 #include <cstdint>
22 #include <string>
23 #include <utility>
24 
25 namespace llvm {
26 
27 class Argument;
28 class Function;
29 class GCNSubtarget;
30 class GlobalValue;
31 class MCRegisterClass;
32 class MCRegisterInfo;
33 class MCSubtargetInfo;
34 class StringRef;
35 class Triple;
36 
37 namespace AMDGPU {
38 
39 struct GcnBufferFormatInfo {
40   unsigned Format;
41   unsigned BitsPerComp;
42   unsigned NumComponents;
43   unsigned NumFormat;
44   unsigned DataFormat;
45 };
46 
47 #define GET_MIMGBaseOpcode_DECL
48 #define GET_MIMGDim_DECL
49 #define GET_MIMGEncoding_DECL
50 #define GET_MIMGLZMapping_DECL
51 #define GET_MIMGMIPMapping_DECL
52 #include "AMDGPUGenSearchableTables.inc"
53 
54 namespace IsaInfo {
55 
56 enum {
57   // The closed Vulkan driver sets 96, which limits the wave count to 8 but
58   // doesn't spill SGPRs as much as when 80 is set.
59   FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
60   TRAP_NUM_SGPRS = 16
61 };
62 
63 /// Streams isa version string for given subtarget \p STI into \p Stream.
64 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream);
65 
66 /// \returns True if given subtarget \p STI supports code object version 3,
67 /// false otherwise.
68 bool hasCodeObjectV3(const MCSubtargetInfo *STI);
69 
70 /// \returns Wavefront size for given subtarget \p STI.
71 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
72 
73 /// \returns Local memory size in bytes for given subtarget \p STI.
74 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
75 
76 /// \returns Number of execution units per compute unit for given subtarget \p
77 /// STI.
78 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
79 
80 /// \returns Maximum number of work groups per compute unit for given subtarget
81 /// \p STI and limited by given \p FlatWorkGroupSize.
82 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
83                                unsigned FlatWorkGroupSize);
84 
85 /// \returns Minimum number of waves per execution unit for given subtarget \p
86 /// STI.
87 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
88 
89 /// \returns Maximum number of waves per execution unit for given subtarget \p
90 /// STI without any kind of limitation.
91 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
92 
93 /// \returns Number of waves per execution unit required to support the given \p
94 /// FlatWorkGroupSize.
95 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
96                                    unsigned FlatWorkGroupSize);
97 
98 /// \returns Minimum flat work group size for given subtarget \p STI.
99 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
100 
101 /// \returns Maximum flat work group size for given subtarget \p STI.
102 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
103 
104 /// \returns Number of waves per work group for given subtarget \p STI and
105 /// \p FlatWorkGroupSize.
106 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
107                               unsigned FlatWorkGroupSize);
108 
109 /// \returns SGPR allocation granularity for given subtarget \p STI.
110 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
111 
112 /// \returns SGPR encoding granularity for given subtarget \p STI.
113 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
114 
115 /// \returns Total number of SGPRs for given subtarget \p STI.
116 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
117 
118 /// \returns Addressable number of SGPRs for given subtarget \p STI.
119 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
120 
121 /// \returns Minimum number of SGPRs that meets the given number of waves per
122 /// execution unit requirement for given subtarget \p STI.
123 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
124 
125 /// \returns Maximum number of SGPRs that meets the given number of waves per
126 /// execution unit requirement for given subtarget \p STI.
127 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
128                         bool Addressable);
129 
130 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
131 /// STI when the given special registers are used.
132 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
133                           bool FlatScrUsed, bool XNACKUsed);
134 
135 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
136 /// STI when the given special registers are used. XNACK is inferred from
137 /// \p STI.
138 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
139                           bool FlatScrUsed);
140 
141 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
142 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
143 /// register counts.
144 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
145 
146 /// \returns VGPR allocation granularity for given subtarget \p STI.
147 ///
148 /// For subtargets which support it, \p EnableWavefrontSize32 should match
149 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
150 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
151                              Optional<bool> EnableWavefrontSize32 = None);
152 
153 /// \returns VGPR encoding granularity for given subtarget \p STI.
154 ///
155 /// For subtargets which support it, \p EnableWavefrontSize32 should match
156 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
157 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
158                                 Optional<bool> EnableWavefrontSize32 = None);
159 
160 /// \returns Total number of VGPRs for given subtarget \p STI.
161 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
162 
163 /// \returns Addressable number of VGPRs for given subtarget \p STI.
164 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
165 
166 /// \returns Minimum number of VGPRs that meets given number of waves per
167 /// execution unit requirement for given subtarget \p STI.
168 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
169 
170 /// \returns Maximum number of VGPRs that meets given number of waves per
171 /// execution unit requirement for given subtarget \p STI.
172 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
173 
174 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
175 /// \p NumVGPRs are used.
176 ///
177 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
178 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
179 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
180                           Optional<bool> EnableWavefrontSize32 = None);
181 
182 } // end namespace IsaInfo
183 
184 LLVM_READONLY
185 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
186 
187 LLVM_READONLY
188 int getSOPPWithRelaxation(uint16_t Opcode);
189 
190 struct MIMGBaseOpcodeInfo {
191   MIMGBaseOpcode BaseOpcode;
192   bool Store;
193   bool Atomic;
194   bool AtomicX2;
195   bool Sampler;
196   bool Gather4;
197 
198   uint8_t NumExtraArgs;
199   bool Gradients;
200   bool G16;
201   bool Coordinates;
202   bool LodOrClampOrMip;
203   bool HasD16;
204 };
205 
206 LLVM_READONLY
207 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
208 
209 struct MIMGDimInfo {
210   MIMGDim Dim;
211   uint8_t NumCoords;
212   uint8_t NumGradients;
213   bool DA;
214   uint8_t Encoding;
215   const char *AsmSuffix;
216 };
217 
218 LLVM_READONLY
219 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
220 
221 LLVM_READONLY
222 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
223 
224 LLVM_READONLY
225 const MIMGDimInfo *getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix);
226 
227 struct MIMGLZMappingInfo {
228   MIMGBaseOpcode L;
229   MIMGBaseOpcode LZ;
230 };
231 
232 struct MIMGMIPMappingInfo {
233   MIMGBaseOpcode MIP;
234   MIMGBaseOpcode NONMIP;
235 };
236 
237 struct MIMGG16MappingInfo {
238   MIMGBaseOpcode G;
239   MIMGBaseOpcode G16;
240 };
241 
242 LLVM_READONLY
243 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
244 
245 LLVM_READONLY
246 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
247 
248 LLVM_READONLY
249 const MIMGG16MappingInfo *getMIMGG16MappingInfo(unsigned G);
250 
251 LLVM_READONLY
252 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
253                   unsigned VDataDwords, unsigned VAddrDwords);
254 
255 LLVM_READONLY
256 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
257 
258 struct MIMGInfo {
259   uint16_t Opcode;
260   uint16_t BaseOpcode;
261   uint8_t MIMGEncoding;
262   uint8_t VDataDwords;
263   uint8_t VAddrDwords;
264 };
265 
266 LLVM_READONLY
267 const MIMGInfo *getMIMGInfo(unsigned Opc);
268 
269 LLVM_READONLY
270 int getMTBUFBaseOpcode(unsigned Opc);
271 
272 LLVM_READONLY
273 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
274 
275 LLVM_READONLY
276 int getMTBUFElements(unsigned Opc);
277 
278 LLVM_READONLY
279 bool getMTBUFHasVAddr(unsigned Opc);
280 
281 LLVM_READONLY
282 bool getMTBUFHasSrsrc(unsigned Opc);
283 
284 LLVM_READONLY
285 bool getMTBUFHasSoffset(unsigned Opc);
286 
287 LLVM_READONLY
288 int getMUBUFBaseOpcode(unsigned Opc);
289 
290 LLVM_READONLY
291 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
292 
293 LLVM_READONLY
294 int getMUBUFElements(unsigned Opc);
295 
296 LLVM_READONLY
297 bool getMUBUFHasVAddr(unsigned Opc);
298 
299 LLVM_READONLY
300 bool getMUBUFHasSrsrc(unsigned Opc);
301 
302 LLVM_READONLY
303 bool getMUBUFHasSoffset(unsigned Opc);
304 
305 LLVM_READONLY
306 bool getSMEMIsBuffer(unsigned Opc);
307 
308 LLVM_READONLY
309 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
310                                                   uint8_t NumComponents,
311                                                   uint8_t NumFormat,
312                                                   const MCSubtargetInfo &STI);
313 LLVM_READONLY
314 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
315                                                   const MCSubtargetInfo &STI);
316 
317 LLVM_READONLY
318 int getMCOpcode(uint16_t Opcode, unsigned Gen);
319 
320 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
321                                const MCSubtargetInfo *STI);
322 
323 amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(
324     const MCSubtargetInfo *STI);
325 
326 bool isGroupSegment(const GlobalValue *GV);
327 bool isGlobalSegment(const GlobalValue *GV);
328 bool isReadOnlySegment(const GlobalValue *GV);
329 
330 /// \returns True if constants should be emitted to .text section for given
331 /// target triple \p TT, false otherwise.
332 bool shouldEmitConstantsToTextSection(const Triple &TT);
333 
334 /// \returns Integer value requested using \p F's \p Name attribute.
335 ///
336 /// \returns \p Default if attribute is not present.
337 ///
338 /// \returns \p Default and emits error if requested value cannot be converted
339 /// to integer.
340 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
341 
342 /// \returns A pair of integer values requested using \p F's \p Name attribute
343 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
344 /// is false).
345 ///
346 /// \returns \p Default if attribute is not present.
347 ///
348 /// \returns \p Default and emits error if one of the requested values cannot be
349 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
350 /// not present.
351 std::pair<int, int> getIntegerPairAttribute(const Function &F,
352                                             StringRef Name,
353                                             std::pair<int, int> Default,
354                                             bool OnlyFirstRequired = false);
355 
356 /// Represents the counter values to wait for in an s_waitcnt instruction.
357 ///
358 /// Large values (including the maximum possible integer) can be used to
359 /// represent "don't care" waits.
360 struct Waitcnt {
361   unsigned VmCnt = ~0u;
362   unsigned ExpCnt = ~0u;
363   unsigned LgkmCnt = ~0u;
364   unsigned VsCnt = ~0u;
365 
366   Waitcnt() {}
367   Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
368       : VmCnt(VmCnt), ExpCnt(ExpCnt), LgkmCnt(LgkmCnt), VsCnt(VsCnt) {}
369 
370   static Waitcnt allZero(const IsaVersion &Version) {
371     return Waitcnt(0, 0, 0, Version.Major >= 10 ? 0 : ~0u);
372   }
373   static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
374 
375   bool hasWait() const {
376     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
377   }
378 
379   bool dominates(const Waitcnt &Other) const {
380     return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
381            LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
382   }
383 
384   Waitcnt combined(const Waitcnt &Other) const {
385     return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
386                    std::min(LgkmCnt, Other.LgkmCnt),
387                    std::min(VsCnt, Other.VsCnt));
388   }
389 };
390 
391 /// \returns Vmcnt bit mask for given isa \p Version.
392 unsigned getVmcntBitMask(const IsaVersion &Version);
393 
394 /// \returns Expcnt bit mask for given isa \p Version.
395 unsigned getExpcntBitMask(const IsaVersion &Version);
396 
397 /// \returns Lgkmcnt bit mask for given isa \p Version.
398 unsigned getLgkmcntBitMask(const IsaVersion &Version);
399 
400 /// \returns Waitcnt bit mask for given isa \p Version.
401 unsigned getWaitcntBitMask(const IsaVersion &Version);
402 
403 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
404 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
405 
406 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
407 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
408 
409 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
410 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
411 
412 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
413 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
414 /// \p Lgkmcnt respectively.
415 ///
416 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
417 ///     \p Vmcnt = \p Waitcnt[3:0]                      (pre-gfx9 only)
418 ///     \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14]  (gfx9+ only)
419 ///     \p Expcnt = \p Waitcnt[6:4]
420 ///     \p Lgkmcnt = \p Waitcnt[11:8]                   (pre-gfx10 only)
421 ///     \p Lgkmcnt = \p Waitcnt[13:8]                   (gfx10+ only)
422 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
423                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
424 
425 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
426 
427 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
428 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
429                      unsigned Vmcnt);
430 
431 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
432 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
433                       unsigned Expcnt);
434 
435 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
436 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
437                        unsigned Lgkmcnt);
438 
439 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
440 /// \p Version.
441 ///
442 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
443 ///     Waitcnt[3:0]   = \p Vmcnt       (pre-gfx9 only)
444 ///     Waitcnt[3:0]   = \p Vmcnt[3:0]  (gfx9+ only)
445 ///     Waitcnt[6:4]   = \p Expcnt
446 ///     Waitcnt[11:8]  = \p Lgkmcnt     (pre-gfx10 only)
447 ///     Waitcnt[13:8]  = \p Lgkmcnt     (gfx10+ only)
448 ///     Waitcnt[15:14] = \p Vmcnt[5:4]  (gfx9+ only)
449 ///
450 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
451 /// isa \p Version.
452 unsigned encodeWaitcnt(const IsaVersion &Version,
453                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
454 
455 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
456 
457 namespace Hwreg {
458 
459 LLVM_READONLY
460 int64_t getHwregId(const StringRef Name);
461 
462 LLVM_READNONE
463 bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI);
464 
465 LLVM_READNONE
466 bool isValidHwreg(int64_t Id);
467 
468 LLVM_READNONE
469 bool isValidHwregOffset(int64_t Offset);
470 
471 LLVM_READNONE
472 bool isValidHwregWidth(int64_t Width);
473 
474 LLVM_READNONE
475 uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
476 
477 LLVM_READNONE
478 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
479 
480 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
481 
482 } // namespace Hwreg
483 
484 namespace SendMsg {
485 
486 LLVM_READONLY
487 int64_t getMsgId(const StringRef Name);
488 
489 LLVM_READONLY
490 int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
491 
492 LLVM_READNONE
493 StringRef getMsgName(int64_t MsgId);
494 
495 LLVM_READNONE
496 StringRef getMsgOpName(int64_t MsgId, int64_t OpId);
497 
498 LLVM_READNONE
499 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict = true);
500 
501 LLVM_READNONE
502 bool isValidMsgOp(int64_t MsgId, int64_t OpId, bool Strict = true);
503 
504 LLVM_READNONE
505 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, bool Strict = true);
506 
507 LLVM_READNONE
508 bool msgRequiresOp(int64_t MsgId);
509 
510 LLVM_READNONE
511 bool msgSupportsStream(int64_t MsgId, int64_t OpId);
512 
513 void decodeMsg(unsigned Val,
514                uint16_t &MsgId,
515                uint16_t &OpId,
516                uint16_t &StreamId);
517 
518 LLVM_READNONE
519 uint64_t encodeMsg(uint64_t MsgId,
520                    uint64_t OpId,
521                    uint64_t StreamId);
522 
523 } // namespace SendMsg
524 
525 
526 unsigned getInitialPSInputAddr(const Function &F);
527 
528 LLVM_READNONE
529 bool isShader(CallingConv::ID CC);
530 
531 LLVM_READNONE
532 bool isCompute(CallingConv::ID CC);
533 
534 LLVM_READNONE
535 bool isEntryFunctionCC(CallingConv::ID CC);
536 
537 // FIXME: Remove this when calling conventions cleaned up
538 LLVM_READNONE
539 inline bool isKernel(CallingConv::ID CC) {
540   switch (CC) {
541   case CallingConv::AMDGPU_KERNEL:
542   case CallingConv::SPIR_KERNEL:
543     return true;
544   default:
545     return false;
546   }
547 }
548 
549 bool hasXNACK(const MCSubtargetInfo &STI);
550 bool hasSRAMECC(const MCSubtargetInfo &STI);
551 bool hasMIMG_R128(const MCSubtargetInfo &STI);
552 bool hasGFX10A16(const MCSubtargetInfo &STI);
553 bool hasG16(const MCSubtargetInfo &STI);
554 bool hasPackedD16(const MCSubtargetInfo &STI);
555 
556 bool isSI(const MCSubtargetInfo &STI);
557 bool isCI(const MCSubtargetInfo &STI);
558 bool isVI(const MCSubtargetInfo &STI);
559 bool isGFX9(const MCSubtargetInfo &STI);
560 bool isGFX10(const MCSubtargetInfo &STI);
561 
562 /// Is Reg - scalar register
563 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
564 
565 /// Is there any intersection between registers
566 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
567 
568 /// If \p Reg is a pseudo reg, return the correct hardware register given
569 /// \p STI otherwise return \p Reg.
570 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
571 
572 /// Convert hardware register \p Reg to a pseudo register
573 LLVM_READNONE
574 unsigned mc2PseudoReg(unsigned Reg);
575 
576 /// Can this operand also contain immediate values?
577 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
578 
579 /// Is this floating-point operand?
580 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
581 
582 /// Does this opearnd support only inlinable literals?
583 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
584 
585 /// Get the size in bits of a register from the register class \p RC.
586 unsigned getRegBitWidth(unsigned RCID);
587 
588 /// Get the size in bits of a register from the register class \p RC.
589 unsigned getRegBitWidth(const MCRegisterClass &RC);
590 
591 /// Get size of register operand
592 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
593                            unsigned OpNo);
594 
595 LLVM_READNONE
596 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
597   switch (OpInfo.OperandType) {
598   case AMDGPU::OPERAND_REG_IMM_INT32:
599   case AMDGPU::OPERAND_REG_IMM_FP32:
600   case AMDGPU::OPERAND_REG_INLINE_C_INT32:
601   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
602   case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
603   case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
604     return 4;
605 
606   case AMDGPU::OPERAND_REG_IMM_INT64:
607   case AMDGPU::OPERAND_REG_IMM_FP64:
608   case AMDGPU::OPERAND_REG_INLINE_C_INT64:
609   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
610     return 8;
611 
612   case AMDGPU::OPERAND_REG_IMM_INT16:
613   case AMDGPU::OPERAND_REG_IMM_FP16:
614   case AMDGPU::OPERAND_REG_INLINE_C_INT16:
615   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
616   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
617   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
618   case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
619   case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
620   case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
621   case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
622   case AMDGPU::OPERAND_REG_IMM_V2INT16:
623   case AMDGPU::OPERAND_REG_IMM_V2FP16:
624     return 2;
625 
626   default:
627     llvm_unreachable("unhandled operand type");
628   }
629 }
630 
631 LLVM_READNONE
632 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
633   return getOperandSize(Desc.OpInfo[OpNo]);
634 }
635 
636 /// Is this literal inlinable
637 LLVM_READNONE
638 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
639 
640 LLVM_READNONE
641 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
642 
643 LLVM_READNONE
644 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
645 
646 LLVM_READNONE
647 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
648 
649 bool isArgPassedInSGPR(const Argument *Arg);
650 
651 LLVM_READONLY
652 bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
653                                       int64_t EncodedOffset);
654 
655 LLVM_READONLY
656 bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,
657                                     int64_t EncodedOffset,
658                                     bool IsBuffer);
659 
660 /// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
661 /// offsets.
662 uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
663 
664 /// \returns The encoding that will be used for \p ByteOffset in the
665 /// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
666 /// S_LOAD instructions have a signed offset, on other subtargets it is
667 /// unsigned. S_BUFFER has an unsigned offset for all subtargets.
668 Optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
669                                        int64_t ByteOffset, bool IsBuffer);
670 
671 /// \return The encoding that can be used for a 32-bit literal offset in an SMRD
672 /// instruction. This is only useful on CI.s
673 Optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
674                                                 int64_t ByteOffset);
675 
676 /// \returns true if this offset is small enough to fit in the SMRD
677 /// offset field.  \p ByteOffset should be the offset in bytes and
678 /// not the encoded offset.
679 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
680 
681 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
682                       const GCNSubtarget *Subtarget, uint32_t Align = 4);
683 
684 /// \returns true if the intrinsic is divergent
685 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
686 
687 // Track defaults for fields in the MODE registser.
688 struct SIModeRegisterDefaults {
689   /// Floating point opcodes that support exception flag gathering quiet and
690   /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
691   /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
692   /// quieting.
693   bool IEEE : 1;
694 
695   /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
696   /// clamp NaN to zero; otherwise, pass NaN through.
697   bool DX10Clamp : 1;
698 
699   /// If this is set, neither input or output denormals are flushed for most f32
700   /// instructions.
701   bool FP32InputDenormals : 1;
702   bool FP32OutputDenormals : 1;
703 
704   /// If this is set, neither input or output denormals are flushed for both f64
705   /// and f16/v2f16 instructions.
706   bool FP64FP16InputDenormals : 1;
707   bool FP64FP16OutputDenormals : 1;
708 
709   SIModeRegisterDefaults() :
710     IEEE(true),
711     DX10Clamp(true),
712     FP32InputDenormals(true),
713     FP32OutputDenormals(true),
714     FP64FP16InputDenormals(true),
715     FP64FP16OutputDenormals(true) {}
716 
717   SIModeRegisterDefaults(const Function &F);
718 
719   static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) {
720     const bool IsCompute = AMDGPU::isCompute(CC);
721 
722     SIModeRegisterDefaults Mode;
723     Mode.IEEE = IsCompute;
724     return Mode;
725   }
726 
727   bool operator ==(const SIModeRegisterDefaults Other) const {
728     return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
729            FP32InputDenormals == Other.FP32InputDenormals &&
730            FP32OutputDenormals == Other.FP32OutputDenormals &&
731            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
732            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
733   }
734 
735   bool allFP32Denormals() const {
736     return FP32InputDenormals && FP32OutputDenormals;
737   }
738 
739   bool allFP64FP16Denormals() const {
740     return FP64FP16InputDenormals && FP64FP16OutputDenormals;
741   }
742 
743   /// Get the encoding value for the FP_DENORM bits of the mode register for the
744   /// FP32 denormal mode.
745   uint32_t fpDenormModeSPValue() const {
746     if (FP32InputDenormals && FP32OutputDenormals)
747       return FP_DENORM_FLUSH_NONE;
748     if (FP32InputDenormals)
749       return FP_DENORM_FLUSH_OUT;
750     if (FP32OutputDenormals)
751       return FP_DENORM_FLUSH_IN;
752     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
753   }
754 
755   /// Get the encoding value for the FP_DENORM bits of the mode register for the
756   /// FP64/FP16 denormal mode.
757   uint32_t fpDenormModeDPValue() const {
758     if (FP64FP16InputDenormals && FP64FP16OutputDenormals)
759       return FP_DENORM_FLUSH_NONE;
760     if (FP64FP16InputDenormals)
761       return FP_DENORM_FLUSH_OUT;
762     if (FP64FP16OutputDenormals)
763       return FP_DENORM_FLUSH_IN;
764     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
765   }
766 
767   /// Returns true if a flag is compatible if it's enabled in the callee, but
768   /// disabled in the caller.
769   static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
770     return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
771   }
772 
773   // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
774   // be able to override.
775   bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
776     if (DX10Clamp != CalleeMode.DX10Clamp)
777       return false;
778     if (IEEE != CalleeMode.IEEE)
779       return false;
780 
781     // Allow inlining denormals enabled into denormals flushed functions.
782     return oneWayCompatible(FP64FP16InputDenormals, CalleeMode.FP64FP16InputDenormals) &&
783            oneWayCompatible(FP64FP16OutputDenormals, CalleeMode.FP64FP16OutputDenormals) &&
784            oneWayCompatible(FP32InputDenormals, CalleeMode.FP32InputDenormals) &&
785            oneWayCompatible(FP32OutputDenormals, CalleeMode.FP32OutputDenormals);
786   }
787 };
788 
789 LLVM_READNONE
790 bool isInlinableIntLiteral(int64_t Literal);
791 
792 } // end namespace AMDGPU
793 } // end namespace llvm
794 
795 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
796